AD1996 [ADI]
Class-D Audio Power Amplifier; D类音频功率放大器
| 型号： | AD1996 |
| 厂家： | 
ADI |
| 描述： | Class-D Audio Power Amplifier |
| 文件： | 总16页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Class-D Audio Power Amplifier
Preliminary Technical Data
AD1990/AD1992/AD1994/AD1996
GENERAL DESCRIPTION
FEATURES
The AD199x is a two channel Bridge Tied Load (BTL)
Integrated Stereo Modulator & Power Stage
0.005% THD+N
101.5dB Dynamic Range
PSRR > 65 dB
switching audio power amplifier with integrated ∑∆ modulator.
The modulator accepts a 1Vrms input signal (maximum power)
and generates a switching waveform to drive speakers directly.
One of the two modulators can control both output stages
providing twice the current for single-channel applications. A
digital, microcontroller-compatible interface provides control of
reset, mute and PGA gain as well as output signals for thermal
and over-current error conditions. The output stage can operate
from supply voltages ranging from 8V to 20V. The analog
modulator and digital logic operate from a 5V supply.
RDS-ON < 0.3 Ω (per transistor)
Efficiency > 80% @ 5W/6 Ω
EMI Optimized Modulator
On-Off-Mute Pop Noise Suppression
Short Circuit Protection
Over-Temperature Protection
Low Cost DMOS Process
APPLICATIONS
AD1990: 5Wx2 (10Wx1)
AD1992: 10Wx2 (20Wx1)
AD1994: 25Wx2 (50Wx1)
AD1996: 40Wx2 (80Wx1)
Flat Panel Televisions
Automotive Amplifiers
PC Audio Systems
Mini Components
62
63
60
53
50
51
32
31
LEFT CHANNEL
RIGHT CHANNEL
41,42
PVDD2
7,8
PVDD
PVDD2
DRIVER
HIGH SIDE
43,44,45
OUTR+
4,5,6
OUTL+
DRIVER
LOW SIDE
LEVEL
SHIFT
+
DEAD
TIME
LEVEL
SHIFT
+
DEAD
TIME
1,2,3
PGND1
9,10
PVDD1
46,47,48
PGND2
39,40
PGND2
PVDD2
Σ∆
MODULATOR
Σ∆
MODULATOR
PGA
PGA
PVDD2
CONTROL
CONTROL
DRIVER
DRIVER
HIGH SIDE
HIGH SIDE
11,12,13
OUTL-
36,37,38
OUTR-
DRIVER
DRIVER
LOW SIDE
LOW SIDE
14,15,16
PGND1
33,34,35
PGND2
PGND1
PGND2
Ø1
Ø2
Ø1
Ø2
55
REF_FILT
VOLTAGE
REFERENCE
57
AVDD
MUTE/
POP
CONTROL
56
AGND
OSCILLATOR
MODE CONTROL LOGIC
TEMPERATURE
SENSE &
OVER-CURRENT
PROTECTION
24,25
DVDD
23,26
DGND
27
CLKI
28
CLKO
30
29
19
18
17
49
22 21 20
Figure 1. Block Diagram
Rev. PrA – 1/20/05
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD199x
Preliminary Technical Data
TABLE OF CONTENTS
General Description ........................................................................ 1
AD199x—Specifications.................................................................. 3
test conditions unless otherwise noted...................................... 3
Absolute Maximum Ratings............................................................ 6
Pin Configurations And Functional Descriptions....................... 7
Typical Performance Characteristics ............................................. 8
Functional Description.................................................................. 10
Device Architecture ................................................................... 10
Amplifier Gain............................................................................ 10
System Design............................................................................. 11
Outline Dimensions....................................................................... 14
ESD Caution................................................................................ 14
Rev. PrA – 1/20/05 | Page 2 of 16
Preliminary Technical Data
AD199X—SPECIFICATIONS
AD199x
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
AVDD
5 V
DVDD
5 V
PVDDX
12 V
Ambient Temperature
Load Impedance
Clock Frequency
25 °C
6 Ω
11.2896 MHz
Measurement Bandwidth 20 Hz to 20 KHz
Table 1. Performance of both channels is identical
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
RL = 6Ω, PVDD = 20 V, 1 kHz (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
OUTPUT POWER (PO)
AD1990
4
5
8
10
16
25
25
40
84
W
W
W
W
W
W
AD1992
AD1994
AD1996
W
W
@ 10% THD+N (FTC)
fIN =1 kHz, PO = 5 W, RL = 6Ω
Efficiency
%
RON
per High Side Transistor
per Low Side Transistor
Maximum Current Through OUTx
Thermal Warning Active
Thermal Shutdown Active
Overcurrent Shutdown Active
Nominal Input Level
0.3
0.2
4
@ 1 A
@ 1 A
Ω
Ω
A
°C
°C
A
VRMS
%
135
150
4
Die temperature
Die temperature
1.0
PGA gain = 0 dB
Modulation Factor
90
PERFORMANCE SPECIFICATIONS
Total Harmonic Distortion (THD+N)
0.005
0.007
0.01
0.02
102
%
%
%
PGA = 0 dB, PO = 5 W
PGA = 6 dB, PO = 5 W
PGA = 12 dB, PO = 5 W
PGA = 18 dB, PO = 5 W
%
Signal/Noise Ratio (SNR)
Dynamic Range (DNR)
Crosstalk
dB
dB
dB
102
-100
-60 dB Input
Measured channel input = 0 VRMS
,
other channel = 1 kHz at 5W
20 Hz - 1 kHz
20 Hz – 20 kHz
Power supply rejection (PSRR)
60
45
dB
dB
DC SPECIFICATIONS
Input Impedance
20
10
AINL and AINR analog inputs
kΩ
mV
Output DC Offset Voltage
Rev. PrA – 1/20/05 | Page 3 of 16
AD199x
Preliminary Technical Data
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
POWER SUPPLIES
Supply Voltage AVDD
Supply Voltage DVDD
Supply Voltage PVDDX
Powerdown Current
AVDD
4.5
4.5
6.5
5
5
8-20
5.5
5.5
22.5
V
V
V
RST/PDN
held low
0.1
0.1
19
0.5
0.5
25
µA
µA
µA
DVDD
PVDDX
MUTE
Mute Current
AVDD
DVDD
held low
19
2.7
1.5
mA
mA
mA
PVDD
Quiesent Current
AVDD
DVDD
Inputs Grounded, Non-Overlap Time = TBD
20
5.2
3.2
mA
mA
mA
PVDDX
Operating Current
AVDD
DVDD
VIN = 1VRMS, PO = 5 W
per FET
22
5.8
mA
mA
A
PVDD
4
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current on Digital Inputs
2.0
DVDD
0.8
V
V
V
V
µA
DVDD-0.8
@ 2 mA
@ 2 mA
0.4
10
Rev. PrA – 1/20/05 | Page 4 of 16
Preliminary Technical Data
AD199x
Table 2 DIGITAL TIMING (Guaranteed over -40°C to +85°C, AVDD = DVDD = 5.0V 10%, PVDDX =12V 10%, Non Overlap Time
tNOL = Shortest, See Table 6: Non-Overlap Time Settings)
Parameter
Min
Typ
Max
Units
Comments
RST/PDN
tPDRP
500
ns
minimum low pulsewidth
MUTE
tMPDL
5
µs
asserted to output initial response
RST/PDN MUTE
tMUTEDLY
1
sec
high to
high delay
OUTL+/
OUTR+
OUTL-/
OUTR-
t
t
NOL
NOL
Figure 2. Output Timing
MUTE
t
PST
t
PST
OUTX
t
t
MPDL
MPDL
Figure 3. Mute Timing
RESET
MUTE
t
MUTEDLY
Figure 4. Reset to Mute Delay
Rev. PrA – 1/20/05 | Page 5 of 16
AD199x
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. AD199x Absolute Maximum Ratings1
1Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Parameter
Rating
AVDD, DVDD to AGND, DGND
PVDDX to PGND
-0.3 V to +6.5 V
-0.3 V to +30.0 V2
-0.3 V to +0.3 V
-0.5 V to +0.5 V
AGND to AVDD
–40°C to +85°C
–65°C to +150°C
150°C
AGND to DGND to PGND
AVDD, to DVDD
Audio Inputs
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
2Including any induced voltage due to inductive load
3°C/W
θJC Thermal Impedance (LFCSP)
θJC Thermal Impedance (PSOP)
Lead Temperature
1°C/W
Soldering (10 sec)
260°C
215°C
220°C
Vapor Phase (60 sec)
Infrared (15 sec)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
•
PGND1
1
2
48 PGND2
47 PGND2
46 PGND2
45 OUTR+
44 OUTR+
43 OUTR+
PIN 1
IDENTIFIER
PGND1
PGND1
OUTL+
OUTL+
OUTL+
3
4
5
6
PV
PV
PV
PV
7
42 PV
41 PV
40 PV
39 PV
DD1
DD1
DD1
DD1
DD2
DD2
DD2
DD2
AD1990/92/94
TOP VIEW
(Not to Scale)
8
9
10
OUTL- 11
OUTL- 12
OUTL- 13
PGND1 14
PGND1 15
PGND1 16
38 OUTR-
37 OUTR-
36 OUTR-
35 PGND2
34 PGND2
33 PGND2
1990-0002
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5. 64 Lead LFCSP Package
Rev. PrA – 1/20/05 | Page 6 of 16
Preliminary Technical Data
AD199x
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Table 4. Pin Function Descriptions
LFCSP
Pin No.
1,2,3
4,5,6
7,8,9,10
11,12,13
14,15,16
17
PSOP
Pin No.
3
2
1,36
35
Name
In/Out Description
PGND1
OUTL+
PVDD1
OUTL-
PGND1
ERR2
Negative power supply for high power transistors A2 and B2
O
O
Output of high power transistor pair, left channel positive polarity
Positive power supply for high power transistors, left channel high-side
Output of high power transistor pair, left channel negative polarity
Negative power supply for high power transistors, left channel low-side
Active low thermal shutdown error output
34
33
O
O
O
I
18
32
ERR1
Active low thermal warning error output
19
31
ERR0
Active low overcurrent error output
20
21
22
23,26
24,25
27
28
29
DCTRL2
DCTRL1
DCTRL0
DGND
DVDD
CLKI
CLKO
MUTE
RST/PDN
PGA1
PGA0
PGND2
OUTR-
PVDD2
OUTR+
PGND2
AGND
NFR+
NFR-
Non-overlap time setting MSB
I
Non-overlap time setting
I
Non-overlap time setting LSB
29,30
28
27
26
25
Negative power supply for low power digital circuitry
Positive power supply for low power digital circuitry
Clock input for 256 × fS audio modulator clock
Inverted version of CLKI for use with external crystal oscillator
Active low mute input
I
O
I
30
24
I
Active low reset/power-down input
31
32
23
22
21
20
I
Programmable gain amplifier (PGA) gain MSB
I
Programmable gain amplifier (PGA) gain LSB
33,34,35
36,37,38
39,40,41,42 18,19
43,44,45
46,47,48
49
50
51
52
53
Negative power supply for right channel high power transistors
Output of high power transistor pair, right channel negative polarity
Positive power supply for right channel high power transistors
Output of high power transistor pair, right channel positive polarity
Negative power supply for right channel high power transistors
Negative power supply for low power analog circuitry
Right channel negative feedback – positive input
Right channel negative feedback – negative input
Not Connected. This pin is not used and should be left floating
Analog input for right channel
O
O
17
16
15
14
13
I
I
NC
AINR
12
I
54
55
56
57
58
59
60
61
NC
Not Connected. This pin is not used and should be left floating
Filter pin for bandgap reference - should be bypassed to AGND
Negative power supply for low power analog circuitry
Positive power supply for low power analog circuitry
Not Connected. This pin is not used and should be left floating
Not Connected. This pin is not used and should be left floating
Analog input for left channel
Not Connected. This pin is not used and should be left floating
Left channel negative feedback – negative input
Left channel negative feedback – positive input
Mono mode (drive left and right output transistors from same modulator)
11
10
9
REF_FILT
AGND
AVDD
NC
NC
AINL
NC
NFL-
NFL+
MONO
O
8
4
7
6
5
I
62
63
64
I
I
I
Rev. PrA – 1/20/05 | Page 7 of 16
AD199x
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
+ 0
-20
-40
-60
-80
0
POWER = 5W
POWER = 100mW
= 6Ω
R
= 6Ω
–20
L
R
L
–40
–60
–80
- 1 0 0
- 1 2 0
–100
–120
–140
–160
- 1 4 0
- 1 60
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
1 0
1 2
1 4
1 6
1 8
20
Frequency (Hz)
FRE QU EN C Y ( KH z )
Figure 6. 1KHz, 100mW into a 6Ω Load
Figure 8. 1KHz, 5W into a 6Ω Load
0
0
–20
POWER = 1W
= 6Ω
-20
-40
R
L
POWER = 1W
R
= 6Ω
–40
L
–60
-60
-80
–80
–100
–120
–140
–160
-100
-120
-140
-160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Frequency (KHz)
FREQUENCY - KHz
Figure 7. 1KHz, 1W into a 6Ω Load
Figure 9. 7KHz, 1W into a 6Ω Load
Rev. PrA – 1/20/05 | Page 8 of 16
Preliminary Technical Data
AD199x
100
90
80
70
60
50
40
30
20
10
0
0
-20
-40
POWER = 1W
R
= 6Ω
L
-60
-80
-100
-120
-140
-160
0
1
2
3
4
5
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY - KHz
Watts Per Channel
Figure 13. Efficiency vs Power
Figure 10. 10KHz, 1W into a 6Ω Load
0
-20
-30
-40
-50
-60
-70
-80
-90
-20
-40
POWER = 1W
= 6Ω
R
L
-60
-80
-100
-120
-140
-160
-100
-110
-120
0
2
4
6
8
10
12
14
16
18
20
20
50
100
200 500
1K
2K
5K
10K 20K
FREQUENCY - KHz
FREQUENCY - Hz
Figure 11. 19KHz, 1W into a 6Ω Load
Figure 14. THD+N vs Distortion, 1W into a 6Ω Load
0
-10
-20
-30
-40
-50
T
PV
= 12V
DD
R
= 6Ω
L
AMPLIFIER GAIN (AV) = 2.7
2
POWER = (V
× AV × 2) /R
RMS
L
-60
-70
f
= 1KHz
f
= 10KHz
IN
IN
-80
-90
f
= 100Hz
IN
-100
-110
-120
0
0.2
0.2W
0.4/
0.78W
0.6/
0.8/
3W
1.0/
5W
1.2/
7W
1.75W
V
(V)
RMS
Figure 12. THD+N vs Input Signal/Power Output
Rev. PrA – 1/20/05 | Page 9 of 16
AD199x
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
driving the OUTx pin. The nature of the inductors is to keep
current flowing. For example the OUTx pin may approach and
pass the PGND level to achieve this. When the voltage at the
OUTx pin is 0.7V below PGND the parasitic diode associated
with the low-side transistor will become forward biased and
turn on. When the high-side transistor turns on the voltage at
OUTx will rise to PVDD and will reverse bias the parasitic
diode. However, by its nature the parasitic diode has a long
reverse recovery time and current will continue to flow through
it to PGND thus causing the entire circuit to draw more current
than necessary. The addition of the schottky diodes prevents
this happening. When the OUTx pin goes more than 0.3V
below PGND the schottky diode becomes forward biased.
When the high-side transistor turns on the schottky diode
becomes reverse biased. The reverse recovery time of the
schottky diode is significantly faster than the parasitic diode so
far less current is wasted. A similar effect happens when the
inductor induces a current which drives the OUTx pin above
PVDD. Figure 16 shows how the external components of a
system are connected to the pins of the AD199x to form the H-
bridge configuration.
DEVICE ARCHITECTURE
The AD199x is an audio quality, switching amplifier with an
integrated sigma-delta modulator. The power stage of the
AD199x is arranged internally as four transistor pairs, which
are used as two H-bridge outputs to provide stereo
amplification. The transistor pairs are driven by the output of
the ∑∆ modulator. A user selectable non-overlap time is
provided between the switching of the high side transistor and
low side transistor to ensure that both transistors are never on at
the same time. The AD199x implements turn on pop
suppression to eliminates any pops or clicks following a reset
or un-mute.
Analog Input Section
The analog input section uses an internal amplifier to bias the
input signal to the reference level. A DC blocking capacitor
should be connected as shown in Figure 15 to remove any
external DC bias contained in the input signal
1.25V
+
AINL/
AINR
0V
AMPLIFIER GAIN
Selecting the Modulator Gain
The AD199x modulator can be thought of as a switching
analog amplifier with a voltage gain controlled by two external
resistors forming a resistor divider between the OUTxx pins
and PGND. The centre of the resistor divider is connected to
the appropriate feedback pin NFx. Selecting the gain along
with the PVDD Voltage will determine how much power can be
delivered to a load for a fixed input signal. The gain of the
modulator is controlled by the values of R1 and R2 (see Figure
16) according to the equation below.
71046-0007
Figure 15. Normal Operation
The Sigma-Delta Modulator
Detailed description pending on patents pending, as well as
announcements, conference proceedings and other scheduled
public disclosures.
Selecting Stereo or Mono Mode
Driving the H-Bridge
Gain = (R1 + R2)/R2
The gain should be selected such that a 1Vrms input signal
doesn’t cause the modulator to generate an output signal which
has a peak to peak value greater than 90% of PVDD. Selecting
a gain that meets this criteria will ensure that the modulator
remains in a stable operating condition.
Each channel of the switching amplifier is controlled by a 4
transistor H-bridge to give a differential output stage. The
outputs of the H-bridges, OUTR+, OUTR-, OUTL+ and
OUTL- will switch between PVDD and PGND as determined
by the sigma delta modulator. The power supply that is used to
drive the power stage of the AD199x should be typically in the
range of +8 V to +20 V and should be capable of supplying
enough current to drive the load. This power supply is
connected across the PVDD and PGND pins. The feedback
pins, NFR+, NFR-, NFL+ and NFL-, are used to supply
negative feedback to the modulator. The pins are connected to
the outputs of the H-bridge via a resister divider network as
shown in Figure 16. See the section on Selecting the Modulator
Gain for more information.
PVDD
PVDD
EXTERNAL COMPONENTS
D3
D4
OUTx+
OUTx-
PGND
NFx-
PGND
NFx+
71046-0004
Figure 16. H-Bridge Configuration
External schottky diodes can be used to reduce power loss
during the non-overlap time when neither of the high-side or
low-side transistors is on. During this time neither transistor is
Rev. PrA – 1/20/05 | Page 10 of 16
Preliminary Technical Data
AD199x
Programmable Gain Amplifier (PGA)
high as required.
The AD199x incorporates a single-ended to differential
converter for each channel in the analog front-end section. Both
single-ended to differential converters feature a programmable
gain amplifier with four different gain settings. The gain is set
using the pins PGA1 and PGA0 as shown in Table 5. The
PGA1 and PGA0 pins are continuously monitored allow the
gain to be changed at any time.
On/Off/Mute Pop Noise Suppression
The AD199x features pop suppression which is activated when
the part is reset or taken out of mute. The pop suppression is
achieved by pulsing the power outputs to bring the outputs of
the LC filter from 0V to mid-scale in a controlled fashion. This
feature eliminates unwanted transients on both the outputs and
the high voltage power supply.
Thermal Protection
The AD199x features thermal protection. When the die
temperature exceeds approximately 135°C the Thermal
Table 5. PGA Gain Settings
PGA1
PGA0
PGA Gain (dB)
0
0
1
1
0
1
0
1
0
6
12
18
ERR1
Warning Error output (
exceeds approximately 150°C the Thermal Shutdown Error
ERR2
) is asserted. If the die temperature
output (
) is asserted. If this occurs, the part shuts down to
prevent damage to the part. When the die temperature drops
below approximately 120°C both error outputs are negated and
the part returns to normal operation.
SYSTEM DESIGN
Over-current Protection
The AD199x features over current or short circuit protection. If
the current through any power transistors exceeds 4A the part
goes into mute and the Over-current error output (
asserted. This is a latched error and does not clear
automatically. To clear the error condition and restore normal
operation, the part must be either reset, or
asserted and negated.
Clocking
The AD199x has two clock pins, CLKI and CLKO which are
used to configure the clocking scheme for the device. The
AD199x should be driven by a clock which is 256 × fS where fS
is the desired sampling rate. If a crystal is to be used as the
clock source it should be connected across the CLKI and
CLKO pins as shown in Figure 17. Crystal Connection The
values and type of capacitors used will be determined by the
crystal manufacturer. A square-wave clock source may be
connected directly to the CLKI pin. The logic levels of the
square wave should be compatible with those defined in the
Digital I/O section of the specifications page.
ERR0
) is
MUTE
must be
Application Considerations
Good board layout and decoupling are vital for correct
operation of the AD199x. Due to the fact that the part switches
high currents there is the potential for large PVDD bounce each
time a transistor transitions. This can cause unpredictable
operation of the part. To avoid this potential problem, close
chip decoupling is essential. It is also recommended that the
decoupling capacitors are placed on the same side of the board
as the AD199x, and connected directly to the PVDD and
PGND pins. By placing the decoupling capacitors on the other
side of the board and decoupling through vias the effectiveness
of the decoupling is reduced. This is because vias have
inductive properties and therefore prevent very fast discharge
of the decoupling capacitors. Best operation is achieved with at
least one decoupling capacitor on each side of the AD199x, or
optionally two capacitors per side can be used to further reduce
the series resistance of the capacitor. If these decoupling
recommendations cannot be followed and decoupling through
vias is the only option, the vias should be made as large as
possible to increase surface area, thereby reducing inductance
and resistance.
XTAL
22pF
22pF
47Ω
Figure 17. Crystal Connection
Output Transistor Non-Overlap Time
Ipsum lorum...
Power-up Considerations
Careful power-up is necessary when using the AD199x to
ensure correct operation and avoid possible latch-up issues. The
RST/PDN
MUTE
and
AD199x should be powered-up with
held low until all the power supplies have stabilized. Once the
supplies have stabilized the AD199x can be brought out of reset
RST/PDN
MUTE
can be brought
by bringing
high and then
Rev. PrA – 1/20/05 | Page 11 of 16
AD199x
Preliminary Technical Data
DVDD
PVDD
+
0.1µF
47µF
0.1µF
100µF
AVDD
PVDD
+
0.1µF
47µF
0.1µF
100µF
PVDD
100µF
L
AINL
AINR
OUTL+
C
R1
R2
NFL+
100µF
R2
R1
NFL-
PVDD
PVDD
OUTL-
L
L
C
C
AD1990
REF_FILT
100nF
47µF
OUTR+
NFR+
R1
R2
MUTE
R2
R1
RST/PDN
NFR-
PVDD
OUTR-
L
C
THERMAL SHUTDOWN
THERMAL WARNING
OVERCURRENT
ERR2
ERR1
ERR0
R1 = 1K47
R2 = 523Ω
L = 18µH
C = 1µF
CLKI
CLKO
Figure 18. Typical Stereo Mode Application Circuit
Rev. PrA – 1/20/05 | Page 12 of 16
Preliminary Technical Data
AD199x
DVDD
PVDD
+
0.1µF
47µF
0.1µF
100µF
AVDD
PVDD
+
0.1µF
47µF
0.1µF
100µF
PVDD
100µF
L
AINL
AINR
OUTL+
C
R1
R2
NFL+
R2
R1
NFL-
PVDD
OUTL-
L
C
AD1990
REF_FILT
100nF
47µF
OUTR+
NFR+
MUTE
RST/PDN
NFR-
DVDD
ST/MO
OUTR-
THERMAL SHUTDOWN
ERR2
ERR1
ERR0
THERMAL WARNING
OVERCURRENT
CLKI
CLKO
Figure 19. Mono Mode Circuit
Rev. PrA – 1/20/05 | Page 13 of 16
AD199x
Preliminary Technical Data
OUTLINE DIMENSIONS
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
64
49
48
1
PIN 1
INDICATOR
4.85
4.70
4.55
8.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
SQ*
0.45
0.40
0.35
33
32
1
6
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12 MAX
û
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 20. 64-Lead Frame Chip Scale Package (LFCSP)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 6. Ordering Guide
Products
Package
Temperature
Power
Rating
Package Description
Package Outline
AD1990ACPZ
AD1992ACPZ
AD1994ACPZ
AD1996ACPZ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
5W per channel
10W per channel
25W per channel
40W per channel
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Power Small Outline Package
CP-64
CP-64
CP-64
PSOP-36
Rev. PrA – 1/20/05 | Page 14 of 16
Preliminary Technical Data
NOTES
AD199x
Rev. PrA – 1/20/05 | Page 15 of 16
AD199x
NOTES
Preliminary Technical Data
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. PR05380-0-1/05(PrA)
Rev. PrA – 1/20/05 | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明