AD394KD [ADI]
Up-Compatible Multiplying Quad 12-Bit D/A Converter; 向上兼容的乘法四路12位D / A转换器型号: | AD394KD |
厂家: | ADI |
描述: | Up-Compatible Multiplying Quad 12-Bit D/A Converter |
文件: | 总12页 (文件大小:626K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
µP-Compatible Multiplying
Quad 12-Bit D/A Converter
AD394
FEATURES
Four, complete, 12-bit CMOS DACs with buffer registers
Linearity error: 1ꢀ2 LSB TMIN, TMAX (AD394T)
Factory-trimmed gain and offset
Precision output amplifiers for VOUT
Full four-quadrant multiplication per DAC
Monoticity guaranteed over full temperature range
Fast settling: 15 µs maximum to 1ꢀ2 LSB
Available in MIL-STD-883B
PRODUCT DESCRIPTION
The AD394 contains four 12-bit, high-speed, low power, voltage
output, multiplying digital-to-analog converters in a compact
28-pin hybrid package. The design is based on a proprietary,
latched, 12-bit, CMOS DAC chip, which reduces chip count and
provides high reliability. The AD394 is ideal for systems
requiring digital control of many analog voltages where board
space is at a premium and low power consumption is a neces-
sity. Such applications include automatic test equipment, process
controllers, and vector stroke displays.
The AD394 is laser-trimmed to ±1ꢀ2 ꢁSB maximum differential
and integral linearity (AD394T) and full-scale accuracy of
±±.±0 percent at 20°C. The high initial accuracy is possible
because of the use of precision, laser-trimmed, thin-film scaling
resistors.
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
1. The AD394 offers a dramatic reduction in printed circuit
board space in systems using multiple low power DACs.
CS1
The individual DAC registers are accessed by the
CS4
through
control pins. These control signals allow any combination
of the DAC select matrix to occur (see Table 3). Once selected,
the DAC is loaded with a single 12-bit wide word. The 12-bit
parallel digital input interfaces to most 12- and 16-bit bus
systems.
2. Each DAC is independently addressable and provides
versatile control architecture for a simple interface to
microprocessors. All latch enable signals are level-
triggered.
The AD394 outputs (VREFIN = 1± V) provide a ±1± V bipolar
output range with positive-true offset binary input coding.
3. The output voltage is trimmed to a full-scale accuracy of
±±.±05. Settling time to ±1ꢀ2 ꢁSB is 10 µs maximum.
The AD394 is packaged in a 28-lead ceramic package and is
available for operation over a −00°C to +120°C temperature
range.
4. A maximum gain TC of 0 ppmꢀ°C is achievable.
0. Two- or four-quadrant multiplication can be achieved
simply by applying the appropriate input voltage signal to
the selected DAC's reference (VREFIN).
6. The AD394TD features guaranteed accuracy and linearity
over the −00°C to +120°C temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD394
TABLE OF CONTENTS
Specifications..................................................................................... 3
Analog Circuit Details ..................................................................8
Operation From ±12 V Supplies..................................................9
Power Supply Decoupling ............................................................9
Improving Full-Scale Stability .....................................................9
Applications ...................................................................................9
Applications ................................................................................ 1±
Package Outline .............................................................................. 12
Ordering Guide .......................................................................... 12
Absolute Maximum Ratings............................................................ 0
ESD Caution.................................................................................. 0
Pin Configuration and Functional Block Diagram...................... 6
Theory of Operation ........................................................................ 7
Multiplying Mode......................................................................... 7
Data and Control Signal Format ................................................ 7
Timing............................................................................................ 8
REVISION HISTORY
9/04–Rev. 0 Changed to Rev. A
Updated format....................................................................... Universal
Deleted AD390 part................................................................ Universal
Change to Product Description...........................................................1
Changes to Specifications table............................................................3
Delete Figure 3 .......................................................................................4
Delete Figure 6 .......................................................................................0
Change to Theory of Operation section.............................................7
7/85–Initial Version: Revision 0
Rev. A | Page 2 of 12
AD394
SPECIFICATIONS
Table 1. TA = 25°C, VREFIN = 10 V, VS = 15 V, ꢀnless otherwise specified
AD394TD and AD394TDꢀ883B1
Model
Min
Typ
Max
Units
DATA INPUTS (Pins 1-16)2
TTL or 5 V CMOS-Compatible
Input Voltage
Bit ON (Logic 1)
Bit OFF (Logic 0)
Input Current
2.4
0
5.5
0.8
40
V
V
µA
Bits
4
RESOLUTION
12
OUTPUT
Voltage Range3
VREFIN
V
Current
5
mA
STATIC ACCURACY
Gain Error
Offset
0.025
0.012
0.012
1ꢀ8
0.05
0.025
% of FSR4
% of FSR
% of FSR
LSB
Bipolar Zero
Integral Linearity Error5
Differential Linearity Error
TEMPERATURE PERFORMANCE
Gain Drift
1ꢀ2
1ꢀ2
1ꢀ4
LSB
5
5
ppm FSRꢀ°C
ppm FSRꢀ°C
Offset Drift
Integrated Linearity Error5
TMIN to TMAX
1ꢀ4
1ꢀ2
LSB
Differential Linearity Error
MONOTONICITY GUARANTEED
OVER FULL TEMPERATURE RANGE
REFERENCE INPUTS
Input Resistance
Voltage Range
5
−11
25
+11
kΩ
V
DYNAMIC PERFORMACE
Setting Time (to 1ꢀ2 LSB)
VPREFIN = 10 V, Change All Digital Inputs from 5.0 V
to 0 V
VREFIN = 0 V to 5 V Step, All Digital Inputs = 0 V
Reference Feedthrough Error
Digital-to-Analog Glitch Impulse6
Crosstalk
10
15
15
µs
µs
10
See Figure 2
250
nV-s
Digital Input (Static)7
Reference8
0.1
2.0
LSB
mV p-p
POWER REQUIREMENTS
Supply Voltage9
13.5
16.5
V
Current (All Digital Inputs 0 V or 5 V)
+VS
−VS
40
18
570
48
28
750
mA
mA
mW
Power Dissipation
Rev. A | Page 3 of 12
AD394
AD394TD and AD394TDꢀ883B1
Typ
Model
Min
Max
Units
POWER SUPPLY GAIN SENSITIVITY
+VS
−VS
0.002
0.0025
%FSꢀ%
%FSꢀ%
TEMPERATURE RANGE
Operating (Full Specifications)
T
−55
−65
125
150
°C
°C
Storage
1 The AD394 T grade is available to MIL-STD-883, Method 5008, Class B. See Analog Devices Military Catalog (1985) for proper part number and detail specification.
2 Timing specifications appear in Table 5 and Figure 6.
3 See the Theory of Operation section for code tables and graphs.
4 FSR means full-scale range and is equal to 20 V for a 10 V bipolar range and 10 V for a 0 V to 10 V unipolar range.
5 Integral nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function.
6 This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the
glitch in nVs and is measured with VREFIN = AGND.
7 Digital crosstalk is defined as the change in any one output’s steady state value as a result of any other output being driven from VOUTMIN to VOUTMAX into a 2kΩ load by
means of varying the digital input code.
8 Reference crosstalk is defined as the change in any one output as a result of any other output being driven from VOUTMIN to VOUTMAX @10 kHz into a 2 kΩ load by means
of varying the amplitude of the reference signal.
9 The AD394 can be used with supply voltages as low as 11.4 V. See Figure 10.
Rev. A | Page 4 of 12
AD394
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress
rating only and functional operation at or above this specifica-
tion is not implied. Exposure to above maximum rating
conditions for extended periods may affect device reliability.
Parameter
Rating
+VS to DGND
−VS to DGND
Digital Inputs (Pins 1-16) to DNGD
VREFIN to DGND
−0.3 V to +17 V
−17 V to +0.3 V
−0.3 V to +7 V
25 V
AGND to DGND
0.6 V
Analog Output (Pins 18, 21, 24, 27)
Indefinite short to AGND
or DGND momentary
short to VS
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
MIL-STD-883
The rigors of the military and aerospace environment, temp-
erature extremes, humidity, mechanical stress, etc., demand the
utmost in electronic circuits. The AD394, with the inherent
reliability of an integrated circuit construction, was designed
with these applications in mind. The hermetically-sealed, low
profile DIP package takes up a fraction of the space required by
equivalent modular designs and protects the chips from
hazardous environments. To further insure reliability, the
AD394 is fully compliant to MIꢁ-STD-833 Class B, Method
0±±8.
Figure 2. Feedthrough VREFIN = 60 Hz (Top Photo) and 400 Hz (Bottom Photo).
The Sine-Wave Digital Code Is Set at 1000 000 0000. Scale: Reference Input Is
5 V/DIV (Thin Trace). Feedthrough Output Is 5 mV/DIV. Time: 5 ms/DIV (Top
Photo), 500 µs/DIV (Bottom Photo).
Rev. A | Page 5 of 12
AD394
PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM
Figure 3. Pin Configuration
Figure 4. Functional Block Diagram (Bipolar)
Rev. A | Page 6 of 12
AD394
THEORY OF OPERATION
The AD394 quad DAC provides four-quadrant multiplication.
It is a hybrid IC comprised of four, monolithic, 12-bit, CMOS,
multiplying DACs and eight precision output amplifiers. Each
of the four independent-buffered channels has an independent
reference input capable of accepting a separate dc or ac signal
for multiplying or for function generation applications. The
CMOS DACs act as digitally programmable attenuators when
used with a varying input signal or, if used with a fixed dc
reference, the DAC would act as a standard bipolar output DAC.
In addition, each DAC has a 12-bit wide data latch to buffer the
converter when connected to a microprocessor data bus.
Figure 5. The AD394 as a Four-Quadrant Multiplier
of Reference and Digital Input
MULTIPLYING MODE
Figure 0 shows the transfer function. The diagram indicates an
area over which many different combinations of the reference
input and digital input can result in a particular analog output
voltage. The highlighted transfer line in the diagram indicates
the transfer function if a fixed reference is at the input. The
digital code above the diagram indicates the midpoint and
endpoints of each function. The relationship between the
reference input (VREFIN), the digital input code, and the analog
output is given in Table 4. Note that the reference input signal
sets the slope of the transfer function (and determines the full-
scale output at code 111...111), while the digital input selects the
horizontal position in each diagram.
DATA AND CONTROL SIGNAL FORMAT
The AD394 accepts 12-bit parallel data in response to Control
Signals . As detailed in Table 3, the four chip select
–
CS1 CS4
lines are used to address the DAC register of interest. It is per-
missible to have more than one chip select active at any time. If
–
are all brought low coincident, all four DAC outputs
CS1 CS4
will be updated to the value located on the data bus. All control
inputs are level-triggered and may be hard-wired low to render
any register (or group of registers) transparent.
Table 3. DAC Select Matrix
CS1
CS2
CS3
CS4
Operation
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
0
0
All DACs latched
Load DAC 1 from data bus
Load DAC 2 from data bus
Load DAC 3 from data bus
Load DAC 4 from data bus
All DACs simultaneously loaded
Table 4. Bipolar Code Table
Data Input
Analog Output
Analog Output Voltage, VREFIN = 10 V
2±47
2±48
⎧
⎨
⎩
⎫
⎬
⎭
1111
1111
0000
0000
0000
1111
0000
0000
1111
0000
0001
0000
1111
0000
0000
1 × (VREFIN
1 × (VREFIN
1 × (VREFIN
1 × (VREFIN
)
)
)
)
9.9951 V
Full Scale − 1 LSB
1ꢀ2 Scale
1 LSB
1±24
2±48
⎧
⎨
⎩
⎫
⎬
⎭
1100
1000
1000
0111
0100
0000
5.000 V
1
2±48
⎧
⎨
⎩
⎫
⎬
⎭
4.88 mV
0.000 V
±
⎧
⎨
⎩
⎫
⎬
⎭
Zero
2±48
1
2±48
⎧
⎨
⎩
⎫
⎬
⎭
−1 × (VREFIN
−1 × (VREFIN
−1 × (VREFIN
)
)
)
−4.88 mV
−5.000 V
−10.000 V
−1LSB
1±24
2±48
⎧
⎨
⎩
⎫
⎬
⎭
−1ꢀ2 Scale
−Full Scale
2±48
2±48
⎧
⎨
⎩
⎫
⎬
⎭
Rev. A | Page 7 of 12
AD394
the DAC outputs are accurately developed between the output
pin and Pin 23 (AGND), delivering these signals to remote
loads can be a problem. These problems are compounded if a
current booster stage is used, or if multiple packages are used.
Figure 8 illustrates the parasitic impedances that influence
output accuracy.
TIMING
CS1
The AD394 control signal timing is very straightforward.
–
CS4
must maintain a minimum pulse width of at least 4±± ns
for a desired operation to occur. When loading data from a bus
into a 12-bit wide data latch, the data must be stable for at least
21± ns before returning CS to a high state. When
CS
is low, the
data latch is transparent, allowing the data at the input to propa-
gate through to the DAC. Data can change immediately after the
chip select returns high. DAC settling time is measured from
the falling edge of the active chip select.
Table 5. AD394 Timing Specifications, TMIN to TMAX
Symbol
Parameter
Typ
170
0
150
5
Units
tCS
tDA
tDS
tDH
Chip Select Pulse Width
Data Access Time
Data Setup Time
Data Hold Time
ns min
ns min
ns min
ns min
Figure 7. Recommended Ground Connections
Figure 6. Timing Diagram
ANALOG CIRCUIT DETAILS
Grounding Rules
Figure 8. Grounding Errors in Multiple AD394 Systems
The AD394 includes two ground connections to minimize
system accuracy degradation arising from grounding errors.
The two ground pins are designated DGND (Pin 17) and
AGND (Pin 23). The DGND pin is the return for the supply
current and serves as the reference point for the digital input
thresholds. Thus, DGND should be connected to the same
ground as the circuitry that drives the digital inputs.
An output buffer configured as a subtracter, as shown in
Figure 9, can greatly reduce these errors. First, sensing the
voltage directly at the load with R4 eliminates the effects of
voltage drops in wiring resistance. Second, sensing the remote
ground directly with R3 eliminates the voltage drops caused by
currents flowing through ZGA. Resistors R1 through R4 should
be well matched to achieve maximum rejection of the voltage
appearing across ZGA. Resistors matched to within 1 percent
(including the effects of RW2 and RW3) reduce ground interac-
tion errors by a factor of 1±±.
Pin 23, AGND, is a high quality analog ground connection.
This pin should serve as the reference point for all analog
circuitry associated with the AD394. It is recommended that
any analog signal path carrying significant currents have its
own return connection to Pin 23, as shown in Figure 7.
Several complications arise in practical systems, particularly if
the load is referred to a remote ground. These complications
include dc gain errors due to wiring resistance between DAC
and load, noise due to currents from other circuits flowing in
power ground return impedances, and offsets due to multiple
load currents sharing the same signal ground returns. While
Rev. A | Page 8 of 12
AD394
The AD271± is a suitable reference source for such systems. It
features a guaranteed maximum temperature coefficient of
±1 ppmꢀ°C. The combination of the AD271±ꢁN and AD394, as
shown in Figure 11, yields a multiple DAC system with maxi-
mum full-scale drift of ±6 ppmꢀ°C and excellent tracking.
Figure 9. Use of Subtracter Amplifier to Preserve Accuracy
OPERATION FROM 12 V SUPPLIES
The AD394 may be used with ±12 V ±05 power supplies if
certain conditions are met. The most important limitation is the
output swing available from the output op amps. These ampli-
fiers are capable of swinging only up to 3 V from either supply.
Thus, the normal ±1± V output range cannot be used. Changing
the output scale is accomplished by changing the reference
voltage. With a supply of ±11.4 V (05 less than ±12 V), the
output range is restricted to a maximum ±8.4 V swing. It may
be useful to scale the output at ±8.192 V (yielding a scale factor
of 4 mV per ꢁSB).
Figure 11. Low Drift Configuration
APPLICATIONS
Interfacing the AD394 to Microprocessors
The AD394 control logic provides a simple interface to micro-
processors. The individual latches allow for multi-DAC inter-
facing to a single data bus.
16-Bit Processors
The AD394 is a 12-bit resolution DAC system and is easily
interfaced to 16-bit wide data buses. Several possible addressing
configurations exist.
Figure 1± shows a suggested circuit to set up a ±8.192 V output
range. To help prevent poor gain drift due to a possible mis-
match between RIN and RTHEVENIN of the divider network, it is
recommended to buffer RIN, the potentiometer wiper voltage,
with an OP-±7.
In the circuit shown in Figure 12, a system write signal is used
to control the decoded address lines and a 74ꢁS139 decoder
driven from the least significant address bits provides the
CS1
CS4
active-low
through
signals. In the circuit in Figure 12,
address lines A± and A1 each select a single DAC of the four
contained in the AD394. The use of a separate address line for
each DAC allows several DACs to be accessed simultaneously.
The address lines are gated by the simultaneous occurrence of a
WR
system
and the appropriately decoded base address.
In the addressing scheme shown in Figure 12, A± represents the
least significant word address bit. Data may reside in either the
12 MSBs (left-justified) or the 12 ꢁSBs (right-justified). ꢁeft
justification is useful when the data-word represents a binary
fraction of full scale, while right-justified data usually represents
an integer value between ± and 4±90.
Figure 10. Connections for 8.192 V Full Scale
(Recommended for 12 V Power Supplies)
POWER SUPPLY DECOUPLING
The power supplies used with the AD394 should be well-filtered
and regulated. ꢁocal supply decoupling consisting of a 1± µF
tantalum capacitor in parallel with ±.1 µF ceramic capacitor is
suggested. The decoupling capacitors should be connected
between the supply pins and the AGND pin. If an output
booster is used, its supplies should also be decoupled to the
load ground.
IMPROVING FULL-SCALE STABILITY
In large systems using multiple DACs, it may be desirable for all
devices to share a common reference. A precision reference can
greatly improve system accuracy and temperature stability.
Figure 12. 16-Bit Bus Interface
Rev. A | Page 9 of 12
AD394
8-Bit Processors
the ADC function since the processor can perform the required
digital operations under software control. A suitable circuit is
shown in Figure 14. The AD311 comparator compares the
unknown input voltage to one of the AD394 outputs for the
analog-to-digital conversion, while the other three outputs are
used as normal DACs. The diode clamp shown limits the
voltage swing at the comparator input and improves conversion
speed. With careful layout, a new compar-ison can be
performed in less than 10 µs, resulting in a 12-bit successive
approximation conversion in under 18± µs. The benefit of using
the AD394 in this application is that one ADC and three DACs
can be implemented with only two IC packages (the AD394 and
the comparator).
The circuit of Figure 13 shows the general principles for
connecting the AD394 to an 8-bit data bus. The 74ꢁS244 buffers
the data bus; its outputs are enabled when the DAC address
appears on the address bus. The first byte sent to the DAC is
loaded to the 74ꢁS373 octal latch and, when the second byte is
sent to the DAC, it is combined with the first byte to create a
12-bit word. The connections shown are for right-hand justified
CS
WR
data.
and
inputs to the DAC are also gated, and when
active, the DAC is loaded. Pull-up resistors at the output of the
74ꢁS244 buffer ensure that the inputs to the DAC do not float at
an ill-defined level when the DAC is not being addressed. This
method of connecting 12-bit DACs to an 8-bit data bus is most
cost effective when multiple DACs are utilized for 8-bit data bus
applications.
Figure 14. Using One AD394 Output for A/D Conversion
Programmable Window Comparator
The AD394 can be used to perform limit testing of responses to
digitally controlled input signals. For example, two DACs may
be used to generate software-controlled test conditions for a
component or circuit. The response to these input conditions
can be either completely converted from analog to digital or
simply tested against high and low limits generated by the two
DACs in the AD394.
Figure 13. 8-Bit Data Bus Interface
APPLICATIONS
The functional density of the AD394 permits complex analog
functions to be produced under digital control, where board
space requirements would otherwise be prohibitive. Multiple-
output plotters, multichannel displays, complex waveform
generation, and multiple programmable voltage sources can all
be implemented with the AD394 in a fraction of the space that
would be needed if separate DACs were used.
Using the AD394 for Analog-to-Digital Conversion
Many systems require both analog output and analog input
capability. While complete integrated circuit analog-to-digital
converters (such as the AD074A) are readily available, the
AD394 can be used as the precision analog section of an ADC
if some external logic is available. Several types of analog-to-
digital converters can be built with a DAC, comparator, and
control logic, including staircase, tracking, and successive-
approximation types. In systems that include a micropro-cessor,
only a comparator must be added to the AD394 to accomplish
Figure 15. Programmable Window Comparator
Used in Power-Supply Testing
In the circuit shown in Figure 10, two AD311 voltage compar-
ators are used within the AD394 to test the output of a 0 V
power-supply regulator. The AD394 VOUT1 output (through an
appropriate current booster) drives the input to the regulator to
simulate variations in input voltage. The output of the regulator
is applied to Comparators 1 and 2, with their outputs wire-
Rev. A | Page 10 of 12
AD394
OR’ed with ꢁED indicators as shown. The test limits for each
comparator are programmed by the AD394 VOUT2 and VOUT3
outputs. When the output of the device under testing is within
the limits, both comparators are off and D1 lights. If the output
is above or below the limits, either D4 or D0 lights.
code is applied to the DAC; the output voltage is the product of
the two—an attenuated version of the input. The maximum
attenuation range obtainable utilizing 12 bits is 4±96:1 or 72 dB.
AD394 as a Multiplier and Attenuator
So far, it has been assumed that the reference voltage VREFIN is
fixed. In fact, VREFIN can be any voltage within the range of
−11 V < VREFIN < +11 V. It can be negative, positive, sinusoidal, or
whatever the user prefers. This leads to the name “multiplying
DꢀA converters” because the output voltage, VOUT, is propor-
tional to the product of the digital input word and the voltage at
the VREFIN terminal.
Figure 16. AD394 as a Multiplier or Attenuator
D
4096
)
VOUT = −1
(
VREFIN
)
(
0 < D < 4095
)
(
D is the fractional binary value of the digital word applied to the
converter. The AD394 multiplies the digital input value by the
analog input voltage at VREFIN for any value of VREFIN up to
22 V p-p. This in itself is a powerful tool. Applications requiring
precision multiplication with minimal zero offset and very low
distortion should consider the AD394 as a candidate. One pop-
ular use for the AD394 is as an audio frequency attenuator. The
audio signal is applied to the VREFIN input and the attenuation
Rev. A | Page 11 of 12
AD394
PACKAGE OUTLINE
1.575 (40.01) MAX
28
15
0.810 (20.57)
0.770 (19.56)
1
14
PIN 1
SEE NOTE 1
0.035 (0.89)
0.015 (0.38)
SEE NOTE 3
0.225 (5.72)
MAX
0.015 (0.38)
0.008 (0.20)
0.180 (4.57)
MIN
0.620 (15.75)
0.550 (13.97)
SEE NOTE 6
0.145 (3.68)
MIN
0.137 (3.48)
MAX
SEE NOTE 5
0.070 (1.78)
0.030 (0.76)
SEE NOTE 2
0.100 (2.54)
0.023 (0.58)
0.014 (0.36)
BSC
SEE NOTE 4, 7
NOTES
1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS LOCATED ADJACENT TO LEAD ONE.
2. THE MINIMUM LIMIT FOR DIMENSION MAY BE 0.023" (0.58 mm) FOR ALL FOUR CORNER LEADS ONLY.
3. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THE BASIC PIN SPACING IS 0.100" (2.54 mm) BETWEEN CENTERLINES.
5. APPLIES TO ALL FOUR CORNERS.
6. MEASURED AT THE CENTERLINE OF THE LEADS.
7. TWENTY SIX SPACES.
8. CONTROLLING DIMENSIONS ARE IN INCHES. MILLIMETER DIMENSIONS ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 17. 28-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP/H]
(DH-28A)
Dimensions Shown in Inches and (Millimeters)
Note: Squared Corner and Dot in Shaded Area Indicate Pin 1.
ORDERING GUIDE
Model
AD394TD
Temperature Range
−55°C to +125°C
−55°C to +125°C
Gain Error
2 LSB
2 LSB
Linearity Error (TMIN–TMAX
)
1ꢀ2 LSB
1ꢀ2 LSB
AD394TDꢀ883B
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04851-0-9ꢀ04(A)
Rev. A | Page 12 of 12
相关型号:
AD394SD
PARALLEL, WORD INPUT LOADING, 10us SETTLING TIME, 12-BIT DAC, CDIP28, HYBRID, BOTTOM BRAZED, DOUBLE WIDTH, CERAMIC, DIP-28
ROCHESTER
AD394SD/883B
IC QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, CDIP28, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-28, Digital to Analog Converter
ADI
AD394TD/883B
IC QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, CDIP28, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-28, Digital to Analog Converter
ADI
AD395JD
D/A Converter, 1 Func, Parallel, Word Input Loading, 10us Settling Time, CDIP28, HYBRID, BOTTOM BRAZED, DOUBLE WIDTH, CERAMIC, DIP-28
ROCHESTER
AD395KD
D/A Converter, 1 Func, Parallel, Word Input Loading, 10us Settling Time, CDIP28, HYBRID, BOTTOM BRAZED, DOUBLE WIDTH, CERAMIC, DIP-28
ROCHESTER
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