AD4002_技术文档

18-Bit, 2 MSPS/1 MSPS/500 kSPS,

Precision, Pseudo Differential, SAR ADCs

Preliminary Technical Data

AD4002/AD4006/AD4010

FEATURES

GENERAL DESCRIPTION

Throughput: 2 MSPS/1 MSPS/500 kSPS options

INL: 2.0 LSB maximum

Guaranteed 18-bit, no missing codes

Low power

The AD4002/AD4006/AD4010 are low noise, low power, high

speed, 18-bit, precision successive approximation register (SAR)

analog-to-digital converters (ADCs). The AD4002, AD4006,

and AD4010 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,

9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS

(VDD only)

respectively. They incorporate ease of use features that reduce

signal chain power consumption, reduce signal chain

70 µW at 10 kSPS, 14 mW at 2 MSPS (total)

SNR: 95 dB typical at 1 kHz, V_REF= 5 V; TBD dB typical at 100 kHz

THD: −120 dB typical at 1 kHz, V_REF= 5 V; TBD dB typical at

100 kHz

Ease of use features reduce system power and complexity

Input overvoltage clamp circuit

Reduced nonlinear input charge kickback

High-Z mode

Long acquisition phase

complexity, and enable higher channel density. The high-Z

mode, coupled with a long acquisition phase, eliminates the

need for a dedicated high power, high speed ADC driver, thus

broadening the range of low power precision amplifiers that can

drive these ADCs directly while still achieving optimum

performance. The input span compression feature enables the

ADC driver amplifier and the ADC to operate off common

supply rails without the need for a negative supply while

preserving the full ADC code range. The low serial peripheral

interface (SPI) clock rate requirement reduces the digital

input/output power consumption, broadens processor options,

and simplifies the task of sending data across digital isolation.

Input span compression

Fast conversion time allows low SPI clock rates

SPI-programmable modes, read/write capability, status word

Pseudo differential (single-ended) analog input range

0 V to V_REFwith V_REFfrom 2.4 V to 5.1 V

Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface

SAR architecture: no latency/pipeline delay, valid first

conversion

Operating from a 1.8 V supply, the AD4002/AD4006/AD4010

sample an analog input (IN+) from 0 V to V_REFwith respect to a

ground sense (IN−) with V_REFranging from 2.4 V to 5.1 V. The

AD4002 consumes only 14 mW at 2 MSPS with a minimum SCK

rate of 75 MHz in turbo mode; the AD4006 consumes only

7 mW at 1 MSPS; and the AD4010 consumes only 3.5 mW at

500 kSPS. The AD4002/AD4006/AD4010 all achieve 2.0 LSB

integral nonlinearity error (INL) maximum, no missing codes

at 18 bits, and 95 dB signal-to-noise ratio (SNR) for an input

frequency (f_IN) of 1 kHz. The reference voltage is applied

First accurate conversion

Guaranteed operation: −40°C to +125°C

SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface

Ability to daisy-chain multiple ADCs and busy indicator

10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP

APPLICATIONS

externally and can be set independently of the supply voltage.

Automatic test equipment

Machine automation

Medical equipment

Battery-powered equipment

Precision data acquisition systems

The SPI-compatible versatile serial interface features seven

different modes including the ability, using the SDI input, to

daisy-chain several ADCs on a single 3-wire bus, and provides

an optional busy indicator. The AD4002/AD4006/AD4010 are

compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the

separate VIO supply.

The AD4002/AD4006 are available in a 10-lead MSOP and

10-lead LFCSP, and the AD4010 is available in a 10-lead LFCSP,

with operation specified from −40°C to +125°C. The devices are

pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).

Rev. PrA

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AD4002/AD4006/AD4010

Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Inputs ............................................................................. 20

Driver Amplifier Choice ........................................................... 21

Ease of Drive Features ............................................................... 22

Voltage Reference Input ............................................................ 23

Power Supply............................................................................... 23

Digital Interface.......................................................................... 24

Register Read/Write Functionality........................................... 25

Status Word ................................................................................. 27

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

Circuit Information.................................................................... 17

Converter Operation.................................................................. 18

Transfer Functions...................................................................... 18

Applications Information .............................................................. 19

Typical Application Diagrams .................................................. 19

CS

Mode, 3-Wire Turbo Mode ................................................. 28

Mode, 3-Wire Without Busy Indicator ............................. 29

Mode, 3-Wire with Busy Indicator .................................... 30

Mode, 4-Wire Turbo Mode ................................................. 31

Mode, 4-Wire Without Busy Indicator ............................. 32

Mode, 4-Wire with Busy Indicator .................................... 33

Daisy-Chain Mode..................................................................... 34

Layout Guidelines....................................................................... 35

Evaluating the AD4002/AD4006/AD4010 Performance ........ 35

Outline Dimensions....................................................................... 36

Rev. PrA | Page 2 of 36

Preliminary Technical Data

FUNCTIONAL BLOCK DIAGRAM

AD4002/AD4006/AD4010

2.4V TO 5.1V

10µF

1.8V

VDD

REF

AD4002/

VIO

SDI

1.8V TO 5V

V

REF

/2

0

AD4006/ HIGH-Z

TURBO

MODE

V

MODE

REF

AD4010

IN+

IN–

SCK

3-WIRE OR 4-WIRE

SPI INTERFACE

(DAISY CHAIN, CS)

SERIAL

INTERFACE

18-BIT

SAR ADC

SDO

CNV

STATUS

BITS

SPAN

COMPRESSION

CLAMP

GND

Figure 1.

Rev. PrA | Page 3 of 36

AD4002/AD4006/AD4010

SPECIFICATIONS

Preliminary Technical Data

VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, V_REF= 5 V, all specifications T_MINto T_MAX, high-Z mode disabled, span compression disabled,

turbo mode enabled, and sampling frequency (f_S) = 2 MSPS for the AD4002, f_S= 1 MSPS for the AD4006, and f_S= 500 kSPS for the AD4010,

unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

16

Bits

ANALOG INPUT

Voltage Range

Operating Input Voltage

IN+ Voltage (V_IN+) − IN− Voltage (V_IN−

V_IN+to GND

V_IN−to GND

Span compression enabled

Acquisition phase, T = 25°C

)

0

V_REF

V_REF+ 0.1

+0.1

V

nA

µA

−0.1

0.1 × V_REF

0.9 × V_REF

Analog Input Current

0.3

1

High-Z mode enabled,

converting dc input at 2 MSPS

THROUGHPUT

Complete Cycle

AD4002

AD4006

AD4010

Conversion Time

Acquisition Phase¹

AD4002

500

ns

1000

2000

270

290

320

290

790

1790

ns

AD4006

AD4010

Throughput Rate²

AD4002

AD4006

AD4010

0

2

1

500

MSPS

kSPS

ns

Transient Response³

DC ACCURACY

No Missing Codes

Integral Nonlinearity Error (INL)

TBD

18

Bits

LSB

ppm

LSB

−2.0

−3.8

TBD

1.6

+2.0

+3.8

TBD

T = 0°C to 85°C

Differential Nonlinearity Error (DNL)

Transition Noise

LSB

Zero Error

TBD

LSB

ppm/°C

LSB

ppm/°C

LSB

µV p-p

Zero Error Drift⁴

Gain Error

Gain Error Drift⁴

Power Supply Sensitivity

1/f Noise⁵

TBD

VDD = 1.8 V 5%

Bandwidth = 0.1 Hz to 10 Hz

TBD

6

AC ACCURACY

Dynamic Range

Total RMS Noise

95.5

30

dB

µV rms

f_IN= 1 kHz, −0.5 dBFS, V_REF= 5 V

Signal-to-Noise Ratio (SNR)

Spurious-Free Dynamic Range (SFDR)

Total Harmonic Distortion (THD)

Signal-to-Noise-and-Distortion Ratio (SINAD)

Oversampled Dynamic Range

TBD

95

dB

TBD

−120

94.5

119.5

Oversampling ratio (OSR) = 256,

V_REF= 5 V

Rev. PrA | Page 4 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

f_IN= 1 kHz, −0.5 dBFS, V_REF= 2.5 V

SNR

SFDR

THD

SINAD

TBD

88.5

TBD

dB

TBD

f_IN= 100 kHz, −0.5 dBFS, V_REF= 5 V

SNR

THD

SINAD

TBD

dB

f_IN= 400 kHz, −0.5 dBFS, V_REF= 5 V

SNR

THD

TBD

10

1

dB

MHz

ns

SINAD

−3 dB Input Bandwidth

Aperture Delay

Aperture Jitter

REFERENCE

ps rms

Voltage Range, V_REF

Current

AD4002

AD4006

AD4010

2.4

5.1

V

V_REF= 5 V

2 MSPS

1 MSPS

0.75

0.325

0.185

mA

500 kSPS

INPUT OVERVOLTAGE CLAMP

IN+/IN− Current, I_IN+/I_IN−

V_REF= 5 V

V_REF= 2.5 V

V_REF= 5 V

V_REF= 2.5 V

V_REF= 5 V

V_REF= 2.5 V

50

mA

V

ns

µA

V_IN+/V_IN−at Maximum I_IN+/I_IN−

5.4

3.1

5.4

2.8

360

100

V_IN+/V_IN−Clamp On/Off Threshold

5.25

2.68

Deactivation Time

REF Current at Maximum I_IN+

DIGITAL INPUTS

V_IN+> V_REF

Logic Levels

Input Low Voltage, V_IL

VIO > 2.7 V

VIO ≤ 2.7 V

VIO > 2.7 V

VIO ≤ 2.7 V

−0.3

0.7 × VIO

0.8 × VIO

−1

+0.3 × VIO

+0.2 × VIO

VIO + 0.3

+1

V

µA

pF

Input High Voltage, V_IH

Input Low Current, I_IL

Input High Current, I_IH

Input Pin Capacitance

DIGITAL OUTPUTS

Data Format

−1

+1

6

Serial 18 bits, straight binary

Pipeline Delay

Conversion results available

immediately after completed

conversion

Output Low Voltage, V_OL

Output High Voltage, V_OH

I_SINK= 500 µA

I_SOURCE= −500 µA

0.4

V

VIO − 0.3

Rev. PrA | Page 5 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

Parameter

POWER SUPPLIES

VDD

Test Conditions/Comments

Min

Typ

Max

Unit

1.71

1.8

1.89

5.5

V

VIO

Standby Current

Power Dissipation

VDD and VIO = 1.8 V, T = 25°C

VDD = 1.8 V, VIO = 1.8 V, V_REF= 5 V

10 kSPS, high-Z mode disabled

500 kSPS, high-Z mode disabled

1 MSPS, high-Z mode disabled

2 MSPS, high-Z mode disabled

500 kSPS, high-Z mode enabled

1 MSPS, high-Z mode enabled

2 MSPS, high-Z mode enabled

500 kSPS, high-Z mode disabled

1 MSPS, high-Z mode disabled

2 MSPS, high-Z mode disabled

500 kSPS, high-Z mode disabled

1 MSPS, high-Z mode disabled

2 MSPS, high-Z mode disabled

500 kSPS, high-Z mode disabled

1 MSPS, high-Z mode disabled

2 MSPS, high-Z mode disabled

1.6

µA

70

3.5

7

14

4

µW

4.2

8.2

16

5

9.9

19

mW

nJ/sample

8

16

2.5

4.9

9.75

0.9

1.9

3.75

0.1

0.2

0.5

7

VDD Only

REF Only

VIO Only

Energy per Conversion

TEMPERATURE RANGE

Specified Performance

T_MINto T_MAX

−40

+125

°C

¹The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the

AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010.

²A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable

throughput for different modes of operation.

³Transient response is the time required for the ADC to acquire a full-scale input step to 0.5 LSB accuracy.

⁴The minimum and maximum values are guaranteed by characterization, but not production tested.

⁵See the 1/f noise plot in Figure 23.

Rev. PrA | Page 6 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

TIMING SPECIFICATIONS

VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, V_REF= 5 V, all specifications T_MINto T_MAX, high-Z mode disabled, span compression disabled,

turbo mode enabled, and f_S= 2 MSPS for the AD4002, f_S= 1 MSPS for the AD4006, and f_S= 500 kSPS for the AD4010, unless otherwise noted.

See Figure 2 for the timing voltage levels.

Table 2. Digital Interface Timing

Parameter

Symbol

t_CONV

Min

Typ

Max

Unit

CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE

270

290

320

ns

ACQUISITION PHASE¹

t_ACQ

AD4002

AD4006

AD4010

290

790

1790

ns

TIME BETWEEN CONVERSIONS

t_CYC

AD4002

AD4006

AD4010

CNV PULSE WIDTH (CS MODE)²

500

1000

2000

10

ns

t_CNVH

t_SCK

SCK PERIOD (CS MODE)³

VIO > 2.7 V

VIO > 1.7 V

9.8

12.3

ns

SCK PERIOD (DAISY-CHAIN MODE)⁴

t_SCK

VIO > 2.7 V

VIO > 1.7 V

20

25

3

ns

SCK LOW TIME

t_SCKL

t_SCKH

t_HSDO

t_DSDO

SCK HIGH TIME

3

SCK FALLING EDGE TO DATA REMAINS VALID DELAY

1.5

SCK FALLING EDGE TO DATA VALID DELAY

VIO > 2.7 V

VIO > 1.7 V

7.5

10.5

ns

CNV OR SDI LOW TO SDO D17 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE)

t_EN

VIO > 2.7 V

VIO > 1.7 V

10

13

ns

CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY

LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY⁵

CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)

t_QUIET1

t_QUIET2

t_DIS

190

60

20

SDI VALID SETUP TIME FROM CNV RISING EDGE

t_SSDICNV

t_HSDICNV

t_HSCKCNV

t_SSDISCK

t_HSDISCK

2

ns

SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)

SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)

SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

2

12

2

¹The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the

AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010.

²For turbo mode, t_CNVHmust match the t_QUIET1minimum.

³A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable

throughput for different modes of operation.

⁴A 50% duty cycle is assumed for SCK.

⁵See Figure 22 for SINAD, SNR, and ENOB vs. t_QUIET2

.

1

Y% VIO

1

X% VIO

t_DELAY

2

V

IH

2

V

IL

1

2

FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.

MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS

IH

IL

SPECIFICATIONS IN TABLE 1.

Figure 2. Voltage Levels for Timing

Rev. PrA | Page 7 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

Table 3. Register Read/Write Timing

Parameter

Symbol

Min

Typ

Max

Unit

READ/WRITE OPERATION

CNV Pulse Width¹

SCK Period

t_CNVH

t_SCK

10

ns

VIO > 2.7 V

VIO > 1.7 V

SCK Low Time

SCK High Time

9.8

12.3

3

ns

t_SCKL

t_SCKH

3

READ OPERATION

CNV Low to SDO D17 MSB Valid Delay

VIO > 2.7 V

VIO > 1.7 V

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO > 2.7 V

t_EN

10

13

ns

t_HSDO

t_DSDO

1.5

7.5

10.5

20

ns

VIO > 1.7 V

CNV Rising Edge to SDO High Impedance

WRITE OPERATION

t_DIS

SDI Valid Setup Time from SCK Rising Edge

SDI Valid Hold Time from SCK Rising Edge

CNV Rising Edge to SCK Edge Hold Time

CNV Falling Edge to SCK Active Edge Setup Time

t_SSDISCK

t_HSDISCK

t_HCNVSCK

t_SCNVSCK

2

0

6

ns

¹For turbo mode, t_CNVHmust match the t_QUIET1minimum.

Table 4. Achievable Throughput for Different Modes of Operation

Parameter

Test Conditions/Comments

Min

Typ

Max Unit

THROUGHPUT, CS MODE

3-Wire and 4-Wire Turbo Mode

f_SCK= 100 MHz, VIO ≥ 2.7 V

f_SCK= 80 MHz, VIO < 2.7 V

f_SCK= 100 MHz, VIO ≥ 2.7 V

f_SCK= 80 MHz, VIO < 2.7 V

f_SCK= 100 MHz, VIO ≥ 2.7 V

f_SCK= 80 MHz, VIO < 2.7 V

f_SCK= 100 MHz, VIO ≥ 2.7 V

f_SCK= 80 MHz, VIO < 2.7 V

2

1.78

1.75

1.62

1.59

1.44

MSPS

3-Wire and 4-Wire Turbo Mode and Six Status Bits

3-Wire and 4-Wire Mode

3-Wire and 4-Wire Mode and Six Status Bits

Rev. PrA | Page 8 of 36

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

AD4002/AD4006/AD4010

THERMAL RESISTANCE

Note that the input overvoltage clamp cannot sustain the

overvoltage condition for an indefinite amount of time.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 5.

Parameter

Rating

Table 6. Thermal Resistance

Analog Inputs

IN+, IN− to GND¹

−0.3 V to V_REF+ 0.4 V

or 130 mA²

Package Type¹

RM-10

θ_JA

θ_JC

38

33

Unit

°C/W

2

3

147

114

Supply Voltage

CP-10-9

REF, VIO to GND

VDD to GND

VDD to VIO

Digital Inputs to GND

Digital Outputs to GND

Storage Temperature Range

Junction Temperature

Lead Temperature Soldering

−0.3 V to +6.0 V

−0.3 V to +2.1 V

−6 V to +2.4 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

¹Test Condition 1: thermal impedance simulated values are based upon use

of 2S2P JEDEC PCB.

²θ_JAis the natural convection junction-to-ambient thermal resistance

measured in a one cubic foot sealed enclosure.

³θ_JCis the junction-to-case thermal resistance.

ESD CAUTION

260°C reflow as per

JEDEC J-STD-020

ESD Ratings

Human Body Model

Machine Model

Field Induced Charged Device Model

4 kV

200 V

1.25 kV

¹See the Analog Inputs section for an explanation of IN+ and IN−.

²Current condition tested over a 10 ms time interval.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. PrA | Page 9 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

10

REF

VDD

IN+

VIO

REF 1

10 VIO

AD4002/

AD4006/

AD4010

TOP VIEW

(Not to Scale)

9

SDI

AD4002/

AD4006

TOP VIEW

(Not to Scale)

VDD 2

IN+ 3

9

8

7

6

SDI

8

SCK

SDO

CNV

SCK

SDO

CNV

IN–

7

IN– 4

GND

6

GND 5

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

THIS CONNECTION IS NOT REQUIRED TO

MEET THE SPECIFIED PERFORMANCE.

Figure 3. 10-Lead MSOP Pin Configuration

Figure 4. 10-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type¹Description

1

REF

AI

Reference Input Voltage. The V_REFrange is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be

decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor.

2

3

VDD

IN+

P

AI

1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor.

Analog Input. Referred to analog ground sense pin (IN−). The device samples the voltage differential

between IN+ and IN− on the leading edge on CNV. The operating input range of IN+ − IN− is 0 V to V_REF

.

4

5

6

IN−

GND

CNV

AI

P

DI

Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground.

Power Supply Ground.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects

the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled

when CNV is low. In daisy-chain mode, the data is read when CNV is high.

7

8

9

SDO

SCK

SDI

DO

DI

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data

level on SDI is output on SDO with a delay of 18 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator

feature is enabled. With CNV low, the device can be programmed by clocking in a 18-bit word on SDI on

the rising edge of SCK.

10

VIO

P

Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor.

Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet

the specified performance.

N/A²

EPAD

¹AI is analog input, P is power, DI is digital input, and DO is digital output.

²N/A means not applicable.

Rev. PrA | Page 10 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 1.8 V; VIO = 3.3 V; V_REF= 5 V; T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and f_S= 2 MSPS for

the AD4002, f_S= 1 MSPS for the AD4006, and f_S= 500 kSPS for the AD4010, unless otherwise noted.

TBD TBD

Figure 5. INL vs. Code for Various Temperatures, V_REF= 5 V

Figure 8. DNL vs. Code for Various Temperatures, V_REF= 5 V

TBD

Figure 6. INL vs. Code for Various Temperatures, V_REF= 2.5 V

Figure 9. DNL vs. Code for Various Temperatures, V_REF= 2.5 V

TBD

Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled,

Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled,

V_REF= 5 V

V

_REF= 5 V

Rev. PrA | Page 11 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

TBD TBD

Figure 11. Histogram of a DC Input at Code Center, V_REF= 2.5 V and V_REF= 5 V

Figure 14. Histogram of a DC Input at Code Transition, V_REF= 2.5 V and V_REF= 5 V

TBD TBD

Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT),

Wide View, V_REF= 5 V

Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, V_REF= 2.5 V

TBD TBD

Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View

Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View

Rev. PrA | Page 12 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

TBD TBD

Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference

Voltage, f_IN= 1 kHz

Figure 20. THD and SFDR vs. Reference Voltage, f_IN= 1 kHz

TBD

Figure 21. THD and SFDR vs. Temperature, f_IN= 1 kHz

Figure 18. SNR, SINAD, and ENOB vs. Temperature, f_IN= 1 kHz

TBD

Figure 22. SINAD, SNR, and ENOB vs. t_QUIET2

Figure 19. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS

Rev. PrA | Page 13 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

TBD

Figure 23. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples

Averaged per Reading

Figure 26. Zero Error and Gain Error vs. Temperature

TBD TBD

Figure 24. Operating Current vs. Temperature, AD4002, 2 MSPS

Figure 27. Operating Current vs. Temperature, AD4006, 1 MSPS

TBD TBD

Figure 25. Operating Current vs. Temperature, AD4010, 500 kSPS

Figure 28. Reference Current vs. Reference Voltage

Rev. PrA | Page 14 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

TBD TBD

Figure 29. Standby Current vs. Temperature

Figure 30. t_DSDOvs. Load Capacitance

Rev. PrA | Page 15 of 36

AD4002/AD4006/AD4010

TERMINOLOGY

Preliminary Technical Data

Total Harmonic Distortion (THD)

Integral Nonlinearity Error (INL)

THD is the ratio of the rms sum of the first five harmonic

components to the rms value of a full-scale input signal and is

expressed in decibels.

INL is the deviation of each individual code from a line drawn

from negative full scale through positive full scale. The point

used as negative full scale occurs ½ LSB before the first code

transition. Positive full scale is defined as a level 1½ LSB beyond

the last code transition. The deviation is measured from the

middle of each code to the true straight line (see Figure 32).

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

the total rms noise measured. The value for dynamic range is

expressed in decibels. It is measured with a signal at −60 dBFS

so that it includes all noise sources and DNL artifacts.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the

maximum deviation from this ideal value. It is often specified in

terms of resolution for which no missing codes are guaranteed.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Zero Error

Zero error is the difference between the ideal voltage that

results in the first code transition (1/2 LSB above analog

ground) and the actual voltage producing that code.

Signal-to-Noise-and-Distortion Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components that are less than

the Nyquist frequency, including harmonics but excluding dc.

The value of SINAD is expressed in decibels.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) occurs at a level

½ LSB above nominal negative full scale (−4.999981 V for the

5 V range). The last transition (from 011 … 10 to 011 … 11)

occurs for an analog voltage 1½ LSB below the nominal full

scale (+4.999943 V for the 5 V range). The gain error is the

deviation of the difference between the actual level of the last

transition and the actual level of the first transition from the

difference between the ideal levels.

Aperture Delay

Aperture delay is the measure of the acquisition performance

and is the time between the rising edge of the CNV input and

when the input signal is held for a conversion.

Transient Response

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the root mean

square (rms) amplitude of the input signal and the peak spurious

signal.

Transient response is the time required for the ADC to acquire a

full-scale input step to 0.5 LSB accuracy.

Power Supply Rejection Ratio (PSRR)

PSRR is the ratio of the power in the ADC output at the

frequency, f, to the power of a 200 mV p-p sine wave applied to

the ADC VDD supply of frequency, f.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

input. It is related to SINAD as follows:

PSRR (dB) = 10 log(P_{VDD_IN}/P_{ADC_OUT}

)

ENOB = (SINAD_dB− 1.76)/6.02

where:

ENOB is expressed in bits.

P

_{VDD_IN}is the power at the frequency, f, at the VDD pin.

_{ADC_OUT}is the power at the frequency, f, in the ADC output.

Rev. PrA | Page 16 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

THEORY OF OPERATION

IN+

SWITCHES CONTROL

SW+

MSB

LSB

131,072C 65,536C

4C

2C

C

BUSY

REF

CONTROL

LOGIC

COMP

GND

131,072C 65,536C

MSB

OUTPUT CODE

SW–

CNV

IN–

Figure 31. ADC Simplified Schematic

frequency range up to 100 kHz. For frequencies greater than

100 kHz and multiplexing, disable high-Z mode.

CIRCUIT INFORMATION

The AD4002/AD4006/AD4010 are high speed, low power,

single-supply, precise, 18-bit pseudo differential ADCs based on

a SAR architecture.

For single-supply applications, a span compression feature

creates additional headroom and footroom for the driving

amplifier to access the full range of the ADC.

The AD4002 is capable of converting 2,000,000 samples per

second (2 MSPS), the AD4006 is capable of converting

The fast conversion time of the AD4002/AD4006/AD4010,

along with turbo mode, allows low clock rates to read back

conversions, even when running at their respective maximum

throughput rates. Note that, for the AD4002, the full throughput

rate of 2 MSPS can be achieved only with turbo mode enabled.

1,000,000 samples per second (1 MSPS), and the AD4010 is

capable of converting 500,000 samples per second (500 kSPS).

The power consumption of the AD4002/AD4006/AD4010

scales with throughput because the devices power down in

between conversions. When operating at 10 kSPS, for example,

they typically consume 70 µW, making them ideal for battery-

powered applications. The AD4002/AD4006/AD4010 also have

a valid first conversion after being powered down for long

periods, which can further reduce power consumed in applications

in which the ADC does not need to be constantly converting.

The AD4002/AD4006/AD4010 can interface with any 1.8 V to

5 V digital logic family. They are available in a 10-lead MSOP

or a tiny 10-lead LFCSP that allows space savings and flexible

configurations.

The AD4002/AD4006/AD4010 are pin for pin compatible with

some of the 14-/16-/18-/20-bit precision SAR ADCs listed in

Table 8.

The AD4002/AD4006/AD4010 provide the user with an on-

chip track-and-hold and do not exhibit any pipeline delay or

latency, making them ideal for multiplexed applications.

Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs

400 kSPS to

250 kSPS 500 kSPS

The AD4002/AD4006/AD4010 incorporate a multitude of

unique ease of use features that result in a lower system power

and footprint.

Bits 100 kSPS

≥1000 kSPS

20¹

AD4020²

18¹AD7989-1²AD7691²

AD4011²,

AD7690²,

AD7989-5²

AD4003²,

AD4007²,

AD7982²,

AD7984²

The AD4002/AD4006/AD4010 each have an internal voltage

clamp that protects the device from overvoltage damage on the

analog inputs.

18³

AD4010²

AD4002²,

AD4006²

The analog input incorporates circuitry that reduces the nonlinear

charge kickback seen from a typical switched capacitor SAR input.

This reduction in kickback, combined with a longer acquisition

phase, means reduced settling requirements on the driving

amplifier. This combination allows the use of lower bandwidth

and lower power amplifiers as drivers. It has the additional benefit

of allowing a larger resistor value in the input RC filter and a

corresponding smaller capacitor, which results in a smaller RC load

for the amplifier, improving stability and power dissipation.

16¹AD7684

AD7687²

AD7688²,

AD7693²,

AD7916²

AD4001²,

AD4005²,

AD7915²

16³AD7680,

AD7683,

AD7685², AD7686²,

AD4000²,

AD4004²,

AD7980²,

AD7983²

AD7694

AD7988-5²,

AD4008²

AD7988-1²

14³AD7940

AD7942²

AD7946²

Not applicable

¹True differential.

²Pin for pin compatible.

³Pseudo differential.

High-Z mode can be enabled via the SPI interface by programming

a register bit (see Table 14). When high-Z mode is enabled,

the ADC input has a low input charging current at low input

signal frequencies as well as improved distortion over a wide

Rev. PrA | Page 17 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

to bring the comparator back into a balanced condition. After

the completion of this process, the control logic generates the

ADC output code and a busy signal indicator.

CONVERTER OPERATION

The AD4002/AD4006/AD4010 are SAR-based ADCs using a

charge redistribution sampling digital-to-analog-converter

(DAC). Figure 31 shows the simplified schematic of the ADC.

The capacitive DAC consists of two identical arrays of 18 binary

weighted capacitors, which are connected to the comparator

inputs.

Because the AD4002/AD4006/AD4010 have on-board conversion

clocks, the serial clock, SCK, is not required for the conversion

process.

TRANSFER FUNCTIONS

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via the SW+

and SW− switches. All independent switches connect the other

terminal of each capacitor to the analog inputs. The capacitor

arrays are used as sampling capacitors and acquire the analog

signal on the IN+ and IN− inputs.

The ideal transfer characteristics for the

AD4002/AD4006/AD4010 are shown in Figure 32 and Table 9.

111...111

111...110

111...101

When the acquisition phase is complete and the CNV input

goes high, a conversion phase initiates. When the conversion

phase begins, SW+ and SW− are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the GND input. The differential voltage between the IN+ and

IN− inputs captured at the end of the acquisition phase is

applied to the comparator inputs, causing the comparator to

become unbalanced. By switching each element of the capacitor

array between GND and V_REF, the comparator input varies by

binary weighted voltage steps (V_REF/2, V_REF/4, …, V_REF/262,144).

The control logic toggles these switches, starting with the MSB,

000...010

000...001

000...000

–FSR

–FSR + 1 LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

ANALOG INPUT

–FSR + 0.5 LSB

Figure 32. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 9. Output Codes and Ideal Input Voltages

Description

FSR − 1 LSB

Midscale + 1 LSB

Midscale

Analog Input, V_REF= 5 V

4.999981 V

2.500019 V

2.5 V

V_REF= 5 V with Span Compression Enabled (V)

Digital Output Code (Hex)

0x3FFFF¹

0x20001

4.499985

2.500015

2.5

0x20000

Midscale − 1 LSB

−FSR + 1 LSB

−FSR

2.499981 V

19.07 µV

0 V

2.499985

0.50001526

0.5

0x1FFFF

0x00001

0x00000²

¹This output code is also the code for an overranged analog input (V_IN+− V_IN−above V_REFwith span compression disabled and above 0.9 × V_REFwith span compression enabled).

²This output code is also the code for an underranged analog input (V_IN+− V_IN−below 0 V with span compression disabled and below 0.1 × V_REFwith span compression enabled).

Rev. PrA | Page 18 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

APPLICATIONS INFORMATION

Figure 34 shows a recommended connection diagram when

using a single-supply system. This setup is preferable when only

a limited number of rails are available in the system and power

dissipation is of critical importance.

TYPICAL APPLICATION DIAGRAMS

Figure 33 shows an example of the recommended connection

diagram for the AD4002/AD4006/AD4010 when multiple

supplies are available. This configuration is used for best

performance because the amplifier supplies can be selected to

allow the maximum signal range.

V+ ≥ +6.5V

1

REF

LDO

1.8V

AMP

V

= V

/2

CM

REF

5V

100nF

10kΩ

10µF

100nF 1.8V TO 5V

HOST

SUPPLY

10kΩ

V+

R

V

AMP

REF

V

= V

/2

REF

VDD

VIO

SDI

CM

REF

C

0V

IN+

IN–

V–

AD4002/

AD4006/

SCK

SDO

CNV

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

2

AD4010

GND

3-WIRE/4-WIRE

INTERFACE

V– ≤ –0.5V

Figure 33. Typical Application Diagram with Multiple Supplies

V+ = 5V

1

REF

LDO

AMP

V

= V

/2

CM

REF

4.096V 1.8V

100nF 100nF

10kΩ

10µF

1.8V TO 5V

HOST

SUPPLY

1

10kΩ

R

0.9 × V

AMP

REF

V

= V

0.1 × V

/2

REF

VDD

VIO

CM

REF

C

REF

SDI

IN+

IN–

AD4002/

AD4006/

AD4010²

SCK

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

3

SDO

CNV

GND

3-WIRE/4-WIRE

INTERFACE

1

2

3

SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. C

SPAN COMPRESSION MODE ENABLED.

SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.

IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).

REF

Figure 34. Typical Application Diagram with a Single Supply

Rev. PrA | Page 19 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

The external RC filter is usually present at the ADC input

to band limit the input signal. During an overvoltage event,

excessive voltage is dropped across R_EXT, and R_EXTbecomes part

of a protection circuit. The R_EXTvalue can vary from 200 Ω to

20 kΩ for 15 V protection. The C_EXTvalue can be as low as 100 pF

for correct operation of the clamp. See Table 1 for input overvoltage

clamp specifications.

ANALOG INPUTS

Figure 35 shows an equivalent circuit of the analog input structure,

including the overvoltage clamp of the AD4002/AD4006/AD4010.

REF

D1

C

IN

R

IN

IN+

EXT

0V TO 15V

V

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these

differential inputs, signals common to both inputs are rejected.

By using IN− to sense a remote signal ground, ground potential

differences between the sensor and the local ADC ground are

eliminated.

C

D2

CLAMP

IN

GND

Figure 35. Equivalent Analog Input Circuit

Input Overvoltage Clamp Circuit

Switched Capacitor Input

Most ADC analog inputs, IN+ and IN−, have no overvoltage

protection circuitry apart from ESD protection diodes. During

an overvoltage event, an ESD protection diode from an analog

input pin (IN+ or IN−) to REF forward biases and shorts the

input pin to REF, potentially overloading the reference or

causing damage to the device. The AD4002/AD4006/AD4010

internal overvoltage clamp circuit with a larger external resistor

(R_EXT= 200 Ω) eliminates the need for external protection

diodes and protects the ADC inputs against dc overvoltages.

During the acquisition phase, the impedance of the analog

inputs (IN+ or IN−) can be modeled as a parallel combination

of Capacitor C_PINand the network formed by the series connection

of R_INand C_IN. C_PINis primarily the pin capacitance. R_INis typically

400 Ω and is a lumped component composed of serial resistors

and the on resistance of the switches. C_INis typically 40 pF and

is mainly the ADC sampling capacitor.

During the conversion phase, in which the switches are open, the

input impedance is limited to C_PIN. R_INand C_INmake a single-

pole, low-pass filter that reduces undesirable aliasing effects and

limits noise.

In applications where the amplifier rails are greater than V_REF

and less than ground, it is possible for the output to exceed

the input voltage range of the device. In this case, the AD4002/

AD4006/AD4010 internal voltage clamp circuit ensures that the

voltage on the input pin does not exceed V_REF+ 0.4 V and prevents

damage to the device by clamping the input voltage in a safe

operating range and avoiding disturbance of the reference,

which is particularly important for systems that share the

reference among multiple ADCs.

RC Filter Values

The RC filter value (represented by R and C in Figure 33 and

Figure 34) and driving amplifier can be selected depending on

the input signal bandwidth of interest at the full throughput.

Lower input signal bandwidth means that the RC cutoff can be

lower, thereby reducing noise into the converter. For optimum

performance at various throughputs, use the recommended RC

values (200 Ω, 180 pF) and the ADA4807-1.

If the analog input exceeds the reference voltage by 0.4 V, t h e

internal clamp circuit turns on and the current flows through

the clamp into ground, preventing the input from rising further

and potentially causing damage to the device. The clamp turns

on before D1 (see Figure 35) and can sink up to 50 mA of current.

The RC values shown in Table 10 are chosen for ease of drive

considerations and greater ADC input protection. The combi-

nation of a large R value (200 Ω) and small C value results in a

reduced dynamic load for the amplifier to drive. The smaller value

of C means fewer stability and phase margin concerns with the

amplifier. The large value of R limits the current into the ADC

input when the amplifier output exceeds the ADC input range.

OV

When the clamp is active, it sets the

clamp flag bit in the

register that can be read back (see Table 14), which is a sticky bit

that must be read to be cleared. The status of the clamp can also

be checked in the status bits using an overvoltage clamp flag (see

Table 15). The clamp circuit does not dissipate static power in the

off state. Note that the clamp cannot sustain the overvoltage

condition for an indefinite amount of time.

Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths

Input Signal Bandwidth (kHz)

R (Ω)

C (pF)

Recommended Amplifier

See the High-Z Mode section

ADA4807-1

ADA4897-1

<10

<200

>200

Multiplexed

200

180

120

Rev. PrA | Page 20 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

DRIVER AMPLIFIER CHOICE

Although the AD4002/AD4006/AD4010 are easy to drive, the

driver amplifier must meet the following requirements:

•

The noise generated by the driver amplifier must be kept

low enough to preserve the SNR and transition noise

performance of the AD4002/AD4006/AD4010. The noise

from the driver is filtered by the single-pole, low-pass filter

of the analog input circuit made by R_INand C_IN, or by the

external filter, if one is used. Because the typical noise of the

AD4002/AD4006/AD4010 is 30 µV rms, the SNR

degradation due to the amplifier is

TBD









Figure 36. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V,

VIO = 3.3 V, V_REF= 5 V, 25°C

(

30μV

π

2

)









SNR_LOSS= 20log

2

(

30μV

)

+

f_{−3 dB}

(

Ne_N

)

where:

_{−3 dB}is the input bandwidth, in megahertz, of the AD4002/

f

AD4006/AD4010 (10 MHz) or the cutoff frequency of the input

filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

e_Nis the equivalent input noise voltage of the op amp, in

nV/√Hz.

TBD

•

For ac applications, the driver must have a THD performance

commensurate with the AD4002/AD4006/AD4010.

For multichannel multiplexed applications, the driver

amplifier and the analog input circuit of the AD4002/

AD4006/AD4010 must settle for a full-scale step onto the

capacitor array at an 18-bit level (0.000191%, 1.91 ppm). In

the data sheet of the amplifier, settling at 0.1% to 0.01% is

more commonly specified. This settling may differ

significantly from the settling time at an 18-bit level and

must be verified prior to driver selection.

Figure 37. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V,

V_REF= 5 V, 25°C Multiplexed Applications

•

The AD4002/AD4006/AD4010 significantly reduce system

complexity and cost for multiplexed applications that require

superior performance in terms of noise, power, and throughput.

Figure 38 shows a simplified block diagram of a multiplexed

data acquisition system including a multiplexer, an ADC driver,

and the precision SAR ADC.

MULTIPLEXER

High Frequency Input Signals

R

ADC

DRIVER

SAR ADC

C

The AD4002/AD4006/AD4010 ac performance over a wide

input frequency range using a 5 V reference voltage is shown

in Figure 36 and Figure 37. Unlike other traditional SAR ADCs,

the AD4002/AD4006/AD4010 maintain exceptional ac perfor-

mance for input frequencies up to the Nyquist frequency with

minimal performance degradation. Note that the input frequency

is limited to the Nyquist frequency of the sample rate in use.

C

R

C

R

C

Figure 38. Multiplexed Data Acquisition Signal Chain Using the

AD4002/AD4006/AD4010

Rev. PrA | Page 21 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

Switching multiplexer channels typically results in large voltage

steps at the ADC inputs. To ensure an accurate conversion result,

the step must be given adequate time to settle before the ADC

samples its inputs (on the rising edge of CNV). The settling

time error is dependent on the drive circuitry (multiplexer

and ADC driver), RC filter values, and the time when the

multiplexer channels are switched. Switch the multiplexer

channels immediately after t_QUIET1has elapsed from the start

of the conversion to maximize settling time while preventing

corruption of the conversion result. To avoid conversion

corruption, do not switch the channels during the t_QUIET1time.

If the analog inputs are multiplexed during the quiet conversion

time (t_QUIET1), the current conversion may be corrupted.

TBD

Figure 40. Input Current vs. Input Differential Voltage, VDD = 1.8 V,

VIO = 3.3 V, V_REF= 5 V, 25°C

EASE OF DRIVE FEATURES

To achieve the optimum data sheet performance from high

resolution precision SAR ADCs, system designers are often

forced to use a dedicated high power, high speed amplifier to

drive the traditional switched capacitor SAR ADC inputs for

their precision applications, which is commonly encountered in

designing a precision data acquisition signal chain. The benefits

of high-Z mode are low input current for slow (<10 kHz) or dc

type signals and improved distortion (THD) performance over

a frequency range of up to 100 kHz. High-Z mode allows a

choice of lower power and lower bandwidth precision

amplifiers with a lower RC filter cutoff to drive the ADC,

removing the need for dedicated high speed ADC drivers,

which saves system power, size, and cost in precision, low

bandwidth applications. High-Z mode allows the amplifier and

RC filter in front of the ADC to be chosen based on the signal

bandwidth of interest and not based on the settling requirements of

the switched capacitor SAR ADC inputs.

Input Span Compression

In single-supply applications, it is desirable to use the full range

of the ADC; however, the amplifier can have some headroom

and footroom requirements, which can be a problem, even if it

is a rail-to-rail input and output amplifier. The AD4002/AD4006/

AD4010 include a span compression feature, which increases

the headroom and footroom available to the amplifier by reducing

the input range by 10% from the top and bottom of the range

while still accessing all available ADC codes (see Figure 39). The

SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the

reduced input range when span compression is enabled. Span

compression is disabled by default but can be enabled by writing

to the relevant register bit (see the Digital Interface section).

90% OF V

= 3.69V

REF

DIGITAL OUTPUT

+FSR

5V

V

= 4.096V

REF

10% OF V

= 0.41V

REF

N

ALL 2

CODES

ADC

Additionally, the AD4002/AD4006/AD4010 can be driven with

a much higher source impedance than traditional SARs, which

means the resistor in the RC filter can have a value 10 times larger

than previous SAR designs and with high-Z mode enabled can

tolerate even larger impedance. Figure 41 shows the THD

performance for various source impedances with high-Z mode

disabled and enabled.

IN+

ANALOG

INPUT

–FSR

Figure 39. Span Compression

High-Z Mode

The AD4002/AD4006/AD4010 incorporate high-Z mode,

which reduces the nonlinear charge kickback when the capacitor

DAC switches back to the input at the start of acquisition. Figure 40

shows the input current of the AD4002/AD4006/AD4010 with

high-Z mode enabled and disabled. The low input current makes

the ADC easier to drive than the traditional SAR ADCs available

in the market, even with high-Z mode disabled. The input current

reduces further to submicroampere range when high-Z mode is

enabled. The high-Z mode is disabled by default but can be

enabled by writing to the register (see Table 14). Disable high-Z

mode for input frequencies above 100 kHz or when multiplexing.

TBD

Figure 41. THD vs. Input Frequency for Various Source Impedances,

VDD = 1.8 V, VIO = 3.3 V, V_REF= 5 V, 25°C

Rev. PrA | Page 22 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

Figure 42 and Figure 43 show the AD4002/AD4006/AD4010

SNR and THD performance using the ADA4077-1 (supply

Long Acquisition Phase

The AD4002/AD4006/AD4010 also feature a very fast

current per amplifier (I_SY) = 400 µA), and ADA4610-1 (I_SY

=

conversion time of 290 ns, which results in a long acquisition

phase. The acquisition is further extended by a key feature of

the AD4002/AD4006/AD4010: the ADC returns to the

acquisition phase typically 100 ns before the end of the conversion.

This feature provides an even longer time for the ADC to acquire

the new input voltage. A longer acquisition phase reduces the

settling requirement on the driving amplifier, and a lower power/

bandwidth amplifier can be chosen. The longer acquisition

phase means that a lower RC filter (represented by R and C in

Figure 33 and Figure 34) cutoff can be used, which means a

noisier amplifier can also be tolerated. A larger value of R can

be used in the RC filter with a corresponding smaller value of C,

reducing amplifier stability concerns without affecting distortion

performance significantly. A larger value of R also results in

reduced dynamic power dissipation in the amplifier.

1.50 mA) precision amplifiers when driving the AD4002/AD4006/

AD4010 at full throughput for high-Z mode both enabled and

disabled with various RC filter values. These amplifiers achieve

TBD dB to TBD dB typical SNR and close to TBD dB typical

TBD with high-Z enabled for a 2.27 MHz RC bandwidth. THD

is approximately TBD dB better with high-Z mode enabled,

even for large R values greater than 200 Ω. SNR maintains close

to TBD dB even with a very low RC filter cutoff.

When high-Z mode is enabled, the ADC consumes approximately

2 mW per MSPS extra power; however, this is still significantly

lower than using dedicated ADC drivers like the ADA4807-1.

For any system, the front end usually limits the overall ac/dc

performance of the signal chain. It is evident from the data

sheets of the selected precision amplifiers shown in Figure 42

and Figure 43 that their own noise and distortion performance

dominates the SNR and THD specification at a certain input

frequency.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such as

the ADR4550. Use a low power reference such as the ADR3450

at the expense of a slight decrease in the noise performance. It is

recommended to use a reference buffer such as the ADA4807-1

between the reference and the ADC reference input. It is important

to consider the optimum capacitance necessary to keep the

reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section (that is, a 10 µF

ceramic chip capacitor, C_REF).

TBD

POWER SUPPLY

Figure 42. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,

f_IN= 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, V_REF= 5 V, 25°C

The AD4002/AD4006/AD4010 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and 5.5 V.

To reduce the number of supplies needed, VIO and VDD can be

tied together for 1.8 V operation. The ADP7118 low noise,

CMOS, low dropout (LDO) linear regulator is recommended to

power the VDD and VIO pins. The AD4002/AD4006/AD4010

are independent of power supply sequencing between VIO and

VDD. Additionally, the AD4002/AD4006/AD4010 are insensitive

to power supply variations over a wide frequency range, as

shown in Figure 44.

TBD

Figure 43. THD vs. RC Bandwidths for Various Precision ADC Drivers,

f_IN= 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V,

VIO = 3.3 V, V_REF= 5 V, 25°C

Rev. PrA | Page 23 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

The mode in which the device operates depends on the SDI

CS

level when the CNV rising edge occurs.

mode is selected if

SDI is high, and daisy-chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, daisy-chain mode is always selected.

In either 3-wire or 4-wire mode, the AD4002/AD4006/AD4010

offer the option of forcing a start bit in front of the data bits.

This start bit can be used as a busy signal indicator to interrupt

the digital host and trigger the data reading. Otherwise, without a

busy indicator, the user must time out the maximum conversion

time prior to readback.

TBD

CS

The busy indicator feature is enabled in

is low when the ADC conversion ends.

mode if CNV or SDI

Figure 44. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, V_REF= 5 V, 25°C

The AD4002/AD4006/AD4010 power down automatically at

the end of each conversion phase; therefore, the power scales

linearly with the sampling rate. This feature makes the device

ideal for low sampling rates (even a few samples per second)

and battery-powered applications. Figure 45 shows the AD4002/

AD4006/AD4010 total power dissipation and individual power

dissipation for each rail.

The state of SDO on power-up is either low or high-Z, depending

on the states of CNV and SDI, as shown in in Table 11.

Table 11. State of SDO on Power-Up

CNV

SDI

SDO

Low

High-Z

0

1

0

1

0

1

The AD4002/AD4006/AD4010 have turbo mode capability in

both 3-wire and 4-wire mode. Turbo mode is enabled by writing

to the configuration register and replaces the busy indicator

feature when enabled. Turbo mode allows a slower SPI clock rate,

making interfacing simpler. The maximum throughput of

2 MSPS for the AD4002 can be achieved only with turbo mode

enabled and a minimum SCK rate of 75 MHz.

TBD

The SCK rate must be sufficiently fast to ensure the conversion

result is clocked out before another conversion is initiated. The

minimum required SCK rate for an application can be derived

based on the sample period (t_CYC), the number of bits that must

be read (including data and optional status bits), and which

digital interface mode is used. Timing diagrams and explanations

for each digital interface mode are given in the digital modes of

Figure 45. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V,

V

_REF= 5 V, 25°C

DIGITAL INTERFACE

Although the AD4002/AD4006/AD4010 have a reduced

number of pins, they offer flexibility in their serial interface

modes. The AD4002/AD4006/AD4010 can also be programmed

via 16-bit SPI writes to the configuration registers.

CS

operation sections (see the

Mode, 3-Wire Turbo Mode

section through the Daisy-Chain Mode section).

Status bits can also be clocked out at the end of the conversion

data if the status bits are enabled in the configuration register.

There are six status bits in total, as shown in Table 15.

CS

When in

mode, the AD4002/AD4006/AD4010 are compatible

with SPI, QSPI™, MICROWIRE®, digital hosts, and digital signal

processors (DSPs). In this mode, the AD4002/AD4006/AD4010

can use either a 3-wire or 4-wire interface. A 3-wire interface

using the CNV, SCK, and SDO signals minimizes wiring con-

nections, which is useful, for instance, in isolated applications.

A 4-wire interface using the SDI, CNV, SCK, and SDO signals

allows CNV, which initiates the conversions, to be independent of

the readback timing (SDI). This interface is useful in low jitter

sampling or simultaneous sampling applications.

The AD4002/AD4006/AD4010 are configured by 16-bit SPI

writes to the desired configuration register. The 16-bit word can

be written via the SDI line while CNV is held low. The 16-bit

word consists of an 8-bit header and 8-bit register data. For

isolated systems, the ADuM141D is recommended, which can

support the 75 MHz SCK rate required to run the AD4002 at its

full throughput of 2 MSPS.

The AD4002/AD4006/AD4010 provide a daisy-chain feature

using the SDI input for cascading multiple ADCs on a single

data line, similar to a shift register.

Rev. PrA | Page 24 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

All register read/writes must occur while CNV is low. Data on

SDI is clocked in on the rising edge of SCK. Data on SDO is

clocked out on the falling edge of SCK. At the end of the data

transfer, SDO is put in a high impedance state on the rising

edge of CNV if daisy-chain mode is not enabled. If daisy-chain

mode is enabled, SDO goes low on the rising edge of CNV.

Register reads are not allowed in daisy-chain mode.

REGISTER READ/WRITE FUNCTIONALITY

The AD4002/AD4006/AD4010 register bits are programmable

and their default statuses are shown in Table 12. The register map

OV

is shown in Table 14. The overvoltage clamp flag ( ) is a read

only sticky bit, and it is cleared only if the register is read and the

overvoltage condition is no longer present. It gives an indication

of overvoltage condition when it is set to 0.

A register write requires three signal lines: SCK, CNV, and SDI.

During a register write, to read the current conversion results

on SDO, the CNV pin must be brought low after the conversion

is completed; otherwise, the conversion results may be incorrect

on SDO. However, the register write occurs regardless.

Table 12. Register Bits

Register Bits

Default Status

Overvoltage (OV) Clamp Flag

Span Compression

High-Z Mode

Turbo Mode

Enable Six Status Bits

1 bit, 1 = inactive (default)

1 bit, 0 = disabled (default)

The LSB of each configuration register is reserved because a

user reading 16-bit conversion data may be limited to a 16-bit

SPI frame. The state of SDI on the last bit in the SDI frame may

be the state that then persists when CNV rises. Because interface

mode is partly set based on the SDI state when CNV rises, in

this scenario, the user may need to set the final SDI state.

All access to the register map must start with a write to the 8-bit

command register in the SPI interface block. The AD4002/

AD4006/AD4010 ignore all 1s until the first 0 is clocked in; the

value loaded into the command register is always a 0 followed

by seven command bits. This command determines whether

that operation is a write or a read. The AD4002/AD4006/

AD4010 command register is shown in Table 13.

The timing diagrams in Figure 46 through Figure 48 show how

data is read and written when the AD4002/AD4006/AD4010

are configured in register read, write, and daisy-chain mode.

Table 13. Command Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WEN

R/W

0

1

0

1

0

Table 14. Register Map

ADDR[1:0] Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x0

Reserved Reserved Reserved Enable six Span

status bits compression

High-Z mode Turbo

mode

Overvoltage (OV) clamp

flag (read only sticky bit)

0xE1

t_CYC

t_CNVH

t_SCK

CNV

SCK

t_SCNVSCK

t_SCKL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

t_HSDISCK

t_SSDISCK

t_SCKH

ADDR[1:0]

SDI

1

0

1

WEN

0

R/W

1

0

1

t_HSDO

t_DSDO

t_EN

t_DIS

D16

B3

SDO

D17

D13

D12

D15

D14

D11

D10

B7

B6

B5

B4

B2

B1

B0

X

Figure 46. Register Read Timing Diagram (X Means Don’t Care)

Rev. PrA | Page 25 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

t_CYC

t_SCK

1

t_CNVH

t_HCNVSCK

CNV

t_SCNVSCK

t_SCKL

SCK

SDI

1

2

3

4

5

9

10

11

12

13

14

15

16

17

18

t_HSDISCK

t_SCKH

t_SSDISCK

1

WEN

R/W

0

1

0

1

ADDR[1:0]

B7

B6

B5

B4

B3

B2

B1

B0

0

1

0

t_HSDO

t_DSDO

t_EN

D8

D7

SDO

1

D17

D16

D15

D14

D13

D12

D11

D10

D9

D6

D5

D4

D3

D2

D1

D0

CONVERSION RESULT ON D17:0

THE USER MUST WAIT t_CONVTIME WHEN READING BACK THE CONVERSION RESULT AND DOING A REGISTER WRITE AT THE SAME TIME.

Figure 47. Register Write Timing Diagram

t_CYC

t_SCK

t_CNVH

CNV

SCK

t_SCNVSCK

t_SCKL

1

24

t_SCKH

SDI

A

0

COMMAND (0x14)

DATA (0xAB)

SDO /SDI

A

B

0

COMMAND (0x14)

DATA (0xAB)

0

t_DIS

SDO

0

COMMAND (0x14)

0

Figure 48. Register Write Timing Diagram, Daisy-Chain Mode

Rev. PrA | Page 26 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

The SDO line goes to high-Z after the sixth status bit is clocked

out (except in daisy-chain mode). The user is not required to

clock out all status bits to start the next conversion. The serial

STATUS WORD

The 6-bit status word can be appended to the end of a conversion

result, and the default conditions of these bits are shown in

Table 15. The status bits must be enabled in the register setting.

CS

interface timing for

mode, 3-wire without busy indicator,

including status bits, is shown in Figure 49.

OV

When the overvoltage clamp flag ( ) is a 0, it indicates an

overvoltage condition. The overvoltage clamp flag status bit

updates on a per conversion basis.

Table 15. Status Bits (Default Conditions)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Overvoltage (OV) clamp flag

Span compression

High-Z mode

Turbo mode

Reserved

SDI = 1

t_CYC

t_CNVH

CNV

ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_SCK

t_QUIET2

t_SCKL

SCK

22

23

24

18

1

2

3

16

t_SCKH

17

t

HSDO

t_EN

t_DSDO

D15

t_DIS

SDO

D17

D16

D1

D0

b1

b0

STATUS BITS B[5:0]

CS

Figure 49. Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)

Rev. PrA | Page 27 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

This mode replaces the 3-wire with busy indicator mode by

programming the turbo mode bit, Bit 1 (see Table 14).

CS MODE, 3-WIRE TURBO MODE

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host. It

provides additional time during the end of the ADC conversion

process to clock out the previous conversion result, providing a

lower SCK rate. The AD4002 can achieve a throughput rate of

2 MSPS only when turbo mode is enabled and using a minimum

SCK rate of 75 MHz. With turbo mode enabled, the AD4006 can

also achieve its maximum throughput rate of 1 MSPS with a

minimum SCK rate of 25 MHz, and the AD4010 can achieve its

maximum throughput rate of 500 kSPS with a minimum SCK rate

of 11 MHz. The connection diagram is shown in Figure 50, and

the corresponding timing diagram is shown in Figure 51.

When SDI is forced high, a rising edge on CNV initiates a

conversion. The previous conversion data is available to read

after the CNV rising edge. The user must wait t_QUIET1time after

CNV is brought high before bringing CNV low to clock out the

previous conversion result. The user must also wait t_QUIET2time

after the last falling edge of SCK to when CNV is brought high.

When the conversion is complete, the AD4002/AD4006/AD4010

enter the acquisition phase and power down. When CNV goes

low, the MSB is output to SDO. The remaining data bits are

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data,

a digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18^thSCK

falling edge or when CNV goes high (whichever occurs first),

SDO returns to high impedance.

CONVERT

DIGITAL HOST

CNV

VIO

AD4002/

AD4006/

AD4010

SDI

SDO

DATA IN

SCK

CLK

CS

Figure 50. Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)

SDI = 1

t_CYC

CNV

t

ACQ

ACQUISITION

CONVERSION

CONV

ACQUISITION

t_SCK

t_SCKL

QUIET2

t_QUIET1

SCK

SDO

1

2

3

16

17

18

t_SCKH

t_HSDO

t_EN

t_DSDO

t_DIS

D17

D16

D15

D1

D0

CS

Figure 51. Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)

Rev. PrA | Page 28 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

CS

selects the

mode, and forces SDO to high impedance. After a

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

conversion is initiated, it continues until completion irrespective of

the state of CNV. This feature can be useful, for instance, to bring

CNV low to select other SPI devices, such as analog multiplexers;

however, CNV must be returned high before the minimum

conversion time elapses and then held high for the maximum

possible conversion time to avoid the generation of the busy

signal indicator.

The connection diagram is shown in Figure 52, and the

corresponding timing diagram is shown in Figure 53.

CONVERT

DIGITAL HOST

CNV

VIO

When the conversion is complete, the AD4002/AD4006/AD4010

enter the acquisition phase and power down. When CNV goes

low, the MSB is output onto SDO. The remaining data bits are

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data,

a digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18^thSCK

falling edge or when CNV goes high (whichever occurs first),

SDO returns to high impedance.

AD4002/

AD4006/

AD4010

SDI

SDO

DATA IN

SCK

CLK

CS

Figure 52. Mode, 3-Wire Without Busy Indicator Connection Diagram

(SDI High)

There must not be any digital activity on SCK during the

conversion.

SDI = 1

t_CYC

t_CNVH

CNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_SCK

t_SCKL

t_QUIET2

SCK

1

2

3

16

17

18

t_SCKH

HSDO

t_EN

t_DSDO

t_DIS

SDO

D17

D16

D15

D1

D0

CS

Figure 53. Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)

Rev. PrA | Page 29 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

When the conversion is complete, SDO goes from high impedance

to low impedance. With a pull-up resistor of 1 kΩ on the SDO

line, this transition can be used as an interrupt signal to initiate

the data reading controlled by the digital host. The AD4002/

AD4006/AD4010 then enter the acquisition phase and power

down. The data bits are then clocked out, MSB first, by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital

host using the SCK falling edge allows a faster reading rate,

provided it has an acceptable hold time. After the optional 19^th

SCK falling edge or when CNV goes high (whichever occurs

first), SDO returns to high impedance.

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host

IRQ

with an interrupt input (

).

The connection diagram is shown in Figure 54, and the

corresponding timing diagram is shown in Figure 55.

CONVERT

VIO

DIGITAL HOST

CNV

VIO

1kΩ

AD4002/

AD4006/

AD4010

SDO

DATA IN

SDI

If multiple AD4002/AD4006/AD4010 devices are selected at the

same time, the SDO output pin handles this contention without

damage or induced latch-up. Meanwhile, it is recommended to

keep this contention as short as possible to limit extra power

dissipation.

IRQ

SCK

CLK

CS

Figure 54. Mode, 3-Wire with Busy Indicator Connection Diagram

(SDI High)

There must not be any digital activity on the SCK during the

conversion.

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

CS

selects the

mode, and forces SDO to high impedance. SDO

is maintained in high impedance until the completion of the

conversion, irrespective of the state of CNV. Prior to the minimum

conversion time, CNV can select other SPI devices, such as analog

multiplexers; however, CNV must be returned low before the

minimum conversion time elapses and then held low for the

maximum possible conversion time to guarantee the generation

of the busy signal indicator.

SDI = 1

t_CYC

t_CNVH

CNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_SCK

t_SCKL

t_QUIET2

SCK

1

2

3

17

18

19

t_HSDO

t_SCKH

t_DSDO

t_DIS

SDO

D17

D16

D1

D0

CS

Figure 55. Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)

Rev. PrA | Page 30 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

This mode replaces the 4-wire with busy indicator mode by

programming the turbo mode bit, Bit 1 (see Table 14).

CS MODE, 4-WIRE TURBO MODE

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host.

It provides additional time during the end of the ADC conversion

process to clock out the previous conversion result, giving a

lower SCK rate. The AD4002 can achieve a throughput rate of

2 MSPS only when turbo mode is enabled and using a minimum

SCK rate of 75 MHz. With turbo mode enabled, the AD4006

can also achieve its maximum throughput rate of 1 MSPS with a

minimum SCK rate of 25 MHz, and the AD4010 can achieve its

maximum throughput rate of 500 kSPS with a minimum SCK

rate of 11 MHz.

With SDI high, a rising edge on CNV initiates a conversion.

The previous conversion data is available to read after the CNV

rising edge. The user must wait t_QUIET1time after CNV is

brought high before bringing SDI low to clock out the previous

conversion result. The user must also wait t_QUIET2time after the

last falling edge of SCK to when CNV is brought high.

When the conversion is complete, the AD4002/AD4006/AD4010

enter the acquisition phase and power down. The ADC result

can be read by bringing its SDI input low, which consequently

outputs the MSB onto SDO. The remaining data bits are then

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data, a

digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18^thSCK

falling edge or when SDI goes high (whichever occurs first),

SDO returns to high impedance.

The connection diagram is shown in Figure 56, and the

corresponding timing diagram is shown in Figure 57.

CS1

CONVERT

VIO

DIGITAL HOST

CNV

1kΩ

AD4002/

AD4006/

AD4010

SDI

SDO

DATA IN

IRQ

SCK

CLK

CS

Figure 56. Mode, 4-Wire Turbo Mode Connection Diagram

CNV

t_CYC

t_SSDICNV

SDI

t_HSDICNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_SCK

t_SCKL

t_QUIET2

t_QUIET1

SCK

1

2

3

16

17

18

t_HSDO

t_SCKH

t_DIS

t_EN

t_DSDO

SDO

D17

D16

D15

D1

D0

CS

Figure 57. Mode, 4-Wire Turbo Mode Timing Diagram

Rev. PrA | Page 31 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

time elapses and then held high for the maximum possible

conversion time to avoid the generation of the busy signal

indicator.

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is typically used when multiple AD4002/AD4006/

AD4010 devices are connected to an SPI-compatible digital host.

When the conversion is complete, the AD4002/AD4006/AD4010

enter the acquisition phase and power down. Each ADC result

can be read by bringing its SDI input low, which consequently

outputs the MSB onto SDO. The remaining data bits are then

clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can capture the data, a

digital host using the SCK falling edge allows a faster reading

rate, provided it has an acceptable hold time. After the 18^thSCK

falling edge or when SDI goes high (whichever occurs first),

SDO returns to high impedance and another AD4002/AD4006/

AD4010 can be read.

A connection diagram example using two AD4002/AD4006/

AD4010 devices is shown in Figure 58, and the corresponding

timing diagram is shown in Figure 59.

With SDI high, a rising edge on CNV initiates a conversion,

CS

selects the

mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data read back. If SDI and CNV are low, SDO is

driven low. Prior to the minimum conversion time, SDI can

select other SPI devices, such as analog multiplexers; however,

SDI must be returned high before the minimum conversion

CS2

CS1

CONVERT

CNV

AD4002/

AD4006/

AD4002/

AD4006/

AD4010

DEVICE B

DIGITAL HOST

SDI

SDO

SDI

SDO

AD4010

DEVICE A

SCK

DATA IN

CLK

CS

Figure 58. Mode, 4-Wire Without Busy Indicator Connection Diagram

CYC

CNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_QUIET2

t_SSDICNV

SDI (CS1)

t_HSDICNV

SDI (CS2)

t_SCK

t_SCKL

SCK

1

2

3

16

17

18

19

20

34

35

36

t_HSDO

t

SCKH

t_DSDO

t_DIS

t_EN

SDO

D17

D16

D15

D1

D0

D17

D16

D1

D0

CS

Figure 59. Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram

Rev. PrA | Page 32 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

With SDI high, a rising edge on CNV initiates a conversion,

CS MODE, 4-WIRE WITH BUSY INDICATOR

CS

selects the

mode, and forces SDO to high impedance. In this

This mode is typically used when a single AD4002/AD4006/

AD4010 device is connected to an SPI-compatible digital host

mode, CNV must be held high during the conversion phase and

the subsequent data read back. If SDI and CNV are low, SDO is

driven low. Prior to the minimum conversion time, SDI can

select other SPI devices, such as analog multiplexers; however,

SDI must be returned low before the minimum conversion time

elapses and then held low for the maximum possible conversion

time to guarantee the generation of the busy signal indicator.

IRQ

with an interrupt input (

), and when it is desired to keep

CNV, which samples the analog input, independent of the signal

used to select the data reading. This independence is particularly

important in applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 60, and the

corresponding timing diagram is shown in Figure 61.

When the conversion is complete, SDO goes from high impedance

to low impedance. With a pull-up resistor of 1 kΩ on the SDO

line, this transition can be used as an interrupt signal to initiate

the data readback controlled by the digital host. The AD4002/

AD4006/AD4010 then enter the acquisition phase and power

down. The data bits are then clocked out, MSB first, by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital

host using the SCK falling edge allows a faster reading rate,

provided it has an acceptable hold time. After the optional 19^th

SCK falling edge or when SDI goes high (whichever occurs

first), SDO returns to high impedance.

CS1

CONVERT

VIO

DIGITAL HOST

CNV

1kΩ

AD4002/

AD4006/

AD4010

SDI

SDO

DATA IN

IRQ

SCK

CLK

CS

Figure 60. Mode, 4-Wire with Busy Indicator Connection Diagram

t_CYC

CNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_QUIET2

t_SSDICNV

SDI

t_SCK

t_HSDICNV

t_SCKL

SCK

SDO

1

2

3

17

18

19

t_SCKH

t_HSDO

t_DSDO

t_DIS

t_EN

D17

D16

D1

D0

CS

Figure 61. Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram

Rev. PrA | Page 33 of 36

AD4002/AD4006/AD4010

Preliminary Technical Data

the daisy-chain outputs its data MSB first, and 18 × N clocks are

required to read back the N ADCs. The data is valid on both

SCK edges. The maximum conversion rate is reduced because of

the total readback time.

DAISY-CHAIN MODE

Use this mode to daisy-chain multiple AD4002/AD4006/AD4010

devices on a 3-wire or 4-wire serial interface. This feature is

useful for reducing component count and wiring connections,

for example, in isolated multiconverter applications or for

systems with a limited interfacing capacity. Data read back is

analogous to clocking a shift register.

It is possible to write to each ADC register in daisy-chain mode.

The timing diagram is shown in Figure 48. This mode requires

4-wire operation because data is clocked in on the SDI line with

CNV held low. The same command byte and register data can

be shifted through the entire chain to program all ADCs in the

chain with the same register contents, which requires 8 × (N + 1)

clocks for N ADCs. It is possible to write different register contents

to each ADC in the chain by writing to the furthest ADC in the

chain, first using 8 × (N + 1) clocks, and then the second furthest

ADC with 8 × N clocks, and so forth until reaching the nearest

ADC in the chain, which requires 16 clocks for the command

and register data. It is not possible to read register contents in

daisy-chain mode; however, the six status bits can be enabled if

the user wants to determine the ADC configuration. Note that

enabling the status bits requires six extra clocks to clock out the

ADC result and the status bits per ADC in the chain. Turbo

mode cannot be used in daisy-chain mode.

A connection diagram example using two AD4002/AD4006/

AD4010 devices is shown in Figure 62, and the corresponding

timing diagram is shown in Figure 63.

When SDI and CNV are low, SDO is driven low. With SCK low,

a rising edge on CNV initiates a conversion, selects daisy-chain

mode, and disables the busy indicator. In this mode, CNV is

held high during the conversion phase and the subsequent data

readback.

When the conversion is complete, the MSB is output onto SDO

and the AD4002/AD4006/AD4010 enter the acquisition phase

and power down. The remaining data bits stored in the internal

shift register are clocked out of SDO by subsequent SCK falling

edges. For each ADC, SDI feeds the input of the internal shift

register and is clocked by the SCK rising edges. Each ADC in

CONVERT

CNV

DIGITAL HOST

DATA IN

AD4002/

AD4006/

AD4010

DEVICE A

SCK

AD4002/

AD4006/

AD4010

SDI

SDO

SDI

SDO

DEVICE B

SCK

CLK

Figure 62. Daisy-Chain Mode, Connection Diagram

SDI = 0

A

t_CYC

CNV

t_ACQ

ACQUISITION

CONVERSION

t_CONV

ACQUISITION

t_SCK

t_SCKL

t_QUIET2

t

QUIET2

SCK

1

2

3

16

17

D

18

19

20

34

35

36

t_SSDISCK

t_SCKH

t_HSCKCNV

t_HSDISCK

t_EN

D

17

D

16

D

15

1

D

0

SDO = SDI

A

B

t_HSDO

t_DIS

t

DSDO

D

17

D

16

D

1

D 0

A

D

16

D

0

SDO

B

A

B

Figure 63. Daisy-Chain Mode, Serial Interface Timing Diagram

Rev. PrA | Page 34 of 36

Preliminary Technical Data

AD4002/AD4006/AD4010

LAYOUT GUIDELINES

EVALUATING THE AD4002/AD4006/AD4010

PERFORMANCE

The PCB that houses the AD4002/AD4006/AD4010 must be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. The pinout of the

AD4002/AD4006/AD4010, with its analog signals on the left

side and its digital signals on the right side, eases this task.

Other recommended layouts for the AD4002/AD4006/AD4010

are outlined in the user guide of the evaluation board for the

AD4002 (EVAL-AD4002FMCZ). The evaluation board package

includes a fully assembled and tested evaluation board with the

AD4002, documentation, and software for controlling the board

from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4002FMCZ

can also be used to evaluate the AD4006/AD4010 by limiting the

throughput to 1 MSPS/500 kSPS in its software (see UG-1042).

Avoid running digital lines under the device because they

couple noise onto the die, unless a ground plane under the

AD4002/AD4006/AD4010 is used as a shield. Fast switching

signals, such as CNV or clocks, must not run near analog signal

paths. Avoid crossover of digital and analog signals.

At least one ground plane must be used. It can be common or

split between the digital and analog sections. In the latter case,

join the planes underneath the AD4002/AD4006/AD4010

devices.

The AD4002/AD4006/AD4010 voltage reference input (REF)

has a dynamic input impedance. Decouple the REF pin with

minimal parasitic inductances by placing the reference

decoupling ceramic capacitor close to (ideally right up against)

the REF and GND pins and connect them with wide, low

impedance traces.

Finally, decouple the VDD and VIO power supplies of the

AD4002/AD4006/AD4010 with ceramic capacitors, typically

0.1 μF, placed close to the AD4002/AD4006/AD4010 and

connected using short, wide traces to provide low impedance

paths and to reduce the effect of glitches on the power supply

lines.

Figure 64. Example Layout of the AD4002 (Top Layer)

An example of the AD4002 layout following these rules is

shown in Figure 64 and Figure 65. Note that the AD4006/

AD4010 layout is equivalent to the AD4002 layout.

Figure 65. Example Layout of the AD4002 (Bottom Layer)

Rev. PrA | Page 35 of 36

AD4002/AD4006/AD4010

OUTLINE DIMENSIONS

Preliminary Technical Data

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 66. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

DETAIL A

(JEDEC 95)

2.48

2.38

2.23

3.10

3.00 SQ

0.50 BSC

2.90

10

6

PIN 1 INDEX

AREA

EXPOSED

PAD

1.74

1.64

1.49

0.50

0.40

0.30

0.20 MIN

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

1

5

BOTTOM VIEW

TOP VIEW

SIDE VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 67. 10-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height

(CP-10-9)

Dimensions shown in millimeters

registered trademarks are the property of their respective owners.

D16233-0-9/17(PrA)

Rev. PrA | Page 36 of 36


型号：	AD4002
厂家：	ADI
描述：	Precision, Pseudo Differential, SAR ADCs
文件：	总36页 (文件大小：599K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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