AD4134_技术文档

Data Sheet

AD4134

24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC

► Crosstalk: 130.7 dBFS

FEATURES

► Daisy-chaining

► Alias free: inherent antialias rejection high performance mode

102.5 dB, typical

► Excellent ac and dc performance

► CRC error checking on data and SPI

► Two power modes: high performance mode and low power mode

► Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95 V

► 1.8 V IOVDD level

► 108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical

► 137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical

► THD: −120 dB typical with 1 kHz input tone

► Offset error drift: 0.9 µV/°C typical

► Gain drift: 2 ppm/°C typical

► INL: ±2 ppm of FSR typical

► Dynamic range enhancement: 4:1 and 2:1 averaging mode

► 126 dB, A weighted dynamic range

► Resistive ADC and reference input

► Easy to sync: asynchronous sample rate converter

► Multidevice synchronization with one signal line

► External reference: 4.096 V or 5 V

► Crystal or external CMOS clock of 48 MHz

► SPI or pin (standalone) configurable operation

► Operating temperature range: −40°C to +105°C

► Available in 8 mm × 8 mm, 56-lead LFCSP with exposed pad

APPLICATIONS

► Electrical test and measurement

► Audio test

► 3-phase power quality analysis

► Control and hardware in loop verification

► Sonars

► Programmable data rates from 0.01 kSPS to 1496 kSPS with

resolution of 0.01 SPS

► Option to control output data rate by external signal

► Condition monitoring for predictive maintenance

► Acoustic and material science research and development

► Linear phase digital filter options

► Low ripple FIR filter: 32 µdB pass-band ripple, dc to 161.942

kHz

► Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz

► Sinc3 filter with 50 Hz/60 Hz rejection

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

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TECHNICAL SUPPORT

Data Sheet

AD4134

TABLE OF CONTENTS

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................3

Specifications........................................................ 4

Timing Specifications....................................... 10

Absolute Maximum Ratings.................................13

Thermal Resistance......................................... 13

ESD Caution.....................................................13

Pin Configuration and Function Descriptions...... 14

Typical Performance Characteristics...................18

Terminology......................................................... 27

Theory of Operation.............................................29

Continuous Time Sigma-Delta Modulator........ 29

Easy to Drive Input and Reference ................. 29

Inherent Antialiasing Filter (AAF)..................... 30

Analog Front-End Design Simplification...........31

Noise Performance and Resolution.....................32

Circuit Information............................................... 36

Core Signal Chain............................................ 36

Analog Inputs................................................... 36

VCM Output......................................................36

Reference Input................................................37

Clock Input....................................................... 37

XCLKOUT Output.............................................37

Power Options..................................................38

Reset................................................................38

Asynchronous Sample Rate Converter............38

Digital Filters.....................................................41

Quick Start Guide................................................ 44

Standalone Mode............................................. 45

Low Latency Synchronous Data Acquisition.... 45

Device Control.....................................................46

Pin Control Mode..............................................46

SPI Control Mode.............................................47

Multifunction Pins............................................. 47

Device Configuration........................................... 48

Programming Output Data Rate and Clock......48

Programming Digital Filter................................52

Programming Data Interface............................ 53

Power Modes................................................... 55

Inherent Antialiasing Filter Modes....................55

Dynamic Range Enhancement, Channel

Averaging...........................................................56

Calibration........................................................... 57

Offset Calibration..............................................57

Gain Calibration................................................57

Applications Information...................................... 58

Power Supply................................................... 58

Reference Noise Filtering.................................59

Multidevice Synchronization.............................60

Coherent Sampling...........................................60

Low Latency Digital Control Loop.....................60

Automatic Gain Control.................................... 60

Front-End Design Examples............................ 61

Digital Interface....................................................63

SPI....................................................................63

Data Interface...................................................65

Minimum I/O Mode...........................................69

Diagnostics..........................................................70

Internal Fuse Integrity Check........................... 70

Analog Input Overrange................................... 71

MCLK Counter..................................................71

SPI Monitoring..................................................71

Memory Map Integrity Check........................... 71

ODR Input Frequency Check........................... 71

Digital Filter Overflow and Underflow...............72

DCLK Error.......................................................72

GPIO Functionality.............................................. 73

Pin Error Reporting...........................................73

Register Map (SPI Control)................................. 74

Register Details................................................... 77

Outline Dimensions............................................. 92

Ordering Guide.................................................92

Evaluation Boards............................................ 92

REVISION HISTORY

11/2021—Revision 0: Initial Version

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Data Sheet

AD4134

GENERAL DESCRIPTION

The AD4134 is a quad channel, low noise, simultaneous sampling,

precision analog-to-digital converter (ADC) that delivers on func-

tionality, performance, and ease of use.

system because it no longer requires a high frequency, low jitter

master clock from the digital back end to be routed to each ADC.

The ASRC acts as a digital filter and decimates the oversampled

data from the Σ-Δ modulator to a lower rate to favor higher preci-

sion. The ADC data is then further processed by one of the AD4134

user-selectable digital filter profiles to further reject the out of band

signals and noises, and reduce the data rate to the final desired

ODR value.

Based on the continuous time sigma-delta (CTSD) modulation

scheme, the AD4134 removes the traditionally required switched

capacitor circuitry sampling preceding the Σ-Δ modulator, which

leads to a relaxation of the ADC input driving requirement. The

CTSD architecture also inherently rejects signals around the ADC

aliasing frequency band, giving the device its inherent antialiasing

capability, and removes the need for a complex external antialiasing

filter.

The AD4134 offers three main digital filter profile options: a wide-

band low ripple filter with a brick wall frequency profile and an ODR

range from 2.5 kSPS to 374 kSPS that is suitable for frequency

domain analysis, a fast responding sinc3 filter with an ODR range

from 0.01 kSPS to 1496 kSPS that is suitable for low latency time

domain analysis and low frequency high dynamic range input types,

and a balanced sinc6 filter with an ODR range from 2.5 kSPS

to 1.496 MSPS, offering optimal noise performance and response

time.

The AD4134 has four independent converter channels in parallel,

each with a CTSD modulator and a digital decimation and filtering

path. The AD4134 enables simultaneous sampling of four separate

signal sources, each supporting a maximum input bandwidth of

391.5 kHz and achieving tight phase matching between these

four signal measurements. The high level of channel integration,

together with its simplified analog front-end requirement, enables

the AD4134 to provide a high density multichannel data acquisition

solution in a small form factor.

The AD4134 is also capable of performing on-board averaging

between two or four of its input channels. The result is a near

3 dB, if two channels are combined, or 6 dB, if all four channels

are combined, improvement in dynamic range while maintaining the

bandwidth.

The signal chain simplification property of the AD4134 also im-

proves the system level performance through the reduction of

noise, error, mismatch, and distortion that is normally introduced by

the analog front-end circuitry.

The AD4134 supports two device configuration schemes: serial pe-

ripheral interface (SPI) and hardware pin configuration (pin control

mode). The SPI control mode offers access to all the features and

configuration options available on the AD4134. SPI control mode

also enables access to the on-board diagnostic features designed

to enable a robust system design. Pin control mode offers the

benefit of simplifying the device configuration, enabling the device

to operate autonomously after power-up operating in a standalone

mode.

The AD4134 offers excellent dc and ac performance. The band-

width of each ADC channel ranges from dc to 391.5 kHz, making

the device an ideal candidate for universal precision data acquisi-

tion solutions supporting a breadth of sensor types, from tempera-

ture and pressure to vibration and shock.

The AD4134 offers a large number of features and configuration

options, giving the user the flexibility to achieve the optimal balance

between bandwidth, noise, accuracy, and power for a given applica-

tion.

In addition to the optional SPI, the AD4134 has a flexible and

independent data interface for transmitting the ADC output data.

The data interface can act as either a bus master or a slave with

various clocking options to support multiple communication bus

protocols. The data interface also supports daisy-chaining and an

optional minimum input/output (I/O) mode designed to minimize the

number of digital isolator channels required in isolated applications.

An integrated asynchronous sample rate converter (ASRC) allows

the AD4134 to precisely control the decimation ratio and, in turn,

the output data rate (ODR) using interpolation and resampling tech-

niques. The AD4134 supports a wide range of ODR frequencies,

from 0.01 kSPS to 1496 kSPS with less than 0.01 SPS adjustment

resolution, allowing the user to granularly vary sampling speed

to achieve coherent sampling. The ODR value can be control-

led through the ODR_VAL_INT_x and ODR_VAL_FLT_x registers

(Register 0x16 to Register 0x1C, ASRC master mode), or using an

external clock source (ASRC slave mode). The ASRC slave mode

operation enables synchronous sampling between multiple AD4134

devices to a single system clock. The ASRC simplifies the clock

distribution requirement within a medium bandwidth data acquisition

The AD4134 has an operating ambient temperature range from

−40°C to 105°C. The device is housed in an 8 mm × 8 mm, 56-lead

lead frame chip scale package (LFCSP).

Note that throughout this data sheet, multifunction pins, such as

FORMAT1/SCLK, are referred to either by the entire pin name or

by a single function of the pin, for example, SCLK, when only that

function is relevant.

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Data Sheet

AD4134

SPECIFICATIONS

AVDD5 = DVDD5 = 4.5 V to 5.5 V, AVDD1V8 = DVDD1V8 = 1.65 V to 1.95 V, CLKVDD = 1.65 V to 1.95 V, LDOIN = 2.6 V to 5.5 V, IOVDD =

1.65 V to 1.95 V, CLKIN = 48 MHz, AGND5 = DGND5 = AGND1V8 = DGND1V8 = IOGND = CLKGND = 0 V, REFIN voltage (V_REF) = 4.096 V,

T_A= −40°C to +105°C, high performance mode, input common-mode voltage (V_CM) = 2.048 V, wideband 0.433 × ODR filter, Antialiasing 1

(AA1) mode, unless otherwise noted. Typical values are for T_A= 25°C, AVDD5 = DVDD5 = 5 V, AVDD1V8 = DVDD1V8 = CLKVDD = 1.8 V,

LDOIN = 1.8 V, IOVDD = 1.8 V, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPEED AND DATA OUTPUT

ODR

Wideband 0.10825 × ODR and

0.433 × ODR Filters^{1, 2}

2.5

374

kSPS

Sinc6 Filter³

Sinc3 Filter⁴

2.5

1496

kSPS

0.01

−3 dB Bandwidth

Wideband 0.433 × ODR Filter

Wideband 0.10825 × ODR Filter

Sinc6 Filter

1.08

0.27

0.47

0.003

161.942

40.48

kHz

278.4

Sinc3 Filter

391.5

Data Output Coding

DYNAMIC PERFORMANCE

Twos complement, MSB first

More information is available in the Noise Performance

and Resolution section

Dynamic Range (DR)

Shorted input

High Performance Mode

ODR = 374 kSPS

105.7

108

137

120

123

dB

ODR = 10 SPS, sinc3 filter

A weighted, 1 kHz input, −60 dBFS, ODR = 48 kSPS

2:1 channel averaging, A weighted, 1 kHz input,

−60 dBFS, ODR = 48 kSPS

4:1 channel averaging, A weighted, 1 kHz input,

−60 dBFS, ODR = 48 kSPS

126

106

dB

Low Power Mode

Signal-to-Noise Ratio

High Performance Mode

Low Power Mode

ODR = 187 kSPS

103.7

1 kHz, −0.5 dBFS, sine wave input

ODR = 374 kSPS

105.3

104.6

107

106

dB

ODR = 187 kSPS

Signal-to-Noise-and-Distortion Ratio

(SINAD)

1 kHz, −0.5 dBFS, sine wave input

High Performance Mode

Low Power Mode

ODR = 374 kSPS

106.5

105.5

dB

ODR = 187 kSPS

Total Harmonic Distortion (THD)

High Performance Mode

Low Power Mode

1 kHz, −0.5 dBFS, sine wave input

−120

−119

dB

Spurious-Free Dynamic Range⁵

1 kHz, −0.5 dBFS, sine wave input

(SFDR)

High Performance Mode

Low Power Mode

125

dBc

INTERMODULATION DISTORTION

(IMD)

With input tone at 9.7 kHz and 10.3 kHz

Second-order

−122

−125

dB

Third-order

ACCURACY

Integral Nonlinearity (INL)

High performance mode

Low power mode

±2

ppm of FSR

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Offset Error⁶

Test Conditions/Comments

Min

Typ

Max

Unit

High performance mode

Low power mode

±100

0.9

±600

3.7

µV

Offset Error Drift

Gain Error⁶

High performance mode

Low power mode

µV/°C

0.8

3

µV/°C

High performance mode, master mode

Low power mode, master mode

±350

±150

2

±850

±500

5.1

ppm of FSR

ppm/°C

µV p-p

Gain Drift

Voltage Noise

0.1 Hz to 10 Hz

1.01

ANALOG INPUTS

Differential Input Voltage Range (V_IN

)

−V_REFis the negative reference voltage and +V_REFis

the positive reference voltage

−V_REF

+V_REF

V

Input Common-Mode Voltage Range

(V_CM

V_REF/2

AVDD5/2

)

Input Current

317

8.3

µA/V

nA/V/°C

kΩ

Input Current Drift

Differential Input Resistance

6.25

VCM PIN

Output Voltage

V_REF/20

AVDD5/2

200

V

Load Regulation (∆V_OUT/∆I_L)

Voltage Regulation (∆V_OUT/∆V_AVDD5V

Short-Circuit Current

313

993

45

µV/mA

µV/V

mA

)

Loading Capacitance

pF

Additive Voltage Noise Density

EXTERNAL REFERENCE

70

nV/√Hz

REFIN Voltage (V_REF

)

REFIN to REFGND high performance mode

REFIN to REFGND low power mode

All channels on, high performance mode

All channels on, low power mode

One channel on, high performance mode

One channel on, low power mode

REFIN off

4.096 or 5

5.85

V

REFIN Current

mA

µA

3.22

1.53

0.9

0.5

REFIN Current Drift

REFIN Resistance

40

nA/V/°C

kΩ

All channels on

0.7

One channel on

2.66

kΩ

All channels on, low power mode

One channel on, low power mode

1.27

kΩ

4.79

kΩ

MODULATOR MAGNITUDE

RESPONSE

High Performance Mode

At 100 kHz, ODR = 374 kSPS

At 20 kHz, ODR = 374 kSPS

At 50 kHz, ODR = 187 kSPS

At 20 kHz, ODR = 187 kSPS

At 20 kHz

−0.0202

−0.0024

−0.0122

−0.00189

dB

Low Power Mode

SYNCHRONIZATION

Channel to Channel Phase Matching⁷

1.57

4.17

3.3

ns

Channel to Channel Phase Matching

Drift

ps/°C

Device to Device Phase Matching⁸

ODR = 1496 kSPS

10

ns

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL FILTER RESPONSE

Low Ripple Wideband

Group Delay

39.8/ODR

79.6/ODR

32

Sec

µdB

Settling Time

Pass-Band Ripple

Pass-Band Frequency (f_PASS

)

Wideband 0.433 × ODR Filter

±32 µdB pass band

−0.1 dB pass band

−3 dB bandwidth

0.4 × ODR

Hz

0.401 × ODR

0.433 × ODR

0.1 × ODR

Wideband 0.10825 × ODR Filter ±32 µdB pass band

−0.1 dB pass band

0.101 × ODR

−3 dB bandwidth

0.10825 ×

ODR

Stop Band Frequency (f_STOP

)

Wideband 0.433 × ODR Filter

Wideband 0.10825 × ODR Filter

Stop Band Attenuation

0.499 × ODR

0.2 × ODR

110

Hz

dB

Sinc6

Group Delay

Settling Time

Pass Band

3.25/ODR

6.5/ODR

−3 dB bandwidth

0.1861 ×

ODR

Sec

Sinc3

Group Delay (GD)

Settling Time

Pass Band

Latency

1.75/ODR

3.5/ODR

Sec

Complete settling

−3 dB bandwidth

0.2617 ×

ODR

Attenuation

At 50 Hz

50 SPS, 50 Hz ± 1 Hz

102

106

102

67

dB

At 60 Hz

60 SPS, 60 Hz ± 1 Hz

At 50 Hz, 60 Hz

10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, sinc3 rejection,

and 50 Hz/60 Hz rejection filter¹

COMBINED RESPONSE

Overall Group Delay

Sinc3 filter, slave gated mode

Sinc6 filter, slave gated mode

High performance mode

7/ODR

Sec

9.5/ODR

REJECTION

Power Supply Rejection Ratio

DC

AVDD5

DVDD5

AVDD1V8

DVDD1V8

IOVDD

LDOIN

97.1

78.5

85.5

100

dB

101

119.2

61.4

CLKVDD

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Power Supply Rejection AC

100 mV p-p, DC to 24 MHz signal on supply with no

decoupling capacitor, value with respect to full-scale

input

AVDD5

101

105

97.5

113

136

95.9

dB

DVDD5

AVDD1V8

DVDD1V8

IOVDD

CLKVDD

Common-Mode Rejection Ratio

(CMRR)

100 mV p-p on V_CMwith no decoupling capacitor

DC

78.4

74.5

130.7

dB

AC

Up to 10 kHz

dB

Crosstalk

−0.5 dBFS, 1 kHz input on adjacent channels

dBFS

Input Signal Alias Rejection (AA_REJ

)

High Performance Mode

−6 dBFS output of band tone from master clock

(MCLK) − 160 kHz to MCLK + 160 kHz, AA1 mode

85.4

102.5

87.4

97.2

dB

−6 dBFS output of band tone from MCLK − 160 kHz to

MCLK + 160 kHz, Antialiasing 2 (AA2) mode

Low Power Mode

−6 dBFS output of band tone from MCLK − 80 kHz to

MCLK + 80 kHz, AA1 mode

−6 dBFS output of band tone from MCLK − 80 kHz to

MCLK + 80 kHz, AA2 mode

EXTERNAL CLOCK INPUT

Frequency

47.9

48

48.1

60

MHz

%

Duty Cycle

40

50:50

Input Voltage High

Input Voltage Low

Input Capacitance

CRYSTAL OSCILLATOR

Frequency

0.65 × CLKVDD

V

0.35 × CLKVDD

V

10

pF

±100 ppm

48

MHz

ms

Start-Up Time

4.4

CLKSEL INPUT LOGIC

Input High Voltage (V_INH

)

0.7 × IOVDD

−1

V

Input Low Voltage (V_INL

Leakage Currents

XCLKOUT PIN

)

0.3 × IOVDD

+1

V

µA

Output Frequency

48

MHz

ps

%

Rise Time/Fall Time (20% to 80%)

Duty Cycle

45 pF load

0.85

53.8

External clock input duty cycle = 50:50

Source current (I_SOURCE) = 100 µA

Sink current (I_SINK) = 100 µA

Output Voltage High

Output Voltage Low

CLKVDD − 0.2

V

0.2

V

ODR PIN

Output Frequency

0.01

1496

kHz

ns

Output Rise Time/Fall Time (20% to

80%)

45 pF load

2.8

Output Voltage High

Output Voltage Low

I_SOURCE= 100 µA

I_SINK= 100 µA

IOVDD − 0.2

V

0.2

V

Input Frequency (f_IN

)

0.01

1496

kHz

V

V_INH

0.7 × IOVDD

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

V_INL

0.3 × IOVDD

V

Input Capacitance

DCLK PIN

Pin configured as input

10

pF

Output Frequency

2.93

48000

kHz

ns

Output Rise Time/Fall Time (20% to

80%)

45 pF load

2.8

Output Duty Cycle

Output Voltage High

Output Voltage Low

f_IN

50:50

%

V

I_SOURCE= 100 µA

I_SINK= 100 µA

IOVDD − 0.2

0.7 × IOVDD

0.2

V

50,000

kHz

V

V_INH

V_INL

0.3 × IOVDD

V

Input Capacitance

LOGIC INPUTS

V_INH

Pin configured as input

10

pF

0.7 × IOVDD

−10

V

V_INL

0.2 × IOVDD

+10

V

Leakage Currents

LOGIC OUTPUTS

µA

Output High Voltage (V_OH

)

I_SOURCE= 100 µA

I_SINK= 100 µA

IOVDD − 0.2

V

Output Low Voltage (V_OL

)

0.2

5.5

INTEGRATED LOW DROPOUT (LDO)

REGULATOR

Output Voltage

1.85

V

Input Voltage

2.6

POWER SUPPLY VOLTAGE

AVDD5 to AGND5

4.5

5

5.5

V

DVDD5 to DGND5

4.5

5

5.5

AVDD5 to AGND5

V_REF= 5 V

4.7

5

5.5

DVDD5 to DGND5

4.7

5

5.5

DVDD1V8 to DGND

AVDD1V8 to AGND1V8

DVDD1V8 to DGND

IOVDD to IOGND

1.65

1.8

1.85

1.8

1.85

1.95

V_REF= 5 V

1.8

1.65

1.8

CLKVDD to CLKGND

POWER SUPPLY CURRENT

V_REF= 5 V

4 channels active, internal LDO regulator bypassed,

XCLKOUT disabled

High Performance Mode

AVDD5

ODR = 374 kSPS

8.2

38.6

56

11

mA

DVDD5

44.8

81

AVDD1V8

DVDD1V8

Sinc3 filter, ODR = 1496 kSPS

Sinc6 filter, ODR = 1496 kSPS

Wideband 0.433 × ODR filter

60

69.7

70.9

105.5

3.17

3.53

60.9

90

IOVDD

2.25

2.8

CLKVDD

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Low Power Mode

AVDD5

ODR = 187 kSPS

8.2

11

mA

DVDD5

14.1

51

16.5

74.6

42.1

43.3

56.8

1.7

AVDD1V8

DVDD1V8

Sinc3 filter, ODR = 1496 kSPS

Sinc6 filter, ODR = 1496 kSPS

Wideband 0.433 × ODR filter

30.6

38.5

48.5

1.27

1.89

IOVDD

CLKVDD

2.3

TOTAL POWER CONSUMPTION

External LDO mode: AVDD5 = DVDD5 = 5 V,

AVDD1V8 = DVDD1V8 = CLKVDD = IOVDD = LDOIN

= 1.8 V, internal LDO regulator bypassed, XCLKOUT

disabled

High Performance Mode

ODR = 374 kSPS, Wideband 0.433 × ODR filter

4 channels active

504

201

472

450

418

446

556.3

342.6

mW

1 channel active

2:1 averaging

4:1 averaging

ODR = 2.5 kSPS, 4 channels active

ODR = 1496 kSPS, 4 channels active, sinc3 filter

ODR = 187 kSPS, Wideband 0.433 × ODR filter

4 channels active

Low Power Mode

297

121

288

254

260

285

mW

1 channel active

2:1 averaging

4:1 averaging

ODR = 2.5 kSPS, 4 channels active

ODR = 1496 kSPS, 4 channels active, sinc3 filter

Internal LDO regulator mode: AVDD5 = DVDD5 = 5 V,

LDOIN = 2.6 V, XCLKOUT disabled

High Performance Mode

ODR = 270 kSPS, Wideband 0.433 × ODR filter

4 channels active

593

246

555

530

484

547

mW

1 channel active

2:1 averaging

4:1 averaging

ODR = 2.5 kSPS, 4 channels active

ODR = 1496 kSPS, 4 channels active, sinc3 filter

ODR = 187 kSPS, Wideband 0.433 × ODR filter

4 channels active

Low Power Mode

386

147

356

334

316

355

1

mW

1 channel active

2:1 averaging

4:1 averaging

ODR = 2.5 kSPS, 4 channels active

ODR = 1496 kSPS, 4 channels active, sinc3 filter

Full Power-Down Mode

Sleep Mode

15

1

For internal LDO regulator mode, the maximum ODR supported for wideband FIR filters is 270 kSPS.

For slave mode, the maximum ODR supported for wideband FIR filters is 365 kSPS.

For slave mode, the maximum ODR supported for the sinc6 filter is 1460 kSPS.

2

3

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Data Sheet

AD4134

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

4

For slave mode, the maximum ODR supported for the sinc3 filter is 1460 kSPS.

Excluding the first five harmonics.

5

6

Following a full system calibration, the offset error and the gain error are in the order of the noise for the programmed output data rate selected. The gain error is a function

of the output data rate in slave mode. Therefore, a gain error calibration is needed when the output data rate is changed. It is recommended to perform a periodic system

calibration to stop aging related drifts.

7

8

Between any two channels on the same device.

Between any two channels on any two devices. SPI slave mode with DCLK as gated input only with the DIG_IF_RESET SPI write issued simultaneously to both devices.

TIMING SPECIFICATIONS

AVDD5 = DVDD5 = 4.5 V to 5.5 V, AVDD1V8 = DVDD1V8 = 1.65 V to 1.95 V, CLKVDD = 1.65 V to 1.95 V, IOVDD = 1.65 V to 1.95 V, CLKIN =

48 MHz, AGND5 = DGND5 = AGND1V8 = DGND1V8 = IOGND = CLKGND = 0 V, T_A= −40°C to 105°C, unless otherwise noted. Typical values

are at T_A= 25°C, unless otherwise noted.

Table 2. Device Clock Timing

Parameter

Description

Test Conditions/Comments

Min

Typ

Max

Unit

f_SYSCLK

MCLK

System clock frequency

Master clock

48

MHz

Hz

High performance mode

Low power mode

f_SYSCLK/2

f_SYSCLK/4

f_SYSCLK/2

Hz

f_DIGCLK

f_DCLK

Internal digital clock (t_DIGCLK) = 1/f_DIGCLK

Data Interface clock (t_DCLK) = 1/f_DCLK

Hz

DCLK as output, SPI control mode

DCLK as output, pin control mode

DCLK as input

f_SYSCLK

50

MHz

f_SCLK

SPI clock rate (t_SCLK) = 1/f_SCLK

50

The signal on DOUTx is driven out on the rising edge of the DCLK. t_{ODR_PERIOD}is 1/ODR. See Figure 2.

Table 3. Data Interface Timing with Gated DCLK

Parameter

Description

Test Conditions/Comments

Min

Typ

Max

Unit

t₁

ODR high time

Master mode, t_DCLK> t_DIGCLK

Master mode, t_DCLK≤ t_DIGCLK

Slave mode

2.5 × t_DCLK

3 × t_DIGCLK

t_DCLK− 2

8

3.5 × t_DCLK

ns

3 × t_DIGCLK+ 4

t₂

t₃

ODR low time

Slave mode

ODR falling edge to DCLK rising edge

Master mode

Slave mode

t₄

t₅

Last data DCLK falling edge to ODR rising edge

DCLK rising to DOUTx invalid

Slave mode

2 × t_DCLK

−4

Master mode

Slave mode

0

t₆

DCLK rising to DOUTx valid

Master mode

0

3

Slave mode

8.2

t₇

t₈

DCLK low time

DCLK high time

t_DCLK/2 − 1

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Data Sheet

AD4134

SPECIFICATIONS

Figure 2. Timing Diagram of Data Interface with Gated DCLK

Signal on DOUTx is driven out on the rising edge of DCLK. See Figure 3.

Table 4. Data Interface Timing with Free Running DCLK

Parameter

Description

Test Conditions/Comments

Min

Typ

Max

Unit

t₉

ODR high time

Master mode, t_DCLK> t_DIGCLK

Master mode, t_DCLK≤ t_DIGCLK

Slave mode, t_DCLK> t_DIGCLK

Slave mode, t_DCLK≤ t_DIGCLK

Slave mode, t_DCLK> t_DIGCLK

Slave mode, t_DCLK≤ t_DIGCLK

Slave mode

2.5 × t_DCLK

3 × t_DIGCLK

3 × t_DCLK

3 × t_DIGCLK

3 × t_DCLK

3 × t_DIGCLK

t_DCLK/2

3.5 × t_DCLK– t_DIGCLK+ 4

3 × t_DIGCLK+ 4

ns

t₁₀

ODR low time

ns

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

DCLK rising edge to ODR rising edge

ODR rising edge to DCLK rising edge

ODR sampled high to DOUTx active

DCLK rising to DOUTx invalid

ns

Slave mode

t_DCLK/2

3 × t_DCLK

−4

3 × t_DCLK+ 4

Master mode

Slave mode

ns

DCLK rising to DOUTx valid

0

2

3

t₁₆

t₁₇

DCLK low time

DCLK high time

t_DCLK/2 − 1

Figure 3. Timing Diagram of Data Interface with Free Running DCLK

SDI is sampled on the rising edge of SCLK. SDO is driven out on the falling edge of SCLK. See Figure 4.

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Data Sheet

SPECIFICATIONS

Table 5. SPI Timing

AD4134

Parameter

Description

Min

Typ

Max

Unit

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

CS falling to data out active

SCLK falling edge to SDO valid

SCLK low time

0

7

8

ns

t_SCLK/2 − 1

SDI setup time

2

SDI hold time

SDO hold time after SCLK falling

SCLK high time

7

t_SCLK/2 − 1

t_SCLK

Last SCLK rising edge to CS rising edge

CS high time

0.9 × t_SCLK/2

9

CS falling edge to SCLK rising edge

Figure 4. SPI Timing Diagram

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Data Sheet

AD4134

ABSOLUTE MAXIMUM RATINGS

Table 6.

THERMAL RESISTANCE

Parameter

Rating

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to PCB

thermal design is required.

AVDD5 to AGND5

−0.3 V to +6 V

DVDD5 to DGND5

AVDD1V8 to AGND1V8

−0.3 V to 2.2 V or LDOIN + 0.3 V

(whichever is lower)

θ_JAis the natural convection junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure. θ_JCis the junction

to case thermal resistance.

DVDD1V8 to DGND1V8

CLKVDD to CLKGND

−0.3 V to 2.2 V or LDOIN + 0.3 V

(whichever is lower)

−0.3 V to 2.2 V or LDOIN + 0.3 V

(whichever is lower)

Table 7. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

IOVDD to IOGND

−0.3 V to +2.2 V

CP-56-9

DGND5 to AGND5

AGND1V8 to AGND5

DGND1V8 to AGND5

IOGND to AGND5

−0.3 V to +0.3 V

2S2P or 1S Test Board

2S2P Test Board with 36 Thermal Vias

37¹

27³

5.4²

N/A⁴

°C/W

−0.3 V to +0.3 V

1

−0.3 V to +0.3 V

Simulated data based on a JEDEC 2S2P test board in a JEDEC natural

convection environment.

CLKGND to AGND5

LDOIN to AGND5

−0.3 V to +0.3 V

2

3

4

AVDD1V8 − 0.3 V to 6 V

−1 V to AVDD5 + 0.3 V

−0.3 V to AVDD5 + 0.3 V

−0.3 V to +0.3 V

Simulated data based on a JEDEC 1S test board, measured at the exposed

pad with a cold plate mounted directly to the package surface.

AINx± Inputs to AGND5

REFIN to AGND5

Simulated data based on a JEDEC 2S2P test board with 36 thermal vias in a

JEDEC natural convection environment.

REFCAP to AGND5

REFGND to AGND5

Digital I/O Pins to IOGND

N/A means not applicable.

−0.3 V to IOVDD + 0.3 V

−0.3 V to CLKVDD + 0.3 V

XCLKOUT, XTAL2/CLKIN, and XTAL1 to

CLKGND

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

Operating Ambient Temperature Range

Storage Temperature Range

−40°C to +105°C

−65°C to +150°C

260°C

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

Pb-Free Temperature, Soldering Reflow

(10 sec to 30 sec)

Junction Temperature

150°C

260°C

Package Classification Temperature

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only, functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

1

FORMAT0/CS

DI

ADC Output Data Format Selection Input 0 in Pin Control Mode (FORMAT0). Tie this pin to IOVDD or to IOGND

to set the number of DOUTx pins used to output ADC conversion data. See the Output Channel Format section for

more details.

Chip Select Input in SPI Control Mode (CS).

2

3

FORMAT1/SCLK

DEC3/SDO

DI

ADC Output Data Format Selection Input 1 in Pin Control Mode (FORMAT1). Tie this pin to IOVDD or to IOGND

to set the number of DOUTx pins used to output ADC conversion data. See the Output Channel Format section for

more details.

Serial Clock Input in SPI Control Mode (SCLK).

DI/O

Decimation Ratio Selection Input 3 in Pin Control Master Mode or Phase-Locked Loop (PLL) Lock Status Output

in Pin Control Slave Mode (DEC3). Tie this pin to IOVDD or to IOGND to set the output data rate. See the

Programming Output Data Rate and Clock section for more details. In pin control slave mode, this pin is output high

to indicate the internal PLL is in lock.

Serial Data Output in SPI Control Mode (SDO).

4

DEC2/SDI

DI

Master Mode Decimation Ratio Selection Input 2 in Pin Control Master Mode (DEC2). Tie this pin to IOVDD or to

IOGND to set the output data rate. See the Programming Output Data Rate and Clock section for more details.

Serial Data Input in SPI Control Mode (SDI).

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

5

DEC1/DCLKMODE

DI

Decimation Ratio Selection Input 1 in Pin Control Master Mode (DEC1). Tie this pin to IOVDD or to IOGND to set

the output data rate. See the Programming Output Data Rate and Clock section for more details.

DCLK Mode Control in Pin Control Slave Mode and in SPI Control Mode (DCLKMODE). Tie this pin high to IOVDD

to set DCLK to operate in free running mode. Tie this pin low to ground to set DCLK to operate in gated mode.

6

DEC0/DCLKIO

DI

Decimation Ratio Selection Input 0 in Pin Control Master Mode (DEC0). Tie this pin to IOVDD or to IOGND to set

the output data rate. See the Programming Output Data Rate and Clock section for more details.

DCLK Pin I/O Direction Control in Pin Control Slave Mode and in SPI Control Mode (DCLKIO). In master mode,

tie this pin to IOVDD to configure DCLK as an output. In slave mode, tie this pin low to ground to set DCLK as an

input. When the DEC1/DCLKMODE pin is high (DCLK is in free running mode), the DCLKIO input is ignored and

the DCLK direction is always the same as the ODR pin.

7

8

DOUT3

DOUT2

DI/O

Data Output 3. The output data is synchronous to DCLK and framed by the ODR pin. In Daisy-Chaining

Configuration this pin functions as input taking data from downstream device.

Data Output 2. The output data is synchronous to DCLK and framed by the ODR pin. In Daisy-Chaining

Configuration this pin functions as input taking data from downstream device.

9

DOUT1

DOUT0

DCLK

DO

Data Output 1. The output data is synchronous to DCLK and framed by the ODR pin.

Data Output 0. The output data is synchronous to DCLK and framed by the ODR pin.

10

11

DO

DI/O

ADC Conversion Data Clock. Conversion data on the DOUT0 pin to the DOUT3 pin is clocked out synchronously

by DCLK. In pin control master mode, DCLK is configured as an output operating in gated mode. In pin control

slave mode or in SPI control mode, the DCLK direction and mode of operation are determined by the DEC1/

DCLKMODE pin and DCLKIO pin. Refer to Table 29 for details. In master mode, DCLK frequency is programmable

through DCLKRATEx in pin control mode or the DATA_PACKET_CONFIG register in SPI control mode.

12

ODR

DI/O

Output Data Rate Control and Framing. The frequency of the ODR signal matches the ADC output data rate. The

edges of the ODR signal can be used to frame the conversion output data bit steam. In master mode, the ODR

pin is configured as an output with the pin-programmable and register-programmable frequency derived from the

device master clock. In slave mode, the ODR pin is configured as an input to allow the external clock to control the

ADC output data rate.

13

14

15

IOVDD

P

Digital I/O Supply. This pin sets the logic levels for all interface I/O pins.

I/O Interface Ground Reference.

IOGND

GND

DI/O

FILTER0/GPIO4

Digital Filter Type Selection Input 0 in Pin Control Mode (FILTER0). Tie this pin to IOVDD or to IOGND to select the

digital filter options. See the Programming Digital Filter section for more details.

General-Purpose Input/Output 4 in SPI Control Mode (GPIO4).

16

17

18

FILTER1/GPIO5

FRAME0/GPIO6

FRAME1/GPIO7

DI/O

Digital Filter Type Selection Input 1 in Pin Control Mode (FILTER1). Tie this pin to IOVDD or to IOGND to select the

digital filter options. See the Programming Digital Filter section for more details.

General-Purpose Input/Output 5 in SPI Control Mode (GPIO5).

Conversion Output Data Frame Control Input 0 in Pin Control Mode (FRAME0). Tie this pin to IOVDD or to IOGND

to select the conversation output data frame. See the Data Frame section for more details.

General-Purpose Input/Output 6 in SPI Control Mode (GPIO6).

Conversion Output Data Frame Control Input 1 in Pin Control Mode (FRAME1). Tie this pin to IOVDD or to IOGND

to select the conversation output data frame. See the Data Frame section for more details.

General-Purpose Input/Output 7 in SPI Control Mode (GPIO7).

Ground Reference for Digital Supply Voltage, 1.8 V.

19

20

DGND1V8

DVDD1V8

GND

P

Digital Supply Voltage, 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either

case, a decoupling capacitor of 10 µF is required between DVDD1V8 and DGND1V8.

21

AVDD1V8

P

Analog Supply Voltage 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either

case, a decoupling capacitor of 10 µF is required between AVDD1V8 and AGND1V8.

22

23

AGND1V8

LDOIN

GND

P

Ground Reference for Analog Supply Voltage, 1.8 V.

Input for Three Internal 1.8 V LDO Regulators Powering AVDD1V8, DVDD1V8, and CLKVDD. Tie this pin to

DVDD1V8 if an external power supply is used to power AVDD1V8, DVDD1V8, and CLKVDD. A 10 µF decoupling

capacitor is required between LDOIN and DGND1V8. See the On-Board LDO Regulators section for more details.

24

25

26

DGND5

DVDD5

AVDD5

GND

P

Ground Reference for Digital Supply Voltage, 5 V.

Digital Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between DVDD5 and DGND5.

Analog Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between AVDD5 and AGND5.

P

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

27

28

29

30

31

32

33

34

AGND5

DNC

GND

DNC

AI

Ground Reference for Analog Supply Voltage, 5 V.

Do Not Connect. Do not connect to this pin.

Positive Analog Input to ADC Channel 0.

Negative Analog Input to ADC Channel 0.

Ground Reference for Analog Supply Voltage, 5 V.

Positive Analog Input to ADC Channel 1.

Negative Analog Input to ADC Channel 1.

AIN0+

AIN0−

AGND5

AIN1+

AIN1−

VCM

AI

GND

AI

AO

Common-Mode Voltage Output. The VCM output can be used to provide a common-mode voltage for the analog

front-end circuit. The VCM pin provides a buffered voltage output. The level is fixed to 1/2 of the voltage on the

REFCAP pin in pin control mode, and is programmable in SPI control mode. When driving capacitive loads larger

than 0.2 nF, it is recommended to place a 50 Ω series resistor between the pin and the capacitive load for stability.

35

36

REFIN

AI

ADC Reference Filter Input. Use an internal 20 Ω resistor together with an external capacitor on the REFCAP pin to

filter the reference source noise.

REFCAP

AO

ADC Reference Direct Input. Connect this pin to the external reference source for a direct reference input.

Alternatively, connect the reference source to the REFIN pin and place a filter capacitor between the REFCAP pin

and REFGND pin to limit the reference noise bandwidth. See the Reference Input section for more details.

37

38

39

40

41

42

43

44

REFGND

AIN2+

GND

AI

ADC Reference Ground Reference.

Positive Analog Input to ADC Channel 2.

Negative Analog Input to ADC Channel 2.

Ground Reference for Analog Supply Voltage, 5 V.

Positive Analog Input to ADC Channel 3.

Negative Analog Input to ADC Channel 3.

Clock Management Circuit Ground Reference.

AIN2−

AI

AGND5

AIN3+

GND

AI

AIN3−

AI

CLKGND

CLKVDD

GND

P

Clock Management Circuit Power Supply, 1.8 V. This pin is supplied from an external source or internal LDO

regulator. In either case, a decoupling capacitor of 2.2 µF is required between the CLKVDD pin and CLKGND pin.

45

XTAL2/CLKIN

DI

Input 2 for Internal Crystal Oscillator (XTAL2). Connect an external crystal between the XTAL1 pin and XTAL2/

CLKIN pin for on-chip clock generation.

Clock Input (CLKIN). For operations using an external clock signal, connect this pin to the external clock source.

See the Clock Input section for more details.

46

XTAL1

DI

Input 1 for Internal Crystal Oscillator. Connect an external crystal between the XTAL1 pin and XTAL2/CLKIN pin

for on-chip clock generation. Leave this pin floating if the device is to operate from a single-ended external clock

signal.

47

48

CLKSEL

DI

Clock Source Selection Input. Connect this pin to IOVDD to enable on-chip clock generation from an external

crystal. Connect this pin to IOGND if the clock signal is provided externally on the XTAL2/CLKIN pin.

XCLKOUT

DO

Crystal Oscillator Buffered Output. A buffered clock signal generated by the internal crystal oscillator is available

on this pin. This signal can be used to drive other AD4134 devices working in parallel. The XCLKOUT output is

enabled by default in pin control mode only if the crystal clock option is selected. The XCLKOUT output is disabled

by default in SPI control mode. See the XCLKOUT Output section for more details.

49

50

51

PIN/SPI

DI

Device Configuration Mode Control Input. Tie this pin to IOVDD to enable device configuration through register

access over the SPI. Tie this pin to ground to enable device configuration through the configuration input pins.

MODE

DI

ASRC Mode Of Operation Control Input. Tie this pin to IOVDD for master mode operation. Tie this pin to IOGND for

slave mode operation.

DCLKRATE0/GPIO0

DI/O

DCLK Frequency Control Input 0 in Pin Control Mode (DCLKRATE0). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 0 in SPI Control Mode (GPIO0).

52

DCLKRATE1/GPIO1

DI/O

DCLK Frequency Control Input 1 in Pin Control Mode (DCLKRATE1). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 1 in SPI Control Mode (GPIO1).

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

53

DCLKRATE2/GPIO2

DI/O

DCLK Frequency Control Input 2 in Pin Control Mode (DCLKRATE2). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 2 in SPI Control Mode (GPIO2).

54

55

RESET

PDN

DI

Hardware Asynchronous Reset Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during

normal operation. Pull this pin low to IOGND to force the device into reset. See the Reset section for more details.

Full Power-Down Mode Control Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during

normal operation. Pull this pin to IOGND to force the device into full power-down mode. See the Power Modes

section for more details.

56

PWRMODE/GPIO3

DI/O

Power Mode Selection Input in Pin Control Mode (PWRMODE). Tie this pin to IOVDD for high performance mode.

Tie this pin to IOGND for low power mode.

General-Purpose Input/Output 3 in SPI Control Mode (GPIO3).

Exposed Pad. Connect the exposed pad to AGND5.

EPAD

1

DI is digital input, DI/O is bidirectional digital input/output, DO is digital output, P is power, GND is ground, DNC is do not connect, AI is analog input, and AO is analog

output.

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

V_REF= 4.096 V, AA1 mode, V_CM= 2.048 V, wideband 0.433 × ODR filter. High performance mode plots are at ODR = 374 kSPS and low power

mode plots are at ODR = 187 kSPS. Sinc3 and sinc6 plots are at ODR = 1496 kSPS, unless otherwise noted.

Figure 9. FFT, High Performance Mode, −0.5 dBFS, Wideband 0.433 × ODR

Filter, ODR = 374 kSPS

Figure 6. Dynamic Range Performance, High Performance Mode, Wideband

0.433 × ODR Filter, ODR = 374 kSPS

Figure 10. FFT, High Performance Mode, Sinc6 Filter, −0.5 dBFS, ODR = 1496

kSPS

Figure 7. Dynamic Range vs. Output Data Rate in High Performance Mode for

Wideband FIR, Sinc3 and Sinc6 Filters

Figure 11. FFT, High Performance Mode, Sinc3 Filter, −0.5 dBFS, ODR = 1496

kSPS

Figure 8. Dynamic Range vs. Input Bandwidth, Wideband 0.433 × ODR Filter

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. IMD with Input Signals at 9.7 kHz and 10.3 kHz, Wideband 0.433 ×

ODR Filter

Figure 12. FFT, Low Power Mode, Wideband 0.433 × ODR Filter, −0.5 dBFS,

ODR = 187 kSPS

Figure 16. Power per Channel vs. Output Data Rate

Figure 13. FFT, Low Power Mode, Sinc6 Filter, −0.5 dBFS

Figure 17. Supply Current vs. Temperature, Wideband 0.433 × ODR Filter

Figure 14. FFT, Low Power Mode, Sinc3 Filter, −0.5 dBFS

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 18. SNR vs. Input Amplitude, Tone at 1 kHz

Figure 21. THD Histogram

Figure 19. THD and THD + N vs. Input Frequency, −6 dBFS Input, 0.433 × ODR

Filter

Figure 22. SNR vs. System Clock Jitter, Wideband 0.433 × ODR Filter

Figure 23. SNR vs. Input Common-Mode Voltage, Wideband 0.433 × ODR

Filter

Figure 20. THD and THD + N vs. Input Amplitude, Wideband Filter, Tone at

1 kHz

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. THD vs. Input Common-Mode Voltage, 0.5 dBFS Input Tone,

Wideband 0.433 × ODR Filter, Full-Scale Input Tone

Figure 27. Shorted Noise, 0.433 × ODR Filter

Figure 28. Shorted Noise, Sinc3 Filter, High Performance Mode

Figure 25. RMS Noise vs. Temperature, for Wideband 0.433 × ODR, Sinc6 and

Sinc3 Filters

Figure 29. RMS Noise per Channel for Various V_REFValues, Wideband 0.433 ×

ODR Filter, High Performance Mode

Figure 26. RMS Noise vs. Temperature, Low Power Mode for Wideband

0.433 × ODR Filter, Sinc6, Sinc3

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. RMS Noise per Channel for Various V_REFValues, Wideband 0.433 ×

ODR Filter, Low Power Mode

Figure 33. Output Amplitude vs. Normalized Frequency (f_IN/f_ODR), Full Scale

Input signal, Wideband 0.433 × ODR Filter, High Performance Mode

Figure 31. In Band Dynamic Range vs. Out of Band Input Frequency of

1 V p‑p Input Signal, Wideband 0.433 × ODR Filter, High Performance Mode

Figure 34. Amplitude vs. Normalized Frequency (f_IN/f_ODR), Sinc Filter Profile,

High Performance Mode

Figure 35. Step Response, Wideband Filter, Wideband 0.433 × ODR Filter

Figure 32. Tone Magnitude In Band vs. Input Frequency, 4 V p‑p Input Signal,

Wideband 0.433 × ODR Filter, High Performance Mode

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 36. Step Response, Sinc3 Filter

Figure 39. INL Error vs. Input Voltage, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 37. INL Error vs. Input Voltage, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 40. INL Error vs. Input Voltage, Full-Scale, Half Scale, and Quarter

Scale Inputs

Figure 38. INL Error vs. Input Voltage, Wideband 0.433 × ODR Filter, Low

Power Mode

Figure 41. INL Distribution, Wideband 0.433 × ODR Filter, High Performance

Mode

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Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 42. Offset Error vs. Input Common-Mode Voltage, Wideband 0.433 ×

ODR Filter, High Performance Mode

Figure 45. Offset Error vs. Temperature, Wideband 0.433 × ODR Filter, Low

Power Mode

Figure 43. Offset Error vs. AVDD5 Supply Voltage, Wideband 0.433 × ODR

Filter, High Performance Mode

Figure 46. Offset Error Distribution, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 44. Offset Error vs. Temperature, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 47. Offset Error Distribution, Wideband 0.433 × ODR Filter, Low Power

Mode

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Rev. 0 | 24 of 92

Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 48. Gain Error vs. Input Common-Mode Voltage, Wideband 0.433 ×

ODR Filter, High Performance Mode

Figure 51. Gain Error vs. Temperature, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 49. Gain Error Distribution, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 52. Gain Error vs. Temperature, Wideband 0.433 × ODR Filter, Low

Power Mode

Figure 50. Gain Error vs. Supply Voltage, Wideband 0.433 × ODR Filter, High

Performance Mode

Figure 53. CMRR vs. Input Frequency, Wideband 0.433 × ODR Filter, High

Performance Mode

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Rev. 0 | 25 of 92

Data Sheet

AD4134

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 54. AC Power Supply Rejection (PSR) vs. Frequency, Wideband 0.433

× ODR Filter, High Performance Mode

Figure 57. Group Delay vs. ODR, Sinc3 Filter

Figure 58. Channel to Channel Phase Difference for 20 kHz Input Tone

Figure 55. Analog Input Current vs. Temperature, Wideband 0.433 × ODR

Filter

Figure 56. Group Delay vs. Input Frequency, Sinc3 Filter, ODR = 1250 kSPS

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Rev. 0 | 26 of 92

Data Sheet

AD4134

TERMINOLOGY

AC Common-Mode Rejection Ratio (CMRR)

Least Significant Bit (LSB)

AC CMRR is defined as the ratio of the power in the ADC output at

frequency, f, to the power of a 100 mV p-p sine wave applied as the

common-mode voltage to the AINx+ pin and AINx− pin at sampling

frequency (f_S).

The least significant bit, or LSB, is the smallest increment that can

be represented by a converter. For a fully differential input ADC with

N bits of resolution, the LSB expressed in volts is

V

REFCAP

LSB = 2 ×

N

2

AC CMRR (dB) = 10 log(Pf/Pf_S)

where:

VREFCAP is the voltage measured on the REFCAP pin.

N = 24 for the AD4134.

Pf is the power at frequency, f, in the ADC output.

Pf_Sis the power at frequency, f_S, in the ADC output.

DC Power Supply Rejection Ratio (DC PSRR)

Integral Nonlinearity (INL) Error

Variations in power supply affect the full-scale transition but not the

linearity of the converter. DC PSRR is the maximum change in the

full-scale transition point due to a change in power supply voltage

from the nominal value.

INL error refers to the deviation of each individual code from a

line drawn from negative full scale through positive full scale. The

point used as negative full scale occurs ½ LSB before the first code

transition. Positive full scale is defined as a level 1½ LSB beyond

the last code transition. The deviation is measured from the middle

of each code to the true straight line.

AC Power Supply Rejection (AC PSR)

AC PSR is the amplitude of the tone observed when a 100 mV p-p

signal is injected on the supply.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,

any active device with nonlinearities creates distortion products at

the sum and difference frequencies of mfa and nfb, where m, n =

0, 1, 2, 3, and so on. Intermodulation distortion terms are those for

which neither m nor n is equal to 0. For example, the second-order

terms include (fa + fb) and (fa − fb), and the third-order terms

include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

For example, if a 100 mV p-p signal injected on the supply at a

frequency of 1 kHz and a −108 dB tone is observed at 1 kHz in the

FFT output, −108 dB is the ac power supply rejection.

Alias Rejection

Alias rejection is defined as the ratio of the power in the ADC

output at frequency, f_IN, to the power of a −6 dBFS input signal at

frequency, MCLK ± f_IN.

The AD4134 is tested using the International Telephonic Consulta-

tive Committee (CCIF) standard, where two input frequencies near

to each other are used. In this case, the second-order terms are

usually distanced in frequency from the original sine waves, and

the third-order terms are usually at a frequency close to the input

frequencies. As a result, the second-order and third-order terms

are specified separately. The calculation of the intermodulation

distortion is as per the THD specification, where it is the ratio of the

rms sum of the individual distortion products to the rms amplitude of

the sum of the fundamentals expressed in decibels.

Alias rejection = 10 log(Pf_IN/PMCLK ± f_IN)

where:

Pf_INis the power at frequency, f_IN, in the ADC output.

PMCLK ± f_INis the power at frequency, MCLK ± f_IN, in the ADC

output.

Group Delay

Group delay is defined as the difference of phase delays measured

at the ADC output and full-scale sine wave ADC input.

Gain Error

Signal-to-Noise Ratio (SNR)

The first transition (from 100 … 000 to 100 …001) occurs at a level

½ LSB above nominal negative full scale (−4.095999755859375 V

for the ±4.096 V range). The last transition (from 011 … 110 to

011 … 111) occurs for an analog voltage 1½ LSB below the nominal

full scale (+4.095999755859375 V for the ±4.096 V range). The

gain error is the deviation of the difference between the actual level

of the last transition and the actual level of the first transition from

the difference between the ideal levels.

SNR is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components below the ODR/2

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Signal-to-Noise-and-Distortion (SINAD) Ratio

SINAD is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components below the ODR/2

frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Gain Drift

Gain drift is the ratio of the gain error change due to a temperature

change of 1°C and the full-scale range (2^N). Gain drift is expressed

in parts per million.

analog.com

Rev. 0 | 27 of 92

Data Sheet

AD4134

TERMINOLOGY

change in output code when the temperature varies over the full

range and take the ratio. Offset error drift is expressed in microvolts

per degree Celsius.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude of

the input signal and the peak spurious signal (excluding the first five

harmonics).

Crosstalk

Crosstalk is measured as tone amplitude observed at Frequency X

on Channel 1 when Channel 0 and Channel 2 are driven simultane-

ously with a full-scale tone at Frequency X.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic compo-

nents to the rms value of a full-scale input signal and is expressed

in decibels.

Overall Group Delay

Overall group delay is the total latency of the AD4134 that a signal

experiences. This latency includes group delays of all the elements,

such as modulator, ASRC, digital filter, and various other digital

interface delays.

Offset Error

Offset error is the difference between the ideal midscale input

voltage (0 V) and the actual voltage producing the midscale output

code.

Offset Error Drift

Offset error drift is the ratio of the offset error change due to

a temperature change of 1°C. For this calculation, observe the

analog.com

Rev. 0 | 28 of 92

Data Sheet

AD4134

THEORY OF OPERATION

Figure 59 shows a simplified signal path of one of the four Σ-Δ ADC

channels of the AD4134. In a typical operation, the CTSD modula-

tor oversamples the analog input signal at the modulator sampling

frequency at MCLK. The ADC quantization noise is modulated to

the higher frequency band during this process. The oversampled

modulator output is then decimated through an ASRC and digital

filter. The decimation removes the additional bandwidth caused by

oversampling along with the shaped quantization. The result is a

high precision data output from the digital filter at the user defined

ODR.

voltage/differential time. The second impact is from the charges

stored in the parasitic capacitance of the switches being pushed

out to the input node when the switch is closed, a phenomenon

known as charge injection or charge kickback. In either case, the

sudden change of current flow at the input of the ADC reacts with

the finite impedance of the driving circuit to create a disturbance in

the form of voltage variation. The profile of the variation depends on

the bandwidth and the impedance of the driving circuit.

To achieve the required level of accuracy, at the end of each

sampling period, the disturbed input signal must settle to the actual

source value within 1 LSB of the ADC target effective resolution,

which is particularly challenging with a higher precision or higher

input bandwidth requirement.

A common solution to overcome the input settling challenge is to

buffer the input with a high bandwidth amplifier with high output

driving capability, as shown in Figure 60.

Figure 59. Signal Path Overview

CONTINUOUS TIME SIGMA-DELTA

MODULATOR

Almost all of the contemporary precision ADCs are designed with a

switched capacitor-based sample-and-hold circuit. The sample-and-

hold circuit is an essential part of the successive approximation

register (SAR) ADC architecture, for example, where it is used to

reduce the aperture time and maintain a steady input level during

conversion. The discrete time Σ-Δ ADCs also use the sample-and-

hold circuit in both the input path and the feedback loop, which

simplifies the design. Because the analog input signal is converted

to a discrete time signal by the sample-and-hold circuit, the ADCs

with the sample-and-hold circuit are also known as discrete time

ADCs.

The sample-and-hold circuit offers many benefits to the ADC de-

sign. However, some side effects of using the sample-and-hold cir-

cuit, such as charge kickback and signal aliasing, require additional

effort in designing the ADC into a system.

Figure 60. Driving the Input of a Discrete Time ADC

The sample-and-hold circuit is also used by the discrete time ADC

on the reference input. A high bandwidth amplifier is also required

to drive the ADC reference input.

The CTSD modulator employs the same Σ-Δ modulation principle,

such as oversampling and noise shaping, as the discrete time

sigma-delta (DTSD) modulator, with the key difference being the

CTSD does not use the sample-and-hold circuit.

The drawbacks of using an ADC driving amplifier include the

following:

► The amplifier bandwidth must be much higher than the input

signal bandwidth, leading to higher power consumption

► The additional components in the signal chain lead to more noise

and error

The CTSD modulator design used on the AD4134 uses both a

continuous time integrator and a continuous time DAC. This archi-

tecture offers some unique system benefits to the precision data

acquisition systems design over the discrete time ADCs.

► Additional design complexity to ensure stability when driving the

dynamic capacitive load of a discrete time ADC

EASY TO DRIVE INPUT AND REFERENCE

The switching action of the sample-and-hold circuit used on the

discrete time ADCs creates disturbances on the input node. There

are two main impacts of the disturbance. The first is the sudden

loading of the input node by the sampling capacitor, for which the

magnitude of the disturbance is proportional to the input differential

CTSD architecture allows the AD4134 to have a constant resistive

input characteristic. This behavior simplifies the front-end circuit

design, allowing lower bandwidth, and low power high performance

precision amplifiers to directly drive the ADC.

analog.com

Rev. 0 | 29 of 92

Data Sheet

AD4134

THEORY OF OPERATION

Similarly, due to the continuous time DAC used in the modulator

feedback loop, the AD4134 reference input also has a constant

resistive input characteristic, making it possible to drive the ADC

reference input directly with a voltage reference IC.

frequency signals from aliasing down, the filter is also known as an

antialiasing filter.

The signal sampling occurs at the very front of the discrete time

ADC in the sample-and-hold circuit. An external antialiasing filter is

required in front of the discrete time ADC to protect it against signal

aliasing.

INHERENT ANTIALIASING FILTER (AAF)

When sampling an analog sinusoid signal at less than twice of its

frequency, reconstruction through interpolation results in a lower

frequency signal than the original. This phenomenon is known as

aliasing. Figure 61 shows an example of signal aliasing viewed

in both the time and frequency domains. The example shows the

digital discrete time representations of a 3 kHz, 17 kHz, and 23

kHz signal sampled at 20 kHz are identical. When interpolating the

result, the output is always a 3 kHz sine wave, which means that, in

this sampling system, the frequency component of the input signal

at 17 kHz and 23 kHz appear at 3 kHz in the output.

The antialiasing filter design requires a fine balance between the

aliasing rejection level and the phase and magnitude distortion of

the input signal. The extra components also introduce error, noise,

and additional power consumption to the signal chain.

Other than being easy to drive, the other major advantage of the

CTSD architecture is its inherent antialiasing property. Without the

sample-and-hold circuit, the sampling of the analog signal takes

place inside the CTSD modulator at the quantizer, after the integra-

tor. This sampling scheme allows the device to take advantage of

the low-pass response of the integrator and intrinsically reject sig-

nals around the sampling frequency of the modulator. This property

provides an inherent aliasing rejection of up to 102.5 dB for the

AD4134. As shown in Figure 62, combining the inherent antialiasing

response of the CTSD modulator with the low ripple wideband

digital filter, the AD4134 is fully protected from the out of band

frequency tones.

The aliasing occurs at the point of sampling of the analog signal.

The only way to guarantee the matching between input and out-

put signal frequency is to limit the input signal bandwidth before

sampling. In the previous example of the frequency component

input signal, if the signal is low-pass filtered with a bandwidth of

10 kHz, the interpolated output always matches the filtered input

signal. Because the purpose of the low-pass filter is to prevent high

Figure 61. Aliasing Explained with an Example Shown in Both Time and Frequency Domains

Figure 62. Combined Magnitude Response of the Inherent Antialiasing Filter and the Digital Filter of the AD4134

analog.com

Rev. 0 | 30 of 92

Data Sheet

AD4134

THEORY OF OPERATION

between the reference IC and the ADC. The circuit incorporates

a second-order low-pass filter to help reduce the wideband noise

from the reference source.

ANALOG FRONT-END DESIGN

SIMPLIFICATION

The result from the two major benefits of the CTSD architecture

described in the Easy to Drive Input and Reference section and the

Inherent Antialiasing Filter (AAF) section is a major simplification

of the analog front-end design of the precision medium bandwidth

data acquisition signal chain.

Figure 64 shows the signal chain of the AD4134. For the continu-

ous time-based AD4134, the easy to drive and inherent antialiasing

property results in significant simplification of the analog front-end

design. Other than the apparent area and cost saving, the front-end

simplification also removes the noise, error, and instability intro-

duced by the removed circuit, improving the overall performance

of the signal chain. As shown in Figure 64, the instrumentation

amplifier can directly drive the resistive inputs of the AD4134,

and the bandwidth of the amplifier adds to the antialias rejection,

making the signal chain an alias free signal chain.

Figure 63 shows the analog front-end circuit for a discrete time

ADC. For discrete time ADC, in between the precision instrumenta-

tion amplifier and the ADC is a third-order antialiasing filter plus an

ADC driving circuit based on a fully differential ADC driving amplifi-

er. An additional RC circuit is required at the ADC input to ensure

stability of the driver and to help further suppress the kickback. A

reference driving circuit based on an operation amplifier is placed

Figure 63. Example Analog Front-End Circuit Design of the Discrete Time-Based ADC

Figure 64. Example Analog Front-End Circuit Design of the AD4134

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Rev. 0 | 31 of 92

Data Sheet

AD4134

NOISE PERFORMANCE AND RESOLUTION

Table 9 to Table 16 contain the data of the noise performance for

the wideband 0.433 × ODR filter, wideband 0.10825 × ODR filter,

sinc6 filter, and the sinc3 digital filter of the AD4134 for various

output data rates and channel averaging settings. The noise values

and dynamic range specified are typical for the bipolar input range

with an external 4.096 V reference (V_REF).

Dynamic Range (dB) = 20log₁₀((2 × V_REF/2√2)/(RMS Noise)

The LSB size is calculated as follows:

LSB Size = (2 × V_REF)/2²⁴

where LSB Size is 488 nV with a 4.096 V reference.

The rms noise is measured with shorted analog inputs. The dynam-

ic range is calculated as

Table 9. Wideband 0.433 × ODR Filter, High Performance Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel 2:1 Channel Averaging

Dynamic Range RMS Noise Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

4:1 Channel Averaging

Dynamic Range

Output Data Rate

(kSPS)

(µV)

(dB)

(µV)

(dB)

RMS Noise (µV)

374

325

285

256

235

200

175

128

100

80

161.94

140.73

123.41

110.85

101.76

86.60

75.78

55.42

43.30

34.64

27.71

13.86

6.93

107.21

12.63

11.41

10.69

10.03

9.47

8.57

8.05

6.70

5.97

5.27

4.68

3.28

2.32

1.87

1.34

0.99

110.46

111.21

111.81

112.5

8.68

7.96

7.43

6.87

6.63

6.02

5.6

113.46

114.25

114.8

6.15

5.61

5.27

4.99

4.67

4.29

3.97

3.37

2.95

2.64

2.33

1.65

1.17

0.94

0.69

0.51

108.09

108.65

109.21

109.71

110.58

111.12

112.72

113.71

114.80

115.83

118.91

121.94

123.80

126.68

129.36

115.26

115.85

116.57

117.25

118.68

119.83

120.78

121.87

124.89

127.8

112.79

113.63

114.27

115.66

116.81

117.9

4.77

4.17

3.68

3.29

2.34

1.66

1.34

0.96

0.7

64

118.87

121.82

124.81

126.67

129.55

132.32

32

16

10

4.33

129.76

132.34

135.08

5

2.17

2.5

1.08

Table 10. Wideband 0.433 × ODR Filter, Low Power Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel 2:1 Channel Averaging

Dynamic Range RMS Noise Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

4:1 Channel Averaging

Output Data Rate

(kSPS)

Dynamic Range

(dB)

(µV)

(dB)

(µV)

RMS Noise (µV)

374

325

285

256

235

200

175

128

100

80

161.94

140.73

123.41

110.85

101.76

86.60

75.78

55.42

43.30

34.64

27.71

13.86

6.93

100.42

27.61

22.93

20.01

18.10

16.91

14.85

13.48

11.15

9.71

103.41

105.04

106.37

107.12

107.89

108.97

109.79

111.32

112.55

113.54

114.68

117.75

120.78

122.72

125.66

128.58

19.55

16.21

13.9

12.75

11.68

10.31

9.37

7.87

6.83

6.09

5.34

3.75

2.64

2.11

106.33

107.96

109.21

110.12

110.64

111.76

112.55

114.31

115.51

116.47

117.61

120.64

123.71

125.76

128.61

131.48

13.96

11.57

10.03

9.03

8.50

7.47

6.82

5.57

4.85

4.34

3.81

2.68

1.88

1.49

1.07

0.77

102.03

103.21

104.08

104.67

105.80

106.64

108.29

109.49

110.58

111.63

114.72

117.69

119.73

122.79

125.64

8.57

64

7.59

32

5.32

16

3.78

10

4.33

2.99

5

2.17

2.10

1.50

1.07

2.5

1.08

1.51

analog.com

Rev. 0 | 32 of 92

Data Sheet

AD4134

NOISE PERFORMANCE AND RESOLUTION

Table 11. Wideband 0.10825 × ODR Filter, High Performance Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel

Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

2:1 Channel Averaging

Dynamic Range RMS Noise

4:1 Channel Averaging

Output Data Rate

(kSPS)

Dynamic Range

(dB)

(µV)

(dB)

(µV)

RMS Noise (µV)

374

325

285

256

235

200

175

128

100

80

40.49

35.18

30.85

27.71

25.44

21.65

18.94

13.86

10.83

8.66

112.80

6.63

6.07

5.65

5.33

5.07

4.74

4.36

3.75

3.32

2.98

2.63

1.91

1.37

1.10

0.83

0.61

116.03

116.84

117.37

117.63

118.13

118.88

119.62

120.88

121.9

4.57

4.16

3.91

3.80

3.59

3.29

3.02

2.61

2.32

2.03

1.87

1.36

0.99

0.79

0.60

0.45

119.01

119.67

120.12

120.71

121.16

121.61

122.37

123.85

124.79

125.85

126.78

129.61

132.36

134.15

136.31

138.84

3.24

3.00

2.85

2.66

2.53

2.40

2.20

1.86

1.66

1.47

1.32

0.95

0.69

0.56

0.44

0.33

113.57

114.20

114.71

115.14

115.72

116.44

117.76

118.82

119.76

120.85

123.64

126.50

128.44

130.91

133.59

123.06

123.78

126.56

129.30

131.23

133.54

136.13

64

6.93

32

3.46

16

1.73

10

1.08

5

0.54

2.5

0.27

Table 12. Wideband 0.10825 × ODR Filter, Low Power Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel 2:1 Channel Averaging

Dynamic Range RMS Noise Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

4:1 Channel Averaging

Output Data Rate

(kSPS)

Dynamic Range

(dB)

(µV)

(dB)

(µV)

RMS Noise (µV)

374

325

285

256

235

200

175

128

100

80

40.49

35.18

30.85

27.71

25.44

21.65

18.94

13.86

10.83

8.66

108.46

10.94

9.94

9.11

8.69

8.35

7.75

7.06

6.12

5.34

4.78

4.22

2.96

2.15

1.68

1.24

0.90

111.64

112.34

113.09

113.61

113.97

114.69

115.35

116.6

7.58

6.99

6.41

6.04

5.79

5.33

4.94

4.28

3.81

3.38

3.01

2.15

1.52

1.23

0.88

0.64

114.53

115.20

115.90

116.42

116.96

117.66

118.24

119.63

120.61

121.76

122.54

125.64

128.61

130.45

133.14

135.84

5.43

5.03

4.64

4.37

4.01

3.79

3.54

3.02

2.69

2.36

2.16

1.51

1.07

0.86

0.63

0.46

109.29

110.05

110.46

110.80

111.45

112.26

113.51

114.69

115.64

116.73

119.81

122.60

124.75

127.37

130.14

117.6

118.64

119.66

122.58

125.58

127.41

130.32

132.99

64

6.93

32

3.46

16

1.73

10

1.08

5

0.54

2.5

0.27

analog.com

Rev. 0 | 33 of 92

Data Sheet

AD4134

NOISE PERFORMANCE AND RESOLUTION

Table 13. Sinc6 Filter, High Performance Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel

Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

2:1 Channel Averaging

4:1 Channel Averaging

Output Data Rate

(kSPS)

Dynamic Range

(dB)

RMS Noise

(µV)

Dynamic Range

(dB)

(µV)

RMS Noise (µV)

1496

1250

1000

750

500

375

325

256

175

128

80

278.406

232.63

186.10

139.58

93.05

69.79

60.48

47.64

32.57

23.82

14.89

11.91

5.96

100.66

26.85

20.56

16.01

12.46

9.54

8.08

7.32

6.34

5.26

4.42

3.50

3.11

104.13

106.34

108.48

110.57

112.87

114.27

115.02

116.20

117.97

119.35

121.50

122.36

125.33

129.87

132.47

135.31

18.01

13.95

10.90

8.57

6.57

5.59

5.13

4.48

3.65

3.12

2.43

2.20

1.56

0.92

0.68

0.49

107.07

109.24

111.44

113.52

115.85

117.32

118.02

119.16

120.90

122.29

124.26

125.46

128.24

132.90

135.29

137.57

12.83

10.00

7.75

6.10

4.66

3.94

3.63

3.19

2.61

2.22

1.77

1.54

1.12

0.65

0.49

0.383

102.98

105.15

107.33

109.64

111.09

111.94

113.20

114.82

116.32

118.34

119.38

122.38

126.98

129.69

131.97

64

32

2.20

1.30

0.95

0.73

10

1.86

5

0.93

2.5

0.47

Table 14. Sinc6 Filter, Low Power Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel 2:1 Channel Averaging

Dynamic Range RMS Noise

4:1 Channel Averaging

Output Data Rate

(kSPS)

−3 dB Bandwidth

(kHz)

Dynamic Range

(dB)

RMS Noise

(µV)

Dynamic Range

(dB)

RMS Noise

(µV)

(dB)

(µV)

1496

1250

1000

750

500

375

325

256

175

128

80

278.406

232.63

186.10

139.58

93.05

69.79

60.48

47.64

32.57

23.82

14.89

11.91

5.96

84.11

180.40

118.22

70.43

37.96

19.74

25.32

12.65

10.76

8.62

87.30

124.98

82.3

90.05

91.06

58.31

34.99

19.12

9.89

17.57

6.38

5.44

4.33

3.62

2.84

2.52

1.78

1.02

0.72

0.54

87.78

90.93

93.92

92.28

95.42

49.04

26.48

13.65

18.32

8.93

98.36

97.65

100.78

106.53

103.98

110.22

111.58

113.63

115.08

117.28

118.21

121.30

126.15

129.11

131.75

103.61

109.33

104.34

113.13

114.51

116.51

118.06

120.16

121.20

124.23

129.02

131.99

134.57

103.33

101.17

107.19

108.60

110.53

112.05

114.25

115.17

118.22

123.03

125.99

128.91

7.63

6.03

7.23

5.10

5.61

3.96

64

5.05

3.56

32

3.55

2.49

10

1.86

2.04

1.42

5

0.93

1.45

1.01

2.5

0.47

1.04

0.74

analog.com

Rev. 0 | 34 of 92

Data Sheet

AD4134

NOISE PERFORMANCE AND RESOLUTION

Table 15. Sinc3 Filter, High Performance Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel

Dynamic Range RMS Noise

−3 dB Bandwidth (kHz) (dB)

2:1 Channel Averaging

4:1 Channel Averaging

Output Data Rate

(kSPS)

Dynamic Range

(dB)

RMS Noise

(µV)

Dynamic Range

(dB)

(µV)

RMS Noise (µV)

1496

1000

750

375

187.5

128

64

391.503

261.70

196.28

98.14

49.07

33.50

16.75

8.37

95.32

49.64

24.03

16.82

9.63

6.58

5.29

3.72

2.61

1.50

1.11

0.83

0.66

0.54

0.38

0.39

0.40

98.67

33.74

16.18

11.51

6.76

4.53

3.72

2.60

1.80

1.06

0.78

0.60

0.48

0.39

0.29

0.30

0.28

101.46

107.97

110.97

115.59

119.04

120.72

123.88

126.87

131.54

134.17

136.30

138.08

139.79

142.62

141.81

141.65

24.48

11.56

8.19

4.81

3.23

2.66

1.85

1.31

0.76

0.56

0.44

0.36

0.29

0.21

0.23

101.62

104.72

109.56

112.88

114.76

117.83

120.91

125.74

128.29

130.89

132.91

134.66

137.59

137.46

137.22

105.05

108.01

112.64

116.11

117.81

120.91

124.10

128.66

131.34

133.60

135.52

137.28

139.89

139.49

140.07

32

16

4.19

5

1.31

2.5

0.654

0.327

0.164

0.016

0.013

0.003

1.25

0.625

0.06

0.05

0.01

Table 16. Sinc3 Filter, Low Power Mode Noise Performance vs. Output Data Rate (V_REF= 4.096 V)

Single Channel 2:1 Channel Averaging

Dynamic Range RMS Noise

4:1 Channel Averaging

Output Data Rate

(kSPS)

−3 dB Bandwidth

(kHz)

Dynamic Range

(dB)

RMS Noise

(µV)

Dynamic Range

(dB)

(µV)

RMS Noise (µV)

1496

1000

750

375

187.5

128

64

391.503

261.70

196.28

98.14

49.07

33.50

16.75

8.37

76.68

424.32

156.58

78.89

33.77

11.08

8.65

79.72

299.01

109.66

126.6

24.94

7.78

82.62

214.21

79.17

39.00

19.52

5.50

4.40

3.00

2.11

85.34

88.44

91.26

91.30

87.19

97.41

98.67

101.30

111.42

113.50

116.70

119.73

124.65

127.59

130.24

133.05

135.23

140.07

139.98

140.67

103.42

114.42

116.36

119.69

122.74

127.7

108.35

110.49

113.73

116.75

121.75

124.63

127.47

130.07

132.59

137.95

137.87

138.06

6.12

5.96

4.23

32

4.21

2.98

16

4.19

2.37

1.69

1.19

0.86

0.63

0.48

0.37

0.23

5

1.31

1.70

1.20

130.54

133.21

135.59

137.85

141.77

141.97

141.78

2.5

0.654

0.327

0.164

0.016

0.013

0.003

1.23

0.89

1.25

0.625

0.06

0.05

0.01

0.91

0.64

0.68

0.50

0.37

0.28

0.37

0.29

0.36

0.26

analog.com

Rev. 0 | 35 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

When the device is powered down, with the PDN pin low, in sleep

mode, or with the PWRDN_CHx bits, the input behaves with high

impedance.

CORE SIGNAL CHAIN

Each ADC channel on the AD4134 has an identical signal path from

the analog input pins to the data interface. Each ADC channel has

its own CTSD modulator that oversamples the analog input and

passes the digital representation to the digital filter block. The data

is filtered, scaled for gain and offset (depending on user settings),

and then output on the data interface. Control of the flexible settings

for the signal chain is provided by either using the pin control or the

SPI control set at power-up by the state of the PIN/SPI input pin.

Input Voltage Range

The resistive input structure of the AD4134 allows its input pins

to tolerate wide input voltage swings without damaging the device.

With the ADC full-scale input being ±V_REF, each of the ADC input

pins can accept absolute input voltages from 0 V to 5 V.

The ADC can use up to a 5 V reference and converts the differential

voltage between the analog inputs (AINx+ and AINx−) into a digital

output. The analog input accepts only differential input. The ADC

converts the voltage difference between the analog input pins into a

digital code on the output. Using a common-mode voltage of V_REF/2

for the analog inputs, AINx+ and AINx−, maximizes the ADC input

range. The 24‑bit conversion result is in twos complement, MSB

first format. See Table 17 for more details.

When the individual ADC input channel is powered down, the input

is high impedance.

Input Common-Mode Range

The AD4134 supports an input common-mode range from V_REF/2 to

AVDD5/2. Optimal performance is achieved with the input common-

mode level equal to half of the reference input voltage.

VCM OUTPUT

ANALOG INPUTS

Input Structure

The AD4134 provides a buffered common-mode voltage output on

the VCM pin. This output can shift the level of the analog input

signals. By incorporating the VCM buffer into the ADC, the AD4134

reduces component count and board space.

Due to the CTSD architecture, the AD4134 has a pure resistive

input, with a simplified input structure diagram, as shown in Figure

65. The ADC supports only fully differential input signals. The input

impedance has a differential resistance value of 6.25 kΩ. Internally,

both AINx+ and AINx− are biased to V_REF/2 through the internal

resistor network. The AD4134 achieves optimal performance with a

differential input signal that has a common-mode voltage equal to

V_REF/2. In Figure 65, C_INmeans input capacitance and R_INmeans

input resistance.

In pin control mode, the VCM potential is fixed to V_REF/2 and is

enabled by default.

In SPI control mode, the user has the option to program the VCM

output voltage level from V_REF/20 to 19 × V_REF/20, or AVDD5/2. The

user can also choose to disable the VCM output if not used in SPI

control mode.

The VCM output level can be configured through the VCMBUF_

REF_DIV_SEL bits and the VCMBUF_REF_SEL bit. The VCM

output can be enabled or disabled using the PWRDN_VCMBUF bit.

When disabled, the VCM behaves with high impedance.

When driving capacitive loads larger than 0.1 µF, it is recommended

to place a 50 Ω series resistor between the VCM pin and the

capacitive load to ensure the stability of the output buffer.

Figure 65. ADC Input Structure

Table 17. Output Codes and Ideal Input Voltages

Description

Analog Input (AINx+ − AINx−), V_REF= 4.096 V

Digital Output Code, Twos Complement (Hex)

Full Scale (FS) − 1 LSB

Midscale + 1 LSB

Midscale

4.095999512 V

488 nV

0x7FFFFF

0x000001

0x000000

0xFFFFFF

0x800001

0x800000

0 V

Midscale − 1 LSB

−FS + 1 LSB

−FS

−488 nV

−4.095999512 V

−4.096 V

analog.com

Rev. 0 | 36 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

REFERENCE INPUT

CLOCK INPUT

Similar to the ADC inputs, the AD4134 reference input is also resis-

tive, which allows the external reference IC to drive the AD4134

directly without the need of a reference buffer. The user can directly

connect the external reference source to the REFCAP pin of the

AD4134.

The AD4134 uses an internal oscillator during the initial power-up

configuration. After the AD4134 has completed the start-up routine,

a clock handover to the externally applied CLKIN occurs.

The AD4134 supports two master clock input options. The device

can accept an external CMOS clock signal or generate the clock

signal using an external crystal. The clock source is determined at

power-on by the state of the CLKSEL pin.

Tie the CLKSEL pin to the IOVDD pin and connect an external

crystal between the XTAL1 pin and the XTAL2/CLKIN pin to enable

the crystal clock option. Tie the CLKSEL pin to the IOGND pin and

connect an external CMOS clock signal to the XTAL2/CLKIN pin to

enable the CMOS clock option.

Figure 66. Direct Reference Input Connection to REFCAP Pin

The user can reduce the noise on the reference source by filtering

the reference signal. An internal 20 Ω resistor between the REFIN

pin and the REFCAP pin enables the user to form a first-order RC

filter by connecting a capacitor on the REFCAP pin.

Figure 68. Master Clock Provided by a Crystal

See the Reference Noise Filtering section for examples on how to

design the reference filter.

Figure 69. Master Clock Provided by an Oscillator

Figure 67. Reference Input Connection Using REFIN Pin

XCLKOUT OUTPUT

When using the crystal clock option, a buffered output from the

internal crystal oscillator can be made available on the XCLKOUT

pin. Distribute this CMOS clock signal to other AD4134 devices in

the same system to allow multiple AD4134 devices to operate from

a single external crystal. The XLKCOUT pin can drive 45 pF of

load.

The series resistor creates a small voltage drop that varies with

the device mode of operation. In SPI control mode, the user can

configure the device to autocorrect this drop in different operating

modes by setting the REFIN_GAIN_CORR_EN bit to 1. The refer-

ence input current reduces by 1/4 with the disable of each individual

ADC channel. This reduction in current is also accounted for with

the reference autocorrection function.

The autocorrection function is disabled in pin control mode.

The reference input behaves with high impedance when the device

is powered down or in power down mode with the PDN pin low.

analog.com

Rev. 0 | 37 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

The typical power consumption in this mode is 15 mW. The device

can resume full operation within 100 µs after exiting this mode.

Both the reference input and input channels go high-Z in

sleep mode.

Full Power-Down

The full power-down mode is activated by holding the PDN pin low.

All internal blocks are powered down in this mode.

The typical power consumption in this mode is 1 mW. The device

requires a power-up time of 10 ms after exiting this mode. After

exiting this mode, the device registers are reset to the default value.

Both the reference input and input channels go high-Z in

sleep mode.

Figure 70. Provide Master Clock to Multiple Devices from a Single Crystal

RESET

When reset, the AD4134 restores the internal register values to the

default and resets the internal logics and functional blocks.

The XCLKOUT output is enabled by default in pin control mode

if the crystal clock options are selected. The XCLKOUT output is

disabled in pin control mode if the CMOS clock option is selected.

Two methods exist for the user to reset the AD4134: through a hard

reset by pulling the RESET pin low, or through a software reset by

writing 1 to SOFT_RESET (self clears).

The XCLKOUT output is disabled by default in SPI control mode

and can be enabled by writing 1 to the XCLKOUT_EN bit.

ASYNCHRONOUS SAMPLE RATE

CONVERTER

POWER OPTIONS

Operating Power Modes

One unique property of the CTSD modulator architecture is having

a fixed time constant. As a result, the AD4134 device operates at a

fixed modulator clock frequency.

Depending on the bandwidth of interest for the measurement, the

AD4134 allows the user to trade measurement bandwidth with

power consumption or resolution through its two selectable power

modes: high performance and low power. The low power mode

operates with half the modulator clock frequency, resulting in com-

parable noise performance to the high performance mode at half

of the output data rate and 40% of power saving. For details of

the performance difference between the two modes, see the Noise

Performance and Resolution section.

To facilitate the accurate adjustment of the output data rate, the

AD4134 features a digitally programmable ASRC.

The ASRC is placed between the modulator and the digital filter of

each ADC channel. The ASRC has the following two inputs:

► Data that comes at the MCLK rate from the modulator

► ODR input, which is either an external asynchronous signal

(slave) or a fractional value (master)

Channel Power-Down

In SPI control mode, the four ADC channels can be individually

powered down to save power when not used.

The PWRDN_CHx bits control the power-down of each channel.

Powering down an ADC channel reduces the supply current and

the input current. The input of a powered down channel goes high-

Z. The reference input current reduces by 1/4 with the power-down

of each ADC channel.

Figure 71. Data Rate at Each Stage of Conversion Path

Sleep Mode

The digital PLL present in the ASRC block tracks and locks on

the ODR input and generates a fractional ratio. The ASRC works

through interpolation and resampling of the modulator output at a

fractional ratio to the sampling frequency of the modulator.

Sleep mode can be activated in SPI control mode by setting the

SLEEP_MODE_EN bit to 1.

In this mode, the device powers down all the blocks except the

digital LDO regulator and it retains its on-chip register values.

analog.com

Rev. 0 | 38 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

The interpolation factor depends on the ODR selected. The frac-

tional sample rate conversion of the ASRC allows the final ODR to

be asynchronous to the sampling clock of the modulator.

The output of the ASRC is then decimated by an integer in the

digital filter to produce the final ODR.

The ASRC only response depends on the ODR selected and has

a notch at the value of interpolation factor × ODR frequency. The

interpolation factor values for the various ODRs are shown in Table

18.

Table 18. Interpolation Factor Values for Different ODR Ranges

ODR Range

Interpolation Factor Value

750 kSPS to 1.496 MSPS

375 kSPS to 749.999 kSPS

366.99 SPS to 374.999 kSPS

10 SPS to 366.99 SPS

8

16

32

1024

Figure 73. Response for ODR of 1496 kSPS

For example, the ASRC response for an ODR of 374 kSPS shows

a notch at 32 × 374 kHz = 11.968 MHz, as shown in Figure 72.

The available output data rate range varies based on the digital

filter type and the ASRC mode selected (see the Digital Filters

section for more information).

The ASRC on the AD4134 has the following two modes of opera-

tion:

► In master mode, the ODR pin is output and the ODR is set

through the pin configuration or a register write.

► In slave mode, the ODR pin is input to the AD4134 and the ODR

is set with an external clock source.

ASRC Master Mode

In master mode, the ASRC resamples the interpolated modulator

output at a fixed ratio to the modulator clock (see Figure 74). The

ratio is internally calculated based on the user setting of the final

ODR. The user can configure the ODR through configuration of the

ODR pin in pin control mode or through register configuration in SPI

control mode.

Figure 72. ASRC Only Response for ODR = 374 kSPS

In ASRC master mode, the ODR pin behaves as an output. It

produces a pulse train signal in the frequency of the output data

rate. The ADC output data is made available for sampling with

respect to the ODR signal. For details of the ASRC master mode

output data rate setting, see the ASRC Master Mode section.

Similarly, the ASRC response for an ODR of 1496 kSPS shows a

notch at 8 × 1496 kHz = 11.968 MHz, as shown in Figure 73.

Figure 74. ASRC Master Mode Functional Diagram

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Rev. 0 | 39 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

The user must provide continuous cycles of the ODR signal until

the PLL is locked by checking the STAT_PLL_LOCK bit and then

reading the data. Any change in the ODR value causes the PLL to

unlock and lock back again and requires a wait time before reading

data.

ASRC Slave Mode

In slave mode, the ODR pin behaves as an input (see Figure

75). The user sets the ODR by providing a clock or pulse train at

the desired ODR frequency (f_ODR) to the ODR pin. The AD4134

measures the ODR frequency using the input signal rising edge. An

internal digital PLL tracks the ODR pin input signal frequency and

uses it to set the resampling rate of the ASRC. The ADC output

data is made available for sampling with respect to the ODR signal.

The user must also ensure that the jitter on the ODR pin is not more

than 100 ns p-p to ensure that the performance is not degraded.

Figure 75. ASRC Slave Mode Functional Diagram

analog.com

Rev. 0 | 40 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

DIGITAL FILTERS

The AD4134 offers four types of digital filters: sinc3, sinc6, and two

wideband filters. The sinc3 filter type includes an additional setting

with 50 Hz/60 Hz rejection (see Table 19). In SPI control mode,

these filters can be chosen on a per channel basis. In pin control

mode, only one filter can be selected for all channels.

The digital filters available can be operated at any output data rate

within the range mentioned in Table 19, allowing the user to choose

the optimal input bandwidth and speed of the conversion vs. the

desired power mode or resolution.

Table 19. Digital Filter Options

−3 dB Band- ODR

Filter Name

width (Hz)

Range

Description

Sinc3 Filter

0.2617 × OD

R

0.01

Fast settling

kSPS to

1496 kS

PS

Figure 76. Sinc6 Filter Frequency Response

Sinc3 Filter with 50

Hz/60 Hz Rejection

0.2753 ×

ODR

0.01

Fast settling with simulta-

kSPS to neous 50 Hz and 60 Hz

1496 kS rejection when ODR = 50

PS

SPS

Sinc6 Filter

0.1861 ×

ODR

2.5

Balancing settling with re-

kSPS to jection

1.496 M

SPS

Wideband 0.433 × ODR

Filter

0.433 × ODR 2.5

kSPS to

Wideband low ripple filter

374 kSP

S

Wideband 0.10825 ×

ODR Filter (Available

Only in SPI Control

Mode)

0.108 × ODR 2.5

Wideband low ripple filter

kSPS to with lower bandwidth

374 kSP

S

Figure 77. Sinc3 Filter Frequency Response

The settling of the sinc6 filter is 6.5/ODR. For a 374 kSPS ODR, the

time to fully settled data is 17.37 µs.

Sinc Filters

The sinc filters on the AD4134 employ a cascaded integrator comb

(CIC) topology to produce a response similar to a sinc function,

equivalent to a running averaging operation on the output samples

from the ASRC. The sinc filters enable a low latency signal path,

useful for applications such as time domain analysis, measurement

of dc inputs, and for control loops. Two types of sinc filters are

available on the AD4134. The sinc6 filter offers a balance between

noise rejection and latency, whereas the sinc3 filter offers the

minimum latency path and supports a wide ODR range down to 10

SPS.

Figure 78. Sinc6 Filter Step Response

The sinc6 filter has a −3 dB bandwidth of 0.1861 × ODR, and

the sinc3 filter has a −3 dB bandwidth of 0.2617 × ODR. The

Noise Performance and Resolution section contains the noise per-

formance for the sinc filters across power modes and ODR values.

The settling of the sinc3 filter is 3.5/ODR cycles. Therefore, for a

374 kSPS ODR, the time to fully settled data is 9.35 µs.

analog.com

Rev. 0 | 41 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

Figure 79. Sinc3 Filter Step Response

Simultaneous 50 Hz and 60 Hz Rejection

Because the sinc filter rejects signals at the frequency around

integer multiples of the ODR, it can be used to reject undesired

interference at a specific frequency higher than the input band

of interest. Because the sinc3 filter supports an ODR down to

10 SPS, a typical application for the sinc3 filter is to make dc to low

bandwidth measurements while rejecting line frequencies at 50 Hz

or 60 Hz.

Figure 81. Sinc3 and Sinc6 Filter Response (ODR = 60 SPS)

When the output data rate is 10 SPS, simultaneous 50 Hz and

60 Hz rejection is obtained. The sinc3 filter provides 102 dB rejec-

tion at 50 Hz ± 1 Hz and 105 dB at 60 Hz ± 1 Hz.

Figure 80 shows the frequency response of the sinc3 filter when the

output data rate is programmed to 50 SPS. The sinc3 filter provides

102 dB rejection at 50 Hz ± 1 Hz.

Figure 82. Sinc3 and Sinc6 Filter Response (ODR = 10 SPS)

Simultaneous 50 Hz and 60 Hz rejection can also be achieved by

selecting the sinc3 and 50 Hz/60 Hz rejection filter path. When

the sinc3 filter places a notch at 50 Hz, the 50 Hz/60 Hz rejection

postfilter places a first-order notch at 60 Hz. The output data rate is

50 SPS. Figure 83 shows the frequency response of the sinc3 and

50 Hz/60 Hz rejection filter path. The rejection at 50 Hz and 60 Hz

(±1 Hz) is in excess of 67 dB.

Figure 80. Sinc3 and Sinc6 Filter Response (ODR = 50 SPS)

Figure 81 shows the frequency response of the sinc3 filter when the

output data rate is programmed to 60 SPS. The sinc3 filter provides

106 dB rejection at 60 Hz ± 1 Hz.

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Rev. 0 | 42 of 92

Data Sheet

AD4134

CIRCUIT INFORMATION

Figure 83. Sinc3 and 50 Hz/60 Hz Rejection Filter Response (ODR = 50 SPS)

Figure 85. Low Ripple Wideband 0.433 × ODR Filter and Wideband 0.10825 ×

ODR Filter Pass-Band Ripple

Wideband Low Ripple Filter

The wideband low ripple filter has a low ripple pass band, narrow

transition band, and high stop band rejection. The filter response

is close to an ideal brick wall filter, making it ideal for frequency

domain measurement and analysis.

Two wideband low ripple filter options are available on the AD4134:

one filter has a −3 dB corner at 0.433 × ODR, and the other filter

has a −3 dB corner at 0.10825 × ODR.

Both wideband low ripple filter options offer a pass-band ripple of

32 µdB and a stop band attenuation of −110 dB. For noise perform-

ance and resolution, see the Noise Performance and Resolution

section.

Figure 86. Low Ripple Wideband 0.433 × ODR Filter and Wideband 0.10825

Hz × ODR Filter Step Response

Figure 84. Low Ripple Wideband 0.433 × ODR Filter and Wideband 0.10825 ×

ODR Filter Frequency Response

analog.com

Rev. 0 | 43 of 92

Data Sheet

AD4134

QUICK START GUIDE

The AD4134 offers users a multichannel platform measurement

solution for ac and dc signal processing. Flexible filtering allows

the AD4134 to be configured to simultaneously sample ac and

dc signals on a per channel basis. The ASRC allows users to

granularly set the output data rate controlling the input bandwidth

of the measurement. This ability, coupled with the flexibility of

the digital filter, allows the user to choose the right application

settings and meet latency, bandwidth, and performance targets.

Key capabilities that allow users to choose the AD4134 as their

platform high resolution ADC are highlighted as follows:

► Wideband, low ripple, digital filter for ac measurement

► Fast sinc3 filter for precision low frequency, low latency measure-

ment

► Two ASRC modes (master mode and slave mode) allow user

flexibility in digital interface

► Two antialias modes enabling the user to choose higher levels of

alias rejection

► Choice of SPI or pin strapped configuration option

► Offset, gain, and phase calibration registers per channel

► Common-mode voltage output buffer to set the common-mode

voltage of the input

► On-board 1.8 V LDO regulators for single-supply operation

► Four fully differential analog inputs

► Fast throughput simultaneous sampling ADCs catering for input

signals up to 391.5 kHz

► Two selectable power modes (high performance and low power)

for scaling the current consumption and input bandwidth of the

ADC to achieve optimal measurement efficiency

Refer to Figure 87 and Table 20 for the typical connections and

minimum requirements to start using the AD4134.

Figure 87. Typical Connections Diagram

Table 20. Requirements to Operate the AD4134

Requirement

Description

5 V AVDD5 and DVDD5 supply, 1.8 V − IOVDD, CLKVDD, AVDD1V8, and DVDD1V8 (LT8606, LT8607)

Power Supplies

External Reference

Input Stage

4.096 V or 5 V (ADR444/ADR445)

AD8421, ADA4075-2, ADA4945-1, LTC6363, LTC6373

Crystal or a CMOS/LVDS clock for the ADC modulator sampling

1.65 V to 1.95 V digital I/O level

External Clock

Field Programmable Gate Array (FPGA)

or Digital Signal Processor (DSP)

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Rev. 0 | 44 of 92

Data Sheet

AD4134

QUICK START GUIDE

STANDALONE MODE

LOW LATENCY SYNCHRONOUS DATA

ACQUISITION

The user has a digital host without an SPI and needs a −3 dB input

bandwidth of 102.4 kHz. The user also desires a flat pass-band

response with robust data interface. The recommended scheme is

pin controlled master mode. The 102.4 kHz input bandwidth with

flat pass band can be achieved by using a 0.433 × ODR FIR filter.

The minimum ODR needed can be calculated as input bandwidth

= 0.433 × ODR. Therefore, the minimum ODR needed is 237

kSPS. From Table 28, the closest ODR value of 256 kSPS can be

programmed.

The user has an input signal bandwidth of 250 kHz and needs a

24-bit output with minimum latency. There are eight channels and

the user needs tight synchronization between the channels.

The recommended scheme is to use two devices in SPI controlled

slave mode. The external ODR signal can synchronize both devices

with a digital interface reset issued simultaneously. See the Multide-

vice Synchronization section for more details.

The 250 kHz input bandwidth with minimum latency can be ach-

ieved by the sinc3 filter. The minimum ODR needed can be calcu-

lated as input bandwidth = 0.2617 × ODR. Therefore, the ODR

required is 956 kSPS.

The robust interface calls for using the cyclic redundancy check

(CRC). Therefore, the frame size is 24 data bits + 8-bit header that

includes a 6-bit CRC and a 2-bit status.

The DCLK value required is >(Frame Size + 6) × ODR, giving the

user a value of 9.7 MHz. From Table 30, the closest DCLK option is

12 MHz.

The external DCLK value required is >(Frame Size + 6) × ODR,

giving the user a value of 29 MHz. Provide the DCLK and ODR

values as per the timing specifications listed in Table 3.

The settings to be configured are pin control mode control, ASRC

master, high performance mode, gated DCLK output, 32-bit frame,

256 kSPS ODR, 12 MHz DCLK, 0.433 × ODR filter, external LDO

regulator, and 4-channel output.

The settings to be configured are SPI control mode control, ASRC

slave, high performance mode, gated DCLK input, 24-bit data

output, 956 kSPS ODR, 29 MHz DCLK, sinc3 filter, external LDO

regulator, and 4-channel output.

Refer to the Device Configuration section for programming these

settings.

Refer to the Device Configuration section for programming these

settings. After power-on, verify the hardware configuration by read-

ing the DEVICE_STATUS register.

Table 21. Configuration 1 Hardware Settings

Pin Function

Supply/Level

Comments

Table 22. Configuration 2 Hardware Settings

AVDD5, DVDD5

5 V

Supply

Pin Function

Supply/Level

Comments

IOVDD, LDOIN, AVDD1V8,

DVDD1V8, CLKVDD

1.8 V

AVDD5, DVDD5

5 V

Supply

IOVDD, CLKVDD, AVDD1V8, LDOIN,

DVDD1V8

1.8 V

PIN/SPI

Low

Pin control

CLKSEL

High

Crystal input

PIN/SPI

High

SPI control

mode

MODE

High

ASRC master

Gated DCLK

DCLKMODE

DCLKIO

Low

CLKSEL

MODE

High

Low

Crystal input

ASRC slave

Gated DCLK

DCLK input

High

DCLK output

FILTER1, FILTER0

FORMAT1, FORMAT0

FRAME1, FRAME0

PWRMODE

Low, low

High, low

High, high

High

0.433 × ODR filter

4-channel output

32-bit output

DCLKMODE

DCLKIO

Program the registers in Table 23 with the values listed and leave

the all the other registers at their default values.

High performance

12 MHz DCLK

DCLKRATE2, DCLKRATE1,

DCLKRATE0

Low, low, high

Table 23. Software Settings

DEC3, DEC2, DEC1, DEC0

Low, low, high, high

256 kSPS ODR

SPI Register

Value

Comments

DATA_PACKET_CONFIG

DEVICE_CONFIG

0x20

0x01

0xAA

0x03

24-bit frame

High performance mode

Sinc3 filter

CHAN_DIG_FILTER_SEL

DIGITAL_INTERFACE_CONFIG

4-channel parallel

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Rev. 0 | 45 of 92

Data Sheet

AD4134

DEVICE CONTROL

The AD4134 has independent paths for reading data from the ADC

conversions and for controlling the device functionality.

PIN CONTROL MODE

Pin control mode eliminates the need for an SPI communication

interface. When a single known configuration is required by the

user, or when only limited reconfiguration is required, the number

of signals that require routing to the digital host can be reduced

using this mode. Pin control mode is useful in digitally isolated ap-

plications where minimal adjustment of the configuration is needed.

Pin control mode helps save on PCB design and eliminates routing

of digital lines.

For control, the device can be configured in either of the following

two modes:

► Pin control mode: pin strapped digital logic inputs (allowing a

subset of the configurability options to be used)

► SPI control mode: over a 3-wire or 4-wire SPI (complete configu-

rability)

On power-up, the state of the PIN/SPI pin determines the mode

used. SPI control mode offers a full set of configurability, including

access to the AD4134 internal diagnostic features. Pin control

mode offers a subset of selectable features in exchange for easy

configurability. The user can choose the mode of operation by the

voltage level applied to the PIN/SPI pin.

Pin control offers a subset of the core functionality and ensures a

known state of operation after power-up or reset. Pin control mode

selectable options include the following:

► Digital filter

► Frame size

► Data interface format

► Decimation rate and DCLK frequency

► High performance mode or low power mode

Along with the PIN/SPI pin, four additional pins must be configured

to ensure the correct operation of either SPI or pin control mode.

Table 24 shows a list of pin controlled functions that are common to

pin control mode and SPI control mode operation. The pins listed in

Table 24 are sampled only when the AD4134 is powered on.

Figure 88 shows pin configurable functions. All the pins except the

ones listed in Table 24 can be changed dynamically.

Table 24. Common Control Pin Function Summary

Refer to Figure 89 for more details. A limited set of diagnostics is

available and CLKOUT is enabled by default in pin control mode

only when the crystal option is selected.

Pin Mnemonic

Pin Function

PIN/SPI

MODE

Controls the mode selection, pin or SPI.

ASRC mode of operation selection, master or slave

mode operation.

CLKSEL

Input clock source selection, crystal or CMOS.

DCLK direction selection.

DEC0/DCLKIO

DEC1/DCLKMODE

Gated or Free Running DCLK selection.

Figure 88. Pin Control Mode Configurable Functions

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Rev. 0 | 46 of 92

Data Sheet

AD4134

DEVICE CONTROL

► XCLKOUT disable

SPI CONTROL MODE

► Option for wideband digital filter FIR 0.108 × ODR

► Digital interface reset

► Programmable gain, offset, and channel delay

► Sleep mode

™

The AD4134 has a 4-wire SPI that is compatible with QSPI

®

,

MICROWIRE , and DSPs. Using the SPI, the user can access the

ADC register map and control the AD4134.

To use SPI control mode, the PIN/SPI pin of the AD4134 must

be set to logic high. The SPI control operates as a 16-bit, 4-wire

interface, allowing read and write access. The SPI serial control

interface of the AD4134 is an independent path for controlling and

monitoring the AD4134. There is no direct link to the data interface.

The timing of ODR and DCLK is not directly related to the timing of

the SPI control interface. Refer to the SPI section for more details.

► 2-channel averaging

► Additional inherent alias mode (AA2)

► Programmable ODR, ODR/2, ODR/4, and ODR/8

► VCM pin output voltage programmability

► Per channel phase delay

MULTIFUNCTION PINS

The SPI control mode allows the user to configure more features

than the pin control mode and use the device fully. The additional

features available in SPI control mode are the following:

The AD4134 has multifunction pins where the function of these

pins changes depending on the selected control mode. Table 25

shows a summary of the multifunction pin functions in each mode of

operation.

► Full suite of diagnostic features

► More options for ODR select and DCLK frequency select in

master mode

Table 25. Multifunction Pin Function Summary

Pin Mnemonic

Pin Function in Pin Control Mode

Pin Function in SPI Control Mode

FORMAT0/CS

FORMAT1/SCLK

DEC3/SDO

ADC output channel format selection

SPI

ASRC master mode decimation ratio selection

DEC2/SDI

DEC1/DCLKMODE

ASRC master mode: decimation ratio selection

DCLK mode selection (free running or gated)

DCLK I/O direction selection (input or output)

General-purpose I/O

ASRC slave mode: DCLK mode selection (free running or gated)

ASRC master mode: decimation ratio selection, DCLK is output

ASRC slave mode: tie pin low to set it as input

DEC0/DCLKIO

DCLKRATE0/GPIO0

DCLKRATE1/GPIO1

DCLKRATE2/GPIO2

PWRMODE/GPIO3

FILTER0/GPIO4

DCLK output frequency selection in ASRC master mode

Device power mode selection (high performance or low power mode)

Digital filter type selection

FILTER1/GPIO5

FRAME0/GPIO6

Output data frame selection

FRAME1/GPIO7

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Data Sheet

AD4134

DEVICE CONFIGURATION

to the pulse frequency. This feature gives the user the flexibility

PROGRAMMING OUTPUT DATA RATE AND

CLOCK

to update the frequency of the external pulse dynamically, which

changes the ODR value, but there is a loss of data during a change

over time plus the filter settling time. The change over time is

dominated by the unlocking and locking of the PLL that tracks the

ODR. For ODR values of >10 kSPS, a change of ODR value to

less than 500 SPS does not cause the PLL to unlock and lock back

again, allowing seamless data. Refer to Table 27 for change over

time for ODR ranges for various filters in slave mode.

Output Data Rate

AD4134 can be programmed to any output data rate from 10 SPS

to 1496 kSPS. Depending on the MODE pin configuration, the ODR

can be generated by the AD4134 or provided externally. When the

AD4134 generates the ODR, the mode is called master mode, and

when ODR is provided externally, the mode is called slave mode.

For Example 1, if the user changes the ODR value from 300 kSPS

to 2500 SPS while using the digital FIR filter, the change over time

is 22 ms + 512/2500 = 226.8 ms.

Table 26. Mode Pin Configuration

MODE Pin

ASRC Mode of Operation

ODR Pin Direction

0

1

Slave

Input

For Example 2, if the user changes the ODR value from 1 MSPS to

500 kSPS while using a sinc3 digital filter, the change over time is

11 ms + 512/500,000 = 12 ms.

Master

Output

ASRC Slave Mode

The supported ODR range varies by the power mode and the digital

filter type selected (see Table 19 for more details).

In ASRC slave mode, the ODR is controlled by a continuous exter-

nal pulse signal connected to the ODR pin, with the ODR equal

Table 27. ODR Change Over Time in Slave Mode

ODR Range

FIR

Sinc6

Sinc3

750 kHz to 1.46 MHz

374 kHz to 750 kHz

365 kHz to 374 kHz

2.5 kHz to 365 kHz

1.46 kHz to 2.5 kHz

732 SPS to 1.46 kHz

366 SPS to 732 SPS

183 SPS to 366 SPS

91.5 SPS to 183 SPS

45.7 SPS to 97.5 SPS

22.8 SPS to 45.7 SPS

11.4 SPS to 22.8 SPS

10 SPS to 11.4 SPS

Not applicable

5.5 ms + 512/ODR

11 ms + 512/ODR

22 ms + 512/ODR

Not applicable

5.5 ms + 512/ODR

11 ms + 512/ODR

22 ms + 512/ODR

44 ms + 512/ODR

88 ms + 512/ODR

6 sec + 512/ODR

12 sec + 512/ODR

24 sec + 512/ODR

48 sec + 512/ODR

96 sec + 512/ODR

192 sec + 512/ODR

Not applicable

ODR range not supported in slave mode

22 ms + 512/ODR

Not applicable

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Rev. 0 | 48 of 92

Data Sheet

AD4134

DEVICE CONFIGURATION

Program ODR_VAL_FLT, Bits[31:0] with 0x2F4103E5.

ASRC Master Mode

In Example 2, for an ODR to be 375 kSPS, calculate the decimation

rate as follows:

In ASRC master mode, the AD4134 device generates the output

data at a programmable decimation ratio. The user can program the

decimation ratio in both pin control and SPI control mode to achieve

the desired output date rate.

Decimation Rate = 24 MHz/375 kHz = 64 = 0x00004000000000

Program ODR_VAL_INT, Bits[23:0] with 0x000040.

In pin control mode, the decimation rate is fixed as per the pre-

defined pin control options. Sixteen decimation ratio options are

available through the configuration of the DEC0/DCLKIO pin to

DEC3/SDO pin. The final ODR value also depends on the digital

filter type. Table 28 summarizes the ODR values available in master

mode.

Program ODR_VAL_FLT, Bits[31:0] with 0x00000000.

Every time the ODR_VAL_INT, Bits[23:0] and ODR_VAL_FLT,

Bits[31:0] are changed, the MASTER_SLAVE_TX_BIT in the

TRANSFER_REGISTER must be set to update the ODR to the

new value.

In SPI control mode, the ODR is available at the full range

described in Table 19. The ODR can be programmed via the

ODR_VAL_INT, Bits[23:0] bits and ODR_VAL_FLT, Bits[31:0] bits

with a resolution of 0.01 SPS.

The user has the flexibility to change the ODR value, but that

means a loss of data of about 2 µs plus the filter settling time. The 2

µs time, t_DELAY, is constant across the ODR range. See Figure 89

for more details.

In Example 1, for an ODR to be 187.23 kSPS, calculate the

decimation rate as follows:

The SPI control mode also allows the user to set a differ-

ent ODR rate for each of the four ADC channels using the

ODR_RATE_SEL_CHx bits. The ODR options are limited to 1, ½,

¼, or ⅛ of the ODR frequency.

Decimation Rate = 24 MHz/187.23 kHz =

24 MHz/187.23 kHz = 128.1846 = 0x0000802F4103E5

Program ODR_VAL_INT, Bits[23:0] with 0x80.

Table 28. Output Data Rate Configuration in Pin Control Master Mode

DEC3

DEC2

DEC1

DEC0

Wideband 0.433 × ODR Filter (kSPS)

Sinc6 Filter (kSPS)

Sinc3 Filter (kSPS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

374

325

285

256

235

200

175

128

100

80

1496

1250

1000

750

500

375

325

256

175

128

80

1496

1000

750

375

187.5

128

64

32

16

5

64

2.5

32

64

1.25

0.625

0.06

0.05

0.01

16

32

10

5

2.5

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Data Sheet

AD4134

DEVICE CONFIGURATION

Figure 89. Master Mode ODR Change Over

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Data Sheet

AD4134

DEVICE CONFIGURATION

when operating in SPI control mode, the DCLK mode of operation

is controlled by the DEC1/DCLKMODE pin and DEC0/DCLKIO pin,

as shown in Table 29.

Data Clock (DCLK)

The data clock can be either an input or an output depending

on the direction of the ODR pin. When ODR is output for master

mode, set the DEC0/DCLKIO pin high to configure DCLK as an

output. When ODR is input for slave mode, tie the DEC0/DCLKIO

pin low to configure DCLK as an input. The data clock can be

operated in gated mode or free running mode controlled by the

DEC1/DCLKMODE pin.

In master mode, the DCLK pin is configured as an output. The

DCLK frequency is derived from the AD4134 device master clock

and can be configured using the DCLKRATE0/GPIO0 pin to

DCLKRATE2/GPIO2 pin in pin control mode, or DCLK_ FREQ_SEL

(Bits[3:0]) in Register 0x11 in SPI control mode. SPI control mode

offers 16 DCLK output frequency options, and pin control mode

offers eight. Table 30 lists all the DCLK output frequency options.

When operated in pin control mode with the ASRC set to master

mode, the DCLK operation is limited to gated output only. When

operating in pin control mode with the ASRC set to slave mode, or

In slave mode, the DCLK pin is an external signal.

Table 29. DCLK Mode of Operation in Pin Control Mode or in SPI Control Mode

DEC1/DCLKMODE

DEC0/DCLKIO

MODE

DCLK Direction

DCLK Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Input

Gated

Reserved

Output

Reserved

Gated

Input

Free running

Reserved

Free running

Reserved

Output

Table 30. DCLK Output Frequency Configuration

DCLKRATE2 or Register 0x11, DCLKRATE1 or

DCLKRATE0 or

Bit 3

Register 0x11, Bit 2

Register 0x11, Bit 1

Register 0x11, Bit 0

DCLK Output Frequency Options

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

48 MHz (SPI/pin control mode default)

24 MHz¹

12 MHz

6 MHz¹

3 MHz

1.5 MHz¹

750 kHz

375 kHz¹

187.5 kHz

93.75 kHz¹

46.875 kHz

234.375 kHz¹

11.71875 kHz

5.859375 kHz¹

2.929688 kHz

1.464844 kHz¹

1

Not available in pin control mode.

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Data Sheet

AD4134

DEVICE CONFIGURATION

via the DIGFILTER_SEL_CHx bits and the additional digital filter

type (wideband 0.10825 × ODR filter or wideband 0.433 × ODR

filter) via the WB_FILTER_ SEL_CHx bits, where x is the channel

number from 0 to 3. Table 31 lists all the digital filter options.

PROGRAMMING DIGITAL FILTER

In pin control mode, four digital filter types are available through the

configuration of the FILTER1/GPIO5 pin and FILTER0/GPIO4 pin.

All four ADC channels share the same digital filter type.

To configure the digital filter dynamically, change the digital filter

first and then change the output data rate to ensure proper opera-

tion.

One additional digital filter type, wideband 0.10825 × ODR filter, is

available only in SPI control mode. In SPI control mode, the digital

filter type can be configured independently for each ADC channel

Table 31. Digital Filter Configuration

FILTER1 or DIGFILTER_SEL_CHx, Bit 1

FILTER0 or DIGFILTER_SEL_CHx, Bit 0

WB_FILTER_SEL_CHx, Bit 0

Digital Filter Type

0

1

0

1

0

1

0

Wideband 0.433 × ODR filter

Wideband 0.10825 × ODR filter¹

Sinc6

1

X²

Sinc3

Sinc3 with additional 60 Hz rejection

1

Available in SPI control mode only.

2

X means don’t care.

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Data Sheet

AD4134

DEVICE CONFIGURATION

fewer pins. Paralleling the output enables a higher output data

PROGRAMMING DATA INTERFACE

rate for a given DCLK frequency. In addition to using fewer I/Os,

serializing the data allows data from multiple AD4134 devices to be

daisy-chained.

The digital interface consists of setting up the format, the frame,

and the averaging options.

The output channel format is controlled by the FORMAT0/ pin and

FORMAT1/SCLK pin in pin control mode and the format bits in the

DIGITAL_INTERFACE_CONFIG register in SPI control mode.

Output Channel Format

The data interface format is determined by setting the FOR-

MAT0/CS pin and FORMAT1/SCLK pin. The logic state of the

FORMAT0/CS pin and FORMAT1/SCLK pin is read on power-up

and determine how many data lines (DOUTx) the ADC conversions

are output on.

Table 32 lists all the output channel format options.

Because the FORMAT0/CS pin and FORMAT1/SCLK pin are read

on power-up of the AD4134 and the device remains in this output

configuration, this function must always be hardwired and cannot

be altered dynamically. Figure 90 and Figure 91 show the format-

ting configuration for the digital output pins on the AD4134.

Calculate the minimum required DCLK rate for a given data inter-

face configuration as follows:

Figure 90. FORMAT1, FORMAT0 = 10, Four Data Output Pins

DCLK (Minimum) = Output Data Rate × Channels per DOUTx ×

(Frame Size + 6)

For example, if data size = 24 and 6-bit CRC is enabled with one

DOUTx line, single-channel daisy-chaining,

DCLK (Minimum) = 374 kSPS × 4 Channels per DOUTx × (24 + 8 +

6) = 44.88 Mbps

Figure 91. FORMAT1, FORMAT0 = 00, One Data Output Pin

The AD4134 can output the data from four ADC channels in parallel

using four output pins, or serialize the data and output them using

Table 32. Output Channel Format Configuration

FORMAT1/SCLK Pin or Bit 1,

FORMAT0/ Pin or Bit 0,

DIGITAL_INTERFACE_CONFIG DIGITAL_INTERFACE_CONFI

Register

G Register

Output Channel Format

0

Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a daisy-chain input.

DOUT1 and DOUT3 are disabled. Data from all four ADC channels are serialized and output on DOUT0

(SPI default mode).

0

1

Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as outputs, and DOUT2 and DOUT3 act as

daisy-chain inputs. Data from Channel 0 and Channel 1 are serialized and output on DOUT0. Data from

Channel 2 and Channel 3 are serialized and output on DOUT1.

1

0

1

Quad-channel parallel output mode. Each ADC channel has a dedicated data output pin.

Channel data averaging mode. In pin control mode, data from all four channels are averaged and output

on DOUT0. DOUT2 acts as daisy-chain input. DOUT1 and DOUT3 are disabled. In SPI control mode, the

averaging operation is defined by the AVG_SEL bits in Register 0x12.

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Data Sheet

DEVICE CONFIGURATION

Data Frame

AD4134

The AD4134 supports two data length options: 16‑bit and 24-bit.

The AD4134 also supports one CRC-6 header option. Table 33 lists

all the output data frame options.

The frame of each ADC sample output data consists of the data

followed by an optional status/CRC header.

Table 33. Data Frame Options

FRAME1/GPIO7 Pin or Bit 1, DATA_PACKET_CON- FRAME0/GPIO6 Pin or Bit 0, DATA_PACKET_CON-

FIG Register

Data Frame

Frame Length

0

1

0

1

0

1

16-bit ADC data

16

24

32

16‑bit data with CRC-6

24-bit ADC data

24-bit data with CRC-6

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Data Sheet

DEVICE CONFIGURATION

Data Delay

AD4134

toggle it back to low. In SPI control mode after power-up, change

the POWER_MODE bit from low to high and after a delay of 10 ms

change it back to low.

The data output of each channel of the AD4134 can be individually

delayed by 0, 1, or 2 MCLK cycles using the MPC_CONFIG

register. The front-end signal chain components can add varying

amounts of phase delay depending on factors like gain setting and

filtering. This feature gives the user flexibility to match the delays

on different channels and thus achieving tight phase matching

between channels.

Also, in pin slave mode, first provide the ODR signal and then

change the power mode to ensure dynamic sampling of the

PWRMODE/GPIO3 pin.

INHERENT ANTIALIASING FILTER MODES

The CTSD architecture allows the AD4134 to reject signals around

the integer multiples of the modulator sampling frequency, protect-

ing its input band of interest from aliasing. The AD4134 offers two

antialiasing modes. The default antialiasing mode, AA1, offers a

typical 85 dB of aliasing rejection.

POWER MODES

The AD4134 offers two power modes, high performance mode and

low power mode. These modes are available in both pin control

mode and SPI control mode. In pin control mode, the PWRMODE/

GPIO3 pin controls the AD4134 operating power mode. In SPI

control mode, the POWER_MODE bit controls the power mode.

Additional sleep mode is available in SPI control mode. Table 34

summarizes the power mode configurations. In both pin control

mode and SPI control mode, a full device power-down can be

initiated through the pin.

The other antialiasing mode, AA2, improves the rejection to 102.5

dB with the cost of a higher offset drift of 1.03 µV/°C, additional

power consumption of 3 mW per channel, and higher noise level

with dynamic range reduction.

The AA2 mode is only available in SPI control mode and can be

enabled by setting the AA_MODE bit to 1.

Table 34. Power Mode Configuration

Table 35 shows typical performance differences in inherent antialias

modes. The filter is wideband 0.433 × ODR FIR filter, and the ODR

value is ODR = 374 kSPS.

PWRMODE/GPIO3 or

POWER_MODE Bit

SLEEP_MODE_EN

Device Power Mode

0

1

X

0

1

Low power mode

High performance mode

Sleep mode

Table 35. Performance Difference in Inherent Antialias Modes

Parameter

AA1 Mode

AA2 Mode

Dynamic Range

SNR

107.4 dB

106.6 dB

85 dB

105.9 dB

105.4 dB

102.5 dB

1.03 µV/°C

129 mW

To operate the device correctly in low power mode, the user must

toggle the setting from low power mode to high performance mode

and back to low power mode.

Alias Rejection

Offset Drift

0.5 µV/°C

126 mW

In pin control mode, to set the AD4134 in low power mode, toggle

the PWRMODE/GPIO3 pin to high and after a delay of 10 ms

Power per Channel

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Rev. 0 | 55 of 92

Data Sheet

AD4134

DYNAMIC RANGE ENHANCEMENT, CHANNEL AVERAGING

The AD4134 is equipped with built-in 4-channel and 2-channel

averaging functions that increase the performance by 6 dB and 3

dB. The device performs on-board averaging of the output data

from two or four of its ADC channels to improve the dynamic range.

Averaging is a digital postprocessing option after the digital filter,

which performs averaging of the output data from multiple ADC

channels. This averaging feature allows the user to measure a sig-

nal with multiple ADC channels and average the result to achieve

higher dynamic range.

In 4:1 averaging mode, a single input signal is applied to all four

input channels, as shown in Figure 92. In this mode with averaging

enabled, the AD4134 is a single-channel device with the dynamic

range improved by 6 dB.

Figure 93. 2:1 Channel Averaging

In 2:1 averaging mode, a single input signal is applied to two input

channels, as shown in Figure 93. In this mode with averaging

enabled, the AD4134 behaves as a 2-channel device with each

channel dynamic range improved by 3 dB.

In pin control mode, only 4:1 averaging is available through the

configuration of the FORMAT0/ pin and FORMAT1/SCLK pin, as

shown in Table 32.

For noise performance of channel averaging, see the Noise Per-

formance and Resolution section.

In SPI control mode, set the format bits, Bits[1:0] in Register 0x12

to 11 to enable the output averaging function. Then use Bits[3:2] in

Register 0x12 to select the channel averaging options.

Figure 92 and Figure 93 show the connection diagrams for using

these functions. For 4:1 channel averaging, short all four inputs

together, but for 2:1 channel averaging short two inputs together.

Figure 92. 4:1 Channel Averaging

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Data Sheet

AD4134

CALIBRATION

In SPI control mode, the AD4134 offers the ability to calibrate offset

and gain individually for each channel. The user can alter the gain

and offset of the AD4134 and subsystem.

The offset range is ±V_REFwith a step size of V_REF/2²². An LSB of

offset register adjustment changes the digital output by 2 LSBs. For

example, changing the offset register from 0 to 100 changes the

digital output by 200 LSBs.

Each channel of the ADC has an associated gain and offset

coefficient that is stored for each ADC after factory programming.

The user can overwrite these gain and offset coefficients using the

gain and offset correction registers. However, after a reset or power

cycle, the gain and offset register values revert to the hard coded,

programmed factory setting.

For additional register information, see the OFFSET_CAL_

EN_CHx bit descriptions in Table 81, Table 87, Table 93, and Table

99.

GAIN CALIBRATION

The gain register is 20 bits with a range of ±50% and the LSB

applying a gain of 0.95 ppm. The gain setting for each channel is

enabled using the GAIN_CAL_SEL_CHx bits.

These options are available in SPI control mode only.

OFFSET CALIBRATION

The offset correction registers provide 23-bit, signed, twos comple-

ment registers for channel offset adjustment. The offset setting for

each channel is enabled using the OFFSET_CAL_ EN_CHx bits.

For additional register information, see the GAIN_CAL_ SEL_CHx

bit descriptions in Table 78, Table 84, Table 90, and Table 96.

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Data Sheet

AD4134

APPLICATIONS INFORMATION

Figure 94. Typical Application Diagram

POWER SUPPLY

The AD4134 has a total of seven power supply input pins: AVDD5,

DVDD5, LDOIN, AVDD1V8, DVDD1V8, CLKVDD, and IOVDD.

Refer to the power supply voltages in Table 1 for operating supply

voltage values for 4.096 V and 5 V reference inputs.

To simplify the power supply design, the user can supply the

AVDD5 pin and DVDD5 pin together with a single, low noise

5 V supply, and supply the AVDD1V8, DVDD1V8, CLKVDD, and

IOVDD pins together with a single low noise 1.8 V supply.

To generate 5 V and 1.8 V rails, the power circuits using LT8606

or LT8607 provide a low EMI, small size solution supporting a wide

range of input voltages.

On-Board LDO Regulators

To simplify the power supply design, the AD4134 provides three

internal LDO regulators to generate the 1.8 V required for the

AVDD1V8, DVDD1V8, and CLKVDD pins from a single 2.6 V to 5.5

V supply connected to the LDOIN pin, as shown in Figure 95.

Figure 95. Internal LDO Regulator Connections

If the internal LDO regulators are used, the AVDD1V8, DVDD1V8,

and CLKVDD pins must be decoupled with a 10 µF, 10 µF, and 2.2

µF capacitor, respectively, to their respective grounds, as shown in

Figure 96.

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Data Sheet

AD4134

APPLICATIONS INFORMATION

Figure 96. Internal LDO Regulator Mode Power Connections

The internal LDO regulators are enabled only when the IOVDD

supply is powered up first by an external 1.8 V supply.

Figure 99. Reference Input Connection Using REFIN Pin

The equivalent noise bandwidth of a first-order filter is 0.25/RC in

Hz.

The internal LDO regulators work properly if the power supply

sequence in Figure 97 is followed. Ensure that the IOVDD and

LDOIN pins are powered after DVDD5, as shown in Figure 97.

The noise contribution of the reference source is proportional to the

ADC input signal. The reference noise contribution is at the highest

when the input signal is at full scale. The reference noise has no

impact on the output when the ADC inputs are shorted.

As a general rule, limit the reference noise to ¼ of the noise of the

ADC to have a minimal effect on the overall SNR.

Figure 97. Power Sequencing in Internal LDO Mode

The total reference noise is the root sum square of its 1/f noise and

its wideband noise.

If the internal LDO regulators are not used, tie the LDOIN pin to

DVDD1V8, as shown in Figure 98.

The 1/f noise of the reference can be estimated by its peak-to-peak

noise specification over the 0.1 Hz to 10 Hz frequency range. The

wideband noise can be calculated from the voltage noise density

specification of the reference and the reference noise bandwidth.

An example to calculate the reference noise requirement based on

the ADC mode of operation follows.

Consider the AD4134 device that is operating in high performance

mode, ODR = 374 kSPS, and wideband 0.433 × ODR filter with a

reference voltage of 4.096 V.

Figure 98. External Power Mode Connections

According to Table 9, the ADC noise in this setup is 12.63 µV rms.

The reference noise is ¼, equal to 3.16 µV rms.

If AVDD1V8, DVDD1V8, and CLKVDD are powered from a sepa-

rate external supply, take caution on the supply sequencing. All

three supplies are connected internally through the back diode of

the regulator. If one supply powers up first, it can supply power

to other supplies through the back diode and the other LDO regula-

tors.

An ADR444 reference IC is chosen to provide the reference voltage

for the AD4134. The ADR444 has a 0.1 Hz to 10 Hz peak noise

of 1.8 µV p-p, and a noise spectrum density of 78.6 nV/√Hz. The

ADR444 1/f noise is 1.8 µV p-p or 1.8/6.6 = 0.273 µV rms.

The total reference noise is the root sum square of its 1/f noise and

its wideband noise. Therefore,

REFERENCE NOISE FILTERING

√(0.273²+ n²_WB) < 3.16

The user can reduce the noise contribution of the reference source

to the overall ADC conversion accuracy by filtering the reference

signal. An internal 20 Ω resistor between the REFIN pin and the

REFCAP pin enables the user to form a first-order RC filter by

connecting a capacitor on the REFCAP pin.

Solving the equation yields the wideband noise, n_WB, of the

ADR444, which must be less than 3.14 µV rms.

The wideband noise of the ADR444 can be calculated by multiply-

ing its noise spectrum density by the square root of the noise

bandwidth.

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Data Sheet

AD4134

APPLICATIONS INFORMATION

78.6 nV/√Hz × √NBW < 3.14 µV rms

where NBW is the noise bandwidth.

COHERENT SAMPLING

The integrated ASRC of the AD4134 allows the user to set granular

sampling speeds from 0.01 kSPS to 1496 kSPS with a resolution

of 0.01 SPS. The ASRC allows the user to detect the line frequen-

cy and change the ODR so that there is a rational relationship

between the input signal frequency and the sampling speed.

The calculation shows that the noise bandwidth must be less than

1.6 kHz. The equivalent noise bandwidth of a first-order filter is

0.25/RC, in Hz.

The AD4134 has an internal 20 Ω resister between the REFIN pin

and the REFCAP pin. By connecting the output of the ADR444

to the REFIN input, a capacitor > 7.9 µF on the REFCAP pin is

sufficient to limit the reference noise to the desired value. It is

recommended to place a 10 µF capacitor on the REFCAP pin.

Mathematically, coherent sampling is expressed as f_IN/f_ODR= num-

ber of cycles in sampling window ÷ number of data points for FFT.

For example, f_ODRis 32 kSPS, f_INis 1 kHz, and the number of

samples is 512.

Number of cycles in the sampling window = 512 × 1000/32 kSPS =

16.

MULTIDEVICE SYNCHRONIZATION

The integrated ASRC of the AD4134 helps achieve multidevice syn-

chronization with a single low speed ODR line, giving less than 10

ns of phase matching between channels on different devices, which

makes it easy to synchronize. Applications like condition-based

monitoring, power quality analyzer, and sonar system demand tight

phase matching across high numbers of channels, making the

digital interface design complex.

If the input frequency is 1.01 kHz, the ODR change is 4096 ×

1010/16 = 258.56 kSPS to achieve coherent sampling.

In applications like power metering and analysis, it is necessary to

achieve the required accuracy on the harmonic data and metering

parameters and ensure coherency between the ADC sampling rate

and the power line frequency.

The devices can be clocked with their own local clock sources yet

can achieve tight phase matching without the need of routing high

speed clock lines that adds to EMI issues. This clocking also means

that for applications demanding isolation, the user can pass fewer

low speed lines across the isolation barrier, as shown in Figure 100.

LOW LATENCY DIGITAL CONTROL LOOP

The control loop demands low latency, but the antialias filter for

noise reduction adds significant delay, increasing the loop latency.

The inherent antialias rejection of the AD4134 removes the need of

the antialias filter, significantly reducing the signal chain latency.

The AD4134 does not require the system clock across isolation to

synchronize isolated devices, which enables higher ODR in isolated

simultaneous sampling applications.

The AD4134 supports throughput rates up to 1496 kSPS, making it

an optimal choice for low latency, 24-bit digital control loops.

AUTOMATIC GAIN CONTROL

To achieve tight synchronization, the user must configure all the

devices in slave mode and use the SPI to set the DIG_IF_RESET

bit to reset the digital interface before the data capture. This

DIG_IF_RESET command must be given to all the slaves simulta-

neously using one single SPI write command.

The AD4134 has additional GPIO functionality when operated in

SPI control mode. One of the diagnostic features of the AD4134

enables GPIO7 to report any of the diagnostic errors by enabling

the ERR_PIN_OUT_EN bit.

The user can use GPIO7 to report any input overrange detection,

and based on the report the user can control the gain of the

front-end amplifier. Configure GPIO7 as an output and set the

ERR_PIN_EN_OR_AIN bit, which enables errors from input over-

range and enables error reporting on GPIO7. Wire the FRAME1/

GPIO7 pin to gain control of the amplifier.

Any input overrange above ±V_REFon the input lines causes GPIO7

to go high, which brings down gain of the PGA, which reduces its

output below ±V_REF. This control happens automatically without any

intervention of the digital host.

Figure 100. Simplified Clocking in AD4134

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Data Sheet

AD4134

APPLICATIONS INFORMATION

Figure 101. Automatic Gain Control

FRONT-END DESIGN EXAMPLES

The analog front-end circuit of the AD4134 must perform the follow-

ing sequence:

Figure 102. Buffered Input with Gain and No Additional Common-Mode

Rejection

1. Provide adequate input impedance to match the source.

2. Provide reasonably low output impedance to drive the 6 kΩ

differential input resistance of the ADC.

3. Convert the input signal to a balanced, fully differential signal

Differential Input with Unregulated Common-

Mode Voltage Low Impedance Source

with fixed common-mode voltage of 2 V to 2.5 V.

If a wider input common-mode range is required, a fully differential

amplifier can be used, as shown in Figure 103.

4. Provide the necessary gain or attenuation to match the maxi-

mum source signal amplitude to the full-scale input range of the

ADC.

The following low noise amplifiers are recommended for various

types of system challenges. Example operational amplifiers include

the ADA4625-2, ADA4610-2, AD8605, and ADA4075-2. Examples

of fully differential amplifiers include the ADA4940-2, LTC6363,

and ADA4945-1. Example instrumentation amplifiers include the

AD8421 and LTC6373.

Differential Input Signal with Controlled

Common-Mode and High Impedance Source

Figure 103. Use a Fully Differential Amplifier to Extend Input Common-Mode

Voltage and Signal Gain/Attenuation

An example of a high impedance source includes a Wheatstone

bridge type of configuration for strain and pressure monitoring.

This circuit can also provide gain or attenuation of the signal and is

responsible for rejecting the input common mode.

The input common mode is well controlled, needing no common-

mode rejection, and a dual op amp configuration works properly.

The circuit in Figure 102 can also provide gain to the signal.

Because of the easy to drive nature of the AD4134, the op amps

do not need to have a high bandwidth and a strong output drive

to overcome kickbacks from traditional ADCs. The ADA4610-2 is

an optimal choice because it offers wide input range, low noise,

suitable bandwidth, and high linearity. The AD8605 is another

optimal choice for rail-to-rail, low voltage, single-supply operation.

Fully differential amplifiers such as the ADA4940-2, ADA4945-1,

and LTC6363 are all suitable choices. Devices such as the

LTC6363-0.5, LTC6363-1, and LTC6363-2 with a highly matched

integrated resistor network offer unmatched CMRR at 94 dB mini-

mum.

Fully Differential Amplifier with Single Unipolar

Supply

The circuit in Figure 104 offers fixed gain for single-ended or

differential inputs having a low impedance source. Single unipolar 5

V supply operation relaxes the power design.

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Data Sheet

AD4134

APPLICATIONS INFORMATION

Precision Dual Amplifier

The circuit in Figure 106 is suitable for a high impedance source,

which can add gain or attenuation. Example operational amplifiers

are the ADA4941-1, LT6350, ADA4805-2, and ADA4075-2.

Figure 104. Fully Differential Amplifier with Single Supply

Single-Ended or Pseudo Differential Input with

High Source Impedance

Figure 106. Dual Operation Amplifier Configuration

The single-ended or pseudo differential input signals must be con-

verted into fully differential signals before driving into the AD4134.

All the circuit examples given in the Front-End Design Examples

section for interfacing with differential signals can work with interfac-

ing with single-ended or pseudo differential signals. Connect the

second input to signal ground or a common-mode voltage source.

Operational Amplifier and Fully Differential

Amplifier

The circuit in Figure 107 is a low input bias operational amplifier

with a fully differential amplifier, like the ADA4945-1, is suitable for

high impedance sources. The fully differential amplifier circuit can

add gain or attenuation.

A number of other circuits can be used to perform single-ended to

differential conversions.

Instrumentation Amplifier with Fully

Differential Output

The typical application diagram (see Figure 94) shows the wide-

band programmable gain amplifier, LTC6373, connected to the

AD4134. The circuit configuration in Figure 94 is suitable for single-

ended input signals, high common-mode range, and very low input

current offering programmable gain.

Figure 107. Op Amp and Fully Differential Amplifier

Instrumentation Amplifier with Single-Ended to

Differential Output Conversion

The circuit configuration in Figure 105 is suitable for single-ended

input signal, high common-mode range, and low input current

suitable for a high impedance source for gain ≥ 1.

Figure 105. Instrumentation Amplifier in Differential Output Configuration

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Data Sheet

AD4134

DIGITAL INTERFACE

The AD4134 digital interface consists of two independent parts:

an SPI for register access and device configuration, and a data

interface for sending out conversion data.

on the falling edge of SCLK and the input data on the SDI pin is

sampled on the rising edge of SCLK.

Figure 109. SCLK Edges

The SPI uses a 7-bit addressing scheme and supports three modes

of operation: 3-wire mode, 4-wire mode, and minimum I/O mode.

An optional CRC function is also available for improving communi-

cation robustness.

3-Wire Mode

Figure 108. Communication Interface of AD4134

In this mode, SDO is disabled and read data is available on the

DEC2/SDI pin. SDO is high impedance in the command, and the

data is shorted to SDI (see Figure 110).

SPI

The SPI control mode is one of the two control modes supported

on the AD4134. The other mode is pin control mode. The user can

choose which mode to operate the device in by setting the logic

level on the PIN/SPI pin. Set the PIN/SPI pin high to enable the SPI

control mode, which enables the SPI of the device.

The AD4134 has a 4-wire SPI that is compatible with QSPI, MI-

CROWIRE, and DSPs. The interface operates in SPI Control Mode

0. In SPI Control Mode 0, the SCLK idles low, the falling edge of

the SCLK is the driving edge, and the rising edge of the SCLK is

the sampling edge. The output data on the SDO pin is clocked out

Figure 110. 3-Wire Mode Write/Read Command

4-Wire Mode

The standard SPI consists of four signals, as shown in Figure 111.

Figure 111. 3-Wire and 4-Wire SPI Transaction Protocols

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Data Sheet

DIGITAL INTERFACE

SPI CRC

AD4134

SPI can be read by completing an SPI read to an SPI register

whose value is known. If the SPI is out of sync, the user initiates an

unlock and resets the SPI. At any point, if the SPI is not responding,

execute a lock and unlock. This unlock/lock does not affect any

data transaction in progress on the data interface and does not

affect the SDO behavior.

The SPI CRC code is an optional feature. Enabling it allows the

user to improve transaction robustness on the SPI bus, for exam-

ple, in a noisy environment.

The SPI CRC is calculated with the x⁸+ x²+ x + 1 polynomial with

an initial seed value of 0xA5.

The SPI CRC achieves a Hamming distance of 4 with a maximum

word length of 119 bits.

Figure 113. SPI Lock/Unlock and Reset

Stream Mode

3-Wire Isolated Mode

Stream mode allows the user to consecutively access one or

more registers repeatedly without having to carry the overhead

associated with setting up the address each cycle. At the end of the

loop, the autogenerated address resets to the beginning address

and resumes counting until the last address is reached again.

The process continues as long as the is not deactivated. When is

deactivated, stream mode is terminated until started again by the

user.

The AD4134 powers up in 3-wire isolated mode and a toggle on the

chip select line makes the AD4134 exit this mode. The chip select

line is not used and must be connected to ground. The SPI packet

is 24 bits, consisting of an 8-bit command and address, 8-bit data

(entity), and 8-bit CRC. See Figure 112 for 3-wire isolated mode.

Also note that a streaming register read or write is not supported in

this mode.

The STREAM_MODE register is used to tell the device how many

consecutive registers are to be accessed in the stream mode. If this

register is 0x00, the default, streaming is not enabled. If the value

in this register is not zero, when streaming is initiated, the value

in this register tells the address generator how many consecutive

addresses are to be written to or read from before looping back

to the beginning address. If the value in this address is 0x01,

the same address is written to or read from for the duration of

the stream event. If the value is 0x02, two consecutive addresses

are written (or read) for the duration. For example, if the stream

entry point is Address 0x10, Address 0x10 is the first address.

Address 0x11 is the second address. After this loop is complete,

the next autogenerated address is 0x10 and so on. This cycle

continues until terminated by the user by deasserting the line.

Figure 112. 3-Wire Isolated Mode

Additional SPI Features

The AD4134 provides the user several options to control the SPI.

Some of the features are listed in the Single Instruction Mode

section through the Master Slave Transfer Bit section.

To initiate stream mode, the user must first set this register,

0x000E, with a nonzero value indicating how many addresses are

to be accessed. Any value between 0x01 and 0xFF is valid. Take

care that all addresses within this scope are suitable for streaming

because some addresses may be specified as do not change. Next,

begin the read or write cycle as usual.

Single Instruction Mode

When the SINGLE_INSTR bit is set, streaming is disabled and only

one read or write operation is performed regardless of the state of

the line. If this bit is set and remains asserted, the state machine

resets after the data byte as if it was deasserted and awaits the

next instruction. Single instruction mode forces each data byte to be

preceded with a new instruction even though the line has not been

deasserted. Single instruction mode also allows additional flexibility

in the usage of the pin if it is required for an application. The default

for this bit is set, resulting in streaming being enabled.

Master Slave Transfer Bit

Bit 0 of the TRANSFER_REGISTER is used as the master slave

transfer bit, which is useful when a register is composed of multiple

bytes that must all be written simultaneously to prevent errone-

ous device operation. In master mode, the ODR_VAL_INT_x and

ODR_VAL_FLT_x registers need this implementation. When this bit

is set, multiple bytes of data that have been transferred using the

SPI are written at one time to the slave. Upon completion of the

transfer, the slave device clears this bit (autoclear), indicating to the

SPI master that the transfer completed and the slave data can be

read back if desired by the control program.

SPI Lock/Unlock

The AD4134 provides the user an option to lock the SPI by per-

forming an SPI write of 24 consecutive 1s. This write blocks the

SPI read/write access to registers. To unlock and reset, the user

must perform an SPI write of 23 1s and one 0. The status of the

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Data Sheet

DIGITAL INTERFACE

DATA INTERFACE

AD4134

The ODR pin is bidirectional with its signal direction dependent on

the ASRC mode of operation.

The AD4134 has a flexible data interface designed to support the

different digital host types and applications requirements.

The output data can be driven out with respect to the ODR falling or

rising edge depending on the mode of DCLK used.

The AD4134 can act as the data interface master or slave. The

data interface supports both gated and free running clock signals,

parallel or serial output data steaming modes, and daisy-chain

configuration.

Choosing the Data Interface Mode of Operation

The direction of the ODR signal depends on the choice of the

ASRC mode of operation. See the Asynchronous Sample Rate

Converter section for more information on the ASRC.

The data interface consists of three signal types: clock, data, and

data framing signal.

Data Interface Status and CRC Header

Data Interface Clock

The user has the option to append a byte width header to each

output data sample for additional status information and/or error

checking. The header consists of 6-bit CRC code with two status

bits, as shown in Table 36.

The AD4134 supports both gated and free running DCLK signals.

The ADC output data is clocked out on the DCLK rising edge.

Table 36. Details of the Header

Bit

Bit Description

7

No Chip error

6

Filter settled and PLL locked

6-bit CRC

[5:0]

Figure 114. DCLK Edges

Bit 7 is cleared if an error is detected by the on-chip diagnostic

circuitry of the AD4134. See the Diagnostics section for more

details of the diagnostic features of the device.

DCLK is a bidirectional pin. The AD4134 can act as an interface

master and generate the DCLK signal, or act as an interface slave

and clock out data based on a received DCLK signal.

Bit 6 is set if the digital filter on the corresponding channel is fully

settled and, when operating in ASRC slave mode, the PLL is locked

after an ODR input frequency change.

When the DCLK pin is configured as an output, the user can

choose the DCLK output frequency through the DATA_ PACK-

ET_CONFIG register or configuration of the DCLKRATEx/GPIOx

pins in pin control mode.

The data sample value does not reflect the correct conversion

result when Bit 6 of the header has a value of zero.

Refer to the Programming Output Data Rate and Clock section for

more information on how to configure the DCLK frequency.

Data CRC Calculation

Data Bus

The CRC is calculated with the polynomial and initial seed value as

shown in Table 37.

The ADC output data appears on the DOUTx pins. Each AD4134

device has four data output pins: DOUT0, DOUT1, DOUT2, and

DOUT3. The user has the option to parallel output the ADC conver-

sion result on the four DOUTx pins or to serialize the data from

multiple channels and output them using one or two of the DOUTx

pins.

Table 37. Data CRC Calculation

CRC Mode

Polynomial

Default Seed Value

CRC-6

x⁶+ x⁵+ x²+ x + 1

0x25

Alternative CRC Mode of Operation

Parallel output configuration allows a high data rate at a low DCLK

frequency. A serialized output configuration requires fewer I/Os

from the digital host and can reduce the number of digital isolator

channels required in an isolation application. The daisy-chain mode

is available only with a serialized output configuration.

The AD4134 uses a linear feedback shift register (LFSR) to calcu-

late the CRC. In pin control mode and in SPI control mode, by

default, the LFSR is reset after each data sample with the default

seed value (see Figure 115). In SPI control mode, the user has

the option to alter the LFSR resetting behavior. Configure CRC_

POLY_RST_SEL to 1 to disable the reset of the LFSR after each

sample, making the current CRC result in the seed value of the next

calculation. This mode allows the processor-based digital host to

check the CRC less frequently and still be able to detect an error in

the bit transfer.

Data Framing Signal

The ODR control signal is dual purposed to act as the framing

signal for the AD4134 data interface.

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Data Sheet

AD4134

DIGITAL INTERFACE

Figure 115. Data CRC Options

ASRC Master Mode Data Interface

When the ASRC is in master mode, the ODR pin behaves as an

output. The user has the choice to operate the DCLK pin in gated

mode or in free running mode.

With the DCLK pin configured as an output, the AD4134 acts as the

data interface master, providing the DCLK signals and the output

data steam synchronously to the ODR signal.

Figure 117. Data interface Example 2, Two AD4134 Devices in ASRC Slave

Mode with Digital Host as Interface Master

Daisy-Chaining

Daisy-chaining allows numerous devices to use the same data

interface lines by cascading the outputs of multiple ADCs from

separate AD4134 devices. The data interface of only one ADC

device is in direct connection with the digital host.

For the AD4134, implement this connection by cascading DOUT0

and DOUT1 through a number of devices, or using only DOUT0.

Figure 116. Data Interface Example 1, First AD4134 Device in ASRC Master

Mode with the Digital Host as Interface Slave

This feature is especially useful for reducing component count and

wiring connections, for example, in isolated multiconverter applica-

tions or for systems with a limited interfacing capacity.

ASRC Slave Mode Data Interface

When the ASRC is in slave mode, the ODR pin behaves as an

input. The user has the choice to operate the DCLK pin in gated

mode or in free running mode.

When daisy-chaining with two channels, DOUT2 and DOUT3 be-

come serial data inputs, and DOUT0 and DOUT1 remain as serial

data outputs.

With the DCLK pin configured as an input, the AD4134 acts as the

data interface slave, providing the output data stream on the input

DCLK driving edge.

Figure 118 shows an example of daisy-chaining the AD4134 devi-

ces with two channels. In this case, the DOUT0 pin and DOUT1 pin

of the AD4134 devices are cascaded to the DOUT2 and DOUT3

pins of the next device in the chain. Data readback is analogous to

clocking a shift register.

If the DCLK pin is configured as a free running input, the user must

ensure that the DCLK pin is synchronized to the ODR signal for

proper data framing.

The scheme operates by passing the output data of the DOUT0 pin

and DOUT1 pin of an AD4134 downstream device to the DOUT2

and DOUT3 inputs of the next AD4134 device upstream in the

chain. The data then continues through the chain until it is clocked

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Data Sheet

AD4134

DIGITAL INTERFACE

onto the DOUT0 pin and DOUT1 pin of the final upstream device in

the chain.

Figure 118. Data Interface Connection with 2-Channel Daisy-Chaining

Configuration

Figure 120. Single Channel Daisy Chain for Master Slave Configuration

The number of devices supported on a chain is limited by the DCLK

frequency chosen for a given output data rate.

The maximum usable DCLK frequency allowed when daisy-chain-

ing devices is limited by the combination of timing specifications

and the DCLK mode of operation.

Data Interface Frame Length

The AD4134 data interface operates with the byte-based transfer

scheme. That is, the transactions are in multiples of eight bits.

The data frame length, defined as the number of data bytes per

ODR cycle per DOUTx pin, depends on the following factors:

► Conversion output word size

► Status or CRC header

► Data output format configuration

► Daisy-chain configuration

► Data averaging

Figure 119. Data Interface Connection with 1-Channel Daisy-Chaining

Configuration

Daisy-chaining can be achieved in a similar manner on the AD4134

when using only the DOUT0 pin. In this case, only the DOUT2 pin

is used as the serial data input pin, as shown in Figure 119.

The conversion output word size can be 16 bits or 24 bits.

It is optional to include a status or CRC header byte with each

conversion result to improve the communication robustness and to

receive real-time error status.

If the AD4134 is used in the chain as a master for generating

the ODR and DCLK, the user must program the DAISY_CHAIN_

DEV_NUM bits to let the device know how many devices are

connected to it. Programming the DAISY_CHAIN_DEV_NUM bits

ensures that the AD4134 generates a sufficient number of DCLK

cycles to clock the data out from all the devices in the chain. For

example, in Figure 120, program the DAISY_CHAIN_ DEV_NUM

bits in the master device to 0x01 so that the AD4134 can generate

the number of DCLK cycles to clock out data from both the devices.

The user can choose to parallel or serialize the output data. Serial-

izing the output data from four ADC channels to one DOUTx pin

increases the data frame length by 4×.

If multiple devices are daisy-chained, the total data frame length is

equal to the sum of the data frame length of the individual devices

on the chain.

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Rev. 0 | 67 of 92

Data Sheet

AD4134

DIGITAL INTERFACE

In pin control mode, unless the device is configured to operate

Frame Length Examples

in quad channel parallel output mode, it assumes a daisy-chain

configuration. If the DCLK pin is configured as a gated output,

the device assumes that four devices are on the daisy chain. The

number of DCLK cycles it generates after each ODR pulse is equal

to four times the data frame length of the devices.

In Case 1, the following conditions apply:

► 16-bit output format

► No status or CRC header

► Parallel output on all four DOUTx pins

► No daisy chain

In SPI control mode, the user has the flexibility to program

the number of devices on the daisy chain through the DAISY_

CHAIN_DEV_NUM bits. The value acts as a multiplier to the num-

ber of DCLK cycles the device outputs after each ODR pulse when

the DCLK is configured as a gated output.

► Averaging disabled

The output data frame length is 16/8 = 2 bytes per ODR period on

each of the four DOUTx pins.

In Case 2, the following conditions apply:

Gated DCLK Output Cycles Examples

► 24-bit data format

In Case 1, the following conditions apply:

► Status and CRC header enabled

► Output on two DOUTx pins

► Daisy chain three devices

► Averaging disabled

► 16-bit output format

► No status or CRC header

► Single-channel daisy-chain mode

► Pin control mode operation

► DCLK configured as gated output

The output data frame length is (24/8 + 1) × 2 × 3 = 24 bytes per

ODR period on each of the two DOUTx pins.

The device outputs 16 × 4 = 64 DCLK cycles after each ODR pulse.

In Case 2, the following conditions apply:

In Case 3, the following conditions apply:

► 24-bit output format

► Status/CRC header enabled

► Output on one DOUTx pins

► Daisy-chain two devices

► 4:1 averaging

► Status and CRC header enabled

► Dual-channel daisy-chain mode

► Averaging disabled

► SPI control mode operation

► DAISY_CHAIN_DEV_NUM = 3 (decimal)

The output data frame length is (24/8 + 1) × 4 × 2/4 = 8 bytes per

ODR period.

The device outputs (24 + 8) × 2 × 3 = 192 DCLK cycles after each

ODR pulse.

DCLK Frequency Selection

The user must ensure an adequate DCLK frequency is used to

clock out the full length of the data frame in time.

Channel Dependent ODR

In SPI control mode, the AD4134 supports the configuration of dif-

ferent ODR rates on each channel using the CHANNEL_ODR_SE-

LECT register. The rate must be a power of two fraction of the

signal frequency on the ODR pin and is limited to a minimum of 1/8

of the main ODR frequency.

The maximum supported DCLK frequency on the AD4134 is 48

MHz as an output and 50 MHz as an input.

Gated DCLK Output Cycles

When DCLK is configured as a gated output, the AD4134 uses an

internal counter to control the number of DCLK cycles to output

after each ODR pulse. The device automatically adjusts the number

of DCLK cycles to output according to its data frame and format

configuration.

Each channel updates its conversion output based on the ODR rate

of the channel. For example, if a channel is configured to have an

output data rate of ODR/4, its output data updates once every four

ODR cycles. Figure 121 shows an example of the data interface

timing of a device with different output data rate settings on each

channel.

However, in daisy-chain mode, the device has no inherent knowl-

edge of the number of devices connected on the chain.

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Rev. 0 | 68 of 92

Data Sheet

AD4134

DIGITAL INTERFACE

Figure 121. Data Interface Timing Example of a Device with Different ODR Settings on Each Channel

disabled. All SPI packets must be 24 bits, which is R/W + Address

(8-bit), data (8-bit), and CRC (8-bit), as described in Figure 114.

To configure the AD4134 to operate with a minimum number of IO

lines, perform the following sequence:

Digital Interface Reset

Bit 1 of the INTERFACE_CONFIG_B register (DIG_IF_RESET)

resets the data interface. In multidevice configuration, this bit syn-

chronizes data channel outputs to achieve device to device channel

phase matching. This bit is self clearing and only available for use

in SPI slave mode operation. Refer to the Multidevice Synchroniza-

tion section.

1. Connect the FORMAT0/ pin to ground.

2. Externally connect DCLK to the FORMAT1/SCLK pin.

3. Configure DCLK to be a gated input.

4. Set ASRC slave mode.

MINIMUM I/O MODE

5. Set FORMATx to 00 wherein data from all four ADC channels

Certain applications require a minimum number of I/O lines to be

used for interfacing with the AD4134. This requirement may be due

to the limited number of I/Os available on the digital host, or for

cost reasons, to minimize the number of digital isolation channels

required in an isolated application.

are converged and output through DOUT0.

6. Set the SDO_PIN_SRC_SEL bit to 1.

The AD4134 is designed to support both register and data access

using as few as only four unidirectional I/O lines.

The minimum I/O mode configuration essentially combines the

register and data access interface on the AD4134 and allows the

digital host to interface with the AD4134 with only one SPI port as

master.

Figure 122. Signal Connection Diagram of Minimum I/O Configuration

The trade-off of minimizing the number of I/O ports is more compli-

cated firmware design and a potentially higher CPU processing

load.

In minimum I/O mode, the user can use the DEC3/SDO pin for both

register content and ADC conversion data readback. Only one of

the SDO and DOUT0 outputs are allowed to be enabled at any

given time. Setting the SDO_PIN_SRC_SEL bit to 1 causes the

signal on DOUT0 to be duplicated on the DEC3/SDO pin.

On power-on, the AD4134 boots up in minimum I/O mode and

a toggle on pin makes the device exit the minimum I/O mode.

Also, SPI CRC is enabled in minimum I/O mode and cannot be

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Data Sheet

AD4134

DIAGNOSTICS

The AD4134 has numerous diagnostic functions on chip that moni-

tor and report errors for the following functional blocks:

cleared if any of the other status error bits are set. This bit sets

back to 1 when all the status bits are cleared, indicating no chip

error.

► Internal fuses

INTERNAL FUSE INTEGRITY CHECK

► Analog input range

► MCLK frequency

► SPI communication

► Memory map value

► ODR input frequency

► Digital filters

The AD4134 uses a fuse type memory to store the factory pro-

grammed calibration values that are unique to each device. When

leaving the factory, a CRC code is calculated based on the final

fuse values of the device and is stored in the device memory.

On each power-up, the device reads the fuse memory for self

configuration. The device also performs a CRC calculation based

on the fuse values read and compares the calculation against the

factory programmed value to detect a fuse reading error.

In SPI control mode, the user can enable or disable the following

diagnostic features through the diagnostic control register:

► Fuse CRC

► Memory map CRC

► SPI CRC

► MCLK counter

► Analog input range

The device sets the ERR_FUSE_CRC bit if a fuse CRC error is

detected.

The user can also initiate a fuse check by using the FUSE_

CRC_CHECK bit in the diagnostic control register. This bit is

cleared when the check is complete. When this check is executed,

the data output is interrupted.

Figure 123 shows all the different types of blocks monitored, as well

as blocks that are enabled using the diagnostic control register.

The fuse CRC supports 1-bit error correction. The device tries

to correct the error when detected. The AD4134 sets the

STAT_FUSE_ECC bit if the error is corrected and sets the

ERR_FUSE_CRC bit if the fuse CRC error correction is not com-

pleted.

The remaining diagnostic features run continuously on the device

and all the bits except the NO_CHIP_ERR bit are cleared on a

read.

As shown in Figure 123, the NO_CHIP_ERR bit in the device

configuration register is the master error status bit. This bit is

Figure 123. Errors

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Data Sheet

AD4134

DIAGNOSTICS

For CRC checksum calculations, the polynomial used is x⁸+ x²+

x+ 1 and has a reset seed of 0xA5.

ANALOG INPUT OVERRANGE

An on-chip, full-scale overrange detection monitor flags a bit on

detection of a positive full-scale input voltage between the AINx+

pins and AINx− pins. This detection is enabled on each channel by

using the ERR_OR_AIN_EN bit in the diagnostic control register,

and an overvoltage bit corresponding to the particular channel is set

if the voltage exceeds the full scale corresponding to that channel.

The 8-bit checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction is

calculated using the 8-bit command word and data. For a read

transaction, the checksum is calculated using the command word

and the data output.

For write or read operation, the host sends the R/W bit, the address

(eight bits), the data (eight bits), and the 8-bit CRC (on R/W,

address, and data).

Four overvoltage flags in the AIN_OR_ERROR register correspond-

ing to the four input channels are cleared on a read.

MCLK COUNTER

In a write operation, while the host is sending the CRC on the

SDI line, the slave simultaneously transmits the CRC calculated on

the write + address + data that the slave has received. The slave

executes a write operation only when the received CRC sent by

the host matches with its calculated CRC. The slave sends a 1-bit

status followed by 15 zeros and the 8-bit CRC (see Figure 124).

A stable MCLK is important because the output data rate, filter

settling time, and the filter notch frequencies are dependent on the

master clock. The AD4134 allows the user to monitor the master

clock. When the MCLK_CNT_EN bit in the diagnostic control regis-

ter is set, the MCLK_COUNTER register increments by one every

12,000 master clock cycles. The user can monitor this register

over a fixed period by running a timer in the controller, and the

master clock frequency can be determined from the result in the

MCLK_COUNTER register.

Figure 124. SPI Write with CRC

MCLK = Register Data × 12,000/Timer Value

where Register Data is in decimal format.

In a read operation, while the host is sending the CRC on the

SDI line, the slave simultaneously transmits the CRC calculated on

the command and the read data. The slave sends a 1-bit status

followed by seven zeros, 8-bit read data, and 8-bit CRC (see Figure

125).

For example, if MCLK is 24 MHz and the timer is set to 100 ms,

the expected MCLK_COUNTER value is 0xC8. This register wraps

around after it reaches its maximum value.

SPI MONITORING

The 1-bit status sent by the slave is the error bit, which indicates

that the previous frame had a read, write, or CRC error.

The AD4134 supports a number of diagnostic measures to improve

the robustness of its SPI.

Accessing Undefined Register Address

When the user tries to access an undefined register address, the

device ignores the instruction and flags an error in the ERR_

SPI_READ bit or the ERR_SPI_WRITE bit. These bits are cleared

on a read.

Figure 125. SPI Read with CRC

MEMORY MAP INTEGRITY CHECK

When the ERR_MM_CRC_EN bit is set in the diagnostic control

register, a CRC of the data from all the on-board registers with

write access is calculated and the results are stored in memory.

The device then continuously performs the CRC calculation at a

frequency of 2.4 kHz, and compares each output with the CRC

value stored in memory. The device sets the ERR_MM_CRC bit if

the two values are different. This bit is cleared on a read. The CRC

value stored in the memory is also recalculated after each SPI write

transaction.

SCLK Counter

The AD4134 uses an SCLK counter to count the number of

SCLK cycles supplied in each of the read and write transactions

framed by the signal. The device flags an error in the ERR_SPI_

SCLK_CNT bit if the number of SCLK cycles at the end of each SPI

transaction is not an integer multiple of 8. This bit is cleared on a

read. The SCLK counter is not available in minimum I/O mode.

This feature is useful for detecting a soft error in the memory map.

SPI CRC

ODR INPUT FREQUENCY CHECK

When the ERR_SPI_CRC_EN bit in the diagnostic control register

is set, a CRC check for all SPI read and write operations is

enabled. The ERR_SPI_CRC bit in the SPI error register is set if

the CRC check fails. This bit is cleared on a read.

An ODR input frequency check applies only to device operation in

ASRC slave mode.

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Data Sheet

AD4134

DIAGNOSTICS

The device checks the input ODR signal frequency after the PLL

locks and sets the ERR_ASRC bit if the ODR frequency detected

is outside the range for the particular type of filter selected as

specified in Table 19. This bit is cleared on a read.

DCLK ERROR

The device has a built-in feature to flag insufficient numbers of data

clocks needed to clock out the complete frame.

The user must program or provide a data clock that is fast enough

to clock out the complete frame for the given ODR and ensure that

for the gated mode,

For example, if the ODR input is set to 600 kSPS and the type of

filter set is wideband, this error is flagged. There is no data output in

this scenario.

ODR Time > t_DCLK× Frame Size + 6 × t_DCLKor t_DIGCLK(whichever

is higher)

DIGITAL FILTER OVERFLOW AND

UNDERFLOW

And for free mode,

The digital filter overflow/underflow occurs when the input is over-

range or due to an incorrect setting of the gain and calibration

register. The AD4134 monitors the digital filter path and sets the

corresponding channel bit in the DIG_FILTER_OFUF register when

an overflow or underflow condition is detected.

ODR Time > t_DCLK× Frame Size + 4 × t_DCLKor t_DIGCLK(whichever

is higher)

The ERR_DCLK flag sets if the programmed or provided DCLK

frequency is such that Equation 1 is not met, resulting in an

insufficient number of data clocks to clock out the entire frame. This

bit is cleared on a read.

For proper usage of this diagnostic feature, it is recommended to

read back these flags after power-up.

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Data Sheet

AD4134

GPIO FUNCTIONALITY

The AD4134 has additional GPIO functionality when operated in

SPI control mode. This fully configurable mode allows the device

to operate eight GPIOs, thus making the AD4134 work as an

SPI-based GPIO expander. The GPIO pins can be set as inputs or

outputs (read or write) on a per pin basis.

input or output. The GPIO_DATA register reflects the status of the

pins when configured as inputs or the user can write to this register

to set the pins when configured as outputs (see Figure 126).

PIN ERROR REPORTING

Additionally, GPIO7 can be used as an output to report any of the

diagnostic errors by enabling Bit ERR_PIN_OUT_EN. Register ER-

ROR_PIN_SRC_CONTROL controls the type of errors that can be

reported on this pin. If multiple types are selected, the output is a

logical OR of all the selected errors.

In write mode, these GPIO pins can be used to control other circuits

such as switches, amplifiers, multiplexers, and buffers over the

same SPI as the AD4134. Sharing the SPI in this way allows the

user to use a lower overall number of data lines from the controller,

compared to a system where multiple control signals are required.

This sharing is especially useful in systems where reducing the

number of control lines across an isolation barrier is important.

Similarly, a GPIO read is a useful feature because it allows a

peripheral device to send information to the input GPIO and then

this information can be read from the SPI of the AD4134.

GPIO6 can be used as an error input from any other device by

enabling the ERR_PIN_IN_EN bit. The status of this bit can be read

using the ERR_PIN_IN_STATUS bit.

The GPIO7 output is a logical OR of all the selected er-

rors, as per the ERROR_PIN_SRC_CONTROL register and the

ERR_PIN_IN_STATUS bit.

The GPIO pins can be used as general-purpose inputs or outputs.

The GPIO_DIR_CTRL register configures the individual pin as an

Figure 126. AD4134 as SPI GPIO Expander

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Data Sheet

AD4134

REGISTER MAP (SPI CONTROL)

See Table 38 for the register map for the device (SPI control).

Table 38. Register Map

Reg

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x0

INTERFACE_

CONFIG_A

SOFT_

RESET

Reserved ADDRESS_

ASCENSION_

BIT

SDO_

ACTIVE_

BIT

SDO_

ACTIVE_

BIT_

ADDRESS_

ASCENSION_

BIT_MIRROR

Reserved

SOFT_

RESET_

MIRROR

0x18

R/W

MIRROR

0x1

0x2

INTERFACE_

CONFIG_B

SINGLE_

INSTR

Reserved MASTER_

SLAVE_

Reserved

DIG_IF_

RESET

Reserved

0x80

0xD0

R/W

RD_CTRL

DEVICE_CONFIG

Reserved

OP_IN_

PROGRESS

NO_CHIP_

ERR

Reserved

POWER_

MODE

0x3

0x4

0x5

0x6

0x7

0xA

0xB

0xC

0xD

0xE

0xF

CHIP_TYPE

0x07

N/A¹

0x00

0x02

0x56

0x04

0x00

R

PRODUCT_ID_LSB

PRODUCT_ID_MSB

CHIP_GRADE

PRODUCT_ID[7:0]

PRODUCT_ID[15:8]

R

PRODUCT_GRADE

DEVICE_VERSION

R

SILICON_REV

SILICON_REVISION_ID

SCRATCH_PAD

R

SCRATCH_PAD

SPI_REVISION

VENDOR_ID_LSB

VENDOR_ID_MSB

STREAM_MODE

R/W

R

SPI_REVSION_NUMBER

VENDOR_ID[7:0]

R

VENDOR_ID[15:8]

STREAM_MODE_BITS

Reserved

R

R/W

TRANSFER_

REGISTER

MASTER_

SLAVE_

TX_BIT

0x10

0x11

DEVICE_CONFIG_1

Reserved

AA_MODE SDO_PIN_

SRC_SEL

REFIN_

GAIN_

CORR_EN

XCLKOUT_

EN

0x00

R/W

DATA_PACKET_

CONFIG

CRC_

POLY_

RST_

SEL

Reserved

Frame

DCLK_FREQ_SEL

0x12

0x13

DIGITAL_INTERFACE

_

CONFIG

DAISY_CHAIN_DEV_NUM

AVG_SEL

Format

0x00

R/W

POWER_DOWN_

CONTROL

Reserved PWRDN_ PWRDN_

PWRDN_

CH1

PWRDN_

CH0

Reserved

PWRDN_

LDO

SLEEP_

MODE_EN

CH3

CH2

0x14

0x15

RESERVED

Reserved

0x00

R/W

R

DEVICE_STATUS

Reserved

STAT_

DCLKMODE

STAT_

DCLKIO

STAT_

MODE

STAT_

CLKSEL

STAT_

FUSE_

ECC

STAT_PLL_

LOCK

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

ODR_VAL_INT_LSB

ODR_VAL_INT_MID

ODR_VAL_INT_MSB

ODR_VAL_FLT_LSB

ODR_VAL_FLT_MID0

ODR_VAL_FLT_MID1

ODR_VAL_FLT_MSB

ODR_VAL_INT[7:0]

0x40

0x00

0x72

0xB7

0xCE

0x2B

0x00

R/W

ODR_VAL_INT[15:8]

ODR_VAL_INT[23:16]

ODR_VAL_FLT[7:0]

ODR_VAL_FLT[15:8]

ODR_VAL_FLT[23:16]

ODR_VAL_FLT[31:24]

CHANNEL_ODR_

SELECT

ODR_RATE_SEL_CH3

DIGFILTER_SEL_CH3

ODR_RATE_SEL_CH2

ODR_RATE_SEL_CH1

ODR_RATE_SEL_CH0

DIGFILTER_SEL_CH0

0x1E

CHAN_DIG_

FILTER_SEL

DIGFILTER_SEL_CH2

DIGFILTER_SEL_CH1

0x00

R/W

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Data Sheet

AD4134

REGISTER MAP (SPI CONTROL)

Table 38. Register Map

Reg

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x1F

FIR_BW_SEL

Reserved

WB_

0x00

R/W

FILTER_

SEL_CH3

FILTER_

SEL_CH2

FILTER_

SEL_CH1

FILTER_

SEL_CH0

0x20

0x21

0x22

GPIO_DIR_CTRL

GPIO_DATA

GPIO_IO_CONTROL

GPIO_DATA

0x00

R/W

ERROR_PIN_

SRC_CONTROL

Reserved

ERR_PIN_EN_

OR_AIN

ERR_PIN_ ERR_PIN_

Reserved

EN_

EN_SPI

INTERNAL

0x23

0x24

0x25

0x26

ERROR_PIN_CONTR

OL

Reserved

ERR_PIN_

IN_STATUS

ERR_PIN

_IN_EN

ERR_PIN

_OUT_EN

0x00

R/W

VCMBUF_CTRL

Diagnostic Control

MPC_CONFIG

Reserved PWRDN_

VCMBUF

VCMBUF_REF_DIV_SEL

VCMBUF_

REF_SEL

Reserved

ERR_OR_AIN_E Reserved

N

MCLK_

CNT_EN

ERR_SPI_

CRC_EN

ERR_MM_

CRC_EN

FUSE_CRC_ 0x00

CHECK

MPC_CLKDEL_EN_

CH3

MPC_CLKDEL_EN_CH2

MPC_CLKDEL_EN_CH1

MPC_CLKDEL_EN_CH0

0x00

0x27

0x28

0x29

CH0_GAIN_LSB

CH0_GAIN_MID

CH0_GAIN_MSB

GAIN_CH0[7:0]

GAIN_CH0[15:8]

GAIN_CAL

_SEL_CH0

OFFSET_CH0[7:0]

OFFSET_CH0[15:8]

OFFSET_CH0[22:16]

0x00

R/W

Reserved

GAIN_CH0[19:16]

0x2A

0x2B

0x2C

CH0_OFFSET_LSB

CH0_OFFSET_MID

CH0_OFFSET_MSB

0x00

R/W

OFFSET_

CAL_EN_

CH0

0x2D

0x2E

0x2F

CH1_GAIN_LSB

CH1_GAIN_MID

CH1_GAIN_MSB

GAIN_CH1[7:0]

GAIN_CH1[15:8]

0x00

R/W

Reserved

GAIN_CAL

_SEL_CH1

OFFSET_CH1[7:0]

OFFSET_CH1[15:8]

OFFSET_CH1[22:16]

GAIN_CH1[19:16]

GAIN_CH2[19:16]

GAIN_CH3[19:16]

0x30

0x31

0x32

CH1_OFFSET_LSB

CH1_OFFSET_MID

CH1_OFFSET_MSB

0x00

R/W

OFFSET_

CAL_EN_

CH1

0x33

0x34

0x35

CH2_GAIN_LSB

CH2_GAIN_MID

CH2_GAIN_MSB

GAIN_CH2[7:0]

GAIN_CH2[15:8]

0x00

R/W

GAIN_CAL

_SEL_CH2

OFFSET_CH2[7:0]

OFFSET_CH2[15:8]

OFFSET_CH2[22:16]

0x36

0x37

0x38

CH2_OFFSET_LSB

CH2_OFFSET_MID

CH2_OFFSET_MSB

0x00

R/W

OFFSET_

CAL_EN_

CH2

0x39

0x3A

0x3B

CH3_GAIN_LSB

CH3_GAIN_MID

CH3_GAIN_MSB

GAIN_CH3[7:0]

GAIN_CH3[15:8]

0x00

R/W

GAIN_CAL

_SEL_CH3

OFFSET_CH3[7:0]

OFFSET_CH3[15:8]

0x3C

0x3D

CH3_OFFSET_LSB

CH3_OFFSET_MID

0x00

R/W

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Data Sheet

AD4134

REGISTER MAP (SPI CONTROL)

Table 38. Register Map

Reg

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x3E

CH3_OFFSET_MSB

OFFSET_

CAL_EN_

CH3

OFFSET_CH3[22:16]

0x00

R/W

0x3F

0x40

MCLK_COUNTER

DIG_FILTER_OFUF

MCLK_COUNT

0x00

R

Reserved

ERR_OFU

F_

ERR_OFUF_

CH2

ERR_OFUF_ ERR_OFUF_ 0x00

CH1

CH0

CH3

0x41

0x42

0x47

0x48

DIG_FILTER_

SETTLED

Reserved

CH3_

SETTLED

CH2_

SETTLED

CH1_

SETTLED

CH0_

SETTLED

0x00

R

INTERNAL_ERROR

ERR_DCLK ERR_FUSE_

CRC

ERR_ASRC

ERR_MM_

CRC

SPI Error

ERR_SPI_

CRC

ERR_SPI_

SCLK_CNT

ERR_SPI_

WRITE

ERR_SPI_

READ

AIN_OR_ERROR

ERR_OR_

AIN3

ERR_OR_

AIN2

ERR_OR_

AIN1

ERR_OR_

AIN0

1

N/A means not applicable. The reset value is time stamp dependent and programmed in production.

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Data Sheet

AD4134

REGISTER DETAILS

Address: 0x0, Reset: 0x18, Name: INTERFACE_CONFIG_A

Table 39. Bit Descriptions for INTERFACE_CONFIG_A

Bits

Bit Name

Settings

Description

Reset

Access

7

SOFT_RESET

Soft Reset of the Device. This bit is cleared on completion of a reset.

0x0

R/W

0

1

Default.

Initiates a soft reset.

Reserved.

6

5

Reserved

0x0

R

ADDRESS_ASCENSION_BIT

Register Map Address Ascension/Descend Control. Used with streaming

mode, address ascension causes sequential register addresses to ascend

in order. Disabling causes sequential register addresses to descend in

order.

R/W

0

1

Sequential register address in descending order.

Sequential register address in ascending order.

SDO Control.

4

SDO_ACTIVE_BIT

0x1

R/W

0

1

SDO disabled, exhibit high impedance.

SDO enabled.

3

2

1

0

SDO_ACTIVE_BIT_MIRROR

ADDRESS_ASCENSION_BIT_MIRROR

Reserved

Mirror Image of SDO_ACTIVE_BIT.

Mirror Image of ADDRESS_ASCENTION_BIT.

Reserved.

0x1

0x0

R

SOFT_RESET_MIRROR

Mirror Image of SOFT_RESET.

Default.

R/W

0

1

Initiates a soft reset.

Address: 0x1, Reset: 0x80, Name: INTERFACE_CONFIG_B

Table 40. Bit Descriptions for INTERFACE_CONFIG_B

Bits

Bit Name

Settings

Description

Reset

Access

7

SINGLE_INSTR

Single Instruction Mode Control. When set, this bit disables streaming regardless of the 0x1

state of . When clear, streaming is enabled.

R/W

0

1

Disable.

Enable.

6

5

Reserved

Reserved.

0x0

R

MASTER_SLAVE_RD_CTRL

Master Slave Readback Control. Determines the data to read back from the master

or slave buffered bits (ODR_VAL_INT_x and ODR_VAL_FLT_x). Set to 1 to read back

from master output. Clear this bit to read back from slave output.

R/W

0

1

Readback of the slave flip flop outputs.

Readback of the master flip flop outputs.

Reserved.

[4:2]

1

Reserved

0x0

R

DIG_IF_RESET

Reserved

Digital Interface Reset.

Reserved.

R/W

0

Address: 0x2, Reset: 0xD0, Name: DEVICE_CONFIG

Table 41. Bit Descriptions for DEVICE_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

5

Reserved

Reserved.

0x3

0x0

R

OP_IN_PROGRESS

Operation in Progress Indicator. A readback value of 0 indicates that the device is busy.

Some operation in progress.

0

1

No operation in progress.

4

NO_CHIP_ERR

Error Flag for all of the Enabled Status Errors. This bit is the OR of all the enabled error bits and

continues to stay clear as long as any error flag is set.

0x1

R

0

1

Device has a chip error.

No chip error.

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Data Sheet

AD4134

REGISTER DETAILS

Table 41. Bit Descriptions for DEVICE_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[3:1]

0

Reserved

Reserved.

0x0

R

POWER_MODE

Device Power Mode Control.

Low power mode.

R/W

0

1

High performance mode.

Address: 0x3, Reset: 0x07, Name: CHIP_TYPE

Table 42. Bit Descriptions for CHIP_TYPE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CHIP_TYPE

Code to Indicate the Type of Device. Read 0x07 to confirm for precision ADC.

0x7

R

Address: 0x4, Reset: 0x00, Name: PRODUCT_ID_LSB

Table 43. Bit Descriptions for PRODUCT_ID_LSB

Bits

[7:0]

1

Bit Name

Settings

Description

Reset

Access

PRODUCT_ID[7:0]

Product ID.

Not applicable¹

R

Reset value is time stamp dependent and programmed in production.

Address: 0x5, Reset: 0x00, Name: PRODUCT_ID_MSB

Table 44. Bit Descriptions for PRODUCT_ID_MSB

Bits

[7:0]

1

Bit Name

Settings

Description

Reset

Access

PRODUCT_ID[15:8]

Product ID.

Not applicable¹

R

Reset value is time stamp dependent and programmed in production.

Address: 0x6, Reset: 0x00, Name: CHIP_GRADE

Table 45. Bit Descriptions for CHIP_GRADE

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

[3:0]

PRODUCT_GRADE

DEVICE_VERSION

Grade of the Device.

Device Version.

0x0

R

Address: 0x7, Reset: 0x02, Name: SILICON_REV

Table 46. Bit Descriptions for SILICON_REV

Bits

Bit Name

Settings

Description

Stores the Revision Number of the Current Silicon.

Reset

Access

[7:0]

SILICON_REVISION_ID

0x0

R

Address: 0xA, Reset: 0x00, Name: SCRATCH_PAD

Table 47. Bit Descriptions for SCRATCH_PAD

Bits

Bit Name

Settings

Description

Scratch Pad for Checking SPI Read and Write Operation.

Reset

Access

[7:0]

SCRATCH_PAD

0x0

R/W

Address: 0xB, Reset: 0x02, Name: SPI_REVISION

Table 48. Bit Descriptions for SPI_REVISION

Bits

Bit Name

Settings

Description

Indicate the Revision Number of the SPI Protocol.

Reset

Access

[7:0]

SPI_REVSION_NUMBER

0x2

R

Address: 0xC, Reset: 0x56, Name: VENDOR_ID_LSB

Table 49. Bit Descriptions for VENDOR_ID_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

VENDOR_ID[7:0]

Vendor ID.

0x56

R

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Data Sheet

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REGISTER DETAILS

Address: 0xD, Reset: 0x04, Name: VENDOR_ID_MSB

Table 50. Bit Descriptions for VENDOR_ID_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

VENDOR_ID[15:8]

Vendor ID.

0x4

R

Address: 0xE, Reset: 0x00, Name: STREAM_MODE

Table 51. Bit Descriptions for STREAM_MODE

Bits

Bit Name

Settings

Description

Defines the Depth of the Loop for User Stream Mode.

Reset

0x0

Access

[7:0]

STREAM_MODE_BITS

R/W

Address: 0xF, Reset: 0x00, Name: TRANSFER_REGISTER

Table 52. Bit Descriptions for TRANSFER_REGISTER

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

0

Reserved

Reserved.

0x0

R

MASTER_SLAVE_TX_BIT

Master Slave Transfer Bit. When this bit is set, data is entered into the master registers

transferred to the slave. Upon completion of the transfer, the slave device clears this bit

(autoclears), indicating to the SPI master that the transfer was complete and the slave

data can be read back if desired by the control program. Prior to a transfer, an attempted

R/W

readback views the prior data unless Bit 5 of Register 0x1 (MASTER_SLAVE_RD_CTRL)

is set. In that case, the master data is accessed. Another method to invoke the transfer is

to use the low to high transition.

Address: 0x10, Reset: 0x00, Name: DEVICE_CONFIG_1

Table 53. Bit Descriptions for DEVICE_CONFIG_1

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved, is always zero.

Sets Inherent Antialiasing Mode.

AA1 mode.

0x0

R/W

AA_MODE

0

1

AA2 mode.

2

SDO_PIN_SRC_SEL

DEC3/SDO Pin Signal Source Selection. In minimum I/O mode, the user can use the

DEC3/SDO pin for both register content and ADC conversion data readback.

0x0

R/W

0

1

DEC3/SDO pin acts as SPI serial data output.

Signal on DOUT0 is duplicated on DEC3/SDO pin.

Enables Reference Gain Correction.

Reference gain correction disabled.

Reference gain correction enabled.

XCLKOUT Output Enable Control.

XCLKOUT disabled.

1

0

REFIN_GAIN_CORR_EN

XCLKOUT_EN

0x0

R/W

0

1

0

1

XCLKOUT enabled.

Address: 0x11, Reset: 0x00, Name: DATA_PACKET_CONFIG

Table 54. Bit Descriptions for DATA_PACKET_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

7

CRC_POLY_RST_SEL

Data Interface CRC Reset Method Selection.

0x0

R/W

0

1

The data interface CRC is reset with default seed value at the end of every data frame.

The data interface CRC does not reset at the end of each data frame. The CRC value

calculated from the proceeding data frame seeds the CRC calculation of the current data

frame.

6

Reserved

Frame

Reserved - Please write 0 to this bit always

ADC Conversion Data Output Frame Control.

16-bit ADC data only.

0x0

R/W

[5:4]

0

1

16-bit ADC data followed by 6-bit CRC.

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Data Sheet

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REGISTER DETAILS

Table 54. Bit Descriptions for DATA_PACKET_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

10 24-bit ADC data only.

11 24-bit ADC data followed by 6-bit CRC.

Controls DCLK Output Frequency.

[3:0]

DCLK_FREQ_SEL

0x0

R/W

0

1

f_DCLK= 48 MHz.

f_DCLK= 24 MHz.

10 f_DCLK= 12 MHz.

11 f_DCLK= 6 MHz.

100 f_DCLK= 3 MHz.

101 f_DCLK= 1.5 MHz.

110 f_DCLK= 750 kHz.

111 f_DCLK= 375 kHz.

1000 f_DCLK= 187.5 kHz.

1001 f_DCLK= 93.75 kHz.

1010 f_DCLK= 46.875 kHz.

1011 f_DCLK= 23.4375 kHz.

1100 f_DCLK= 11.71875 kHz.

1101 f_DCLK= 5.859 kHz.

1110 f_DCLK= 2.929 kHz.

1111 f_DCLK= 1.464 kHz.

Address: 0x12, Reset: 0x00, Name: DIGITAL_INTER-FACE_CONFIG

Table 55. Bit Descriptions for DIGITAL_INTERFACE_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

DAISY_CHAIN_DEV_NUM

Sets the Number of Devices Connected in a Daisy-Chain Configuration. This register

is only applicable to a device set to output DCLK to other devices in a daisy-chain

configuration. The register value acts as a clock cycle multiplier in DCLK output

configuration. For example, setting the daisy-chain device number to two doubles the

number of DCLK cycles output per ODR cycle.

0x0

R/W

0

1

Only one device is used.

2 devices are in daisy-chain configuration.

10 3 devices are in daisy-chain configuration.

11 4 devices are in daisy-chain configuration.

100 5 devices are in daisy-chain configuration.

101 6 devices are in daisy-chain configuration.

110 7 devices are in daisy-chain configuration.

111 8 devices are in daisy-chain configuration.

1000 9 devices are in daisy-chain configuration.

1001 10 devices are in daisy-chain configuration.

1010 11 devices are in daisy-chain configuration.

1011 12 devices are in daisy-chain configuration.

1100 13 devices are in daisy-chain configuration.

1101 14 devices are in daisy-chain configuration.

1110 15 devices are in daisy-chain configuration.

1111 16 devices are in daisy-chain configuration.

Multichannel ADC Conversion Data Averaging Control.

[3:2]

AVG_SEL

0x0

R/W

0

Data from all four channels are averaged and output on DOUT0. DOUT2 acts as

daisy-chain input. DOUT1 and DOUT3 are disabled.

1

Data from Channel 0 and Channel 1 are averaged and output on DOUT0. DOUT1 is

disabled. Channel 2 and Channel 3 are under normal operation.

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Data Sheet

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REGISTER DETAILS

Table 55. Bit Descriptions for DIGITAL_INTERFACE_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

10 Data from Channel 2 and Channel 3 are averaged and output on DOUT2. DOUT3 is

disabled. Channel 0 and Channel 1 are under normal operation.

11 Data from Channel 0 and Channel 1 are averaged and output on DOUT0. Data from

Channel 2 and Channel 3 are averaged and output on DOUT1. DOUT2 and DOUT3 act

as daisy-chain inputs.

[1:0]

Format

DOUTx Output Format Configuration.

0x0

R/W

0

1

Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a

daisy-chain input. DOUT1 and DOUT3 are disabled. Data from all four ADC channels

are output on DOUT0.

Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as output and DOUT2 and

DOUT3 act as daisy-chain input. Data from Channel 0 and Channel 1 are output on

DOUT0. Data from Channel 2 and Channel 3 are output on DOUT1.

10 Quad channel parallel output mode. Each ADC channel has a dedicated data output

pin.

11 Channel data averaging mode, averaging operation is defined by AVG_SEL.

Address: 0x13, Reset: 0x00, Name: POWER_DOWN_CONTROL

Table 56. Bit Descriptions for POWER_DOWN_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

7

6

Reserved

Reserved.

0x0

R

PWRDN_CH3

Powers Down Analog Input Channel 3.

Power up.

R/W

0

1

Power down.

5

4

3

PWRDN_CH2

PWRDN_CH1

PWRDN_CH0

Powers Down Analog Input Channel 2.

Power up.

0x0

R/W

0

1

Power down.

Powers Down Analog Input Channel 1.

Power up.

0

1

Power down.

Powers Down Analog Input Channel 0.

Power up.

0

1

Power down.

2

1

Reserved

Reserved.

0x0

R

PWRDN_LDO

Powers Down the Internal Analog and Clock LDO Regulators.

Internal LDO regulators powered.

Internal LDO regulators powered down.

R/W

0

1

0

SLEEP_MODE_EN

All Blocks Except Digital LDO Regulator are Turned Off. On-chip register contents remain the

same.

0x0

R/W

0

1

Sleep mode disabled.

Sleep mode enabled.

Address: 0x14, Reset: 0x00, Name: RESERVED

Table 57. Bit Descriptions for RESERVED

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

Reserved

Reserved. Always zero.

0x0

R/W

Address: 0x15, Reset: 0x00, Name: DEVICE_STATUS

Table 58. Bit Descriptions for DEVICE_STATUS

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

Reserved

Reserved.

0x0

R

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Data Sheet

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Table 58. Bit Descriptions for DEVICE_STATUS

Bits

Bit Name

Settings

Description

Reset

Access

5

STAT_DCLKMODE

DEC1/DCLKMODE Pin Status Indicates if DCLK is in Free Running or Gated Mode.

DCLK is in gated mode. Compatible with SPI interface.

DCLK is in free running mode.

0x0

R

0

1

4

3

2

1

0

STAT_DCLKIO

STAT_MODE

DEC0/DCLKIO Pin Status Indicates DCLK Pin Direction.

DCLK is input.

0x0

R

0

1

DCLK is output.

MODE Pin Status Indicates Whether Device is Master or Slave.

Slave mode: ODR is input.

0

1

Master mode: ODR is output.

STAT_CLKSEL

STAT_FUSE_ECC

STAT_PLL_LOCK

CLKSEL Pin Status Indicates the Clock Source.

CMOS input clock is connected.

0

1

Crystal input is connected.

Status Bit that Indicates Application of Fuse Error Correction Code. This bit is cleared on is read.

Error code correction not applied.

0

1

Error code correction applied.

PLL Status in Slave Mode. Indicates if PLL has locked or not. Setting this bit indicates PLL is

locked.

0

1

PLL not locked.

PLL locked.

Address: 0x16, Reset: 0x40, Name: ODR_VAL_INT_LSB

Table 59. Bit Descriptions for ODR_VAL_INT_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_INT[7:0]

Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master

mode, the user can program this register to set the ODR output frequency.

0x40

R/W

Address: 0x17, Reset: 0x00, Name: ODR_VAL_INT_MID

Table 60. Bit Descriptions for ODR_VAL_INT_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_INT[15:8]

Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master

mode, the user can program this register to set the ODR output frequency.

0x0

R/W

Address: 0x18, Reset: 0x00, Name: ODR_VAL_INT_MSB

Table 61. Bit Descriptions for ODR_VAL_INT_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_INT[23:16]

Integer Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master

mode, the user can program this register to set the ODR output frequency.

0x0

R/W

Address: 0x19, Reset: 0x72, Name: ODR_VAL_FLT_LSB

Table 62. Bit Descriptions for ODR_VAL_FLT_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_FLT[7:0]

Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master

mode, the user can program this register to set the ODR output frequency.

0x72

R/W

Address: 0x1A, Reset: 0xB7, Name: ODR_VAL_FLT_MID0

Table 63. Bit Descriptions for ODR_VAL_FLT_MID0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_FLT[15:8]

Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In master 0xB7

mode, the user can program this register to set the ODR output frequency.

R/W

Address: 0x1B, Reset: 0xCE, Name: ODR_VAL_FLT_MID1

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Data Sheet

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Table 64. Bit Descriptions for ODR_VAL_FLT_MID1

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_FLT[23:16]

Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In

master mode, the user can program this register to set the ODR output frequency.

0xCE

R/W

Address: 0x1C, Reset: 0x2B, Name: ODR_VAL_FLT_MSB

Table 65. Bit Descriptions for ODR_VAL_FLT_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

ODR_VAL_FLT[31:24]

Fractional Portion of Decimation Rate. Decimation rate is the ratio of 24 MHz to ODR. In

master mode, the user can program this register to set the ODR output frequency.

0x2B

R/W

Address: 0x1D, Reset: 0x00, Name: CHANNEL_ODR_SELECT

Table 66. Bit Descriptions for CHANNEL_ODR_SELECT

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

ODR_RATE_SEL_CH3

Select Output Data Rate to ODR Frequency Ratio for Channel 3.

Output data rate = ODR.

0x0

R/W

0

1

Output data rate = ODR/2.

10 Output data rate = ODR/4.

11 Output data rate = ODR/8.

[5:4]

[3:2]

[1:0]

ODR_RATE_SEL_CH2

ODR_RATE_SEL_CH1

ODR_RATE_SEL_CH0

Select Output Data Rate to ODR Frequency Ratio for Channel 2.

R/W

0

1

Output data rate = ODR.

Output data rate = ODR/2.

10 Output data rate = ODR/4.

11 Output data rate = ODR/8.

Select Output Data Rate to ODR Frequency Ratio for Channel 1.

0

1

Output data rate = ODR.

Output data rate = ODR/2.

10 Output data rate = ODR/4.

11 Output data rate = ODR/8.

Select Output Data Rate to ODR Frequency Ratio for Channel 0.

0

1

Output data rate = ODR.

Output data rate = ODR/2.

10 Output data rate = ODR/4.

11 Output data rate = ODR/8.

Address: 0x1E, Reset: 0x00, Name: CHAN_DIG_FILTER_SEL

Table 67. Bit Descriptions for CHAN_DIG_FILTER_SEL

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

DIGFILTER_SEL_CH3

Channel 3 Digital Filter Type Selection.

Wideband filter.

0x0

R/W

0

01 Sinc6 filter.

10 Sinc3 filter.

11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection.

Channel 2 Digital Filter Type Selection.

[5:4]

[3:2]

DIGFILTER_SEL_CH2

DIGFILTER_SEL_CH1

0x0

R/W

0

Wideband filter.

01 Sinc6 filter.

10 Sinc3 filter.

11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection.

Channel 1 Digital Filter Type Selection.

0

Wideband filter.

01 Sinc6 filter.

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Data Sheet

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Table 67. Bit Descriptions for CHAN_DIG_FILTER_SEL

Bits

Bit Name

Settings

Description

Reset

Access

10 Sinc3 filter.

11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection.

Channel 0 Digital Filter Type Selection.

[1:0]

DIGFILTER_SEL_CH0

0x0

R/W

0

Wideband filter.

01 Sinc6 filter.

10 Sinc3 filter.

11 Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection.

Address: 0x1F, Reset: 0x00, Name: FIR_BW_SEL

Table 68. Bit Descriptions for FIR_BW_SEL

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved.

0x0

R

WB_FILTER_SEL_CH3

Channel 3 Wideband Filter Bandwidth Selection.

Wideband filter has a bandwidth of 0.433 × ODR.

Wideband filter has a bandwidth of 0.10825 × ODR.

Channel 2 Wideband Filter Bandwidth Selection.

Wideband filter has a bandwidth of 0.433 × ODR.

Wideband filter has a bandwidth of 0.10825 × ODR.

Channel 1 Wideband Filter Bandwidth Selection.

Wideband filter has a bandwidth of 0.433 × ODR.

Wideband filter has a bandwidth of 0.10825 × ODR.

Channel 0 Wideband Filter Bandwidth Selection.

Wideband filter has a bandwidth of 0.433 × ODR.

Wideband filter has a bandwidth of 0.10825 × ODR.

R/W

0

1

2

1

0

WB_FILTER_SEL_CH2

WB_FILTER_SEL_CH1

WB_FILTER_SEL_CH0

0x0

R/W

0

1

0

1

0

1

Address: 0x20, Reset: 0x00, Name: GPIO_DIR_CTRL

Table 69. Bit Descriptions for GPIO_DIR_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GPIO_IO_CONTROL

GPIO I/O Direction Control. Each bit controls the direction of a GPIO pin. A value of 0 sets the

GPIO pin as an input. A value of 1 sets the GPIO pin as an output. Bit 0 is associated with

GPIO0.

0x0

R/W

Address: 0x21, Reset: 0x00, Name: GPIO_DATA

Table 70. Bit Descriptions for GPIO_DATA

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GPIO_DATA

GPIO Data Value. If a GPIO pin is configured as an input, the corresponding bit is read only and its

value reflects the input logic status of the pin. If a GPIO pin is configured as an output, write to the

corresponding bit to control the output logic of the pin. Bit 0 is associated with GPIO0. 1 = logic high and 0

= logic low.

0x0

R/W

Address: 0x22, Reset: 0x00, Name: ERROR_PIN_SRC_CON-TROL

Table 71. Bit Descriptions for ERROR_PIN_SRC_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

5

Reserved

Reserved.

0x0

R

ERR_PIN_EN_OR_AIN

Enables Error Reporting on GPIO7 for Input Overrange Errors.

Disables pin toggle for overvoltage error.

Enables pin toggle for overvoltage error.

R/W

0

1

4

ERR_PIN_EN_INTERNAL

Enables Error Reporting on GPIO7 for Any Internal Errors. Internal error can be digital

overflow or underflow error, memory map CRC error, ASRC error, fuse CRC error, or

0x0

R/W

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Data Sheet

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REGISTER DETAILS

Table 71. Bit Descriptions for ERROR_PIN_SRC_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

DCLK counter error. Make sure to enable the corresponding error in the diagnostic control

register to enable this reporting.

0

1

Disables pin toggle for internal errors.

Enables pin toggle for internal errors.

3

ERR_PIN_EN_SPI

Enables error reporting on GPIO7 if there are any SPI errors such as read, write, CRC

check, and clock counter errors. Make sure to enable SPI CRC error for reporting those

errors on the pin.

0x0

R/W

0

1

Disables pin toggle for SPI related errors.

Enables pin toggle for SPI related errors.

Reserved.

[2:0]

Reserved

0x0

R

Address: 0x23, Reset: 0x00, Name: ERROR_PIN_CONTROL

Table 72. Bit Descriptions for ERROR_PIN_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

[7:3]

2

Reserved

Reserved.

0x0

R

ERR_PIN_IN_STATUS

This bit is the readback of the latched status of the error input, GPIO6, when it is enabled

using the ERR_PIN_IN_EN bit.

1

0

ERR_PIN_IN_EN

Enables GPIO6 as an error input. This bit allows error to be daisy-chained from a digital host

and is OR’ed with internal errors.

0x0

R/W

ERR_PIN_OUT_EN

Enables GPIO7 as an error output pin. The source of this error is defined by the

ERROR_PIN_SRC_CONTROL register.

Address: 0x24, Reset: 0x00, Name: VCMBUF_CTRL

Table 73. Bit Descriptions for VCMBUF_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

6

Reserved

Reserved.

0x0

R

PWRDN_VCMBUF

VCM Buffer Power Control.

VCM buffer powered on.

R/W

0

1

VCM buffer powered down.

V_CMOutput Voltage Level Selection when VCMBUF_REF_SEL = 0.

V_CM= V_REF× 10/20.

[5:1]

VCMBUF_REF_DIV_SEL

0x0

R/W

0

1

Reserved.

10 V_CM= V_REF× 19/20.

11 V_CM= V_REF× 18/20.

100 V_CM= V_REF× 17/20.

101 V_CM= V_REF× 16/20.

110 V_CM= V_REF× 15/20.

111 V_CM= V_REF× 14/20.

1000 V_CM= V_REF× 13/20.

1001 V_CM= V_REF× 12/20.

1010 V_CM= V_REF× 11/20.

1011 V_CM= V_REF× 9/20.

1100 V_CM= V_REF× 8/20.

1101 V_CM= V_REF× 7/20.

1110 V_CM= V_REF× 6/20.

1111 V_CM= V_REF× 5/20.

10000 V_CM= V_REF× 4/20.

10001 V_CM= V_REF× 3/20.

10010 V_CM= V_REF× 2/20.

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Rev. 0 | 85 of 92

Data Sheet

AD4134

REGISTER DETAILS

Table 73. Bit Descriptions for VCMBUF_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

10011 V_CM= V_REF× 1/20.

11101 V_CM= V_REF× 10/20.

11110 V_CM= V_REF× 10/20.

11111 V_CM= V_REF× 10/20.

0

VCMBUF_REF_SEL

VCM Output Source Selection.

0x0

R/W

0

1

VCM as a ratio of V_REF. The VCM output level is V_REFdivided by the ratio set with

VCMBUF_REF_DIV_SEL.

V_CMis fixed to AVDD5/2.

Address: 0x25, Reset: 0x00, Name: Diagnostic Control

Table 74. Bit Descriptions for Diagnostic Control

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

5

Reserved

Reserved.

0x0

R

ERR_OR_AIN_EN

Enables Overrange Monitor on all Enabled Analog Input Channels.

Input overvoltage monitor is disabled.

Input overvoltage monitor is enabled.

Reserved

R/W

0

1

4

3

Reserved

0x0

R

MCLK_CNT_EN

Enables Master Clock Counter. Starts the MCLK counter, which monitors the external clock being 0x0

used by the ADC.

R/W

0

1

Disables MCLK counter.

Enables MCLK counter.

2

1

0

ERR_SPI_CRC_EN

ERR_MM_CRC_EN

FUSE_CRC_CHECK

Enables CRC Check on SPI Read and Write Operations. The ERR_SPI_CRC bit in the SPI error 0x0

register is set if the CRC check fails. In addition, an 8-bit CRC word is appended to all SPI read

operations.

R/W

0

1

SPI CRC disabled.

SPI CRC enabled.

Enables Memory Map CRC Calculation. CRC calculation is performed on the memory map each 0x0

time the registers are written to. Following this write, periodic CRC checks are performed on the

on-chip registers. If the register contents have changed, the ERR_MM_CRC bit is set.

0

1

Disables memory map CRC check.

Enables memory map CRC check.

Initiates a CRC Calculation on the Fuse Contents. If the fuse contents have changed, the

ERR_FUSE_CRC bit is set. This bit is cleared on completion of the check.

0x0

0

1

CRC calculation disabled.

CRC calculation enabled.

Address: 0x26, Reset: 0x00, Name: MPC_CONFIG

Table 75. Bit Descriptions for MPC_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

MPC_CLKDEL_EN_CH3

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 3.

00 Magnitude and phase clock delay: 0 clock delays.

0x0

R/W

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delays.

[5:4]

[3:2]

MPC_CLKDEL_EN_CH2

MPC_CLKDEL_EN_CH1

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 2.

00 Magnitude and phase clock delay: 0 clock delays.

0x0

R/W

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delays.

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 1.

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Rev. 0 | 86 of 92

Data Sheet

AD4134

REGISTER DETAILS

Table 75. Bit Descriptions for MPC_CONFIG

Bits

Bit Name

Settings

Description

Reset

Access

00 Magnitude and phase clock delay: 0 clock delays.

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delay.

Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 0.

00 Magnitude and phase clock delay: 0 clock delays.

01 Magnitude and phase clock delay: 1 clock delay.

10 Magnitude and phase clock delay: 2 clock delays.

11 Magnitude and phase clock delay: 0 clock delay.

[1:0]

MPC_CLKDEL_EN_CH0

0x0

R/W

Address: 0x27, Reset: 0x00, Name: CH0_GAIN_LSB

Table 76. Bit Descriptions for CH0_GAIN_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH0[7:0]

Channel 0 Gain Calibration Value.

0x0

R/W

Address: 0x28, Reset: 0x00, Name: CH0_GAIN_MID

Table 77. Bit Descriptions for CH0_GAIN_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH0[15:8]

Channel 0 Gain Calibration Value.

0x0

R/W

Address: 0x29, Reset: 0x00, Name: CH0_GAIN_MSB

Table 78. Bit Descriptions for CH0_GAIN_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

4

Reserved

Reserved.

0x0

R

GAIN_CAL_SEL_CH0

GAIN_CH0[19:16]

Enables Gain Calibration on Channel 0.

Channel 0 Gain Calibration Value.

R/W

[3:0]

Address: 0x2A, Reset: 0x00, Name: CH0_OFFSET_LSB

Table 79. Bit Descriptions for CH0_OFFSET_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH0[7:0]

Channel 0 Offset Calibration Value.

0x0

R/W

Address: 0x2B, Reset: 0x00, Name: CH0_OFFSET_MID

Table 80. Bit Descriptions for CH0_OFFSET_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH0[15:8]

Channel 0 Offset Calibration Value.

0x0

R/W

Address: 0x2C, Reset: 0x00, Name: CH0_OFFSET_MSB

Table 81. Bit Descriptions for CH0_OFFSET_MSB

Bits

Bit Name

Settings

Description

Reset

Access

7

OFFSET_CAL_EN_CH0

OFFSET_CH0[22:16]

Enables Offset Calibration on Channel 0.

Channel 0 Offset Calibration Value.

0x0

R/W

[6:0]

Address: 0x2D, Reset: 0x00, Name: CH1_GAIN_LSB

Table 82. Bit Descriptions for CH1_GAIN_LSB

Bits

Bit Name

Settings

Description

Reset

0x0

Access

[7:0]

GAIN_CH1[7:0]

Channel 1 Gain Calibration Value.

R/W

Address: 0x2E, Reset: 0x00, Name: CH1_GAIN_MID

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Data Sheet

AD4134

REGISTER DETAILS

Table 83. Bit Descriptions for CH1_GAIN_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH1[15:8]

Channel 1 Gain Calibration Value.

0x0

R/W

Address: 0x2F, Reset: 0x00, Name: CH1_GAIN_MSB

Table 84. Bit Descriptions for CH1_GAIN_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

4

Reserved

Reserved.

0x0

R

GAIN_CAL_SEL_CH1

GAIN_CH1[19:16]

Enables Gain Calibration on Channel 1.

Channel 1 Gain Calibration Value.

R/W

[3:0]

Address: 0x30, Reset: 0x00, Name: CH1_OFFSET_LSB

Table 85. Bit Descriptions for CH1_OFFSET_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH1[7:0]

Channel 1 Offset Calibration Value.

0x0

R/W

Address: 0x31, Reset: 0x00, Name: CH1_OFFSET_MID

Table 86. Bit Descriptions for CH1_OFFSET_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH1[15:8]

Channel 1 Offset Calibration Value.

0x0

R/W

Address: 0x32, Reset: 0x00, Name: CH1_OFFSET_MSB

Table 87. Bit Descriptions for CH1_OFFSET_MSB

Bits

Bit Name

Settings

Description

Reset

Access

7

OFFSET_CAL_EN_CH1

OFFSET_CH1[22:16]

Enables Offset Calibration on Channel 1.

Channel 1 Offset Calibration Value.

0x0

R/W

[6:0]

Address: 0x33, Reset: 0x00, Name: CH2_GAIN_LSB

Table 88. Bit Descriptions for CH2_GAIN_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH2[7:0]

Channel 2 Gain Calibration Value.

0x0

R/W

Address: 0x34, Reset: 0x00, Name: CH2_GAIN_MID

Table 89. Bit Descriptions for CH2_GAIN_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH2[15:8]

Channel 2 Gain Calibration Value.

0x0

R/W

Address: 0x35, Reset: 0x00, Name: CH2_GAIN_MSB

Table 90. Bit Descriptions for CH2_GAIN_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

4

Reserved

Reserved.

0x0

R

GAIN_CAL_SEL_CH2

GAIN_CH2[19:16]

Enables Gain Calibration on Channel 2.

Channel 2 Gain Calibration Value.

R/W

[3:0]

Address: 0x36, Reset: 0x00, Name: CH2_OFFSET_LSB

Table 91. Bit Descriptions for CH2_OFFSET_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH2[7:0]

Channel 2 Offset Calibration Value.

0x0

R/W

Address: 0x37, Reset: 0x00, Name: CH2_OFFSET_MID

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Rev. 0 | 88 of 92

Data Sheet

AD4134

REGISTER DETAILS

Table 92. Bit Descriptions for CH2_OFFSET_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH2[15:8]

Channel 2 Offset Calibration Value.

0x0

R/W

Address: 0x38, Reset: 0x00, Name: CH2_OFFSET_MSB

Table 93. Bit Descriptions for CH2_OFFSET_MSB

Bits

Bit Name

Settings

Description

Reset

Access

7

OFFSET_CAL_EN_CH2

OFFSET_CH2[22:16]

Enables Offset Calibration on Channel 2.

Channel 2 Offset Calibration Value.

0x0

R/W

[6:0]

Address: 0x39, Reset: 0x00, Name: CH3_GAIN_LSB

Table 94. Bit Descriptions for CH3_GAIN_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH3[7:0]

Channel 3 Gain Calibration Value.

0x0

R/W

Address: 0x3A, Reset: 0x00, Name: CH3_GAIN_MID

Table 95. Bit Descriptions for CH3_GAIN_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

GAIN_CH3[15:8]

Channel 3 Gain Calibration Value.

0x0

R/W

Address: 0x3B, Reset: 0x00, Name: CH3_GAIN_MSB

Table 96. Bit Descriptions for CH3_GAIN_MSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

4

Reserved

Reserved.

0x0

R

GAIN_CAL_SEL_CH3

GAIN_CH3[19:16]

Enables Gain Calibration on Channel 3.

Channel 3 Gain Calibration Value.

R/W

[3:0]

Address: 0x3C, Reset: 0x00, Name: CH3_OFFSET_LSB

Table 97. Bit Descriptions for CH3_OFFSET_LSB

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH3[7:0]

Channel 3 Offset Calibration Value.

0x0

R/W

Address: 0x3D, Reset: 0x00, Name: CH3_OFFSET_MID

Table 98. Bit Descriptions for CH3_OFFSET_MID

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

OFFSET_CH3[15:8]

Channel 3 Offset Calibration Value.

0x0

R/W

Address: 0x3E, Reset: 0x00, Name: CH3_OFFSET_MSB

Table 99. Bit Descriptions for CH3_OFFSET_MSB

Bits

Bit Name

Settings

Description

Reset

Access

7

OFFSET_CAL_EN_CH3

OFFSET_CH3[22:16]

Enables Offset Calibration on Channel 3.

Channel 3 Offset Calibration Value.

0x0

R/W

[6:0]

Address: 0x3F, Reset: 0x00, Name: MCLK_COUNTER

Table 100. Bit Descriptions for MCLK_COUNTER

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

MCLK_COUNT

8-Bit Counter that Increments Once Every 12,000 MCLK Cycles. The counter output is read back,

which enables the user to determine the frequency of the external clock. The MCLK counter starts

when MCLK_CNT_EN is set, and ends when it reaches 255 MCLK cycles.

0x0

R

Address: 0x40, Reset: 0x00, Name: DIG_FILTER_OFUF

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Rev. 0 | 89 of 92

Data Sheet

AD4134

REGISTER DETAILS

Table 101. Bit Descriptions for DIG_FILTER_OFUF

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved.

0x0

R

ERR_OFUF_CH3

Channel 3 Digital Filter Overflow or Underflow Error.

No overflow or underflow error.

0

1

Overflow or underflow error.

2

1

0

ERR_OFUF_CH2

ERR_OFUF_CH1

ERR_OFUF_CH0

Channel 2 Digital Filter Overflow or Underflow Error.

No overflow or underflow error.

0x0

R

0

1

Overflow or underflow error.

Channel 1 Digital Filter Overflow or Underflow Error.

No overflow or underflow error.

0

1

Overflow or underflow error.

Channel 0 Digital Filter Overflow or Underflow Error.

No overflow or underflow error.

0

1

Overflow or underflow error.

Address: 0x41, Reset: 0x00, Name: DIG_FILTER_SETTLED

Table 102. Bit Descriptions for DIG_FILTER_SETTLED

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved.

0x0

R

CH3_SETTLED

Channel 3 Digital Filter Status.

Digital filter not settled.

Digital filter is settled.

0

1

2

1

0

CH2_SETTLED

CH1_SETTLED

CH0_SETTLED

Channel 2 Digital Filter Status.

Digital filter not settled.

Digital filter is settled.

0x0

R

0

1

Channel 1 Digital Filter Status.

Digital filter not settled.

Digital filter is settled.

0

1

Channel 0 Digital Filter Status.

Digital filter not settled.

Digital filter is settled.

0

1

Address: 0x42, Reset: 0x00, Name: INTERNAL_ERROR

Table 103. Bit Descriptions for INTERNAL_ERROR

Bits

Bit Name

Settings

Description

Reset

0x0

Access

[7:4]

3

Reserved

Reserved.

R

ERR_DCLK

DCLK Error Flag Indicates that the DCLK Programmed or Provided is Low to Clock Out the Complete 0x0

Frame.

0

1

No DCLK error.

DCLK error.

2

ERR_FUSE_CRC

Fuse Error Flag Indicates a CRC Error in Fuse Contents. When enabled, a CRC calculation is

performed on the fuse contents. If the contents have changed, this bit is set.

0x0

R

0

1

No fuse CRC error.

Fuse CRC error.

1

0

ERR_ASRC

ASRC Error Flag Indicates if ODR is Out of Range of the Filter Selected.

0x0

R

0

1

No ASRC error.

ASRC error.

ERR_MM_CRC

Memory Map Error Flag Indicates CRC Error in On-Chip Register Contents. When enabled, a CRC

calculation is performed on the memory map each time the registers are written to. Following this

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Rev. 0 | 90 of 92

Data Sheet

AD4134

REGISTER DETAILS

Table 103. Bit Descriptions for INTERNAL_ERROR

Bits

Bit Name

Settings

Description

Reset

Access

calculation, periodic CRC checks are performed on the on-chip registers. If the register contents have

changed, an error is flagged.

0

1

No memory map error.

Memory map error.

Address: 0x47, Reset: 0x00, Name: SPI Error

Table 104. Bit Descriptions for SPI Error

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved.

0x0

R

ERR_SPI_CRC

SPI CRC Error Flag Indicates CRC Error During SPI Communications. This error reporting is

enabled using the ERR_SPI_CRC_EN bit in the diagnostic control register.

0

1

No CRC error.

CRC error detected.

2

ERR_SPI_SCLK_CNT

SCLK counter error flag indicates that the number of SCLK cycles during SPI communication is 0x0

not a multiple of eight.

R

0

1

No error.

SCLK counter error detected.

1

0

ERR_SPI_WRITE

ERR_SPI_READ

SPI Write Error Flag Indicates Error During SPI Write Operation.

0x0

R

0

1

No error.

SPI write error.

SPI Read Error Flag Indicates Error During SPI Read Operation.

0

1

No error.

Read error detected.

Address: 0x48, Reset: 0x00, Name: AIN_OR_ERROR

Table 105. Bit Descriptions for AIN_OR_ERROR

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

3

Reserved

Reserved.

0x0

R

ERR_OR_AIN3

Input Overvoltage Flag on Channel 3. When enabled, this bit detects the input voltage exceeding the

absolute value of V_REF

.

0

1

No overvoltage input detected.

Overvoltage input detected.

2

1

0

ERR_OR_AIN2

ERR_OR_AIN1

ERR_OR_AIN0

Input Overvoltage Flag on Channel 2. When enabled, this bit detects the input voltage exceeding the

0x0

R

absolute value of V_REF

.

0

1

No overvoltage input detected.

Overvoltage input detected.

Input Overvoltage Flag on Channel 1. When enabled, this bit detects the input voltage exceeding the

absolute value of V_REF

.

0

1

No overvoltage input detected.

Overvoltage input detected.

Input Overvoltage Flag on Channel 0. When enabled, this bit detects the input voltage exceeding the

absolute value of V_REF

.

0

1

No overvoltage input detected.

Overvoltage input detected.

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Rev. 0 | 91 of 92

Data Sheet

AD4134

OUTLINE DIMENSIONS

Figure 127. 56-Lead Lead Frame Chip Scale Package [LFCSP]

8 mm × 8 mm Body and 0.75 mm Package Height

(CP-56-9)

Dimensions shown in millimeters

Updated: November 01, 2021

ORDERING GUIDE

Package

Option

Model¹

Temperature Range

Package Description

Packing Quantity

AD4134BCPZ

−40°C to +105°C

56-Lead LFCSP (8 mm × 8 mm w/ EP)

Tray, 260

Reel, 750

CP-56-9

AD4134BCPZ-RL7

1

Z = RoHS Compliant Part.

EVALUATION BOARDS

Model¹

Description

EVAL-AD4134FMCZ

EVAL-SDP-CH1Z

Evaluation Board

Controller Board

1

Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

One Analog Way, Wilmington, MA 01887-2356, U.S.A.

Rev. 0 | 92 of 92


型号：	AD4134
厂家：	ADI
描述：	24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC
文件：	总92页 (文件大小：5067K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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