AD4600ACPZ-R7_技术文档

4.25 Gbps, 8 × 8,

Asynchronous Crosspoint Switch

ADN4600

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Full 8 × 8 crossbar connectivity

ADN4600

Fully buffered signal path supports multicast and broadcast

operation

RECEIVE

EQUALIZATION

CROSSPOINT

ARRAY

TRANSMIT

PRE-EMPHASIS

IP[7:0]

IN[7:0]

OP[7:0]

ON[7:0]

Optimized for dc to 4.25 Gbps data

Programmable receive equalization

Compensates for up to 30 in. of FR4 @ 4.25 Gbps

Programmable transmit pre-emphasis/de-emphasis

Compensates for up to 30 in. of FR4 @ 4.25 Gbps

Flexible 1.8 V to 3.3 V core supply

EQ

PE

ADDR[1:0]

SCL

CONTROL LOGIC

SDA

RESETB

Per lane positive/negative (P/N) pair inversion for routing ease

Low power: 125 mW/channel at 4.25 Gbps

DC- or ac-coupled differential CML inputs

Programmable CML output levels

Figure 1.

50 Ω on-chip termination

−40°C to +85°C temperature range operation

Supports 8b10b, scrambled or uncoded nonreturn-to-zero

(NRZ) data

I²C control interface

Package: 64-lead LFCSP

APPLICATIONS

1×, 2×, 4× FibreChannel

XAUI

Gigabit Ethernet over backplane

10GBase-CX4

InfiniBand®

50 Ω cables

The ADN4600 nonblocking switch core implements an 8 × 8

crossbar and supports independent channel switching through the

I²C control interface. Every channel implements an asynchronous

path supporting NRZ data rates from dc to 4.25 Gbps. Each

channel is fully independent of other channels. The ADN4600

has low latency and very low channel-to-channel skew.

GENERAL DESCRIPTION

The ADN4600 is an asynchronous, nonblocking crosspoint

switch with eight differential PECL-/CML-compatible inputs

with programmable equalization and eight differential CML

outputs with programmable output levels and pre-emphasis or

de-emphasis. The operation of this device is optimized for NRZ

data at rates up to 4.25 Gbps.

The main application for the ADN4600 is to support switching

on the backplane, line card, or cable interface sides of serial links.

The receive inputs provide programmable equalization with

nine settings to compensate for up to 30 in. of FR4 and

programmable pre-emphasis with seven settings to compensate

for up to 30 in. of FR4 at 4.25 Gbps.

The ADN4600 is packaged in a 9 mm × 9 mm, 64-lead LFCSP

package and operates from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADN4600

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 13

Introduction................................................................................ 13

Receivers...................................................................................... 13

Switch Core ................................................................................. 15

Transmitters ................................................................................ 16

I²C Control Interface.................................................................. 22

PCB Design Guidelines ............................................................. 24

Control Register Map..................................................................... 25

Package Outline Dimensions........................................................ 28

Ordering Guide .......................................................................... 28

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Specifications............................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

REVISION HISTORY

6/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 2

ADN4600

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

V_CC= 1.8 V, V_EE= 0 V, V_TTI= V_TTO= V_CC, R_L= 50 Ω, differential output swing = 800 mV p-p differential, 4.25 Gbps, PRBS 2⁷− 1,

T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Conditions

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum Data Rate per Channel

Deterministic Jitter

Random Jitter

Residual Deterministic Jitter with

Receive Equalization

In NRZ format

Data rate < 4.25 Gbps; BER = 1e − 12

V_CC= 1.8 V

Data rate < 3.25 Gbps; 0 in. to 30 in. FR4

Data rate < 4.25 Gbps; 0 in. to 30 in. FR4

Data rate < 3.25 Gbps; 0 in. to 30 in. FR4

Data rate < 4.25 Gbps; 0 in. to 30 in. FR4

20% to 80%

4.25

Gbps

ps p-p

ps rms

UI

ps

ns

30

1.5

0.16

0.20

0.13

0.18

75

Residual Deterministic Jitter with

Transmit Pre-Emphasis

Output Rise/Fall Time

Channel-to-Channel Skew

Propagation Delay

50

1

OUTPUT PRE-EMPHASIS

Equalization Method

Maximum Boost

One-tap programmable pre-emphasis

800 mV p-p output swing

200 mV p-p output swing

Minimum

6

12

2

dB

mA

Pre-Emphasis Tap Range

Maximum

12

INPUT EQUALIZATION

Minimum Boost

Maximum Boost

Number of Equalization Steps

Gain Step Size

EQBY = 1

Maximum boost occurs @ 2.125 GHz

1.5

22

8

dB

Steps

dB

2.5

INPUT CHARACTERISTICS

Input Voltage Swing

Input Voltage Range

1

Differential, V_ICM= V_CC− 0.6 V; V_CC= 3.3 V

300

45

2000

55

mV p-p

V p-p

Ω

Single-ended absolute voltage level, V_Lminimum

Single-ended absolute voltage level, V_Hmaximum

Single-ended

V_EE+ 0.4

V_CC+ 0.5

50

Input Resistance

Input Return Loss

Measured at 2.5 GHz

5

dB

OUTPUT CHARACTERISTICS

Output Voltage Swing

@ dc, differential, PE = 0, default, V_CC= 1.8 V

@ dc, differential, PE = 0, default, V_CC= 3.3 V

635

740

800

100

1300

1800

V_CC− 1.1

870

mV p-p

V

@ dc, differential, PE = 0, min output level², V_CC= 1.8 V

@ dc, differential, PE = 0, min output level², V_CC= 3.3 V

@ dc, differential, PE = 0, max output level², V_CC= 1.8 V

@ dc, differential, PE = 0, max output level², V_CC= 3.3 V

Single-ended absolute voltage level,

TxHeadroom = 0; V_Lmin

Output Voltage Range

Single-ended absolute voltage level,

TxHeadroom = 0; V_Hmax

Single-ended absolute voltage level,

TxHeadroom = 1; V_Lmin

Single-ended absolute voltage level,

TxHeadroom = 1; V_Hmax

V_CC+ 0.6

V_CC− 1.2

V_CC+ 0.6

V

Output Current

Minimum output current per channel

Maximum output current per channel, V_CC= 1.8 V

Single ended

2

mA

21

50

5

Output Resistance

Output Return Loss

45

55

Ω

dB

Measured at 2.5 GHz

Rev. 0 | Page 3 of 3

ADN4600

Parameter

POWER SUPPLY

Operating Range

V_CC

Conditions

Min

Typ

Max

Unit

V_EE= 0 V

1.7

3.0

1.8

3.3

1.8

3.6

V

DV_CC

V_TTI

V_EE= 0 V, DV_CC≤ (V_CC+ 1.3 V)

(V_EE+ 0.4 V + 0.5 × V_ID) < V_TTI< (V_CC+ 0.5 V)

V_EE

0.4

+

V_TTO

(V_CC− 1.1 V + 0.5 × V_OD) < V_TTO< (V_CC+ 0.5 V)

V_CC

1.1

−

1.8

3.6

V

Supply Current³

I_TTO

I_CC

I_EE

I_TTO

I_CC

I_EE

All outputs enabled

Single channel enabled

63

69

565

mA

460

586

16

173

205

18

214

LOGIC CHARACTERISTICS

Input High (V_IH)

Input Low (V_IL)

DVCC = 3.3 V

2.5

V

1.0

Output High (V_OH

Output Low (V_OL

)

1.0

THERMAL CHARACTERISTICS

Operating Temperature Range

θ_JA

−40

+85

°C

°C/W

22

¹V_ICMis the input common-mode voltage.

²Programmable via I²C.

³Assumes dc-coupled outputs. For ac-coupled outputs, I_TTOcurrents will double.

Rev. 0 | Page 4 of 4

ADN4600

TIMING SPECIFICATIONS

Table 2. I²C Timing Parameters

Parameter

Min

Max

400

N/A

300

N/A

7

Unit

kHz

μs

Description

f_SCL

0

SCL clock frequency

t_HD;STA

t_SU;STA

t_LOW

0.6

1.3

0.6

0

Hold time for a start condition

Setup time for a repeated start condition

Low period of the SCL clock

High period of the SCL clock

Data hold time

μs

t_HIGH

t_HD;DAT

t_SU;DAT

t_r

μs

ns

10

1

0.6

1

5

Data setup time

Rise time for both SDA and SCL

Fall time for both SDA and SCL

Setup time for a stop condition

Bus-free time between a stop and a start condition

Capacitance for each I/O pin

t_f

ns

t_SU;STO

t_BUF

C_IO

μs

ns

Pf

I²C Timing Specifications

SDA

t_SU:DAT

t_f

t_BUF

t_HD:STA

t_f

t_LOW

t_f

SCL

t_HD:STA

t_SU:STA

t_SU:STO

t_HIGH

t_HD:DAT

S

Sr

P

S

Figure 2. I²C Timing Diagram

Rev. 0 | Page 5 of 5

ADN4600

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

V_CCto V_EE

V_TTI

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

3.7 V

V_CC+ 0.6 V

V_TTO

Internal Power Dissipation

Differential Input Voltage

Logic Input Voltage

Storage Temperature Range

Lead Temperature

4.26 W

2.0 V

V_EE− 0.3 V < V_IN< V_CC+ 0.6 V

−65°C to +125°C

300°C

ESD CAUTION

Rev. 0 | Page 6 of 6

ADN4600

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

RESETB

VEE

IN0

1

2

3

4

5

6

7

8

9

48 SCL

47 SDA

46 VEE

45 IP7

44 IN7

43 VCC

42 IP6

41 IN6

40 VTTI

39 IP5

38 IN5

37 VEE

36 IP4

35 IN4

34 VCC

33 VEE

IP0

VCC

IN1

IP1

VTTI

IN2

IP2 10

VEE 11

IN3 12

ADN4600

TOP VIEW

(Not to Scale)

IP3 13

DVCC 14

VCC 15

VEE 16

NOTES

1. PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO VEE.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1

RESETB

Control

Power

Reset Input (Active Low)

Negative Supply

2, 11, 16, 17, 27, VEE

30, 32, 33, 37,

46, 53, 62, 64

3, 6, 9, 12, 35,

38, 41, 44

4, 7, 10, 13, 36,

39, 42, 45

IN0 to IN7

IP0 to IP7

I/O

High Speed Inputs

I/O

High Speed Input Complements

Positive Supply

5, 15, 18, 21, 31, VCC

34, 43, 59, 63

Power

8, 40

14

19, 22, 25, 28,

51, 54, 57, 60

VTTI

DVCC

ON7 to ON0

Power

I/O

Input Termination Supply

Digital Positive Supply (3.3 V)

High Speed Outputs

20, 23, 26, 29,

52, 55, 58, 61

OP7 to ON0

I/O

High Speed Output Complements

24, 56

47

48

49

50

VTTO

SDA

SCL

ADDR0

ADDR1

EPAD

Power

Output Termination Supply

Control

Power

I²C Control Interface Data Input/Output

I²C Control Interface Clock Input

I²C Control Interface Address LSB

I²C Control Interface Address MSB

Connect to VEE

Rev. 0 | Page 7 of 7

ADN4600

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 to Figure 8 were obtained using the standard test circuit shown in Figure 4.

50Ω CABLES

2

INPUT

OUTPUT

DATA OUT

50Ω

HIGH SPEED

SAMPLING

ADN4600

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

TP1

TP2

OSCILLOSCOPE

Figure 4. Standard Test Circuit (No Channel)

50ps/DIV

Figure 5. 3.25 Gbps Input Eye

(TP1 from Figure 4)

Figure 7. 3.25 Gbps Output Eye, No Channel

(TP2 from Figure 4)

50ps/DIV

Figure 6. 4.25 Gbps Input Eye

(TP1 from Figure 4)

Figure 8. 4.25 Gbps Output Eye, No Channel

(TP2 from Figure 4)

Rev. 0 | Page 8 of 8

ADN4600

Figure 10 to Figure 13 were obtained using the standard test circuit shown in Figure 9.

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

FR4 TEST BACKPLANE

50Ω

DIFFERENTIAL

STRIPLINE TRACES

8mils WIDE, 8mils SPACE,

8mils DIELECTRIC HEIGHT

ADN4600

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

OSCILLOSCOPE

TP1

TP2

TP3

TRACE LENGTHS = 30''

Figure 9. Input Equalization Test Circuit, FR4 (See Figure 5 and Figure 6 for the Reference Eye Diagrams at TP1)

50ps/DIV

Figure 10. 3.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

Figure 12. 3.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

50ps/DIV

Figure 11. 4.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

Figure 13. 4.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

Rev. 0 | Page 9 of 9

ADN4600

Figure 15 to Figure 18 were obtained using the standard test circuit shown in Figure 14.

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

FR4 TEST BACKPLANE

50Ω

DIFFERENTIAL

STRIPLINE TRACES

8mils WIDE, 8mils SPACE,

8mils DIELECTRIC HEIGHT

ADN4600

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

TP1

TP2

TP3

OSCILLOSCOPE

TRACE LENGTHS = 30''

Figure 14. Output Pre-Emphasis Test Circuit, FR4

50ps/DIV

Figure 15. 3.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = 0

(TP3 from Figure 14)

Figure 17. 3.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = Best Setting

(TP3 from Figure 14)

50ps/DIV

Figure 16. 4.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = 0

(TP3 from Figure 14)

Figure 18. 4.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = Best Setting

(TP3 from Figure 14)

Rev. 0 | Page 10 of 10

ADN4600

Test conditions: V_CC= 1.8 V, V_EE= 0 V, V_TTI= V_TTO= V_CC, R_L= 50 Ω, differential output swing = 800 mV p-p differential, T_A= 25°C,

unless otherwise noted.

80

100

70

60

50

40

80

60

40

20

V

= 3.3V

CC

30

20

10

V

= 1.8V

CC

0

1.0

20

40

60

1.5

2.0

2.5

3.0

3.5

4.0

DATA RATE (Hz)

INPUT COMMON MODE (V)

Figure 19. Deterministic Jitter vs. Data Rate

Figure 22. Deterministic Jitter vs. Input Common Mode

100

90

80

70

60

50

40

30

20

10

0

100

80

60

40

20

0

1.0

0

0.5

1.0

1.5

2.0

2.5

1.5

2.0

2.5

(V)

3.0

3.5

4.0

DIFFERENTIAL INPUT SWING (V)

V

CC

Figure 20. Deterministic Jitter vs. Input Swing

Figure 23. Deterministic Jitter vs. Supply Voltage

100

80

60

40

20

80

60

40

20

V

= 1.8V

CC

V

= 3.3V

CC

0

1.0

0

–60

1.5

2.0

2.5

(V)

3.0

3.5

4.0

–40

–20

0

20

40

60

80

100

V

TEMPERATURE (°C)

TTO

Figure 21. Deterministic Jitter vs. Temperature

Figure 24. Deterministic Jitter vs. Output Termination Voltage

Rev. 0 | Page 11 of 11

ADN4600

450000

400000

350000

300000

250000

200000

150000

100000

50000

100

90

80

70

60

t

/t

F

R

0

–8

50

–60

–6

–4

–2

0

2

4

6

8

10

–40

–20

0

20

40

60

80

100

JITTER (ps)

TEMPERATURE (°C)

Figure 25. Random Jitter Histogram

Figure 26. Rise Time/Fall Time vs. Temperature

Rev. 0 | Page 12 of 12

ADN4600

THEORY OF OPERATION

inversion function, which allows the user to swap the sign of the

input signal path to eliminate the need for board-level

crossovers in the receiver channel.

INTRODUCTION

The ADN4600 is an 8 × 8, buffered, asynchronous, 8-channel

crosspoint switch that allows fully nonblocking connectivity

between its transmitters and receivers. The switch supports

multicast and broadcast operation, allowing the ADN4600 to

work in redundancy and port-replication applications.

Table 5 illustrates some, but not all, possible combinations of

input supply voltages.

Equalization Settings

The ADN4600 receiver incorporates a multizero transfer

function with a continuous time equalizer, providing up to

22 dB of high-frequency boost at 2.25 GHz to compensate for

up to 30 in. of FR4 at 4.25 Gbps. The ADN4600 also allows

independent control of the equalizer transfer function on each

channel through the I²C control interface.

ADN4600

RECEIVE

EQUALIZATION

CROSSPOINT

ARRAY

TRANSMIT

PRE-EMPHASIS

IP[7:0]

IN[7:0]

OP[7:0]

ON[7:0]

EQ

PE

ADDR[1:0]

SCL

In the basic mode of operation, the equalizer transfer function

allows independent control of the boost in two frequency ranges

for optimal matching with the loss shape of the channel (for

example, the shape due primarily to skin effect or to dielectric

loss). The total equalizer shape space is reduced to two independent

frequency response groups—one optimized for cable and the

other optimized for FR4 material. The RX EQ bits of the

RX[7:0] configuration registers provide eight settings for each

frequency response group to ease programming for typical

channels.

CONTROL LOGIC

SDA

RESETB

Figure 27. Simplified Functional Block Diagram

The ADN4600 offers extensively programmable output levels

and pre-emphasis, as well as a squelch function and the ability

to fully disable the device. The receivers integrate a programmable,

multizero transfer function that has been optimized to compensate

either typical backplane or typical cable losses. The ADN4600

provides a balanced, high speed switch core that maintains low

channel-to-channel skew and preserves edge rates.

Table 6 summarizes the high-frequency boost for the frequency

response grouping optimized for the FR4 material; it lists the basic

control settings and the typical length of FR4 trace compensated

for by each setting. All eight channels of the ADN4600 use the

FR4-optimized frequency response grouping by default. The

user can override this default by setting the respective RX LUT

select bit high and then selecting the frequency response grouping

by setting the RX LUT FR4/CX4 bit high for FR4 and low for

cable. Setting the RX EQBY bit of the RX[7:0] configuration

registers high sets the equalization to 1.5 dB of boost, which

compensates for 0 m to 2 m of CX4 or 0 in. to 10 in. of FR4.

The I/O on-chip termination resistors are tied to user-settable

supplies to support dc coupling in various logic styles. The

ADN4600 supports a wide core supply range; V_CCcan be set

from 1.8 V to 3.3 V. These features together with programmable

transmitter output levels allow for several dc- and ac-coupled

I/O configurations.

RECEIVERS

Input Structure and Input Levels

SIMPLIFIED RECEIVER INPUT CIRCUIT

VCC

In the advanced mode of operation, full control of the equalizer is

available through the I²C control interface. The user can specify

the boost in the midfrequency range and the boost in the high

frequency range independently. This is accomplished by

circumventing the frequency response groupings shown in

Table 6 by setting the EQ CTL SRC bit (Bit 6 of the RX[7:0]

EQ1 control registers) high and writing directly to the equalizer

control bits on a per channel basis. Therefore, write values to

Bits[5:0] of the RX[7:0] EQ1 control registers and to Bits[5:0]

of the RX[7:0] EQ3 control registers for the channel of interest.

The bits of these registers are ordered such that Bit 5 is a sign

bit, and midlevel boost is centered around 0x00. Setting Bit 5

low and increasing the LSBs decreases the boost, whereas

setting Bit 5 high and increasing the LSBs increases the boost.

VTTI

RLN

RL

RLP

RL

RP

52Ω

RN

52Ω

R1

750Ω

Q1

IPx

INx

R3

1kΩ

Q2

R2

750Ω

I1

VEE

Figure 28. Simplified Input Structure

The ADN4600 receiver inputs incorporate 50 Ω termination

resistors, ESD protection, and a multizero transfer function

equalizer that can be optimized for backplane and cable operation.

Each receive channel also provides a positive/negative (P/N)

Rev. 0 | Page 13 of 13

ADN4600

Table 5. Common Input Voltage Levels

Configuration

V_CC(V)

1.8

V_TTI(V)

1.6

1.8

Low V_TTI, AC-Coupled Input

Single 1.8 V Supply

3.3 V Core

3.3

1.8

Single 3.3 V Supply

3.3

Table 6. Receive Equalizer Boost vs. Setting

RX EQ Bit Settings

Boost (dB)

Typical FR4 Trace Length (Inches)

0

1

2

3

4

5

6

7

3.5

3.9

4.25

4.5

4.75

5.0

5 to 10

10 to 15

15 to 20

20 to 25

25 to 30

30 to 35

35 to 40

5.3

5.5

Table 7. Equalization Control Registers

Name

Addr

Bit 7

Bit 6

Bit 5

RX EQBY

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

RX[7:0] Configuration 0xB8, 0xB0,

0xA8, 0xA0,

RX PNSWAP

RX EN

RX EQ[2]

RX EQ[1]

RX EQ[0]

0x30

0x98, 0x90,

0x88, 0x80

RX[7:0] EQ1 Control

RX[7:0] EQ3 Control

RX[7:0] FR4 Control

0xBB, 0xB3,

0xAB, 0xA3,

0x9B, 0x93,

0x8B, 0x83

EQ CTL SRC

RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX EQ1[1] RX EQ1[0] 0x00

RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00

0xBC, 0xB4,

0xAC, 0xA4,

0x9C, 0x94,

0x8C, 0x84

0xBD, 0xB5,

0xAD, 0xA5,

0x9D, 0x95,

0x8D, 0x85

RX LUT

select

RX LUT

FR4/CX4

0x00

for each of the eight channels and is controlled through the I²C

control interface.

Lane Inversion

The receiver P/N inversion feature is a convenience intended to

allow the user to implement the equivalent of a board-level

crossover in a much smaller area and without additional via

impedance discontinuities that degrade the high-frequency

integrity of the signal path. The P/N inversion is independent

Warning

Using the lane inversion feature to account for signal inversions

downstream of the receiver requires additional attention when

switching connectivity.

Rev. 0 | Page 14 of 14

ADN4600

desired output changes has been preprogrammed. Bit 3 of the

XPT configuration register (Address 0x40) signals whether a

broadcast condition is desired. If this bit is set high, the input

selected by Bits[6:4] is sent to all outputs. All output connections

can then be programmed simultaneously by passing the data

from the first rank of latches into the second rank by writing

0x01 to the XPT update register (Address 0x41). This is a self-

clearing register and therefore always reads back as 0x00. The

output connections always reflect the data programmed into the

second rank of latches and do not change until the first rank of data

is passed into the second rank by strobing the XPT update register.

SWITCH CORE

The ADN4600 switch core is a fully nonblocking 8 × 8 array

that allows multicast and broadcast configurations. The

configuration of the switch core is controlled through the I²C

control interface. The control interface receives and stores the

desired connection matrix for the eight input and eight output

signal pairs. The interface consists of eight rows of double-rank

latches, one for each output. The 2-bit data-word stored in these

latches indicates to which (if any) of the eight inputs the output

will be connected.

One output at a time can be preprogrammed by addressing the

output and writing the desired connection data into the first rank

of latches. This is done by writing to the XPT configuration

register (Address 0x40). The output being addressed is written

into Bits[2:0], and the input being sent to this output is written

into Bits[6:4]. This process can be repeated until each of the

If necessary for system verification, the data in the first rank of

latches can be read back from the control interface. This is done

by reading from the XPT Temp[3:0] registers, which show the

status of the input data programmed in the first rank of latches

for each output.

Table 8. Switch Core Control and Status Registers

Name

Addr Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

XPT Configuration

0x40

IN PORT

[2]

IN PORT

[1]

IN PORT

[0]

Broadcast

OUT PORT

[2]

OUT PORT

[1]

OUT PORT

[0]

0x00

XPT Update

XPT Status 0

XPT Status 1

XPT Status 2

XPT Status 3

XPT Status 4

XPT Status 5

XPT Status 6

XPT Status 7

0x41

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

Update

OUT0[0]

OUT1[0]

OUT2[0]

OUT3[0]

OUT4[0]

OUT5[0]

OUT6[0]

OUT7[0]

0x00

N/A

OUT0[2]

OUT1[2]

OUT2[2]

OUT3[2]

OUT4[2]

OUT5[2]

OUT6[2]

OUT7[2]

OUT0[1]

OUT1[1]

OUT2[1]

OUT3[1]

OUT4[1]

OUT5[1]

OUT6[1]

OUT7[1]

Table 9. Switch Core Temporary Registers

Name

Addr Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

N/A

XPT Temp 0

XPT Temp 1

XPT Temp 2

XPT Temp 3

0x58

0x59

0x5A

0x5B

OUT1[2] OUT1[1]

OUT3[2] OUT3[1]

OUT5[2] OUT5[1]

OUT7[2] OUT7[1]

OUT1[0]

OUT3[0]

OUT5[0]

OUT7[0]

OUT0[2]

OUT2[2]

OUT4[2]

OUT6[2]

OUT0[1]

OUT2[1]

OUT4[1]

OUT6[1]

OUT0[0]

OUT2[0]

OUT4[0]

OUT6[0]

Rev. 0 | Page 15 of 15

ADN4600

The output equalization is optimized for less than 2.5 Gbps

operation, but can be optimized for higher speed applications

up to 4.25 Gbps through the I²C control interface by writing to

the TX DATA RATE bit (Bit 4) of the TX[7:0] configuration

register, with high representing 4.25 Gbps and low representing

2.5 Gbps. The TX[7:0] CTL SRC bit (Bit 7) in the TX[7:0]

Output Level Control 1 register determines whether the pre-

emphasis and output current controls for the channel of interest

are selected from the optimized map or directly from the

TX[7:0] Output Level Control[1:0] registers (per channel).

Setting this bit high selects pre-emphasis control directly from

the TX[7:0] Output Level Control[1:0] registers, and setting it

low selects pre-emphasis control from the optimized map.

TRANSMITTERS

Output Structure and Output Levels

The ADN4600 transmitter outputs incorporate 50 Ω termination

resistors, ESD protection, and output current switch. Each

channel provides independent control of both the absolute

output level and the pre-emphasis output level. It should be

noted that the choice of output level affects the output common-

mode level. A 600 mV p-p differential output level with full

pre-emphasis range requires an output termination voltage

of 2.5 V or greater; therefore, for the VTTO pin, V_CCmust be

equal to or greater than 2.5 V.

Pre-Emphasis

TX SIMPLIFIED DIAGRAM

The total output amplitude and pre-emphasis setting space is

reduced to a single map of basic settings that provides seven

settings of output equalization to ease programming for typical

channels. The full resolution of seven settings is available through

the I²C interface by writing to Bits[2:0] (the TX PE[2:0] bits) of

the TX[7:0] configuration registers. Table 10 summarizes the

absolute output level, pre-emphasis level, and high frequency

boost for each of the control settings and the typical length of

FR4 trace compensated for by each setting.

VCC

ON-CHIP

TERMINATION

ESD

VTTO

V3

VC

RP

RN

52Ω

V2

VP

OPx

ONx

V1

VN

Q1

Q2

Full control of the transmit output levels is available through the

I²C control interface. This full control is achieved by writing to

the TX[7:0] Output Level Control[1:0] registers for the channel

of interest. The supported output levels are shown in Table 12.

The TX[7:0] Output Level Control[1:0] registers must be

programmed to one of the supported settings listed in this table;

other settings are not supported.

IT

I

+ T

PE

DC

VEE

Figure 29. Simplified Output Structure

Table 10. Transmit Pre-Emphasis Boost and Overshoot vs. Setting

TX PE

Boost (dB)

Overshoot

DC Swing (mV p-p Differential)

Typical FR4 Trace Length (Inches)

0

1

2

3

4

5

6

0

2

0%

25%

50%

75%

100%

133%

200%

800

600

400

0 to 5

3.5

4.9

6

7.4

9.5

10 to 15

15 to 20

25 to 30

30 to 35

35 to 40

Table 11. Transmitters Control Registers

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Def.

TX[7:0]

Configuration

0xE0, 0xE8,

0xF0, 0xF8,

0xD8, 0xD0,

0xC8, 0xC0

TX EN

TX data

rate

TX PE[2]

TX PE[1]

TX PE[0]

0x20

0x40

TX[7:0] Output

Level Control 1

0xE1, 0xE9,

0xF1, 0xF9,

0xD9, 0xD1,

0xC9, 0xC1

TX[7:0]

CTL SRC

TX[7:0]_OLEV1[6:0]

TX[7:0]_OLEV0[6:0]

TX[7:0] Output

Level Control 0

0xE2, 0xEA,

0xF2, 0xFA,

0xDA, 0xD2,

0xCA, 0xC2

Rev. 0 | Page 16 of 16

ADN4600

Table 12. Output Level Programming

V_OD(mV)

V_DPeak (mV)

PE (dB)

0.00

9.54

13.98

16.90

19.08

20.83

22.28

0.00

6.02

9.54

12.04

13.98

15.56

16.90

0.00

4.44

7.36

9.54

11.29

12.74

13.98

0.00

3.52

6.02

7.96

9.54

10.88

12.04

0.00

2.92

5.11

6.85

8.30

9.54

10.63

0.00

2.50

4.44

6.02

7.36

8.52

9.54

0.00

2.18

3.93

5.38

6.62

7.71

8.67

0.00

1.94

3.52

I_TOT(mA)

2

6

10

14

18

22

26

4

Tx[7:0] Output Level Control 0

Tx[7:0] Output Level Control 1

50

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x81

0x91

0x92

0xA2

0xA3

0xB3

0xB4

0xC4

150

250

350

450

550

650

100

200

300

400

500

600

700

150

250

350

450

550

650

750

200

300

400

500

600

700

800

250

350

450

550

650

750

850

300

400

500

600

700

800

900

350

450

550

650

750

850

950

400

500

600

100

150

200

250

300

350

400

8

12

16

20

24

28

6

10

14

18

22

26

30

8

12

16

20

24

28

32

10

14

18

22

26

30

34

12

16

20

24

28

32

36

14

18

22

26

30

34

38

16

20

24

Rev. 0 | Page 17 of 17

ADN4600

V_OD(mV)

400

450

500

550

600

650

700

750

800

850

900

V_DPeak (mV)

700

800

900

1000

450

550

650

750

850

950

1050

500

600

700

800

900

1000

1100

550

650

750

850

950

1050

1150

600

700

800

PE (dB)

4.86

6.02

7.04

7.96

0.00

1.74

3.19

4.44

5.52

6.49

7.36

0.00

1.58

2.92

4.08

5.11

6.02

6.85

0.00

1.45

2.69

3.78

4.75

5.62

6.41

0.00

1.34

2.50

3.52

4.44

5.26

6.02

0.00

1.24

2.33

3.30

4.17

4.96

0.00

1.16

2.18

3.10

3.93

0.00

1.09

2.05

2.92

0.00

1.02

1.94

0.00

0.97

0.00

I_TOT(mA)

28

32

36

40

18

22

26

30

34

38

42

20

24

28

32

36

40

44

22

26

30

34

38

42

46

24

28

32

36

40

44

48

26

30

34

38

42

46

28

32

36

40

44

30

34

38

42

32

36

40

34

38

36

Tx[7:0] Output Level Control 0

Tx[7:0] Output Level Control 1

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x01

0x12

0x23

0x34

0x45

0x56

0x02

0x13

0x24

0x35

0x46

0x03

0x14

0x25

0x36

0x04

0x15

0x26

0x05

0x16

0x06

0xC4

0xC5

0xD5

0xD6

0xE6

900

1000

1100

1200

650

750

850

950

1050

1150

700

800

900

1000

1100

750

850

950

1050

800

900

1000

850

950

900

Rev. 0 | Page 18 of 18

ADN4600

VTTO

High Current Setting and Output Level Shift

dV

In low voltage applications, users must pay careful attention to

both the differential and common-mode signal levels (see Figure 30

and Table 13). Failure to understand the implications of signal

level and choice of ac or dc coupling will almost certainly lead

to transistor saturation and poor transmitter performance.

OCM

V

H

V

OD

V

OCM

V

L

TxHeadroom

There is a TxHeadroom register (I²C Register Address 0x23)

that allows configuration of the individual transmitters for

extra headroom at the output for high current applications. The

bits in this register are active high (default). There is one bit for

each transmitter of the device (see Table 17). Setting this bit

high puts the respective transmitter in a configuration for extra

headroom, and setting this bit low does not provide extra

headroom.

V

= 2 × V

OD

ODPP

VEE

Figure 30. Simplified Output Voltage Levels Diagram

Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs

Table 13. Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs

Output Levels and Output Compliance

AC-Coupled Transmitter

V_HV_L

Peak Peak dV_OCMV_H

DC-Coupled Transmitter

V_HV_LMin Max

Peak Peak V_L

TxHeadroom = 0

TxHeadroom = 1

V_D

Min

V_CC− V_LV_CC

Min

V_L

Max

V_CC− V_LMin

V_ODI_TOTPeak PE

PE

dV_OCMV_H

V_L

(mV) (V) (V) (V)

(mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V)

(V)

V

_CC(V)

V_TTOand V_CC= 3.3 V

200

8

200 1.00 0.00 200

300 1.50 3.52 300

400 2.00 6.02 400

500 2.50 7.96 500

600 3.00 9.54 600

700 3.50 10.88 700

800 4.00 12.04 800

300 1.00 0.00 300

400 1.33 2.50 400

500 1.67 4.44 500

600 2.00 6.02 600

700 2.33 7.36 700

800 2.67 8.52 800

900 3.00 9.54 900

400 1.00 0.00 400

500 1.25 1.94 500

600 1.50 3.52 600

700 1.75 4.86 700

800 2.00 6.02 800

900 2.25 7.04 900

3.2

3

3.2

3

100

3.3 3.1 3.3

3.25 3.05 3.3

3.1

3

2.225 1.1

1.8

1.9

1.8

1.9

1.8

1.9

2

1.2

2

2.2

2

2.2

2

200 12

200 16

200 20

200 24

200 28

200 32

300 12

300 16

300 20

300 24

300 28

300 32

300 36

400 16

400 20

400 24

400 28

400 32

400 36

400 40

600 24

600 28

600 32

600 36

600 40

600 44

600 48

3.1 2.9 3.15 2.85 150

2.8 3.1 2.7 200

2.9 2.7 3.05 2.55 250

2.8 2.6 2.4 300

2.7 2.5 2.95 2.25 350

2.6 2.4 2.9 2.1 400

3.15 2.85 3.15 2.85 150

3.05 2.75 3.1 2.7 200

2.95 2.65 3.05 2.55 250

2.85 2.55 3 2.4 300

2.75 2.45 2.95 2.25 350

2.65 2.35 2.9 2.1 400

2.55 2.25 2.85 1.95 450

3.1 2.7 3.1 2.7 200

2.6 3.05 2.55 250

2.9 2.5 2.4 300

2.8 2.4 2.95 2.25 350

2.7 2.3 2.9 2.1 400

2.6 2.2 2.85 1.95 450

3

3.2

3

3.3

2.9

2.8

2.7

2.6

2.5

3

3.15 2.95 3.3

3.1 2.9 3.3

3.05 2.85 3.3

3

2.8 3.3

3.3

3

3.25 2.95 3.3

3.2 2.9 3.3

3.15 2.85 3.3

3.1 2.8 3.3

3.05 2.75 3.3

2.9

2.8

2.7

2.6

2.5

2.4

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.7

2.6

2.5

2.4

2.3

2.2

2.1

3

2.7 3.3

3.3 2.9 3.3

3.25 2.85 3.3

3.2 2.8 3.3

3.15 2.75 3.3

3.1 2.7 3.3

3.05 2.65 3.3

3

2

2.2

1000 2.50 7.96 1000 2.5 2.1 2.8

1.8

2.4

500

300

3

2.6 3.3

600 1.00 0.00 600

700 1.17 1.34 700

800 1.33 2.50 800

900 1.50 3.52 900

3

2.4

3

3.3 2.7 3.3

3.25 2.65 3.3

3.2 2.6 3.3

3.15 2.55 3.3

3.1 2.5 3.3

3.05 2.45 3.3

2.1

1.1

2.9 2.3 2.95 2.25 350

2.8 2.2 2.9 2.1 400

2.7 2.1 2.85 1.95 450

2.8 1.8 500

1200 1.83 5.26 1100 2.5 1.9 2.75 1.65 550

1400 2.00 6.02 1200 2.4 1.8 2.7 1.5 600

2.225 1.1

1000 1.67 4.44 1000 2.6

2

2.1

1.1

3

2.4 3.3

Rev. 0 | Page 19 of 19

ADN4600

Output Levels and Output Compliance

V_D

AC-Coupled Transmitter

V_HV_L

Peak Peak dV_OCMV_H

DC-Coupled Transmitter

V_HV_LMin Max

Peak Peak V_L

TxHeadroom = 0

TxHeadroom = 1

Min

V_CC− V_LV_CC

Min

V_L

Max

V_CC− V_LMin

V_ODI_TOTPeak PE

PE

dV_OCMV_H

V_L

(mV) (V) (V) (V)

(mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V)

V_TTOand V_CC= 1.8 V¹

(V)

V_CC(V)

200

8

200 1.00 0.00 200

300 1.50 3.52 300

400 2.00 6.02 400

500 2.50 7.96 500

600 3.00 9.54 600

300 1.00 0.00 300

400 1.33 2.50 400

500 1.67 4.44 500

600 2.00 6.02 600

700 2.33 7.36 700

400 1.00 0.00 400

500 1.25 1.94 500

600 1.50 3.52 600

700 1.75 4.86 700

800 2.00 6.02 800

600 1.00 0.00 600

1.7 1.5 1.7

1.5

100

1.8 1.6 1.8

1.75 1.55 1.8

1.7 1.5 1.8

1.65 1.45 1.8

1.6 1.4 1.8

1.8 1.5 1.8

1.75 1.45 1.8

1.7 1.4 1.8

1.65 1.35 1.8

1.6 1.3 1.8

1.8 1.4 1.8

1.75 1.35 1.8

1.7 1.3 1.8

1.65 1.25 1.8

1.6 1.2 1.8

1.8 1.2 1.8

1.6

1.5

1.4

1.3

1.2

1.5

1.4

1.3

1.2

1.1

1.4

1.3

1.2

1.1

1

0.725 1.1

1.8

1.9

0.5

NA

200 12

200 16

200 20

200 24

300 12

300 16

300 20

300 24

300 28

400 16

400 20

400 24

400 28

400 32

600 24

1.6 1.4 1.65 1.35 150

1.5 1.3 1.6 1.2 200

1.4 1.2 1.55 1.05 250

1.3 1.1 1.5 0.9 300

1.65 1.35 1.65 1.35 150

1.55 1.25 1.6 1.2 200

1.45 1.15 1.55 1.05 250

1.35 1.05 1.5 0.9 300

1.25 0.95 1.45 0.75 350

1.6 1.2 1.6 1.2 200

1.5 1.1 1.55 1.05 250

1.4 1.5 0.9 300

1.3 0.9 1.45 0.75 350

1

1.2 0.8 1.4

1.5 0.9 1.5

0.6

0.9

400

300

1.2

0.6

1.1

1

TxHeadroom = 1 is not an option at V_TTOand V_CC= 1.8 V.

Table 14. Symbol Definitions for Output Levels vs. Setting

Symbol

Formula

Definition

Peak differential output voltage

V_OD

25 Ω × I_DC

V_ODPP

25 Ω × I_DC× 2 = 2 × V_OD

25 Ω × I_TX/2 = V_ODPP/4 + (I_PE/2 × 25)

50 Ω × I_TX/2 = V_ODPP/2 + (I_PE/2 × 50)

V_OD/R_TERM

Peak-to-peak differential output voltage

Output common-mode shift

dV_{OCM_DC-COUPLED}

dV_{OCM_AC-COUPLED}

Output common-mode shift

I_DC

I_PE

I_TX

V_H

V_L

Output current that sets output level

Output current used for PE

–

I_DC+ I_PE

Total transmitter output current

Maximum single-ended output voltage

Minimum single-ended output voltage

V_TTO− dV_OCM+ V_OD/2

V_TTO− dV_OCM− V_OD/2

Rev. 0 | Page 20 of 20

ADN4600

Selective Squelch and Disable

the output termination resistors. The transmitter recovers from

squelch in less than 100 ns.

Each transmitter is equipped with disable and squelch controls.

Disable is a full power-down state: all transmitter current,

including output current, is reduced to 0 mA and the output

pins are pulled up to VTTO, but there is a delay of

approximately 1 μs associated with re-enabling the transmitter.

The output disable control is accessed through the TX EN bit

(Bit 5) of the TX[7:0] configuration registers through the I²C

control interface.

The output squelch and the output disable control can both be

accessed through the TX[7:0] squelch control registers, with the

top nibble representing the squelch control and the bottom nibble

representing the output disable for one channel. The channels

are disabled or squelched by writing 0s to the corresponding

nibbles. The channels are enabled by writing all 1s, which is the

default setting. For example, to squelch channel TX0, Register

0xC3 must be set to 0x0F. The entire nibble must be written to

all 0s for this functionality.

Squelch simply reduces the output current to submicroamp

levels, allowing both output pins to pull up to VTTO through

Table 15. Transmitters Squelch Control Registers

Name

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

TX[7:0] Squelch Control 0xE3, 0xEB,

0xF3, 0xFB,

SQUELCHb[3:0]

DISABLEb[3:0]

0xFF

0xDB, 0xD3,

0xCB, 0xC3

Rev. 0 | Page 21 of 21

ADN4600

I²C CONTROL INTERFACE

Serial Interface General Functionality

7. Send the data (eight bits) to be written to the register

whose address was set in Step 5. This transfer should be

MSB first.

The ADN4600 register set is controlled through a 2-wire I²C

interface. The ADN4600 acts only as an I²C slave device. Therefore,

the I²C bus in the system needs to include an I²C master to

configure the ADN4600 and other I²C devices that may be on

the bus. Data transfers are controlled by the two I²C wires: the

SCL input clock pin and the SDA bidirectional data pin.

The ADN4600 I²C interface can be run in the standard (100 kHz)

and fast (400 kHz) modes. The SDA line only changes value

when the SCL pin is low, with two exceptions: the SDA pin is

driven low while the SCL pin is high to indicate the beginning

or continuation of a transfer, and the SDA line is driven high

while the SCL line is high to indicate the end of a transfer.

Therefore, it is important to control the SCL clock to toggle

only when the SDA line is stable, unless indicating a start,

repeated start, or stop condition.

8. Wait for the ADN4600 to acknowledge the request.

9. Send a stop condition (that is, while holding the SCL line

high, pull the SDA line high) and release control of the bus.

10. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 in this procedure to perform another write.

11. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 of the read procedure (see the I²C Interface Data

Transfers: Data Read section) to perform a read from

another address.

12. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 8 of the read procedure (in the I²C Interface Data

Transfers: Data Read section) to perform a read from the

same address set in Step 5 of the write procedure.

I²C Interface Data Transfers: Data Write

To write data to the ADN4600 register set, a microcontroller

(or any other I²C master) needs to send the appropriate control

signals to the ADN4600 slave device. Use the following steps,

where the signals are controlled by the I²C master unless otherwise

specified. A diagram of the procedure is shown in Figure 31.

In Figure 31, the ADN4600 write process is shown. The SCL

signal is shown, along with a general write operation and a

specific example. In the example, Data 0x92 is written to Register

Address 0x6D of an ADN4600 part with a slave address of 0x4B.

The slave address is seven bits wide. The upper five bits of the

slave address are internally set to b10010. The lower two bits

are controlled by the ADDR[1:0] pins. In this example, the bits

controlled by the ADDR[1:0] pins are set to b11. In the figure,

the corresponding step number is visible in the circle under the

waveform. The SCL line is driven by the I²C master, not by the

ADN4600 slave. As for the SDA line, the data in the shaded

polygons of Figure 31 is driven by the ADN4600, whereas the

data in the nonshaded polygons is driven by the I²C master. The

end phase case shown corresponds with Step 9.

1. Send a start condition (that is, while holding the SCL line

high, pull the SDA line low).

2. Send the ADN4600 part address (seven bits), whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the ADDR1 and ADDR0 input pins.

This transfer should be MSB first.

3. Send the write indicator bit (0).

4. Wait for the ADN4600 to acknowledge the request.

5. Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

It is important to note that the SDA line only changes when

the SCL line is low, except when a start, stop, or repeated start

condition is being sent, as is the case in Step 1 and Step 9.

6. Wait for the ADN4600 to acknowledge the request.

SCL

GENERAL CASE

ADDR

[1:0]

START

FIXED PART ADDR

REGISTER ADDR

DATA

STOP

SDA

R/W ACK

ACK

EXAMPLE

SDA

1

2

3

4

5

6

7

8

9

Figure 31. I²C Write Diagram

Rev. 0 | Page 22 of 22

ADN4600

I²C Interface Data Transfers: Data Read

14. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 of the write procedure (see the I²C Interface Data

Transfers: Data Write section) to perform a write.

15. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 2 of the read procedure to perform a read from a

another address.

16. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low) and continue with

Step 8 of the read procedure to perform a read from the

same address.

To read data from the ADN4600 register set, a microcontroller

(or any other I²C master) needs to send the appropriate control

signals to the ADN4600 slave device. Use the following steps,

where the signals are controlled by the I²C master unless otherwise

specified. A diagram of the procedure is shown in Figure 32.

1. Send a start condition (that is, while holding the SCL line

high, pull the SDA line low).

2. Send the ADN4600 part address (seven bits), whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the ADDR1 and ADDR0 input pins.

This transfer should be MSB first.

In Figure 32, the ADN4600 read process is shown. The SCL

signal is shown, along with a general read operation and a

specific example. In the example, Data 0x49 is read from Register

Address 0x6D of an ADN4600 part with a slave address of 0x4B.

The part address is seven bits wide. The upper five bits of the

slave address are internally set to b10010. The lower two bits

are controlled by the ADDR[1:0] pins. In this example, the bits

controlled by the ADDR[1:0] pins are set to b11. In Figure 32,

the corresponding step number is visible in the circle under the

waveform. The SCL line is driven by the I²C master, not by the

ADN4600 slave. As for the SDA line, the data in the shaded

polygons of Figure 32 is driven by the ADN4600, whereas the

data in the nonshaded polygons is driven by the I²C master. The

end phase case shown corresponds with Step 13.

3. Send the write indicator bit (0).

4. Wait for the ADN4600 to acknowledge the request.

5. Send the register address (eight bits) from which data is to

be read. This transfer should be MSB first. The register

address is kept in the ADN4600 memory until the part is

reset or the register address is written over with the same

procedure (Step 1 to Step 6 of the write procedure; see the

I²C Interface Data Transfers: Data Write section).

6. Wait for the ADN4600 to acknowledge the request.

7. Send a repeated start condition (that is, while holding the

SCL line high, pull the SDA line low).

8. Send the ADN4600 part address (seven bits), whose upper

five bits are the static value b10010 and whose lower two

bits are controlled by the ADDR1 and ADDR0 input pins.

This transfer should be MSB first.

It is important to note that the SDA line only changes when

the SCL line is low, except when a start, stop, or repeated start

condition is being sent, as is the case in Step 1, Step 7, and Step 13.

In Figure 32, Sr represents a repeated start where the SDA line

is brought high before SCL is raised. SDA is then dropped while

SCL is still high.

9. Send the read indicator bit (1).

10. Wait for the ADN4600 to acknowledge the request.

11. The ADN4600 then serially transfers the data (eight bits) held

in the register indicated by the address set in Step 5.

12. Acknowledge the data.

13. Send a stop condition (that is, while holding the SCL line

high, pull the SDA line high) and release control of the bus.

SCL

GENERAL CASE

ADDR R/

FIXED PART

ADDR

FIXED PART

ADDR

START

REGISTER ADDR

DATA

STOP

SDA

A

6

Sr

A

[1:0]

W

EXAMPLE

SDA

1

2

3

4

5

7

8

9

10

11

12

13

NOTES

1. A = ACK.

2. Sr = A REPEATED START WHERE THE SDA LINE IS BROUGHT HIGH BEFORE SCL IS RAISED.

Figure 32. I²C Read Diagram

Rev. 0 | Page 23 of 23

ADN4600

Transmission Lines

PCB DESIGN GUIDELINES

Use of 50 ꢀ transmission lines is required for all high frequency

input and output signals to minimize reflections. It is also necessary

for the high speed pairs of differential input traces, as well as the

high speed pairs of differential output traces, to be matched in

length to avoid skew between the differential traces.

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the VEE

plane using plugged vias so that solder does not leak through

the vias during reflow.

Soldering Guidelines for Chip Scale Package

The lands on the LFCSP are rectangular. The printed circuit

board pad for these should be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land should be centered on the pad. This ensures that the

solder joint size is maximized. The bottom of the chip scale

package has a central exposed pad. The pad on the printed

circuit board should be at least as large as this exposed pad. The

user must connect the exposed pad to VEE using plugged vias

so that solder does not leak through the vias during reflow. This

ensures a solid connection from the exposed pad to VEE.

Use of a 10 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. It is recommended that 0.1 μF and 1 nF ceramic chip

capacitors be placed in parallel at each supply pin for high

frequency power supply decoupling. When using 0.1 μF and 1 nF

ceramic chip capacitors, they should be placed between the IC

power supply pins (VCC, VTTI, VTTO) and VEE, as close as

possible to the supply pins.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be attained by using close spacing

between the planes. This capacitance is given by

C

_PLANE= 0.88ε_rA/d (pF)

where:

ε_ris the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm²).

d is the separation between planes (mm).

For FR4, ε_r= 4.4 and 0.25 mm spacing, C ~15 pF/cm².

Rev. 0 | Page 24 of 24

ADN4600

CONTROL REGISTER MAP

Table 16. Basic Mode I²C Register Definitions

Addr

(Hex) Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0x00

0x40

Reset

XPT

Configuration

IN PORT[2]

IN PORT[1]

IN PORT[0]

Broadcast

OUT PORT[2]

OUT PORT[1]

OUT PORT[0]

0x00

0x41

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x80

XPT Update

XPT Status 0

XPT Status 1

XPT Status 2

XPT Status 3

XPT Status 4

XPT Status 5

XPT Status 6

XPT Status 7

XPT Temp 0

XPT Temp 1

XPT Temp 2

XPT Temp 3

Update

OUT0[2]

OUT1[2]

OUT2[2]

OUT3[2]

OUT4[2]

OUT5[2]

OUT6[2]

OUT7[2]

OUT0[2]

OUT2[2]

OUT4[2]

OUT6[2]

RX EQ[2]

OUT0[1]

OUT1[1]

OUT2[1]

OUT3[1]

OUT4[1]

OUT5[1]

OUT6[1]

OUT7[1]

OUT0[1]

OUT2[1]

OUT4[1]

OUT6[1]

RX EQ[1]

OUT0[0]

OUT1[0]

OUT2[0]

OUT3[0]

OUT4[0]

OUT5[0]

OUT6[0]

OUT7[0]

OUT0[0]

OUT2[0]

OUT4[0]

OUT6[0]

RX EQ[0]

OUT1[2]

OUT3[2]

OUT5[2]

OUT7[2]

OUT1[1]

OUT3[1]

OUT5[1]

OUT7[1]

RX EQBY

OUT1[0]

OUT3[0]

OUT5[0]

OUT7[0]

RX EN

RX0

RX

0x30

0x20

Configuration

PNSWAP

0x88

0x90

0x98

0xA0

0xA8

0xB0

0xB8

0xC0

0xC8

0xD0

0xD8

0xE0

0xE8

0xF0

0xF8

RX1

Configuration

RX

PNSWAP

RX EQBY

TX EN

RX EN

RX EQ[2]

TX PE[2]

RX EQ[1]

TX PE[1]

RX EQ[0]

TX PE[0]

RX2

Configuration

RX

PNSWAP

RX EN

RX3

Configuration

RX

PNSWAP

RX EN

RX4

Configuration

RX

PNSWAP

RX EN

RX5

Configuration

RX

PNSWAP

RX EN

RX6

Configuration

RX

PNSWAP

RX EN

RX7

Configuration

RX

PNSWAP

RX EN

TX0

Configuration

TX data rate

TX1

Configuration

TX EN

TX2

Configuration

TX EN

TX3

Configuration

TX EN

TX7

Configuration

TX EN

TX6

Configuration

TX EN

TX5

Configuration

TX EN

TX4

TX EN

Configuration

Rev. 0 | Page 25 of 25

ADN4600

Table 17. Advanced Mode I²C Register Definitions

Addr

(Hex) Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0x00

0x23

0x83

TxHeadroom

TxH_B3

TxH_B2

EQ CTL SRC

TxH_B1

RX EQ1[5]

TxH_B0

RX EQ1[4]

TxH_A3

RX EQ1[3]

TxH_A2

RX EQ1[2]

TxH_A1

RX EQ1[1]

TxH_A0

RX EQ1[0]

RX0 EQ1

Control

0x00

0x84

0x85

0x8B

0x8C

0x8D

0x93

0x94

0x95

0x9B

0x9C

0x9D

0xA3

0xA4

0xA5

0xAB

0xAC

RX0 EQ3

Control

RX EQ3[5]

RX EQ3[4]

RX EQ3[3]

RX EQ3[2]

RX EQ3[1]

RX EQ3[0]

0x00

0x40

0xFF

0x40

0xFF

RX0 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX1 EQ1

Control

EQ CTL SRC

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX EQ3[0]

RX1 EQ3

Control

RX EQ3[1]

RX1 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX2 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX2 EQ3

Control

RX EQ3[1]

RX EQ3[0]

RX2 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX3 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX EQ3[0]

RX3 EQ3

Control

RX EQ3[1]

RX3 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX4 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX4 EQ3

Control

RX EQ3[1]

RX EQ3[0]

RX4 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX5 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX EQ3[0]

RX5 EQ3

Control

RX EQ3[1]

0xAD RX5 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

0xB3

0xB4

0xB5

0xBB

0xBC

0xBD

0xC1

0xC2

0xC3

0xC9

0xCA

0xCB

RX6 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX EQ3[0]

RX6 EQ3

Control

RX EQ3[1]

RX6 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

RX7 EQ1

Control

RX EQ1[5]

RX EQ3[5]

RX EQ1[4]

RX EQ3[4]

RX EQ1[3]

RX EQ3[3]

RX EQ1[2]

RX EQ3[2]

RX EQ1[1]

RX EQ1[0]

RX7 EQ3

Control

RX EQ3[1]

RX EQ3[0]

RX7 FR4

Control

RX LUT

select

RX LUT

FR4/CX4

TX0 Output

Level Control 1 SRC

TX0 CTL

TX0_OLEV1[6:0]

TX0_OLEV0[6:0]

TX0 Output

Level Control 0

TX0 Squelch

Control

SQUELCHb[3:0]

DISABLEb[3:0]

TX1 Output

Level Control 1 SRC

TX1 CTL

TX1_OLEV1[6:0]

TX1_OLEV0[6:0]

TX1 Output

Level Control 0

TX1 Squelch

Control

SQUELCHb[3:0]

DISABLEb[3:0]

Rev. 0 | Page 26 of 26

ADN4600

Addr

(Hex) Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0xD1

0xD2

0xD3

0xD9

TX2 Output

Level Control 1 SRC

TX2 CTL

TX2_OLEV1[6:0]

0x40

TX2 Output

Level Control 0

TX2_OLEV0[6:0]

0x40

0xFF

0x40

0xFF

0x40

0xFF

0x40

0xFF

0x40

0xFF

0x40

0xFF

TX2 Squelch

Control

SQUELCHb[3:0]

DISABLEb[3:0]

TX3 Output

Level Control 1 SRC

TX3 CTL

TX3_OLEV1[6:0]

TX3_OLEV0[6:0]

0xDA TX3 Output

Level Control 0

0xDB

0xE1

0xE2

0xE3

0xE9

0xEA

0xEB

0xF1

0xF2

0xF3

0xF9

0xFA

0xFB

TX3 Squelch

Control

SQUELCHb[3:0]

DISABLEb[3:0]

TX7 Output

Level Control 1 SRC

TX7 CTL

TX7_OLEV1[6:0]

TX7_OLEV0[6:0]

TX7 Output

Level Control 0

TX7 Squelch

Control

TX6 Output

Level Control 1 SRC

TX6 CTL

TX6_OLEV1[6:0]

TX6_OLEV0[6:0]

TX6 Output

Level Control 0

TX6 Squelch

Control

TX5 Output

Level Control 1 SRC

TX5 CTL

TX5_OLEV1[6:0]

TX5_OLEV0[6:0]

TX5 Output

Level Control 0

TX5 Squelch

Control

TX4 Output

Level Control 1 SRC

TX4 CTL

TX4_OLEV1[6:0]

TX4_OLEV0[6:0]

TX4 Output

Level Control 0

TX4 Squelch

Control

Rev. 0 | Page 27 of 27

ADN4600

PACKAGE OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

0.60 MAX

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

*

6.15

6.00 SQ

5.85

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50 BSC

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 33. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADN4600ACPZ¹

Temperature Range

Package Description

Package Option

CP-64-2

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

AD4600ACPZ-R7¹−40^oC to +85^oC

ADN4600-EVALZ¹

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D07061-0-6/08(0)

Rev. 0 | Page 28 of 28


型号：	AD4600ACPZ-R7
厂家：	ADI
描述：	4.25 Gbps, 8 】 8, Asynchronous Crosspoint Switch 4.25 Gbps的速率， 8 】 8 ，异步交叉点开关复用器开关复用器或开关信号电路
文件：	总28页 (文件大小：1114K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD4600ACPZ-R7 [ADI]

相关型号：

AD4630-24

AD4630-24BBCZ

AD4630-24BBCZ-RL

AD4632-24

AD4680

AD4680BCPZ-RL

AD4680BCPZ-RL7

AD4681

AD4681BCPZ-RL

AD4681BCPZ-RL7

AD4682

AD4682BCPZ-RL