AD5060ARJ-1_技术文档

Fully Accurate 14-/16-Bit V_OUTnanoDAC^™

SPI Interface 2.7 V to 5.5 V, in an SOT-23

AD5040/AD5060

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Single 14-/16-bit DAC, 1 LSB INL

Power-on reset to midscale or zero scale

Guaranteed monotonic by design

3 power-down functions

Low power serial interface with Schmitt-triggered inputs

Small 8-lead SOT-23 package, low power

Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply

V

DD

REF

POWER-ON

RESET

AD5040/

AD5060

BUF

OUTPUT

BUFFER

REF(+)

DAC

REGISTER

V

OUT

AGND

Low glitch on power-up

SYNC interrupt facility

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

RESISTOR

NETWORK

APPLICATIONS

Process control

SYNC SCLK DIN

DACGND

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Figure 1.

PRODUCT HIGHLIGHTS

GENERAL DESCRIPTION

1. Available in a small, 8-lead SOT-23 package.

2. 14-/16-bit accurate, 1 LSB INL.

3. Low glitch on power-up.

The AD5040 and the AD5060, members of the ADI nanoDAC

family, are low power, single 14-/16-bit buffered voltage-out

DACs that operate from a single 2.7 V to 5.5 V supply. The

AD5040/AD5060 parts offer a relative accuracy specification

of 1 LSB and operation are guaranteed monotonic with a

1 LSB DNL specification. The parts use a versatile 3-wire serial

interface that operates at clock rates up to 30 MHz and is

compatible with standard SPI®, QSPI™, MICROWIRE™, and

DSP interface standards. The reference for both the AD5040

and AD5060 is supplied from an external V_REFpin. A reference

buffer is also provided on-chip. The AD5060 incorporates a

power-on reset circuit that ensures the DAC output powers up

to midscale or zero scale and remains there until a valid write

takes place to the device. The AD5040 and the AD5060 both

contain a power-down feature that reduces the current con-

sumption of the device to typically 330 nA at 5 V and provides

software-selectable output loads while in power-down mode.

The parts are put into power-down mode over the serial

interface. Total unadjusted error for the parts is <2 mV.

Both parts exhibit very low glitch on power-up.

4. High speed serial interface with clock speeds up to 30 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (midscale, zero scale).

Table 1. Related Devices

Part No. Description

AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23

AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23

AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5040/AD5060

TABLE OF CONTENTS

Features .............................................................................................. 1

Reference Buffer ......................................................................... 15

Serial Interface............................................................................ 15

Power-On reset ........................................................................... 16

Software Reset............................................................................. 16

Power-Down Modes .................................................................. 17

Microprocessor Interfacing....................................................... 17

Applications..................................................................................... 19

Choosing a Reference for the AD5040/ AD5060................... 19

Bipolar Operation Using the AD5040/ AD5060.................... 19

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

DAC Architecture....................................................................... 15

Using the AD5040/AD5060 with a Galvanically Isolated

Interface Chip ............................................................................. 20

Power Supply Bypassing and Grounding................................ 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5040/AD5060

SPECIFICATIONS

V_DD= 5.5 V, V_REF= 4.096 V @ R_L= unloaded, C_L= unloaded; T_MINto T_MAX, unless otherwise noted.

Table 2.

A, B Grade¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

16

14

Bits

LSB

AD5060

AD5040

Relative Accuracy (INL)²

0.5

0.1

0.5

1

−40°C to +85°C, AD5040/AD5060

−40°C to +125°C, AD5060 Y grade

−40°C to +85°C, AD5040/AD5060

−40°C to +125°C, AD5060 Y grade

1.5

2.0

1

Total Unadjusted Error (TUE)²

Differential Nonlinearity (DNL)²

mV

LSB

Guaranteed monotonic,

−40°C to +85°C, AD5040/AD5060

0.5

1

Guaranteed monotonic,

−40°C to +125°C, Y grade

Gain Error

0.01

0.02

0.03

% of FSR

T_A= −40°C to +85°C, AD5040/AD5060

T_A= −40°C to +125°C AD5060 Y grade

Gain Error Temperature Coefficient

Offset Error

1

ppm of FSR/°C

mV

0.02

1.5

2.0

T_A= −40°C to + 85°C, AD5040/AD5060

T_A= −40°C to + 125°C, AD5060 Y grade

Offset Error Temperature Coefficient

Full-Scale Error

0.5

0.05

μV/°C

mV

2.0

All 1s loaded to DAC register,

AD5040 AD5060; T_A= −40°C to +85°C

All 1s loaded to DAC register,

0.05

T_A= −40°C to +125°C, AD5060 Y grade

OUTPUT CHARACTERISTICS³

Output Voltage Range

0

V_REF

V

Output Voltage Settling Time

4

μs

¼ scale to ¾ scale code transition to

1 LSB, R_L= 5 kΩ

Output Noise Spectral Density

Output Voltage Noise

64

6

DAC code = midscale, 1 kHz

nV/√Hz

μV p-p

DAC code = midscale , 0.1 Hz to 10 Hz

bandwidth

Digital-to-Analog Glitch Impulse

2

nV-s

1 LSB change around code 57386,

R_L= 5 kΩ, C_L= 200 pF

Digital Feedthrough

DC Output Impedance (Normal)

DC Output Impedance (Power-Down)

0. 003

0. 015

nV-s

Ω

DAC code = full scale

Output impedance tolerance 10%

(Output Connected to 1 kΩ

Network)⁴

(Output Connected to 100 kΩ

Network)

Capacitive Load Stability

Slew Rate

1

kΩ

Output impedance tolerance 400 Ω

Output impedance tolerance 20 kΩ

Loads used R_L= 5 kΩ, R_L= 100 kΩ, R_L= ∞

¼ scale to ¾ scale code transition to

1 LSB, R_L= 5 kΩ, C_L= 200 pF

DAC code = full scale, output shorted to

GND, T_A= 25°C

DAC code = zero scale, output shorted to

V_DD, T_A= 25°C

Time to exit power-down mode to normal

mode of AD5060, 24^thclock edge to 90%

of DAC final value, output unloaded

100

1

nF

V/μs

1. 2

60

Short-Circuit Current

ma

μs

45

DAC Power-Up Time

4.5

DC Power Supply Rejection Ratio

Wideband Spurious-Free Dynamic

−92.11

−67

db

V_DD10%, DAC code = full scale

Output frequency = 10 kHz

Rev. 0 | Page 3 of 24

AD5040/AD5060

A, B Grade¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Range (SFDR)

REFERENCE INPUT/OUTPUT

V_REFInput Range⁵

Input Current (Power-Down)

Input Current (Normal)

DC Input Impedance

LOGIC INPUTS

2

V_DD− 50

0.5

mV

μA

0.1

1

Zero scale loaded

MΩ

Input Current⁶

V_IL, Input Low Voltage

1

2

0.8

μA

V

V_DD= 4.5 V to 5.5 V

V_DD= 2.7 V to 3.6 V

V_DD= 2.7 V to 5.5 V

V_DD= 2.7 V to 3.6 V

V_IH, Input High Voltage

2.0

1.8

V

Pin Capacitance

POWER REQUIREMENTS

V_DD

4

pF

V

2.7

5.5

All digital inputs at 0 V or V_DD

I_DD(Normal Mode)

V_DD= 2.7 V to 5.5 V

DAC active and excluding load current

V_IN= V_DDand V_IL= GND, V_DD= 5.0 V,

1.0

1.2

mA

V

_REF= 4.096 V, code = midscale

0. 82

1. 0

V

_IN= V_DDand V_IL= GND, V_DD= 3.0 V,

V_REF= 2.7 V, code = midscale

I_DD(All Power-Down Modes)

V_DD= 2.5 V to 5.5 V

0.33

1

μA

V_IH= V_DDand V_IL= GND, V_DD= 5.5 V,

V_REF= 4.096 V, code = midscale

0.065

V_IH= V_DDand V_IL= GND, V_DD= 3.0 V,

V

_REF= 4.096 V, code = midscale

¹Temperature range for the B grade is −40°C to + 85° C, typical at 25°C; temperature range for the Y grade is −40°C to +125°C.

²Linearity calculated using a reduced code range (160 to code 65535 for AD5060 ) and (40 to code 16383 for AD5040).

³Guaranteed by design and characterization, not production tested.

⁴1 kΩ power-down network not available with the AD5040.

⁵The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 26.

⁶Total current flowing into all pins.

Rev. 0 | Page 4 of 24

AD5040/AD5060

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAXunless otherwise noted.

,

Table 3.

Parameter

Limit¹

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

2

t₁

33

5

ns min

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

3

SCLK low time

10

3

SYNC to SCLK falling edge setup time

Data setup time

2

Data hold time

0

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignore

12

9

¹All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 30 MHz.

t₄

t₂

t₁

t₉

SCLK

SYNC

t₇

t₃

t₈

t₆

t₅

DIN

D23

D22

D2

D1

D0

D23

D22

Figure 2. AD5060 Timing Diagram

Rev. 0 | Page 5 of 24

AD5040/AD5060

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

V_DDto GND

Digital Input Voltage to GND

V_OUTto GND

V_REFto GND

Operating Temperature Range

Industrial (A, B Grade)

Extended Automotive Temperature

Range (Y Grade)

Storage Temperature Range

Maximum Junction Temperature

SOT-23 Package

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−0.3 V to +7.0 V

−0.3 V to V_DD+ 0.3 V

−40°C to +85°C

−40°C to +125°C

This device is a high performance integrated circuit with an

ESD rating of <2 kV. It is ESD sensitive. Proper precautions

should be taken for handling and assembly.

−65°C to +150°C

150°C

Power Dissipation

(T_Jmax − T_A)/θ_JA

206°C/W

91°C/W

θ_JAThermal Impedance

θ_JcThermal Impedance

Reflow Soldering (Pb-free)

Peak Temperature

260°C

Time-at-Peak Temperature

ESD (AD5040/AD5060)

10 sec to 40 sec

1. 5 kV

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5040/AD5060

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

8

7

6

5

DIN

SCLK

AD5040/

AD5060

TOP VIEW

(Not to Scale)

V

DD

SYNC

DACGND

V

REF

V

AGND

OUT

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

DIN

Serial Data Input. These parts have a 16-/24-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input.

2

3

4

5

6

7

V_DD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and V_DDshould be decoupled to GND.

Reference Voltage Input.

Analog Output Voltage from DAC.

Ground Reference Point for Analog Circuitry.

Ground Input to the DAC Core.

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 16th/24th clock cycle unless SYNC is taken high before this edge, in which case

the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.

V_REF

V_OUT

AGND

DACGND

SYNC

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

Rev. 0 | Page 7 of 24

AD5040/AD5060

TYPICAL PERFORMANCE CHARACTERISTICS

1.6

0.6

0.5

V

= 5.5V

V

= 5.5V

DD

1.4

= 4.096V

REF

1.2

T

= 25°C

T

= 25°C

A

0.4

1.0

0.8

0.3

0.6

0.2

0.4

0.1

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

160

10160

20160

30160

40160

50160

60160

160

2260

4360

6460

8560 10660 12760 14860

DAC CODE

Figure 4. Typical AD5060 INL Plot

Figure 7. Typical AD5040 INL Plot

1.6

1.4

0.40

0.35

V

= 5.5V

V

= 5.5V

DD

= 4.096V

= 25°C

DD

= 4.096V

V

REF

1.2

0.30

T

= 25°C

T

A

1.0

0.25

0.8

0.20

0.6

0.15

0.4

0.10

0.2

0.05

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

–0.40

160

10160

20160

30160

40160

50160

60160

160

2260

4360

6460

8560 10660 12760 14860

DAC CODE

Figure 8. Typical AD5040 DNL Plot

Figure 5. Typical AD5060 DNL Plot

0.020

0.015

0.010

0.005

0

0.10

0.08

0.06

0.04

0.02

0

V

T

= 5.5V

V

T

= 5.5V

DD

= 4.096V

REF

= 25°C

A

–0.02

–0.04

–0.06

–0.08

–0.10

–0.005

–0.010

–0.015

–0.020

160

2260

4360

6460

8560 10660 12760 14860 16960

DAC CODE

160

10160

20160

30160

40160

50160

60160

DAC CODE

Figure 9. Typical AD5040 TUE Plot

Figure 6. Typical AD5060 TUE Plot

Rev. 0 | Page 8 of 24

AD5040/AD5060

1.6

1.4

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

T

A

= 25°C

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

DD

REF

1.2

1.0

MAX OFFSET ERROR @

= 2.7V

V

0.8

MAX OFFSET ERROR @

= 5.5V

DD

V

DD

0.6

MAX INL ERROR @ V = 5.5V

DD

0.4

0.2

0

MIN OFFSET ERROR @

= 5.5V

0

V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN INL ERROR @ V = 5.5V

DD

MIN OFFSET ERROR @

= 2.7V

V

DD

–40

–20

0

20

40

60

80

100

120

140

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 10. INL vs. Reference Input Voltage¹

Figure 13. Typical Offset Error vs. Temperature¹

1.6

1.4

0.5

0.4

T

A

= 25°C

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

DD

REF

1.2

1.0

0.3

0.8

MAX GAIN ERROR @

0.2

V

= 2.7V

0.6

DD

MAX GAIN ERROR @

= 5.5V

0.4

MAX DNL ERROR @ V = 5.5V

DD

0.1

V

DD

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN GAIN ERROR @

= 5.5V

–0.1

–0.2

–0.3

–0.4

–0.5

MIN DNL ERROR @ V = 5.5V

DD

V

DD

MIN GAIN ERROR @

= 2.7V

V

DD

–40

–20

0

20

40

60

80

100

120

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

Figure 14. Typical Gain Error vs. Temperature¹

Figure 11. DNL vs. Reference Input Voltage¹

1.4

1.2

1.0

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

T

= 25°C

DD

REF

A

1.0

0.8

0.6

MAX INL ERROR @

= 2.7V

0.6

0.4

V

DD

MAX TUE ERROR @ V = 5.5V

DD

0.4

0.2

MAX INL ERROR @

= 5.5V

0.2

0

V

DD

MIN INL ERROR @

= 5.5V

MIN TUE ERROR @ V = 5.5V

DD

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

MIN INL ERROR @

V

= 2.7V

DD

–40

–20

0

20

40

60

80

100

120

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 15. Typical INL Error vs. Temperature¹

Figure 12. TUE vs. Reference Input Voltage¹

¹AD5060 only.

Rev. 0 | Page 9 of 24

AD5040/AD5060

1.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

V

T

= 5.5V

DD

REF

FULL-SCALE

THREE QUARTER SCALE

DD

= 4.096V

0.8

0.6

REF

= 25°C

A

MAX DNL ERROR @

= 2.7V

0.4

V

DD

0.2

MID-SCALE

MAX DNL ERROR @

= 5.5V

QUARTER-SCALE

ZERO-SCALE

0

V

DD

MIN DNL ERROR @

= 5.5V

–0.2

–0.4

–0.6

–0.8

–1.0

V

DD

MIN DNL ERROR @

V

= 2.7V

DD

–40

–20

0

20

40

60

80

100

120

140

0

5M

10M 15M 20M 25M 30M 35M 40M 45M

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 16. Typical DNL Error vs. Temperature¹

Figure 19. Typical Supply Current vs. Frequency @ 5.5 V¹

1.0

0.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

DD

REF

V

= 3V

DD

= 2.5V

= 25°C

V

REF

T

A

0.6

MAX TUE ERROR @

= 5.5V

THREE QUARTER SCALE

V

0.4

DD

FULL-SCALE

MAX TUE ERROR @

0.2

V

= 2.7V

DD

0

MID-SCALE

QUARTER-SCALE

MIN TUE ERROR @

= 5.5V

–0.2

–0.4

–0.6

–0.8

–1.0

V

DD

ZERO-SCALE

MIN TUE ERROR @

V

= 2.7V

DD

–40

–20

0

20

40

60

80

100

120

140

0

5M

10M 15M 20M 25M 30M 35M 40M 45M

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 17. Typical TUE Error vs. Temperature¹

Figure 20. Typical Supply Current vs. Frequency @ 3 V¹

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

DD

REF

V

T

= 2.5V

REF

= 25°C

A

MAX I

@

DD

CODE = MIDSCALE

V

= 5.5V

DD

MAX I

@

DD

V

= 2.7V

DD

–40

–20

0

20

40

60

80

100

120

140

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

Figure 18. Typical Supply Current vs. Temperature¹

Figure 21. Typical Supply Current vs. Supply Voltage¹

¹AD5060 only.

Rev. 0 | Page 10 of 24

AD5040/AD5060

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

T

= 25°C

V

= 3V

A

DD

DAC = FULL SCALE

= 2.7V

V

REF

= 25°C

T

A

V

= 5.5V, V

= 4.096V

REF

DD

V

= 3.0V, V = 2.5V

REF

DD

Y AXIS = 2μV/DIV

X AXIS = 4s/DIV

0

10000

20000

30000

40000

50000

60000

70000

DAC CODE

Figure 22. Typical Supply Current vs. Digital Input Code¹

Figure 25. 0.1 Hz to 10 Hz Noise Plot

0.50

24TH CLOCK FALLING

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

CH1 = SCLK

CH2 = V

OUT

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

REFERENCE VOLTAGE (V)

CH2 50mV/DIV CH1 2V/DIV

TIME BASE 400ns/DIV

Figure 23. AD5060 Digital-to-Analog Glitch Impulse

(See Figure 24)

Figure 26. V_DDHeadroom vs. Reference Voltage

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

4.65

4.60

4.55

0.117

0.116

0.115

0.114

0.113

0.112

0.111

0.110

0.109

0.108

0.107

0.106

0.105

0.104

0.103

0.102

0.101

V

T

= 5.0V

= 25°C

V

= 5V

DD

= 4.096V

A

REF

DAC = FULL-SCALE

R = 5kΩ

C = 220pF

CODE = 57386

4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00

V

(V)

REF

SAMPLES

Figure 24. AD5060 Digital-to-Analog Glitch Energy

Figure 27. Output Voltage vs. Reference Voltage

¹AD5060 only.

Rev. 0 | Page 11 of 24

AD5040/AD5060

5.005

C4 = 143mV p-p

V

= 5V

REF

T

= 25°C

A

ZERO-SCALE

1kΩ TO GND

5.000

4.995

4.990

4.985

4.980

4.975

CH4 50.0mV

M4.00μs

CH1

1.64V

5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00

(V)

V

DD

Figure 31. Glitch upon Entering Software Power-Down to Zero Scale

Figure 28. Typical Output vs. Supply Voltage

C4 = 50mV p-p

CH3 = SCLK

1kΩ TO GND

ZERO-SCALE

CH2 = V

OUT

CH1 = TRIGGER

CH4 20.0mV

M1.00μs

CH1

1.64V

CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs

Figure 29. Time to Exit Power-Down to Midscale

400

Figure 32. Glitch upon Exiting Software Power-Down to Zero Scale

V

= 5V

DD

= 4.096V

REF

350

300

250

200

150

100

50

C2

25mV p-p

T

= 25°C

A

FULL-SCALE

C3

4.96V p-p

T

2

MID-SCALE

C3 FALL

935.0μs

C3 RISE

QUARTER-SCALE

∞s

NO VALID

T

EDGE

3

0

ZERO-SCALE

10k

–50

CH3 2.00V CH2 50mV

M1.00ms

CH3

1.36V

100

1k

100k

1M

FREQUENCY (Hz)

Figure 33. Glitch upon Entering Hardware Power-Down to Three-State

Figure 30. Noise Spectral Density

Rev. 0 | Page 12 of 24

AD5040/AD5060

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

V

= 5.5V

DD

= 4.096V

REF

C2

10% TO 90% RISE TIME = 0.688

SLEW RATE = 1.16V/

μs

30mV p-p

μs

2.04V

C3

4.96V p-p

T

2

C3 FALL

∞s

NO VALID

EDGE

DAC

OUTPUT

T

C3 RISE

946.2μs

3

1.04V

CH3 2.00V CH2 50mV

M1.00ms

CH3

1.36V

–10μs –8μs –6μs –4μs –2μs

0

2μs 4μs 6μs 8μs 9.96μs

Figure 34. Glitch upon Exiting Hardware Power-Down to Zero Scale

Figure 37. Typical Output Slew Rate

0.0010

16

14

12

10

8

CODE = MID-SCALE

V

= 5V, V

= 3V, V

= 4.096V

= 2.5V

0.0008

0.0006

0.0004

0.0002

0

DD

REF

6

–0.0002

–0.0004

–0.0006

–0.0008

V

= 5.5V

DD

4

2

V

= 3V

DD

0

–25 –20 –15 –10 –5

0

5

10

15

20

25

30

0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 MORE

BIN

CURRENT (mA)

Figure 35. Typical Output Load Regulation

Figure 38. I_DDHistogram V_DD= 3.0 V

0.10

0.08

0.06

0.04

0.02

0

14

CODE = MIDSCALE

V

= 5V, V

= 3V, V

= 4.096V

= 2.5V

DD

REF

12

10

8

V

= 3V, V

= 2.5V

REF

DD

6

–0.02

–0.04

–0.06

–0.08

–0.10

4

V

= 5V, V

= 4.096V

0

DD

REF

2

0

–25 –20 –15 –10 –5

5

10

15

20

25

30

1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11MORE

BIN

I

(mA)

OUT

Figure 36. Typical Current Limiting Plot

Figure 39. I_DDHistogram V_DD= 5.0 V

Rev. 0 | Page 13 of 24

AD5040/AD5060

TERMINOLOGY

Relative Accuracy

Total Unadjusted Error (TUE)

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

function. A typical AD5060 INL vs. code plot is shown in

Figure 4.

Total unadjusted error is a measure of the output error taking

all the various errors into account. A typical AD5060 TUE vs.

code plot is shown in Figure 6.

Offset Error Drift

This is a measure of the change in zero-code error with a

change in temperature. It is expressed in μV/°C.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity. This DAC is guaranteed monotonic by

design. A typical AD5060 DNL vs. code plot is shown in Figure 5.

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s

and is measured when the digital input code is changed by

1 LSB at the worst case code 53786; see Figure 23 and Figure 24.

The expanded view in Figure 23 shows the glitch generated

following completion of the calibration routine; Figure 24

zooms in on this glitch.

Offset Error

Offset error is a measure of the output error when zero code

(0x0000) is loaded to the DAC register. Ideally, the output

should be 0 V. The zero-code error is always positive in the

AD5040/AD5060 because the output of the DAC cannot go

below 0 V. This is due to a combination of the offset errors in

the DAC and output amplifier. Zero-code error is expressed

in mV.

Digital Feedthrough

Full-Scale Error

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but is measured when the DAC output is not updated. It

is specified in nV-s and measured with a full-scale code change

on the data bus—that is, from all 0s to all 1s, and vice versa.

Full-scale error is a measure of the output error when full-scale

code (0xFFFF AD5060, 0x3FFF AD5040) is loaded to the DAC

register. Ideally, the output should be V_DD− 1 LSB. Full-scale

error is expressed in percent of full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the DAC transfer characteristic from ideal,

expressed as a percent of the full-scale range.

Rev. 0 | Page 14 of 24

AD5040/AD5060

THEORY OF OPERATION

The AD5040/AD5060 are single 14-/16-bit, serial input, voltage

output DACs. The parts operate from supply voltages of 2.7 V

to 5.5 V. Data is written to the AD5060 in a 24-bit word format,

and to the AD5040 in a 16-bit word format, via a 3-wire serial

interface.

SERIAL INTERFACE

The AD5060/AD5040 have a 3-wire serial interface (

,

SYNC

SCLK, and DIN), which is compatible with SPI, QSPI, and

MICROWIRE interface standards, as well as most DSPs.

Figure 2 shows a timing diagram of a typical AD5060 write

sequence.

Both the AD5040 and AD5060 incorporate a power-on reset

circuit that ensures the DAC output powers up to a known out-

put state (midscale or zero-scale, see the Ordering Guide). The

devices also have a software power-down mode that reduces the

typical current consumption to less than 1 μa.

The write sequence begins by bringing the

line low. For

SYNC

the AD5060, data from the DIN line is clocked into the 24-bit

shift register on the falling edge of SCLK. The serial clock

frequency can be as high as 30 MHz, making these parts

compatible with high speed DSPs. On the 24th falling clock

edge, the last data bit is clocked in and the programmed

function is executed (that is, a change in the DAC output or a

change in the mode of operation).

DAC ARCHITECTURE

The DAC architecture of the AD5060 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 40. The 4 MSBs of the 16-bit data-word are decoded to

drive 15 switches, E1 to E15. Each of these switches connects

1 of 15 matched resistors to either DACGND or the V_REFbuffer

output. The remaining 12 bits of the data-word drive switches

S0 to S11 of a 12-bit voltage mode R-2R ladder network.

At this stage, the

line can be kept low or be brought

SYNC

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence so that a falling edge of

can initiate the next write sequence. Because the

SYNC

buffer draws more current when V_IH= 1.8 V than it does when

_IH= 0.8 V, should be idled low between write sequences

SYNC

V

OUT

2R

S1

2R

E1

2R

E2

2R

S0

V

SYNC

E15

S11

for an even lower power operation of the part. As previously

indicated, however, it must be brought high again just before

the next write sequence. The AD5040 requires 16 clock periods

to update the input shift register. On the 16th falling clock edge,

the last data bit is clocked in and the programmed function is

executed (that is, a change in the DAC output or a change in the

mode of operation).

V

REF

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 40. AD5060 DAC Ladder Structure

REFERENCE BUFFER

Input Shift Register

The AD5040 andAD5060 operate with an external reference.

The reference input (V_REF) has an input range of 2 V to

V_DD− 50 mV. This input voltage is then used to provide a

buffered reference for the DAC core.

The AD5060 input shift register is 24 bits wide; see Figure 41.

PD1 and PD0 are control bits that control the operating mode

of the part—normal mode or any one of three power-down

modes (see the Power-Down Modes section for more detail).

The next 16 bits are the data bits. These are transferred to the

DAC register on the 24th falling edge of SCLK.

DB15 (MSB)

DB0 (LSB)

0

PD1 PD0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA BITS

NORMAL OPERATION

3-STATE

0

1

0

1

0

1

100kΩ TO GND

1kΩ TO GND

POWER-DOWN MODES

Figure 41. AD5060 Input Register Content

Rev. 0 | Page 15 of 24

AD5040/AD5060

The AD5040 input shift register is 16 bits wide; see Figure 42.

PD1 and PD0 are control bits that control the operating mode

of the part—normal mode or any one of two power-down

modes (see Power-Down Modes section for more detail). The

next 14 bits are the data bits. These are transferred to the DAC

register on the 16th falling edge of SCLK.

POWER-ON RESET

The AD5040 and AD5060 both contain a power-on reset

circuit that controls the output voltage during power-up. The

DAC register is filled with the zero-scale code or midscale code

and the output voltage is set to zero scale or midscale (see the

Ordering Guide for more details on the reset model). It remains

there until a valid write sequence is made to the DAC. This is

useful in applications where it is important to know the output

state of the DAC while it is in the process of powering up.

Interrupt

SYNC

In a normal write sequence for the AD5060, the

line is

SYNC

kept low for at least 24 falling edges of SCLK, and the DAC is

updated on the 24th falling edge. However, if is brought

SOFTWARE RESET

SYNC

high before the 24th falling edge, the write sequence is

interrupted. The shift register is reset and the write sequence is

considered invalid. Neither an update of the DAC register

contents nor a change in the operating mode occurs; see Figure

The AD5060 device can be put into software reset by setting all

bits in the DAC register to 1; this includes writing 1s to Bit D23

and Bit D16, which is not the normal mode of operation. For

the AD5040 this includes writing 1s to Bit D15 and Bit D14,

which is also not the normal mode of operation. Note that the

43. In a normal write sequence for the AD5040, the

line

SYNC

is kept low for at least 16 falling edges of SCLK, and the DAC is

updated on the 16th falling edge. However, if is brought

interrupt command cannot be performed if a software

SYNC

reset command is started in the AD5040 or AD5060.

high before the 16th falling edge, the write sequence is

interrupted. The shift register is reset and the write sequence is

considered invalid. Neither an update of the DAC register

contents nor a change in the operating mode occurs.

DB13 (MSB)

DB0 (LSB)

PD1 PD0 D13 D12 D11 D10 D9 D8

D7 D6 D5

D4 D3

D2

D1 D0

DATA BITS

0

1

0

1

0

NORMAL OPERATION

3-STATE

POWER-DOWN MODES

100kΩ TO GND

Figure 42. AD5040 Input Register Content

SCLK

SYNC

DIN

DB23

DB0

DB23

DB0

INVALID WRITE SEQUENCE:

TH

VALID WRITE SEQUENCE, OUTPUT UPDATES

TH

SYNC HIGH BEFORE 24 FALLING EDGE

ON THE 24 FALLING EDGE

SYNC

Figure 43. AD5060

Interrupt Facility

Rev. 0 | Page 16 of 24

AD5040/AD5060

MICROPROCESSOR INTERFACING

AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface

POWER-DOWN MODES

The AD5060 features four operating modes, and the AD5040

features three operating modes. These modes are software pro-

grammable by setting two bits in the control register (Bit DB17

and Bit DB16 in the AD5060 and Bit DB15 and Bit DB14 in the

AD5040). Table 6 and Table 7 show how the state of the bits

corresponds to the operating mode of the two devices.

Figure 45 shows a serial interface between the AD5040/AD5060

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

should be set up to operate in the SPORT transmit alternate

framing mode. The ADSP-2101/ADSP-2103 sport is pro-

grammed through the SPORT control register and should be

configured for internal clock operation, active low framing, and

16-bit word length. Transmission is initiated by writing a word

to the Tx register after the SPORT has been enabled.

Table 6. Operating Modes for the AD5060

DB17

DB16

Operating Mode

Normal operation

Power-down modes:

3-state

0

ADSP-2101/

AD5040/

ADSP-2103¹

0

1

0

1

AD5060¹

100 kΩ to GND

1 kΩ to GND

TFS

DT

SYNC

DIN

SCLK

Table 7. Operating Modes for the AD5040

DB15

DB14

Operating Mode

Normal operation

Power-down modes:

3-state

100 kΩ to GND

See Software Reset section

1

ADDITIONAL PINS OMITTED FOR CLARITY

0

Figure 45. AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface

0

1

0

1

AD5040/AD5060 to 68HC11/68L11 Interface

Figure 46 shows a serial interface between the AD5040/

AD5060 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK pin of the AD5040/AD5060,

while the MOSI output drives the serial data line of the DAC.

In both the AD5060 and the AD5040, when the two most

significant bits are set to 0, the part has normal power

consumption. However, for the three power-down modes of the

AD5060 and the two power down modes of the AD5040, the

supply current falls to less than 1ꢀA at 5 V (65 nA at 3 V). Not

only does the supply current fall, but the output stage is also

internally switched from the output of the amplifier to a resistor

network of known values. This is advantageous because the

output impedance of the part is known while the part is in

power-down mode. The output is connected internally to GND

through a 1 kΩ resistor (AD5060 only) or a 100 kΩ resistor, or

it is left open-circuited (three-stated). The output stage is

illustrated in Figure 44.

The

signal is derived from a port line (PC7). The setup

SYNC

conditions for correct operation of this interface require that the

68HC11/68L11 be configured so that its CPOL bit is 0 and its

CPHA bit is 1. When data is being transmitted to the DAC, the

line is taken low (PC7). When the 68HC11/68L11 is

SYNC

configured where its CPOL bit is 0 and its CPHA bit is 1, data

appearing on the MOSI output is valid on the falling edge of

SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit

bytes with only 8 falling clock edges occurring in the transmit

cycle. Data is transmitted MSB first. In order to load data to the

AD5040/AD5060, PC7 is left low after the first eight bits are

transferred, and a second serial write operation is performed to

the DAC. PC7 is taken high at the end of this procedure.

OUTPUT

BUFFER

AD5040/

V

OUT

AD5060

DAC

68HC11/

AD5040/

68L11¹

AD5060¹

PC7

SCK

SYNC

SCLK

DIN

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

MOSI

Figure 44. Output Stage During Power-Down

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 46. AD5040/AD5060 to 68HC11/68L11 Interface

The bias generator, the DAC core, and other associated linear

circuitry are all shut down when power-down mode is

activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit power-down

is typically 2.5 μs for V_DD= 5 V, and 5 μs for V_DD= 3 V;

see Figure 29.

Rev. 0 | Page 17 of 24

AD5040/AD5060

AD5040/AD5060 to Blackfin® ADSP-BF53x Interface

AD5040/AD5060 to MICROWIRE Interface

Figure 47 shows a serial interface between the AD5040/

AD5060 and the Blackfin ADSP-53x microprocessor. The

ADSP-BF53x processor family incorporates two dual-channel

synchronous serial ports, SPORT1 and SPORT0, for serial and

multiprocessor communications. Using SPORT0 to connect to

the AD5040/AD5060, the setup for the interface is: DT0PRI

drives the SDIN pin of the AD5040/AD5060, while TSCLK0

Figure 49 shows an interface between the AD5040/AD5060 and

any MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and is clocked into the

AD5040/AD5060 on the rising edge of the SK.

MICROWIRE¹

AD5040/

AD5060¹

drives the SCLK of the part; the

is driven from TFS0.

SYNC

CS

SK

SO

SYNC

SCLK

DIN

ADSP-BF53x¹

AD5040/

AD5060¹

1

DT0PRI

TSCLK0

TFS0

DIN

ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

SYNC

Figure 49. AD5040/AD5060 to MICROWIRE Interface

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. AD5040/AD5060 to Blackfin® ADSP-BF53x Interface

AD5040/AD5060 to 80C51/80L51 Interface

Figure 48 shows a serial interface between the AD5060/

AD5040 and the 80C51/80L51 microcontroller. The setup

for the interface is: TxD of the 80C51/80L51 drives SCLK of

the AD5040/AD5060 while RxD drives the serial data line

of the part. The

signal is again derived from a bit-

SYNC

programmable pin on the port. In this case, Port Line P3.3 is

used. When data is to be transmitted to the AD5040, P3.3 is

taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus only 8 falling clock edges occur in the transmit cycle. To

load data to the DAC, P3.3 is left low after the first eight bits are

transmitted, and a second write cycle is initiated to transmit the

second byte of data. P3.3 is taken high following the completion

of this cycle. The 80C51/80L51 outputs the serial data in a

format which has the LSB first. The AD5040/AD5060 require

data to be received with the MSB as the first bit. The

80C51/80L51 transmit routine should take this into account.

80C51/80L51¹

AD5040/

AD5060¹

P3.3

TxD

RxD

SYNC

SCLK

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 48. AD5040/AD5060 to 80C51/80L51 Interface

Rev. 0 | Page 18 of 24

AD5040/AD5060

APPLICATIONS

output noise in the 0.1 Hz to 10 Hz region. Table 8 shows

examples of recommended precision references for use as a

supply to the AD5040/AD5060.

CHOOSING A REFERENCE FOR THE AD5040/

AD5060

To achieve the optimum performance from the AD5040/

AD5060, carefully choose a precision voltage reference. The

AD5040/AD5060 have just one reference input, V_REF. The

voltage on the reference input is used to supply the positive

input to the DAC. Therefore, any error in the reference is

reflected in the DAC.

Table 8. Precision References for the AD5040/AD5060

Initial

Accuracy Temp. Drift

(mV max) (ppm/°C max)

0.1 Hz to 10 Hz

Noise (μV p-p typ)

Part No.

ADR435

ADR425

ADR02

ADR395

2

3

5

3 (SO-8)

3 (SC70)

9 (TSOT-23)

8

3.4

10

8

There are four possible sources of error to consider when

choosing a voltage reference for high accuracy applications:

initial accuracy, ppm drift, long-term drift, and output voltage

noise. Initial accuracy on the output voltage of the DAC leads

to a full-scale error in the DAC. To minimize these errors, a

reference with high initial accuracy is preferred. Also, choosing

a reference with an output trim adjustment, such as an ADR43x

device, allows a system designer to trim out system errors by

setting a reference voltage to a voltage other than the nominal.

The trim adjustment can also be used at temperature to trim

out any errors.

BIPOLAR OPERATION USING THE AD5040/

AD5060

The AD5040/AD5060 have been designed for single-supply

operation, but a bipolar output range is also possible using the

circuit in Figure 51. The circuit shown yields an output voltage

range of 5 V. Rail-to-rail operation at the amplifier output is

achievable using an AD8675/AD820/AD8032 or an OP196/

OP295.

Because the supply current required by the AD5040/AD5060 is

extremely low, the parts are ideal for low supply applications.

The ADR395 voltage reference is recommended. This requires

less than 100 μA of quiescent current and can, therefore, drive

multiple DACs in one system, if required. It also provides very

good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.

The output voltage for any input code can be calculated as

D

65536

R1+ R2

R1

R2

R1

⎡

⎤

⎛

⎜

⎝

⎞ ⎛

⎠ ⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

V_O= V_DD

×

−V

×

DD

⎟ ⎜

⎢

⎥

⎣

⎦

where D represents the input code in decimal (0 to 65536,

AD5060).

7V

5V

ADR395

With V_REF= 5 V, R1 = R2 = 10 kΩ:

10×D

65536

⎛

⎜

⎝

⎞

⎟

⎠

V_O

=

−5 V

SYNC

SCLK

DIN

3-WIRE

SERIAL

V

= 0V TO 5V

OUT

AD5040/

AD5060

INTERFACE

Using the AD5060, this is an output voltage range of 5 V

with 0x0000 corresponding to a −5 V output and 0xFFFF

corresponding to a +5 V output .

Figure 50. ADR395 as Reference to AD5060/AD5040

R2 = 10kΩ

Long-term drift is a measure of how much the reference drifts

over time. A reference with a tight long-term drift specification

ensures that the overall solution remains relatively stable during

its entire lifetime. The temperature coefficient of a reference

output voltage affects INL, DNL, and TUE. A reference with a

tight temperature coefficient specification should be chosen to

reduce the temperature dependence of the DAC output voltage

on ambient conditions.

+5V

R1 = 10kΩ

–

AD820/

OP295

+

±5V

AD5040/

AD5060

–5V

V

OUT

V

REF

10μF

0.1μF

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered. It

is important to choose a reference with as low an output noise

voltage as practical for the system noise resolution required.

Precision voltage references, such as the ADR435, produce low

3-WIRE

SERIAL

INTERFACE

Figure 51. Bipolar Operation with the AD5040/AD5060

Rev. 0 | Page 19 of 24

AD5040/AD5060

USING THE AD5040/AD5060 WITH A

GALVANICALLY ISOLATED INTERFACE CHIP

POWER SUPPLY BYPASSING AND GROUNDING

In process control applications in industrial environments, it is

often necessary to use a galvanically isolated interface to protect

and isolate the controlling circuitry from any hazardous

common-mode voltages that can occur in the area where the

DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. Because the AD5040/AD5060 use a 3-wire serial logic

interface, the ADuM130x family provides an ideal digital

solution for the DAC interface.

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the

board. The printed circuit board containing the AD5040/

AD5060 should have separate analog and digital sections, each

having its own area of the board. If the AD5040/AD5060 are in

a system where other devices require an AGND-to-DGND

connection, the connection should be made at one point only.

This ground point should be as close as possible to the

AD5040/AD5060.

The ADuM130x isolators provide three independent isolation

channels in a variety of channel configurations and data rates.

They operate across the full range from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier.

The power supply to the AD5040/AD5060 should be bypassed

with 10 μF and 0.1 μF capacitors. The capacitors should be

physically as close as possible to the device with the 0.1 μF

capacitor ideally right up against the device. The 10 μF

capacitors are the tantalum bead type. It is important that the

0.1 μF capacitor has low effective series resistance (ESR) and

effective series inductance (ESI), as do common ceramic types

of capacitors. This 0.1 μF capacitor provides a low impedance

path to ground for high frequencies caused by transient

currents due to internal logic switching.

Figure 52 shows a typical galvanically isolated configuration

using the AD5040/AD5060. The power supply to the part

also needs to be isolated; this is accomplished by using a

transformer. On the DAC side of the transformer, a 5 V

regulator provides the 5 V supply required for the

AD5040/AD5060.

The power supply line itself should have as large a trace as

possible to provide a low impedance path and reduce glitch

effects on the supply line. Clocks and other fast switching

digital signals should be shielded from other parts of the board

by a digital ground. Avoid crossover of digital and analog

signals, if possible. When traces cross on opposite sides of the

board, ensure that they run at right angles to each other to

reduce feedthrough effects on the board. The best board layout

technique is the microstrip technique where the component

side of the board is dedicated to the ground plane only, and the

signal traces are placed on the solder side. However, this is not

always possible with a two-layer board.

5V

REGULATOR

10μF

0.1μF

POWER

V

DD

SCLK

SDI

V1A

V0A

V0B

V0C

SCLK

SYNC

DIN

AD5040/

AD5060

ADuM1300

V

V1B

V1C

OUT

DATA

GND

Figure 52. AD5040/AD5060 with a Galvanically Isolated Interface

Rev. 0 | Page 20 of 24

AD5040/AD5060

OUTLINE DIMENSIONS

2.90 BSC

8

1

7

2

6

3

5

4

1.60 BSC

2.80 BSC

PIN 1

INDICATOR

0.65 BSC

1.95

BSC

1.30

1.15

0.90

1.45 MAX

0.22

0.08

0.60

0.45

0.30

8°

4°

0°

0.38

0.22

0.15 MAX

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

−40°C to +85°C

Package

Option

RJ-8

Model

INL

Description

Package Description

8 Lead SOT-23

Branding

D4C

D3Z

AD5040BRJZ-500RL7¹

1 LSB

2 LSB

2.7 V to 5.5 V, reset to 0 V

2.7 V to 5.5 V, reset to mid-

scale

2.7 V to 5.5 V, reset to mid-

scale

2.7 V to 5.5 V, reset to 0 V

2.7 V to 5.5 V, reset to mid-

scale

1

AD5040BRJZ-REEL7

1

AD5060ARJZ-1500RL7

1

AD5060ARJZ-1REEL7

1

AD5060ARJZ-2REEL7

D41

1

AD5060ARJZ-2500RL7

−40°C to +85°C

2 LSB

8 Lead SOT-23

RJ-8

D41

1

AD5060BRJZ-1500RL7

−40°C to +85°C

1 LSB

8 Lead SOT-23

RJ-8

D3W

D3X

1

AD5060BRJZ-1REEL7

1

AD5060BRJZ-2REEL7

1

AD5060BRJZ-2500RL7

−40°C to +85°C

1 LSB

2.7 V to 5.5 V, reset to mid-

scale

2.7 V to 5.5 V, reset to 0 V

8 Lead SOT-23

RJ-8

D3X

1

AD5060YRJZ-1500RL7

AD5060YRJZ-1REEL7

−40°C to +125°C

1 LSB

8 Lead SOT-23

Evaluation Board

RJ-8

D6F

1

EVAL-AD5060EB

EVAL-AD5040EB

¹Z = Pb-free part.

Rev. 0 | Page 21 of 24

AD5040/AD5060

NOTES

Rev. 0 | Page 22 of 24

AD5040/AD5060

NOTES

Rev. 0 | Page 23 of 24

AD5040/AD5060

NOTES

©

registered trademarks are the property of their respective owners.

D04767–0–10/05(0)

Rev. 0 | Page 24 of 24


型号：	AD5060ARJ-1
厂家：	ADI
描述：	IC SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO8, SOT-23, 8 PIN, Digital to Analog Converter 输入元件光电二极管转换器
文件：	总24页 (文件大小：457K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5060ARJ-1 [ADI]

相关型号：

AD5060ARJ-1500RL7

AD5060ARJ-1REEL7

AD5060ARJ-2REEL7

AD5060ARJZ-1500RL7

AD5060ARJZ-1REEL7

AD5060ARJZ-2500RL7

AD5060ARJZ-2REEL7

AD5060ARJZ-3500RL7

AD5060ARJZ-3REEL7

AD5060BRJ-1REEL7

AD5060BRJZ-1500RL7

AD5060BRJZ-1REEL7