AD5062BRJZ-1REEL7 [ADI]
2.7 V-5.5 V, Full Accurate 16-Bit VOUT nanoDAC® Converter, Unbuffered, in a Sot 23;
| 型号： | AD5062BRJZ-1REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.7 V-5.5 V, Full Accurate 16-Bit VOUT nanoDAC® Converter, Unbuffered, in a Sot 23 光电二极管 转换器 |
| 文件： | 总21页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fully Accurate 16-Bit VOUT nanoDAC™
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5062
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
REF
DD
Single 16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
POWER-ON
RESET
AD5062
BUF
Low power serial interface with Schmitt-triggered inputs
Tiny 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
Unbuffered voltage capable of driving 60 kΩ load
SYNC interrupt facility
REF(+)
DAC
DAC
REGISTER
V
OUT
AGND
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
APPLICATIONS
Process control
SYNC SCLK DIN
DACGND
Data acquisition systems
Figure 1.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
Description
AD5061
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
4 LSBs INL, SOT-23.
AD5063
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP.
AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,
1 LSB INL, SOT-23.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Available in a tiny 8-lead LOT-23 package.
2. 16-bit accurate, 1 ꢀLB INꢀ.
3. ꢀow glitch on power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero-scale or mid-scale).
The AD5062, a member of ADI’s nanoDAC family, is a low
power, single 16-bit unbuffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of 1 ꢀLB, and operation is guaranteed
monotonic with a 1 ꢀLB DNꢀ specification. The part uses a
versatile 3-wire serial interface that operates at clock rates up
to 30 MHz, and is compatible with standard LPI®, QLPI™,
MICROWIRE™, and DLP interface standards. The reference for
the AD5062 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to zero
scale or mid-scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
300 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <0.8 mV.
This part exhibits very low glitch on power-up.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
AD5062* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD5062 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• Evaluation Board for the AD5040/AD5060, AD5061 and
AD5062
DISCUSSIONS
View all AD5062 EngineerZone Discussions.
DOCUMENTATION
Data Sheet
• AD5062: Fully Accurate 16-Bit VOUT nanoDAC™ SPI
Interface 2.7 V to 5.5 V, in an SOT-23 Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
User Guides
• UG-923: Evaluating the AD5040/AD5060, AD5061, and
AD5062 16-/14-Bit, nanoDAC
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD5040/AD5060/AD5061/AD5062/AD5063 Software
Evaluation
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Technical Articles
• Designing DACs into Precision Industrial 10 V Applications
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AD5062
TABLE OF CONTENTS
Features .............................................................................................. 1
Reference Buffer ......................................................................... 14
Lerial Interface............................................................................ 14
Input Lhift Register .................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Lpecifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ELD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
DAC Architecture....................................................................... 14
LYNC
Interrupt .......................................................................... 14
Power-On to Midscale or Zero Lcale....................................... 15
Loftware Reset............................................................................. 15
Power-Down Modes .................................................................. 15
Microprocessor Interfacing....................................................... 15
Applications..................................................................................... 17
Choosing a Reference for the AD5062.................................... 17
Bipolar Operation Using the AD5062..................................... 17
Using AD5062 with a Galvanically Isolated Interface Chip. 18
Power Lupply Bypassing and Grounding................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/09—Rev. 0 to Rev. A
Changes to Figure 43...................................................................... 17
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5062
SPECIFICATIONS
VDD = 5.5 V, VREF = 4.096 V, RL = Unloaded, CL = 22 pF to GND; TMIN to TMAX, unless otherwise noted.
Table 2.
A,B Grade1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)2
16
Bits
LSB
0.ꢀ
0.ꢀ
1
2
−40°C to +8ꢀ°C, B grade
−40°C to +8ꢀ°C, A grade
−40°C to +8ꢀ°C, B grade
−40°C to +8ꢀ°C, A grade
Guaranteed monotonic
−40°C to +8ꢀ°C, B grade
Guaranteed monotonic
−40°C to +8ꢀ°C, A grade
TA = −40°C to +8ꢀ°C B grade
TA = −40°C to +8ꢀ°C A grade
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
ꢀ00
ꢀ00
0.ꢀ
800
800
1
μV
LSB
0.ꢀ
1
Gain Error
0.01
0.01
1
0.02ꢀ
0.02ꢀ
0.ꢀ
0.02
0.02
% of FSR
Gain Error Temperature Coefficient
Offset Error
ppm of FSR/°C
mV
0. 0ꢀ
0. 0ꢀ
TA = −40°C to + 8ꢀ°C, B grade
TA = −40°C to + 8ꢀ°C, A grade
Offset Error Temperature Coefficient
Full-Scale Error
μV/°C
μV
ꢀ00
800
800
All 1s loaded to DAC register, B grade
TA = −40°C to +8ꢀ°C
All 1s loaded to DAC register, A grade
TA = −40°C to +8ꢀ°C
ꢀ00
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VREF
V
Unipolar operation
Output Voltage Settling Time
4
μs
¼ scale to ¾ scale code transition to
1LSB.
Output Noise Spectral Density
Output Voltage Noise
24
6
DAC code = midscale, 1 kHz
nV/√Hz
μV p-p
DAC code = midscale, 0.1 to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse
Digital Feedthrough
2
0.1
8
nV-s
nV-s
kΩ
1 LSB change around major carry
DC Output Impedance (Normal)
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network)
(Output Connected to 100 kΩ Network)
REFERENCE INPUT/ OUTPUT
VREF Input Range2
Input Current (Power-Down)
Input Current (Normal)
DC Input Impedance
Output impedance tolerance 20%
1
100
kΩ
kΩ
Output impedance tolerance 20%
Output impedance tolerance 20%
2
VDD − ꢀ0 mV
μA
0.1
1
Zero-scale loaded
0. ꢀ
μA
Bipolar/unipolar operation
MΩ
LOGIC INPUTS
Input Current4
VIL, Input Low Voltage
1
2
0.8
0.8
μA
V
VDD = 4.ꢀ V to ꢀ.ꢀ V
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to ꢀ.ꢀ V
VDD = 2.7 V to 3.6 V
VIH, Input High Voltage
Pin Capacitance
2.0
1.8
V
4
pF
Rev. A | Page 3 of 20
AD5062
A,B Grade1
Typ
Parameter
Min
Max
Unit
V
Test Conditions/Comments
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 2.7 V to ꢀ.ꢀ V
2.7
ꢀ.ꢀ
0.7
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIN = VDD and VIL = GND, VDD = ꢀ.ꢀ V,
VREF = 4.096 V, code = midscale
0.6ꢀ
mA
IDD (All Power-Down Modes)
VDD = 2.ꢀ V to ꢀ.ꢀ V
1
μA
VIH = VDD and VIL = GND VDD = ꢀ.ꢀ V,
VREF = 4.096 V, code = midscale
Power Supply Rejection Ratio (PSRR)
0.ꢀ
LSB
∆VDD 10%, VDD = ꢀ V, unloaded
1 Temperature range for the B grade: −40°C to +8ꢀ°C, typical at 2ꢀ°C; temperature range for the Y grade: −40°C to +12ꢀ°C.
2 Refer to Figure 27, Figure 28, Figure 29, Figure 30, and Figure 31 for device performance under lower supply and reference voltage conditions.
3 Guaranteed by design and characterization, not production tested.
4 Total current flowing into all pins.
Rev. A | Page 4 of 20
AD5062
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX unless otherwise noted.
,
Table 3.
Parameter
Limit1
Unit
Test Conditions/Comments
SCLK cycle time
SCLK high time
2
t1
33
ꢀ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
tꢀ
t6
t7
t8
t9
3
SCLK low time
10
3
SYNC to SCLK falling edge setup time
Data setup time
2
Data hold time
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
12
9
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t2
t1
t9
SCLK
SYNC
t7
t3
t8
t6
t5
DIN
D23
D22
D2
D1
D0
D23
D22
Figure 2. Timing Diagram
Rev. A | Page ꢀ of 20
AD5062
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
Digital Input Voltage to GND
VOUT to GND
−0.3 V to +7.0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VREF to GND
Operating Temperature Range
Industrial (B grade)
Storage Temperature Range
Maximum Junction Temperature
SOT-23 Package
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and is ESD-sensitive. Proper precautions
should be taken for handling and assembly.
−40°C to +8ꢀ°C
−6ꢀ°C to +1ꢀ0°C
1ꢀ0°C
Power Dissipation
(TJ max − TA)/θJA
206°C/W
44°C/W
θJA Thermal Impedance
θJc Thermal Impedance
Reflow Soldering (Pb-free)
Peak Temperature
260°C
Time-at-Peak Temperature
ESD
10 sec to 40 sec
1 kV
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5062
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5
DIN
SCLK
AD5062
V
TOP VIEW
DD
SYNC
(Not to Scale)
DACGND
V
REF
V
AGND
OUT
Figure 3.
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
3
4
ꢀ
6
7
VDD
Power Supply Input. These parts can be operated from 2.7 V to ꢀ.ꢀ V, and VDD should be decoupled to GND.
VREF
VOUT
AGND
DACGND
SYNC
Reference Voltage Input.
Analog Output Voltage from DAC.
Ground Reference Point for Analog Circuitry.
Ground Input to the DAC.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Rev. A | Page 7 of 20
AD5062
TYPICAL PERFORMANCE CHARACTERISTICS
1.6
1.2
1.0
T
V
= 25°C
DD
A
V
V
= 5.5V, V
= 2.7V, V
= 4.096V
= 2.0V
DD
DD
REF
REF
1.4
1.2
= 5V, V = 4.096V
REF
MAX INL @ V = 5.5V
DD
0.8
1.0
0.8
0.6
0.6
0.4
0.4
MAX INL @ V = 2.7V
DD
0.2
0.2
MIN INL @ V = 5.5V
DD
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
MIN INL @ V = 2.7V
DD
0
10000
20000
30000
40000
50000
60000
–40
–20
0
20
40
60
80
100
DAC CODE
TEMPERATURE (°C)
Figure 4. Typical INL Plot
Figure 7. INL vs. Temperature
0.15
0.12
0.09
0.06
0.03
0
1.2
1.0
T
V
= 25°C
DD
A
V
V
= 5.5V, V
= 2.7V, V
= 4.096V
= 2.0V
DD
DD
REF
REF
= 5V, V
= 4.096V
REF
0.8
0.6
0.4
MAX DNL @ V = 5.5V
DD
0.2
0
MAX DNL @ V = 2.7V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.03
–0.06
–0.09
–0.12
–0.15
MIN DNL @ V = 2.7V
DD
MIN DNL @ V = 5.5V
DD
0
10000
20000
30000
DAC CODE
40000
50000
60000
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 5. Typical TUE Plot
Figure 8. DNL vs. Temperature
1.5
1.3
1.2
1.0
T
V
= 25°C
DD
A
V
V
= 5.5V, V
= 2.7V, V
= 4.096V
= 2.0V
DD
DD
REF
REF
= 5V, V
= 4.096V
REF
1.1
0.8
0.9
0.6
0.7
0.5
0.4
MAX TUE @ V = 5.5V
DD
MAX TUE @ V = 2.7V
DD
0.3
0.2
0.1
0
–0.1
–0.3
–0.5
–0.7
–0.9
–1.1
–1.3
–1.5
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
MIN TUE @ V = 5.5V
DD
MIN TUE @ V = 2.7V
DD
0
10000
20000
30000
40000
50000
60000
–40
–20
0
20
40
60
80
100
DAC CODE
TEMPERATURE (°C)
Figure 6. Typical DNL Plot
Figure 9. TUE vs. Temperature
Rev. A | Page 8 of 20
AD5062
1.6
1.4
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
T
A
= 25°C
V
V
= 5.5V, V
= 2.7V, V
= 4.096V
= 2.0V
DD
DD
REF
REF
1.2
1.0
MAX INL ERROR @ V = 5.5V
DD
0.8
0.6
0.4
MAX OFFSET @ V = 5.5V
DD
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
–0.035
–0.040
MAX OFFSET @ V = 2.7V
DD
MIN INL ERROR @ V = 5.5V
DD
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.0
5.0
5.5
5.5
5.5
–40
–20
0
20
40
60
80
100
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. INL vs. Reference Input Voltage
Figure 13. Offset vs. Temperature
0.8
0.7
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
A
= 25°C
T
= 25°C
A
CODE = MID-SCALE
0.6
0.5
0.4
V
= 5.5V, V
= 4.096V
REF
DD
0.3
MAX DNL ERROR @ V = 5.5V
DD
0.2
0.1
V
= 5.0V, V
= 4.096V
REF
DD
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
V
= 3.0V, V
= 2.5V
REF
DD
MIN DNL ERROR @ V = 5.5V
DD
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–40
–20
0
20
40
60
80
100
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 11. DNL vs. Reference Input Voltage
Figure 14. Supply Current vs. Temperature
1.0
0.8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
T
= 25°C
A
A
CODE = MID-SCALE
0.6
0.4
V
= 5.5V, V
= 4.096V
= 2.5V
DD
REF
0.2
MAX TUE ERROR @ V = 5.5V
DD
0
V
= 3.0V, V
REF
DD
MIN TUE ERROR @ V = 5.5V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
10000
20000
30000
40000 50000
60000
70000
REFERENCE VOLTAGE (V)
DAC CODE
Figure 12. TUE vs. Reference Input Voltage
Figure 15. Supply Current vs. Digital Input Code
Rev. A | Page 9 of 20
AD5062
1.0
V
= 2.5V
REF
= 25°C
CH3 = SCLK
T
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
A
CODE = MID-SCALE
CH2 = V
OUT
CH1 = TRIGGER
CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 19. Exiting Power-Down @ VDD=3.0 V
Figure 16. Supply Current vs. Supply Voltage
V
= 3V
DD
24TH CLOCK FALLING
DAC= FULL SCALE
= 2.7V
V
REF
T
= 25°C
A
CH1 = SCLK
CH2 = V
OUT
Y AXIS = 2μV/DIV
X AXIS = 4s/DIV
CH2 50mV/DIV CH1 2V/DIV
TIME BASE 400ns/DIV
Figure 20. 0.1 Hz to 10 Hz Noise Plot
Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21
V
= 5V
= 4.096
= 25°C
300
250
200
150
100
50
DD
V
T
= 5V
V
DD
= 25°C
REF
T
A
A
V
= 4.096V
10ns/SAMPLE
REF
FULL SCALE
MIDSCALE
ZERO SCALE
0
50 100 150 200 250 300 350 400 450 500
SAMPLES
0
100
1000
10000
100000
1000000
FREQUENCY (Hz)
Figure 21. Glitch Energy
Figure 18. Output Noise Spectral Density
Rev. A | Page 10 of 20
AD5062
0.010
0.008
0.006
0.004
0.002
0
V
V
= 5.5V V
= 2.7V V
= 4.096V
= 2.0V
DD
DD
REF
REF
CH1 = V
DD
GAIN ERROR @ V = 5.5V
DD
–0.002
–0.004
–0.006
–0.008
–0.010
CH2 = V
OUT
V
= 5V V = 4.096V
REF DD
DD
GAIN ERROR @ V = 2.7V
DD
RAMP RATE = 200μs
T
= 25°C
A
CH1 2V/DIV CH2 1V/DIV TIME BASE = 100μs
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 22. Gain Error vs. Temperature
Figure 25. Hardware Power-Down Glitch
16
14
12
10
8
CH1 = SCLK
CH2 = SYNC
6
CH3 = V
OUT
4
V
T
= 5V V
= 4.096V
REF DD
DD
= 25°C
2
CH4 = TRIGGER
A
0
CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV
TIME BASE 1μs/DIV
0.45
0.46
0.47
0.48
0.49
BIN
0.50
0.51
0.52 MORE
Figure 26. Exiting Software Power-Down Glitch
Figure 23. IDD Histogram @ VDD = 3 V
1.2
T
V
= 25°C
A
16
14
12
10
8
1.0
0.8
= 5.5V
DD
MAX INL @ V = 5.5V
DD
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
6
MIN INL @ V = 5.5V
DD
4
2
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
REFERENCE VOLTAGE (V)
0.60
0.61
0.62
0.63
BIN
0.64
0.65
MORE
Figure 27. INL vs. VREF @ VDD = 5.5 V
Figure 24. IDD Histogram @ VDD = 5 V
Rev. A | Page 11 of 20
AD5062
1.2
1.0
1.2
1.0
T
V
= 25°C
T = 25°C
A
A
= 5.0V
V
= 2.7V
DD
DD
0.8
0.8
MAX INL @ V = 5.0V
DD
0.6
0.6
MAX INL @ V = 2.7V
DD
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
MIN INL @ V = 2.7V
DD
MIN INL @ V = 5.0V
DD
–1.2
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5
3.2
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 28. INL vs. VREF @ VDD = 5.0 V
Figure 31. INL vs. VREF @VDD = 2.7 V
1.2
1.0
0.10
0.08
0.06
0.04
0.02
0
T
V
= 25°C
V
V
= 5.5V, V
= 2.7V, V
= 4.096V
= 2.0V
A
DD
DD
REF
REF
= 4.5V
DD
0.8
MAX INL @ V = 4.5V
DD
MAX GAIN ERROR @ V = 5.5V
DD
0.6
0.4
MAX GAIN ERROR @ V = 2.7V
DD
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.02
–0.04
–0.06
–0.08
–0.10
MIN GAIN ERROR @ V = 2.7V
DD
MIN INL @ V = 4.5V
DD
MIN GAIN ERROR @ V = 5.5V
DD
–1.2
1.5
2.0
2.5
3.0
3.5
4.0
–40
–20
0
20
40
60
80
100
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 29. INL vs. VREF @ VDD = 4.5 V
Figure 32. Gain Error vs. Temperature
1.2
1.0
T
= 25°C
A
V
= 3.0V
DD
0.8
0.6
MAX INL @ V = 3.0V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
MIN INL @ V = 3.0V
DD
–1.2
1.8
2.0
2.2
2.4
2.6
2.8
3.0
REFERENCE VOLTAGE (V)
Figure 30. INL vs. VREF @ VDD = 3.5 V
Rev. A | Page 12 of 20
AD5062
TERMINOLOGY
Total Unadjusted Error (TUE)
Relative Accuracy
Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical TUE vs. code plot
is shown in Figure 5.
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. code plot is shown in Figure 4.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 7.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Zero-Code Error
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition; see Figure 17 and Figure 21.
The expanded view in Figure 17 shows the glitch generated
following completion of the calibration routine; Figure 21
zooms in on this glitch.
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5062 because the output of the DAC cannot go below 0 V.
This is due to the offset errors in the DAC. Zero-code error is
expressed in mV.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in percent
of full-scale range.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus; that is, from all 0s to all 1s, and vice versa.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Rev. A | Page 13 of 20
AD5062
THEORY OF OPERATION
The AD5062 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5062 in a 24-bit word format, via a 3-wire
serial interface.
SYNC
line low. Data
The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
The AD5062 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 μA.
At this stage, the
high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of
line may be kept low or be brought
SYNC
DAC ARCHITECTURE
The DAC architecture of the AD5062 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 33. The four MSBs of the 16-bit data-word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or VREF buffer
output. The remaining 12 bits of the data-word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
can initiate the next write sequence. Because the
SYNC
buffer draws more current when VIN = 1.8 V than it does when
VIN = 0.8 V, should be idled low between write sequences
SYNC
SYNC
for even lower power operation of the part. As previously indi-
cated, however, it must be brought high again just before the
next write sequence.
V
OUT
INPUT SHIFT REGISTER
2R
2R
S0
2R
S1
2R
2R
E1
2R
E2
2R
E15
S11
The input shift register is 24 bits wide; see Figure 34. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
V
REF
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 33. DAC Ladder Structure
REFERENCE BUFFER
SYNC INTERRUPT
The AD5062 operates with an external reference. The reference
input (VREF) has an input range of 2 V to VDD − 50 mV. This
input voltage is then used to provide a buffered reference for the
DAC core.
In a normal write sequence, the
line is kept low for at
SYNC
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if is brought high before the
SYNC
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see Figure 37.
SERIAL INTERFACE
SYNC
The AD5062 has a 3-wire serial interface (
, SCLK, and
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
DB15 (MSB)
DB0 (LSB)
0
0
0
0
0
0
PD1 PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
NORMAL OPERATION
3-STATE
0
0
1
1
0
1
0
1
100kΩ TO GND
1kΩ TO GND
POWER-DOWN MODES
Figure 34. Input Register Contents
Rev. A | Page 14 of 20
AD5062
POWER-ON TO MIDSCALE OR ZERO SCALE
The AD5062 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the midscale code and the output voltage is midscale or the
DAC register is filled with the zero-scale code and the output
voltage is zero-scale. It remains there until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up.
AD5062
V
OUT
DAC
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 35. Output Stage During Power-Down
The bias generator, the DAC core, and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are unaf-
fected when in power-down. The time to exit power-down is
typically 2.5 ꢀs for VDD = 5 V, and 5 ꢀs for VDD = 3 V; see Figure 19.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bit D23 to
Bit D16, which is not the normal mode of operation. Note that
the
interrupt command cannot be performed if a soft-
SYNC
MICROPROCESSOR INTERFACING
AD5062 to ADSP-2101/ADSP-2103 Interface
ware reset command is started.
POWER-DOWN MODES
Figure 36 shows a serial interface between the AD5062 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
The AD5062 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation for the AD5062
DB17
DB16
Operating Mode
Normal operation
Power-down mode:
3-state
100 kΩ to GND
1 kΩ to GND
0
0
ADSP-2101/
AD5062
ADSP-21031
0
1
1
1
0
1
TFS
DT
SYNC
DIN
When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power-
down modes, the supply current falls to less than 1 μA at 5.5 V.
Not only does the supply current fall, but the output stage is
also internally switched from the output of the DAC to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options. The
output is connected internally to GND through a 1 kΩ resistor
or a 100 kΩ resistor, or it is left open-circuited (3-state). The
output stage is illustrated in Figure 35.
SCLK
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. AD5062 to ADSP-2101/ADSP-2103 Interface
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24 FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
TH
TH
ON THE 24 FALLING EDGE
SYNC
Figure 37.
Interrupt Facility
Rev. A | Page 15 of 20
AD5062
AD5062 to 68HC11/68L11 Interface
AD5062 to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5062 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5062, while the MOSI output
Figure 40 shows a serial interface between the AD5062 and the
80C51/80L51 microcontroller. The setup for the interface is:
TxD of the 80C51/80L51 drives SCLK of the AD5062 while
drives the serial data line of the DAC. The
signal is
RxD drives the serial data line of the part. The
signal is
SYNC
SYNC
derived from a port line (PC7). The setup conditions for correct
operation of this interface require that the 68HC11/68L11 be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to
the AD5062, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5062 requires its data with the MSB as the first bit received;
the 80C51/80L51 transmit routine should take this into account.
data is being transmitted to the DAC, the
line is taken
SYNC
low (PC7). When the 68HC11/68L11 is configured where its
CPOL bit is 0 and its CPHA bit is 1, data appearing on the
MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5062,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
AD50621
80C51/80L511
68HC11/
AD50621
68L111
P3.3
TxD
RxD
SYNC
SCLK
DIN
PC7
SCK
SYNC
SCLK
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
Figure 40. AD5062 to 80C51/80L51 Interface
1
ADDITIONAL PINS OMITTED FOR CLARITY
AD5062 to MICROWIRE Interface
Figure 38. AD5062 to 68HC11/68L11 Interface
Figure 41 shows an interface between the AD5062 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5062 on the rising edge of the SK.
AD5062 to Blackfin® ADSP-BF53x Interface
Figure 39 shows a serial interface between the AD5062 and the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces-
sor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5062,
the setup for the interface is: DT0PRI drives the SDIN pin of
the AD5062, while TSCLK0 drives the SCLK of the part; the
AD50621
MICROWIRE1
CS
SK
SO
SYNC
SCLK
DIN
is driven from TFS0.
SYNC
AD50621
ADSP-BF53x1
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5062 to MICROWIRE Interface
DT0PRI
DIN
TSCLK0
TFS0
SCLK
SYNC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD5062 to Blackfin ADSP-BF53x Interface
Rev. A | Page 16 of 20
AD5062
APPLICATIONS
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR435, produce low
output noise in the 0.1 Hz to 10 Hz region. Table 7 shows
examples of recommended precision references for use as
supply to the AD5062.
CHOOSING A REFERENCE FOR THE AD5062
To achieve the optimum performance from the AD5062,
thought should be given to the choice of a precision voltage
reference. The AD5062 has just one reference input, VREF. The
voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.
There are four possible sources of error when choosing a
voltage reference for high accuracy applications: initial
accuracy, ppm drift, long-term drift, and output voltage noise.
Initial accuracy on the output voltage of the DAC will lead to a
full-scale error in the DAC. To minimize these errors, a refer-
ence with high initial accuracy is preferred. Also, choosing a
reference with an output trim adjustment, such as the ADR43x
family, allows a system designer to trim out system errors by
setting a reference voltage to a voltage other than the nominal.
The trim adjustment can also be used at the operating
temperature to trim out any error.
Table 7. Precision References Part List for the AD5062
Initial
Accuracy Drift
(mV max) (ppm/°C max)
Temperature
Part
No.
0.1 Hz to 10 Hz
Noise (μV p-p typ)
ADR43ꢀ
ADR42ꢀ
ADR02
ADR02
ADR39ꢀ
2
2
3
3
ꢀ
3 (SO-8)
3 (SO-8)
3 (SO-8)
3 (SC70)
9 (TSOT-23)
8
3.4
10
10
8
BIPOLAR OPERATION USING THE AD5062
Because the supply current required by the AD5062 is
The AD5062 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit in
Figure 43. The circuit shown yields an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820/AD8032 or an OP196/OP295.
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended. This requires
less than 100 μA of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.
The output voltage for any input code can be calculated as
follows:
7V
5V
ADR395
D
65536
R1+ R2
R1
R2
R1
⎡
⎤
⎛
⎜
⎝
⎞ ⎛
⎠ ⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = VDD
×
×
−V
×
⎟ ⎜
DD
⎢
⎥
⎣
⎦
SYNC
SCLK
DIN
3-WIRE
SERIAL
V
= 0V TO 5V
OUT
where D represents the input code in decimal (0–65536).
With VREF = 5 V, R1 = R2 = 10 kΩ:
AD5062
INTERFACE
10× D
65536
⎛
⎜
⎝
⎞
⎟
⎠
Figure 42. ADR395 as Reference to AD5062
V =
− 5V
O
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference’s
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce temperature dependence of the DAC output voltage on
ambient conditions.
This is an output voltage range of 5 V with 0x0000
corresponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
–
AD820/
OP295
+
±5V
–5V
V
OUT
V
REF
AD5062
10µF
0.1µF
3-WIRE
SERIAL
INTERFACE
Figure 43. Bipolar Operation with the AD5062
Rev. A | Page 17 of 20
AD5062
USING AD5062 WITH A GALVANICALLY ISOLATED
INTERFACE CHIP
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5062 should
have separate analog and digital sections, each having its own
area of the board. If the AD5062 is in a system where other
devices require an AGND-to-DGND connection, the
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that may occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. Because the AD5062 uses a 3-wire serial logic interface,
the ADuM130x family provides an ideal digital solution for the
DAC interface.
connection should be made at one point only. This ground
point should be as close as possible to the AD5062.
The power supply to the AD5062 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), as do common ceramic types of capacitors.
This 0.1 μF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier.
Figure 44 shows a typical galvanically isolated configuration
using the AD5062. The power supply to the part also needs to
be isolated; this is accomplished by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5062.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
5V
REGULATOR
10μF
0.1μF
POWER
V
DD
SCLK
SDI
V1A
V0A
V0B
V0C
SCLK
SYNC
DIN
AD5062
ADuM1300
V
V1B
V1C
OUT
DATA
GND
Figure 44. AD5062 with a Galvanically Isolated Interface
Rev. A | Page 18 of 20
AD5062
OUTLINE DIMENSIONS
3.00
2.90
2.80
8
1
7
6
3
5
4
3.00
2.80
2.60
1.70
1.60
1.50
2
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
0.22 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.60
0.45
0.30
0.15 MAX
0.05 MIN
8°
4°
0°
SEATING
PLANE
0.60
BSC
0.38 MAX
0.22 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 45. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
Model
INL
Description
Branding
D46
D46
D47
D47
ADꢀ062BRJZ-1REEL71
ADꢀ062BRJZ-1ꢀ00RL71
ADꢀ062BRJZ-2REEL71
ADꢀ062BRJZ-2ꢀ00RL71
ADꢀ062ARJZ-1ꢀ00RL71
ADꢀ062ARJZ-1REEL71
EVAL ADꢀ062EB
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
1 LSB
1 LSB
1 LSB
1 LSB
2 LSB
2 LSB
2.7 V to ꢀ.ꢀ V, Reset to 0 V
2.7 V to ꢀ.ꢀ V, Reset to 0 V
2.7 V to ꢀ.ꢀ V, Reset to Midscale
2.7 V to ꢀ.ꢀ V, Reset to Midscale
2.7 V to ꢀ.ꢀ V, Reset to 0 V
2.7 V to ꢀ.ꢀ V, Reset to 0 V
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
8 Lead SOT-23
Evaluation Board
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
D48
D48
1 Z = RoHS Compliant Part.
Rev. A | Page 19 of 20
AD5062
NOTES
©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04766-0-5/09(A)
Rev. A | Page 20 of 20
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