AD5066ARUZ [ADI]
Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP; 完全准确的16位无缓冲DAC VOUT SPI接口的2.7 V至5.5 V采用TSSOP
| 型号： | AD5066ARUZ |
| 厂家： | 
ADI |
| 描述： | Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| 文件： | 总20页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fully Accurate 16-Bit UnBuffered VOUT DAC SPI
Interface 2.7 V to 5.5 V in a TSSOP
Preliminary Technical Data
AD5066
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Low power Quad 16 bit DAC, 1LSB INL
Individual reference pins
2.7 V to 5.5 V power supply
Unbuffered voltage output capable of driving 60KΩ
Fast Settling time of 4 us typically
Power-on reset to zero scale or mid-scale
Per channel power-down
3 power-down functions
Low glitch on power up
Hardware LDAC with LDAC override function
CLR Function to programmable code
Small 16 lead TSSOP
Figure 1.AD5066
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
Description
AD5666
Quad,16-bit buffered D/A,16 LSB INL, TSSOP
AD5065/45/25 Quad,16-bit buffered D/A,1 LSB INL, TSSOP
AD5064/44/24 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
AD5063/62
AD5061
AD5060/40
16-bit nanoDAC, 1 LSB INL, MSOP
16-/14bit nanoDAC, 4 LSB INL, SOT-23
16-/14bit nanoDAC, 1 LSB INL, SOT-23
GENERAL DESCRIPTION
The AD5066 is a low power, 16-bit quad-channel, unbuffered
voltage-out DAC offering relative accuracy specs of 1LSB INL
with individual reference pin and can operate from a single
2.7V to 5.5V. The AD5066 parts also offer a differential
accuracy specification of 1 LSB. Reference buffers are also
provided on-chip. The parts use a versatile 3-wire, low power
Schmitt trigger serial interface that operates at clock rates up to
50 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The AD5066
incorporates a power-on reset circuit that ensures the DAC
output powers up zero scale or midscale and remains there until
a valid write takes place to the device. The AD5066 contain a
power-down feature that reduces the current consumption of
the device to typically 330 nA at 5 V and provides software
selectable output loads while in power-down mode. The part
can be placed into power-down mode over the serial interface.
Total unadjusted error for the part is <0.8 mV. Both parts
exhibit very low glitch on power-up.
The outputs of all DACs can be updated simultaneously using
the function, with the added functionality of user-select-
LDAC
able DAC channels to simultaneously update. There is also an
asynchronous that clears all DACs to a software-selectable
CLR
code - 0 V, midscale, or full scale.
PRODUCT HIGHLIGHTS
1. Quad channel available in 16-lead TSSOP package.
2. Individual voltage reference pins
3. 16 bit accurate, 1 LSB INL.
4. Low glitch on power-up.
5. High speed serial interface with clock speeds up to 50 MHz.
6. Three power-down modes available to the user.
7. Reset to known output voltage (zero scale).
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2007 Analog Devices, Inc. All rights reserved.
AD5066
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Rev. PrB | Page 2 of 20
Preliminary Technical Data
SPECIFICATIONS
AD5066
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 2.2V ≤VREFIN ≤. VDD unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
A Grade1 2
Typ
B Grade1
Typ
Parameter
STATIC PERFORMANCE3
Min
Max
Min
Max
Unit
Conditions/Comments
Resolution
Relative Accuracy
16
16
Bits
LSB
AD5066
±0.5
±0.5
±0.5
±0.5
±4
±4
±1
±1
±0.5
±0.5
±0.5
±0.5
±1
±1.5
±1
AD5066 TA = -40°C to +105°C
AD5066 TA = -40°C to +125°C
AD5066 TA = -40°C to +105°C
AD5066 TA = -40°C to +125°C
AD5066 TA = -40°C to +105°C
Differential Nonlinearity
LSB
μV
±1
Total Unadjusted Error
(TUE)
±500 ±±00
±500 ±00
±500 ±±00
±500 ±00
μV
±ꢀV
ꢁV/°C
AD5066 TA = -40°C to +125°C
All 0s loaded to DAC register
Offset Error
Offset Error Teꢀperature
Coefficient
0.05
±0.5
0.1
0.05
±0.5
0.1
Full-Scale Error
±500 ±±00
±500 ±00
±500 ±00
μV
μV
TA = -40°C to +105°C All 1s loaded to DAC
register
TA = -40°C to +125°C
±500 ±±00
±0.01 ±0.02
±1
Gain Error
Gain Teꢀperature Coefficient
DC Power Supply Rejection
Ratio
DC Crosstalk
±0.01 ±0.02 % FSR
±1
ppꢀ
dB
Ppꢀ Of FSR/°C
VDD ± 10%
–±0
–±0
0.5
0.5
LSB
Due to single-channel full-scale output
change,
(External Reference)
RL = 2 kΩ to GND or VDD
0.5
0.5
0.5
0.5
LSB/ꢀ
A
LSB
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS4
Output Voltage Range
0
VDD
0
VDD
V
DC Output Iꢀpedance
(Norꢀal ꢀode)
±
±
kΩ
Output iꢀpedance tolerance ±10%
DC Output Iꢀpedance
DAC in Power Down ꢀode
(output connected to 100kΩ
network)
(output connected to 1kΩ
network)
100
1
kΩ
kΩ
ꢁs
Output iꢀpedance tolerance ± 20kΩ
Output iꢀpedance tolerance ± 400Ω
Power-Up Tiꢀe
4.5
4.5
All DACs coꢀing out of power-down ꢀode
VDD = 5 V
DC PSRR
Wideband SFDR
-92
-67
-92
-67
dB
dB
VDD±10%, DAC = full scale
Output frequency = 10Khz
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Iꢀpedance
2
2
VDD
50
2
2
VDD
50
V
ꢁA
KΩ
40
120
40
120
Per DAC channel
Per DAC channel
LOGIC INPUTS4
Input Current5
Input Low Voltage, VINL
Input High Voltage, VINH
±3
0.±
±3
0.±
ꢁA
V
V
All digital inputs
VDD = 5 V
VDD = 5 V
Rev. PrB | Page 3 of 20
AD5066
Preliminary Technical Data
A Grade1 2
B Grade1
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
Pin Capacitance
POWER REQUIREMENTS
VDD
4
4
pF
2.7
5.5
2.7
5.5
V
All digital inputs at 0 or VDD
DAC active, excludes load current
VIH = VDD and VIL = GND
IDD (Norꢀal Mode)6
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)7
VDD = 4.5 V to 5.5 V
3
4
1
3
4
1
ꢀA
ꢁA
0.4
0.4
VIH = VDD and VIL = GND
1 Teꢀperature range is −40°C to +105°C, typical at 25°C.
2 A grade offered in AD5064 only
3 Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
4 Guaranteed by design and characterization; not production tested.
5 Total current flowing into all pins.
6. Interface inactive. All DACs active. DAC outputs unloaded
7. All four DACs powered down
Rev. PrB | Page 4 of 20
Preliminary Technical Data
AD5066
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = 4.096 unless otherwise specified. All specifications TMIN to TMAX
,
unless otherwise noted.
Table 3.
Parameter1, 2
Min Typ
Max
Unit
Conditions/Comments3
Output Voltage Settling Tiꢀe
5
ꢁs
¼ to ¾ scale settling to ±1 LSB,RL = 5kΩ single channel update
including DAC calibration sequence
Output Voltage Settling Tiꢀe
14
ꢁs
¼ to ¾ scale settling to ±1 LSB,RL = 5kΩ all channel update including
DAC calibration sequence
Slew Rate
1.5
4
−90
0.1
0.5
6
V/ꢁs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
Digital-to-Analog Glitch Iꢀpulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
1 LSB change around ꢀajor carry
VREF = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
6.5
6
AC PSRR
TBD
340
−±0
64
60
6
Multiplying Bandwidth
Total Harꢀonic Distortion
Output Noise Spectral Density
kHz
VREF = 2 V ± 0.2 V p-p
dB
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0x±400, 1 kHz
DAC code = 0x±400, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terꢀinology section.
3 Teꢀperature range is −40°C to + 105°C, typical at 25°C.
Rev. PrB | Page 5 of 20
AD5066
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
1
t1
t2
t3
t4
20
10
10
16.5
5
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
us ꢀin
us ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
ns ꢀin
us ꢀin
SCLK cycle tiꢀe
SCLK high tiꢀe
SCLK low tiꢀe
SYNC to SCLK falling edge set-up tiꢀe
Data set-up tiꢀe
t5
t6
t7
5
0
Data hold tiꢀe
SCLK falling edge to SYNC rising edge
Miniꢀuꢀ SYNC high tiꢀe (single channel update)
Miniꢀuꢀ SYNC high tiꢀe ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
t±
1.9
10.5
16.5
0
t±
t9
t10
t11
t12
t13
t14
t15
20
20
10
10
10.6
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation tiꢀe
1 Maxiꢀuꢀ SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2mA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
50pF
2mA
I
OH
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. PrB | Page 6 of 20
Preliminary Technical Data
AD5066
t10
t1
t9
SCLK
t2
t8
t7
t3
t4
SYNC
t6
t5
DIN
1
DB23
DB0
t14
t11
LDAC
t12
2
LDAC
t13
CLR
t15
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 3. Serial Write Operation
Rev. PrB | Page 7 of 20
AD5066
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Teꢀperature Range
Industrial
Storage Teꢀperature Range
−40°C to +125°C
−65°C to +150°C
+150°C
Junction Teꢀperature (TJ MAX
)
TSSOP Package
Power Dissipation
θJA Therꢀal Iꢀpedance
(TJ MAX − TA)/θJA
150.4°C/W
Reflow Soldering Peak Teꢀperature
SnPb
Pb Free
240°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accuꢀulate on
the huꢀan body and test equipꢀent and can discharge without detection. Although this product features
proprietary ESD protection circuitry, perꢀanent daꢀage ꢀay occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recoꢀꢀended to avoid perforꢀance
degradation or loss of functionality.
Rev. PrB | Page ± of 20
Preliminary Technical Data
AD5066
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to siꢀultaneously update. Alternatively, this pin can be tied perꢀanently low.
2
SYNC
Active Low Control Input. This is the fraꢀe synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated froꢀ 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 ꢁF capacitor in parallel with a 0.1 ꢁF capacitor to GND.
4
5
6
7
±
VREF
VREF
VOUT
VOUT
POR
B
A
A
C
Dac B reference input .This is the reference voltage input pin for Dac B.
Dac A reference input .This is the reference voltage input pin for Dac A.
Unbuffered analog output voltage froꢀ DAC A.
Unbuffered analog output voltage froꢀ DAC C.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to ꢀidscale.
9
VREF
C
Dac B reference input .This is the reference voltage input pin for Dac C.
10
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, ꢀidscale, or full scale. Default setting clears the output to 0 V.
11
12
13
14
15
VREF
VOUT
VOUT
GND
DIN
D
D
B
Dac A reference input .This is the reference voltage input pin for Dac D.
Unbuffered analog output voltage froꢀ DAC D.
Unbuffered analog output voltage froꢀ DAC B.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. PrB | Page 9 of 20
AD5066
Preliminary Technical Data
TERMINOLOGY
Relative Accuracy
Full-Scale Error
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Error! Reference source not found. shows a plot of
typical INL vs. code.
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Error! Reference source not found. and Error! Reference
source not found..
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Error! Reference source not found. shows a
plot of typical DNL vs. code.
Offset Error
DC Power Supply Rejection Ratio (PSRR)
Offset error is a measure of the difference between the actual
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied 10%.
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5066 with Code xxx loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
DC Crosstalk
Zero-Code Error
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5066, because the output of the DAC cannot go below 0
V. It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Error! Reference source not found. shows a plot of typical
zero-code error vs. Supply.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
decibels.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
is high). It is expressed in
LDAC
Zero-Code Error Drift
Digital Feedthrough
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
Gain Error Drift
(
held high). It is specified in nV-s and measured with a
SYNC
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Rev. PrB | Page 10 of 20
Preliminary Technical Data
AD5066
Digital Crosstalk
Multiplying Bandwidth
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-s.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Analog Crosstalk
Total Harmonic Distortion (THD)
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
code change (all 0s to all 1s or vice versa) while keeping
LDAC
high, and then pulsing
low and monitoring the output of
LDAC
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
low and monitoring the output of another DAC. The
LDAC
energy of the glitch is expressed in nV-s.
Rev. PrB | Page 11 of 20
AD5066
Preliminary Technical Data
THEORY OF OPERATION
D/A SECTION
R
R
R
The AD5066 are Quad 16-bit, serial input, voltage output
DACs. The parts operate from supply voltages of 2.7 V to 5.5 V.
Data is written to the AD5066 in a 32-bit word format via a 3-
wire serial interface. The AD5066 incorporates a power-on reset
circuit that ensures the DAC output powers up to a known out-
put state (midscale or zero-scale, see the Ordering Guide). The
devices also have a software power-down mode that reduces the
typical current consumption to less than 1 ꢀa.
TO OUTPUT
AMPLIFIER
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
R
R
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT =VREFIN
×
2N
The ideal output voltage when using and internal reference is
given by
Figure 7. Resistor String
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT
×
2N
SERIAL INTERFACE
where:
The AD5066 has a 3-wire serial interface (
, SCLK, and
SYNC
D = decimal equivalent of the binary code that is loaded to the
DAC register. 0 to 65,535 for AD5066 (16 bits).N = the DAC
resolution.
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 3 for a
timing diagram of a typical write sequence.
DAC ARCHITECTURE
STANDALONE MODE
The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure
5. The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
15 matched resistors to either GND or VREF buffer output. The
remaining 12 bits of the data word drive switches S0 to S11 of a
12-bit voltage mode R-2R ladder network.
The write sequence begins by bringing the
line low. Data
SYNC
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5066 compatible with high speed
DSPs. On the 32nd falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
V
OUT
operation. At this stage, the
line can be kept low or be
SYNC
2R
E1
2R
E2
2R
2R
2R
S0
2R
S1
2R
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
E15
S11
V
REF
falling edge of
can initiate the next write sequence.
SYNC
Because the
buffer draws more current when VIN = 2 V
SYNC
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
than it does when VIN = 0.8 V,
should be idled low
SYNC
between write sequences for even lower power operation of the
part. As is mentioned previously, however, must be
Figure 6. Dac Ladder Structure
SYNC
brought high again just before the next write sequence.
REFERENCE BUFFER
The AD5066 operates with an external reference. Each of the
four onboard dac’s will have a dedicated voltage reference pin.
In either case the reference input pin has an input range of 2 V
to VDD. This input voltage is then used to provide a buffered
reference for the DAC core.
Rev. PrB | Page 12 of 20
Preliminary Technical Data
AD5066
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up DCEN register (Daisy chain enable)
Set up DIO direction and Value
Reserved
Table 8. Address Commands
Address (n)
Selected DAC
Channel
A3
0
A2
0
A1
0
A0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
0
1
1
1
1
0
1
1
Reserved
Reserved
All DACs
Rev. PrB | Page 13 of 20
AD5066
Preliminary Technical Data
INTERRUPT
SYNC
INPUT SHIFT REGISTER
In a normal write sequence, the
line is kept low for at
SYNC
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if
is brought high before the
The AD5066 input shift register is 32 bits wide (see Figure 8).
The first four bits are don’t cares. The next four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 9) and finally the bit
data-word. The data-word comprises of 16-bit input code
followed by 4 don’t care bits for the AD5066 (see Figure 8).
These data bits are transferred to the DAC register on the 32nd
falling edge of SCLK.
SYNC
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Error! Reference
source not found.).
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 8. AD5066 Input Register Content
POWER-ON RESET
The AD5066 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the POR pin
low, the AD5066 output powers up to 0 V; by connecting the
POR pin high, the AD5066 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
When both Bit DB9 and Bit DB8, in the control register are set to
0, the part works normally with its normal power consumption
of TBD at 5 V. However, for the three power-down modes, the
supply current falls to TBD at 5 V (TBD at 3 V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the Dac to a resistor network of
known values. This has the advantage that the output
impedance of the part is known while the part is in power-
down mode. There are three different options. The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output
stage is illustrated in Figure 9.
(see Table 7). Any events on
or during power-on
LDAC CLR
reset are ignored.
POWER-DOWN MODES
The bias generator, resistor string, and other associated linear
circuitry are shut down when the power-down mode is activated.
However, the contents of the DAC register are unaffected when
in power-down. The time to exit power-down is typically 2.5 ꢀs
for VDD = 5 V and VDD = 3 V (see Error! Reference source not
found.).
The AD5066 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register (refer to
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device. Any or all DACs (DAC
A - DAC D) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 12 for the contents of the input shift register during
power-down/
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (
Low) or to the value in the
LDAC
DAC register before powering down (
high).
LDAC
power-up operation.
Rev. PrB | Page 14 of 20
Preliminary Technical Data
AD5066
Table 9. DCEN (Daisy-Chain Enable) Register
(DB1)
(DB0)
Action
0
1
0
0
Standalone ꢀode (default)
DCEN ꢀode
Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
1
0
0
0
X
X
X
X
1/0
Don’t cares
Coꢀꢀand bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
DCEN
register
Table 11. Modes of Operation
DB9
DB8
Operating Mode
Norꢀal operation
Power-down ꢀodes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 12. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31 to
DB28
DB10 to
DB19
DB4 to
DB7
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB9
DB8
DB3
DB2
DAC C
DB1
DAC B
DB0
X
0
1
0
0
X
X
X
X
X
PD1
PD0
X
DAC D
DAC A
Don’t
cares
Coꢀꢀand bits (C2 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-down
ꢀode
Don’t
cares
Power-down/power-up channel selection—
set bit to 1 to select
Figure 9. Output Stage During Power-Down
Rev. PrB | Page 15 of 20
AD5066
Preliminary Technical Data
updates synchronously; that is, the DAC register is updated
CLEAR CODE REGISTER
after new data is read, regardless of the state of the
pin.
LDAC
The AD5066 has a hardware
pin that is an asynchronous
CLR
It effectively sees the
pin as being tied low. (See Table 15
LDAC
clear input. The
input is falling edge sensitive. Bringing the
CLR
for the
register mode of operation.) This flexibility is
LDAC
line low clears the contents of the input register and the
CLR
DAC registers to the data contained in the user-configurable
register and sets the analog outputs accordingly. (see Table
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
CLR
13) This function can be used in system calibration to load zero
scale, midscale, or full scale to all channels together. These clear
code values are user-programmable by setting two bits, Bit DB1
and Bit DB0, in the control register (see Table 13). The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register (see Table 7).
Writing to the DAC using command 0110 loads the 4-bit
LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the pin works normally. Setting the bits to 1 means the
LDAC
DAC channel is updated regardless of the state of the
LDAC
pin. See Table 16 for the contents of the input shift register
during the load register mode of operation.
LDAC
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If
sequence, the write is aborted.
is activated during a write
CLR
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5066.
The pulse activation time—the falling edge of
to when
CLR
CLR
the output starts to change—is typically TBD ns. However, if
outside the DAC linear region, it typically takes TBD ns after
executing
for the output to start changing (see Error!
CLR
Reference source not found.).
See Table 14 for contents of the input shift register during the
loading clear code register operation
The power supply to the AD5066 should be bypassed with 10 ꢀF
and 0.1 ꢀF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 ꢀF capacitor ideally
right up against the device. The 10 ꢀF capacitors are the
tantalum bead type. It is important that the 0.1 ꢀF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 ꢀF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
FUNCTION
LDAC
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
LDAC
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on the falling edge of the 32nd SCLK pulse.
can be permanently low or pulsed as in Figure 3
LDAC
Asynchronous
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
: The outputs are not updated at the same
LDAC
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
goes
LDAC
Alternatively, the outputs of all DACs can be updated
simultaneously using the software
function by writing to
LDAC
Input Register n and updating all DAC registers. Command
0010 is reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
LDAC
Rev. PrB | Page 16 of 20
Preliminary Technical Data
AD5066
Table 13. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0x±000
1
0
0xFFFF
1
1
No operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
0
1
0
1
X
X
X
X
1/0
Don’t cares
Coꢀꢀand bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
Table 15.
Overwrite Definition
LDAC
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
1/0
LDAC Operation
0
1
Deterꢀined by LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
X—don’t care
Table 16. 32-Bit Input Shift Register Contents for
Overwrite Function
LDAC
MSB
LSB
DB31
to
DB4
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB3
DB2
DB1
DAC B
DB0
X
0
1
1
0
X
X
X
X
X
DAC D
DAC C
DAC A
Don’t
cares
Coꢀꢀand bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
LDAC
LDAC
bit to 1 override pin
Setting
Rev. PrB | Page 17 of 20
AD5066
Preliminary Technical Data
AD5066 to 80C51/80L51 Interface
MICROPROCESSOR INTERFACING
Figure 12 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/ 80L51 drives SCLK of the AD5066,
AD5066 to Blackfin® ADSP-BF53X Interface
Figure 10 shows a serial interface between the AD5066 and the
Blackfin ADSP-BF53X microprocessor. The ADSP-BF53X
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, while TSCLK0 drives the
SYNC
and RxD drives the serial data line of the part. The
signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5066, P3.3 is taken low. The 80C51/80L51 transmit data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 output
the serial data in a format that has the LSB first. The AD5066
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
SYNC
SCLK of the parts. The
is driven from TFS0.
1
ADSP-BF53x
1
AD5066
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
AD5066
1
80C51/80L51
1
1
P3.3
TxD
RxD
SYNC
SCLK
DIN
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 10. AD5066 to Blackfin ADSP-BF53X Interface
AD5066 to 68HC11/68L11 Interface
Figure 11 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
the serial data line of the DAC.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 12. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
1
Figure 13 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
AD5025/45/65 on the rising edge of the SCLK.
68HC11/68L11
AD5066
1
PC7
SCK
SYNC
SCLK
DIN
MOSI
1
MICROWIRE
AD5066
1
ADDITIONAL PINS OMITTED FOR CLARITY.
CS
SK
SO
SYNC
DIN
Figure 11. AD5066 to 68HC11/68L11 Interface
SYNC
The
signal is derived from a port line (PC7). The setup
SCLK
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
line is taken low (PC7). When the 68HC11/ 68L11 is
Figure 13. AD5066/45/654 to MICROWIRE Interface
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
Rev. PrB | Page 1± of 20
Preliminary Technical Data
APPLICATIONS
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5066
AD5066
+5 V output.
R2 = 10kΩ
+5V
Because the supply current required by the AD5066 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the parts (see Figure 14). This is
+5V
R1 = 10kΩ
AD820/
OP295
±5V
V
V
especially useful if the power supply is quite noisy or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5066. If the low dropout REF195 is used, it
must supply 500 ꢀA of current to the AD5066, with no load on
the output of the DAC. When the DAC output is loaded, the
REF195 also needs to supply the current to the load. The total
current required (with a 5 kΩ load on the DAC output) is
DD
OUT
10µF
0.1µF
AD5066
–5V
THREE-WIRE
SERIAL
INTERFACE
Figure 15. Bipolar Operation with the AD5066
USING THE AD5066 WITH A
GALVANICALLY ISOLATED INTERFACE
500 ꢀA + (5 V/5 kΩ) = 1.5 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 ꢀV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so the
ADuM1300 three-channel digital isolator provides the required
isolation (see Figure 16). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5066.
15V
5V
REF195
V
DD
SYNC
THREE-WIRE
V
= 0V TO 5V
OUT
SERIAL
SCLK
DIN
AD
5066
INTERFACE
5V
REGULATOR
10µF
0.1µF
POWER
Figure 14. REF195 as Power Supply to the AD5025/45/65
BIPOLAR OPERATION USING THE AD5066
The AD5066 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 15. The circuit gives an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V
V
V
V
OA
SCLK
IA
ADuM1300
AD5066
V
SDI
OUT
SYNC
V
IB
OB
OC
The output voltage for any input code can be calculated as
follows:
V
DATA
DIN
IC
GND
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
V = V
×
×
− V
×
⎢
O
DD
DD
⎝
⎠
⎣
Figure 16. AD5025/45/65 with a Galvanically Isolated Interface
where D represents the input code in decimal (0 to 65,535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
10 × D
65,536
⎛
⎜
⎞
⎟
V =
− 5 V
O
⎝
⎠
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
Rev. PrB | Page 19 of 20
AD5066
Preliminary Technical Data
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Accuracy
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
Resolution
16 bits
16 bits
16 bits
16 bits
AD5066BRUZ-11
AD5066BRUZ-1REEL7
AD5066ARUZ
RU-16
RU-16
RU-16
RU-16
Zero
Zero
Zero
Zero
AD5066ARUZ-REEL7
Eval-AD5066 EBZ
Evaluation board
1 Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06845-0-6/07(PrB)
Rev. PrB | Page 20 of 20
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