AD5144BRUZ100 [ADI]
The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.; 在AD5124 / AD5144 / AD5144A电位为128 / 256位调整应用的非易失性解决方案，提供的保证低电阻容差误差为±8 ％，最高至±6 mA的电流密度在AX， BX，和WX销。
| 型号： | AD5144BRUZ100 |
| 厂家： | 
ADI |
| 描述： | The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. |
| 文件： | 总36页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Channel, 128-/256-Position, I2C/SPI,
Nonvolatile Digital Potentiometer
Data Sheet
AD5124/AD5144/AD5144A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
LOGIC
LRDAC
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: 6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
AD5124/AD5144
POWER-ON
RESET
RDAC1
A1
W1
B1
A2
W2
B2
A3
W3
B3
A4
W4
B4
INPUT
REGISTER 1
Fast start-up time < 75 μs
Linear gain setting mode
RESET
DIS
RDAC2
INPUT
REGISTER 2
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
4 mm × 4 mm package option
4 kV ESD protection
SCLK/SCL
SDI/SDA
SERIAL
INTERFACE
RDAC3
7/8
INPUT
REGISTER 3
SYNC/ADDR0
SDO/ADDR1
RDAC4
INPUT
REGISTER 4
APPLICATIONS
EEPROM
MEMORY
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
GND
V
SS
WP
Figure 1. AD5124/AD5144 24-Lead LFCSP
GENERAL DESCRIPTION
The AD5124/AD5144/AD5144A potentiometers provide a
nonvolatile solution for 128-/256-position adjustment applications,
offering guaranteed low resistor tolerance errors of 8ꢀ and up to
6 mA current density in the Ax, Bx, and Wx pins.
The AD5124/AD5144/AD5144A are available in a compact,
24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts
are guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
Table 1. Family Models
Model
Channel Position Interface Package
AD51231
AD5124
AD5124
AD51431
AD5144
AD5144
Quad
Quad
Quad
Quad
Quad
Quad
128
128
128
256
256
256
256
128
128
256
256
128
256
I2C
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
SPI/I2C
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these devices
suitable for filter design.
AD5144A Quad
AD5122 Dual
AD5122A Dual
AD5142 Dual
AD5142A Dual
The low wiper resistance of only 40 Ω at the ends of the resistor
array allow for pin-to-pin connection.
The wiper values can be set through an SPI-/I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
AD5121
AD5141
Single
Single
LFCSP
1 Two potentiometers and two rheostats.
Rev. A
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Tel: 781.329.4700
Technical Support
©2012 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5124/AD5144/AD5144A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RDAC Register and EEPROM.................................................. 23
Input Shift Register .................................................................... 23
Serial Data Digital Interface Selection, DIS............................ 23
SPI Serial Data Interface............................................................ 23
I2C Serial Data Interface............................................................ 25
I2C Address.................................................................................. 25
Advanced Control Modes ......................................................... 27
EEPROM or RDAC Register Protection................................. 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams—TSSOP............................................ 3
Specifications..................................................................................... 4
Electrical Characteristics—AD5124 .......................................... 4
Electrical Characteristics—AD5144 and AD5144A................ 7
Interface Timing Specifications................................................ 10
Shift Register and Timing Diagrams ....................................... 11
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 17
Test Circuits..................................................................................... 22
Theory of Operation ...................................................................... 23
LRDAC
Load RDAC Input Register (
)..................................... 28
RDAC Architecture.................................................................... 31
Programming the Variable Resistor......................................... 31
Programming the Potentiometer Divider............................... 32
Terminal Voltage Operating Range ......................................... 32
Power-Up Sequence ................................................................... 32
Layout and Power Supply Biasing............................................ 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 34
REVISION HISTORY
12/12—Rev. 0 to Rev. A
Changes to Table 12 and Table 13 ................................................ 25
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 36
Data Sheet
AD5124/AD5144/AD5144A
FUNCTIONAL BLOCK DIAGRAMS—TSSOP
V
V
V
V
DD
LOGIC
DD
LOGIC
AD5124/AD5144
AD5144A
POWER-ON
RESET
POWER-ON
RESET
RDAC 1
RDAC 1
A1
W1
B1
A1
W1
B1
INPUT
REGISTER 1
INPUT
REGISTER 1
RDAC 2
RDAC 2
SYNC
SCLK
SDI
RESET
SCL
A2
W2
B2
A3
W3
B3
A4
W4
B4
A2
W2
B2
A3
W3
B3
A4
W4
B4
INPUT
REGISTER 2
INPUT
REGISTER 2
2
SPI
I C
SERIAL
SERIAL
INTERFACE
RDAC 3
RDAC 3
SDA
INTERFACE
7/8
8
INPUT
REGISTER 3
INPUT
REGISTER 3
SDO
ADDR
RDAC 4
RDAC 4
INPUT
REGISTER 4
INPUT
REGISTER 4
EEPROM
MEMORY
EEPROM
MEMORY
GND
V
GND
V
SS
SS
Figure 2. AD5124/AD5144 20-Lead TSSOP
Figure 3. AD5144A 20-Lead TSSOP
Rev. A | Page 3 of 36
AD5124/AD5144/AD5144A
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5124
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity2
N
R-INL
7
Bits
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−1
−2.5
0.1
1
+1
+2.5
LSB
LSB
−0.5
−1
0.1
0.25 +1
+0.5
LSB
LSB
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
−0.5
−8
0.1
1
35
+0.5
+8
LSB
%
ppm/°C
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
Nominal Resistance Match
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
0.1
0.1
0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
0.1
LSB
LSB
+0.5
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1
0.25
5
1.5
0.5
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. A | Page 4 of 36
Data Sheet
AD5124/AD5144/AD5144A
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
400
−0.7
2
320
1
5.5
µA
nA
µA
mA
µA
nA
µW
dB
VDD = 2.3 V
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
120
−60
3.5
−66
∆VDD/∆VSS = VDD 10%,
code = full scale
Rev. A | Page 5 of 36
AD5124/AD5144/AD5144A
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1
Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. A | Page 6 of 36
Data Sheet
AD5124/AD5144/AD5144A
ELECTRICAL CHARACTERISTICS—AD5144 AND AD5144A
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
N
R-INL
8
Bits
Resistor Integral Nonlinearity2
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
−2
−5
0.2
1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
0.1
0.5
0.2
1
+1
+2
+0.5
+8
LSB
LSB
LSB
%
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Code = full scale
Code = zero scale
RAB = 10 kΩ
35
ppm/°C
55
130
125
400
Ω
Ω
RAB = 100 kΩ
Bottom Scale or Top Scale
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
40
60
0.2
80
230
+1
Ω
Ω
%
Nominal Resistance Match
RAB1/RAB2
−1
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
INL
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
0.2
0.1
0.2
+1
+0.5
+0.5
LSB
LSB
LSB
Differential Nonlinearity4
Full-Scale Error
DNL
VWFSE
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
0.2
LSB
LSB
+1
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 100 kΩ
(ΔVW/VW)/ΔT × 106 Code = half scale
1.2
0.5
5
3
1
LSB
LSB
ppm/°C
Voltage Divider Temperature
Coefficient3
Rev. A | Page 7 of 36
AD5124/AD5144/AD5144A
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
RESISTOR TERMINALS
Maximum Continuous Current
IA, IB, and IW
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
25
12
pF
pF
Capacitance W3
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = VW = VB
12
5
15
pF
pF
nA
Common-Mode Leakage Current3
−500
+500
DIGITAL INPUTS
Input Logic3
High
VINH
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
Low
VINL
VHYST
IIN
0.2 × VLOGIC
1
V
V
µA
pF
Input Hysteresis3
Input Current3
0.1 × VLOGIC
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
CIN
5
VOH
VOL
RPULL-UP = 2.2 kΩ to VLOGIC
ISINK = 3 mA
ISINK = 6 mA, VLOGIC > 2.3 V
VLOGIC
V
V
V
µA
pF
0.4
0.6
+1
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
−1
2
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
VSS = GND
2.3
2.25
1.8
5.5
V
V
V
V
2.75
VDD
VDD
Single supply, VSS = GND
Dual supply, VSS < GND
VIH = VLOGIC or VIL = GND
VDD = 5.5 V
2.25
Positive Supply Current
IDD
0.7
400
−0.7
2
320
1
5.5
µA
nA
µA
mA
µA
nA
µW
dB
VDD = 2.3 V
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection Ratio
ISS
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
−5.5
IDD_EEPROM_STORE
IDD_EEPROM_READ
ILOGIC
PDISS
PSRR
120
−60
3.5
−66
∆VDD/∆VSS = VDD 10%,
code = full scale
Rev. A | Page 8 of 36
Data Sheet
AD5124/AD5144/AD5144A
Parameter
Symbol
Test Conditions/Comments
Min
Typ 1 Max
Unit
DYNAMIC CHARACTERISTICS9
Bandwidth
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
3
0.43
MHz
MHz
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
THD
eN_WB
tS
VDD/VSS = 2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
0.5 LSB error band
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
2
µs
µs
12
10
25
−90
1
Crosstalk (CW1/CW2)
CT
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
Analog Crosstalk
Endurance10
CTA
TA = 25°C
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS
= 2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. A | Page 9 of 36
AD5124/AD5144/AD5144A
Data Sheet
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter1
Test Conditions/Comments
Min
20
30
10
15
10
15
10
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t1
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
VLOGIC > 1.8 V
VLOGIC = 1.8 V
SCLK cycle time
t2
t3
SCLK high time
SCLK low time
t4
t5
t6
t7
SYNC-to-SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to next SCLK fall ignored
Minimum SYNC high time
5
10
20
2
t8
3
t9
50
SCLK rising edge to SDO valid
SYNC rising edge to SDO pin disable
t10
500
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Refer to t
t
for memory commands operations (see Table 6).
EEPROM_PROGRAM and
EEPROM_READBACK
3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. I2C Interface
Parameter1 Test Conditions/Comments
Min
Typ Max Unit Description
2
fSCL
t1
Standard mode
Fast mode
Standard mode
Fast mode
100
400
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Serial clock frequency
4.0
0.6
4.7
1.3
250
100
0
SCL high time, tHIGH
t2
Standard mode
Fast mode
SCL low time, tLOW
t3
Standard mode
Fast mode
Data setup time, tSU; DAT
t4
Standard mode
Fast mode
3.45
0.9
Data hold time, tHD; DAT
0
t5
Standard mode
Fast mode
4.7
0.6
4
0.6
4.7
1.3
4
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
t6
Standard mode
Fast mode
t7
Standard mode
Fast mode
t8
Standard mode
Fast mode
0.6
t9
Standard mode
Fast mode
1000 ns
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
300
300
300
ns
ns
ns
t10
t11
t11A
Standard mode
Fast mode
Standard mode
Fast mode
Fall time of SDA signal, tFDA
1000 ns
300 ns
1000 ns
Rise time of SCL signal, tRCL
Standard mode
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 5)
Fast mode
20 + 0.1 CL
300
ns
Rev. A | Page 10 of 36
Data Sheet
AD5124/AD5144/AD5144A
Parameter1 Test Conditions/Comments
Min
Typ Max Unit Description
t12
Standard mode
Fast mode
Fast mode
300
300
50
ns
ns
ns
Fall time of SCL signal, tFCL
20 + 0.1 CL
0
3
tSP
Pulse width of suppressed spike
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter
Min
1
Typ
Max
Unit
μs
Description
t1
End command to LRDAC falling edge
Minimum LRDAC low time
t2
50
0.1
ns
t3
10
50
30
75
μs
RESET low time
1
tEEPROM_PROGRAM
15
7
ms
μs
Memory program time (not shown in Figure 8)
Memory readback time (not shown in Figure 8)
Start-up time (not shown in Figure 8)
Reset EEPROM restore time (not shown in Figure 8)
tEEPROM_READBACK
2
tPOWER_UP
μs
μs
tRESET
30
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2 Maximum time after VDD − VSS is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DB15 (MSB)
DB8
A0
DB7
D7
DB0 (LSB)
D0
D1
A1
D6
D5
D4
D3
C3
C2
C1
C0
A3
A2
D2
DATA BITS
CONTROL BITS
ADDRESS BITS
Figure 4. Input Shift Register Contents
t11
t12
t6
t8
t2
SCL
SDA
t5
t1
t6
t10
t9
t4
t3
t7
P
S
S
P
Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence)
Rev. A | Page 11 of 36
AD5124/AD5144/AD5144A
Data Sheet
t4
t1
t2
t7
SCLK
t3
t8
SYNC
SDI
t5
t6
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 6. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1
t1
t2
t7
t4
SCLK
t3
t8
SYNC
t5
t6
SDI
C3
C2
C1
C0
D7
D6
D5
D2
D1
D0
t9
t10
SDO
C3*
C2*
C1*
C0*
D7*
D6*
D5*
D2*
D1*
D0*
*PREVIOUS COMMAND RECEIVED.
Figure 7. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0
SCLK
SPI INTERFACE
SYNC
SCL
2
I C INTERFACE
SDA
P
t2
t1
LRDAC
RESET
t3
Figure 8. Control Pins Timing Diagram
Rev. A | Page 12 of 36
Data Sheet
AD5124/AD5144/AD5144A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
VDD to GND
VSS to GND
VDD to VSS
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7 V
VLOGIC to GND
−0.3 V to VDD + 0.3 V or
THERMAL RESISTANCE
+7.0 V (whichever is less)
VA, VW, VB to GND
IA, IW, IB
VSS − 0.3 V, VDD + 0.3 V
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Pulsed1
Table 8. Thermal Resistance
Frequency > 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Frequency ≤ 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
6 mA/d2
1.5 mA/d2
Package Type
24-Lead LFCSP
20-Lead TSSOP
θJA
θJC
3
45
Unit
°C/W
°C/W
351
1431
6 mA/√d2
1.5 mA/√d2
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
Digital Inputs
−0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
ESD CAUTION
3
Operating Temperature Range, TA
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
ESD4
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
4 kV
FICDM
1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
4 Human body model (HBM) classification.
Rev. A | Page 13 of 36
AD5124/AD5144/AD5144A
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
20
19
18
17
16
15
14
13
12
11
SYNC
GND
A1
SDO
SDI
3
SCLK
4
W1
B1
V
LOGIC
DD
AD5124/
AD5144
5
V
TOP VIEW
6
A3
B4
W4
A4
B2
W2
(Not to Scale)
7
W3
B3
8
9
V
SS
10
A2
Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144)
Table 9. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144)
Pin No. Mnemonic
Description
1
SYNC
GND
A1
Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
2
3
4
5
W1
B1
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
6
A3
Terminal A of RDAC3. VSS ≤ VA ≤ VDD.
7
8
W3
B3
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
9
VSS
A2
W2
B2
A4
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Terminal A of RDAC4. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
Serial Data Input.
10
11
12
13
14
15
16
17
18
19
20
W4
B4
VDD
VLOGIC
SCLK
SDI
SDO
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
Rev. A | Page 14 of 36
Data Sheet
AD5124/AD5144/AD5144A
1
2
20
19
18
17
16
15
14
13
12
11
RESET
GND
A1
ADDR
SDA
SCL
3
4
W1
V
LOGIC
DD
AD5144A
5
B1
V
TOP VIEW
(Not to Scale)
6
A3
B4
W4
A4
B2
W2
7
W3
8
B3
9
V
SS
10
A2
Figure 10. 20-Lead TSSOP, I2C Interface Pin Configuration (AD5144A)
Table 10. 20-Lead TSSOP, I2C Interface Pin Function Descriptions (AD5144A)
Pin No. Mnemonic Description
1
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not
used, tie RESET to VLOGIC
.
2
3
GND
A1
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
4
5
W1
B1
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
6
A3
Terminal A of RDAC3. VSS ≤ VA ≤ VDD.
7
8
W3
B3
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
9
VSS
A2
W2
B2
A4
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Terminal A of RDAC4. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
Serial Data Input/Output.
10
11
12
13
14
15
16
17
18
19
20
W4
B4
VDD
VLOGIC
SCL
SDA
ADDR
Programmable Address for Multiple Package Decoding.
Rev. A | Page 15 of 36
AD5124/AD5144/AD5144A
Data Sheet
PIN 1
INDICATOR
GND
A1
W1
B1
A3
W3
1
2
3
4
5
6
18 DIS
17 SCL/SCLK
AD5124/
AD5144
16 V
LOGIC
15 V
DD
TOP VIEW
14 B4
13 W4
(Not to Scale)
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
.
SS
Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144)
Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144)
Pin No. Mnemonic
Description
1
2
GND
A1
Ground Pin, Logic Ground Reference.
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
3
4
W1
B1
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
5
A3
Terminal A of RDAC3. VSS ≤ VA ≤ VDD.
6
7
W3
B3
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
8
9
VSS
A2
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
10
11
12
13
14
15
16
17
W2
B2
A4
W4
B4
VDD
VLOGIC
SCL/SCLK
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Terminal A of RDAC4. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition.
SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition.
18
19
DIS
Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be
left floating.
Serial Data Input/Output (SDA), When DIS = 1.
Serial Data Input (SDI), When DIS = 0.
SDA/SDI
20
WP
Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when
reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used,
tie WP to VLOGIC
.
21
22
ADDR1/SDO
ADDR0/SYNC
Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.
Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0.
Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1.
Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into
the input shift register.
23
24
LRDAC
Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their
associated input registers were previously loaded using Command 2 (see Table 20). This allows simultaneous
update of all RDAC registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to VLOGIC
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used,
tie RESET to VLOGIC
Internally Connect the Exposed Pad to VSS.
.
RESET
EPAD
.
Rev. A | Page 16 of 36
Data Sheet
AD5124/AD5144/AD5144A
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.2
0.1
10kΩ, +125°C
10kΩ, +25°C
0.4
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
0.3
0
100kΩ, –40°C
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
100
200
0
100
200
CODE (Decimal)
CODE (Decimal)
Figure 12. R-INL vs. Code (AD5144/AD5144A)
Figure 15. R-DNL vs. Code (AD5144/AD5144A)
0.20
0.10
0.05
0.15
0.10
0
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0
–0.05
–0.10
–0.15
–0.20
–0.25
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 13. R-INL vs. Code (AD5124)
Figure 16. R-DNL vs. Code (AD5124)
0.3
0.2
0.1
0
0.10
0.05
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.1
–0.2
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
–0.3
0
0
100
200
100
200
CODE (Decimal)
CODE (Decimal)
Figure 17. DNL vs. Code (AD5144/AD5144A)
Figure 14. INL vs. Code (AD5144/AD5144A)
Rev. A | Page 17 of 36
AD5124/AD5144/AD5144A
Data Sheet
0.15
0.10
0.05
0
0.06
0.04
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.05
–0.10
–0.15
0
50
100
0
50
100
CODE (Decimal)
CODE (Decimal)
Figure 18. INL vs. Code (AD5124)
Figure 21. DNL vs. Code (AD5124)
450
400
350
300
250
200
150
100
50
450
100kΩ
10kΩ
10kΩ
100kΩ
400
350
300
250
200
150
100
50
0
0
–50
–50
AD5144/
AD5144/
0
0
50
25
100
50
150
75
200
100
255
127
AD5144A
0
0
50
25
100
50
150
75
200
100
255
127
AD5144A
AD5124
AD5124
CODE (Decimal)
CODE (Decimal)
Figure 19. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106)
vs. Code
Figure 22. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
800
1200
I
I
I
, V = 2.3V
I
I
I
, V
= 2.3V
= 3.3V
= 5V
V
V
= V
LOGIC
= GND
2
DD DD
LOGIC LOGIC
DD
SS
I C, V
= 1.8V
= 2.3V
= 3.3V
= 5V
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
2
, V = 3.3V
, V
I C, V
DD DD
LOGIC LOGIC
2
700
600
500
400
300
200
100
0
, V = 5V
, V
I C, V
DD DD
LOGIC LOGIC
2
I C, V
1000
800
600
400
200
0
2
I C, V
= 5.5V
= 1.8V
= 2.3V
= 3.3V
= 5V
SPI, V
SPI, V
SPI, V
SPI, V
SPI, V
= 5.5V
–40
10
60
TEMPERATURE (°C)
110 125
0
1
2
3
4
5
INPUT VOLATGE (V)
Figure 20. Supply Current vs. Temperature
Figure 23. ILOGIC Current vs. Digital Input Voltage
Rev. A | Page 18 of 36
Data Sheet
AD5124/AD5144/AD5144A
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x10 (0x08)
0x8 (0x04)
0x80 (0x40)
0x40 (0x20)
–10
0x20 (0x10)
–20
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x10 (0x08)
0x8 (0x04)
–30
0x4 (0x02)
0x00
0x2 (0x01)
0x1 (0x00)
–40
0x00
–50
AD5144/AD5144A (AD5124)
AD5144/AD5144A (AD5124)
–60
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. 10 kΩ Gain vs. Frequency vs. Code
Figure 27. 100 kΩ Gain vs. Frequency vs. Code
–40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
10kΩ
100kΩ
10kΩ
V
/V = ±2.5V
= 1V rms
= GND
DD SS
100kΩ
V
V
A
B
–50
–60
CODE = HALF SCALE
NOISE FILTER = 22kHz
–70
–80
V
f
/V = ±2.5V
DD SS
–90
= 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
IN
–100
20
200
2k
FREQUENCY (Hz)
20k
200k
0.001
0.01
0.1
1
VOLTAGE (V rms)
Figure 25. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
Figure 28. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
20
10
0
V
R
/V = ±2.5V
DD SS
= 10kΩ
AB
0
–20
–10
–20
–30
–40
–50
–60
–70
–40
–60
–80
QUARTER SCALE
–80
QUARTER SCALE
MIDSCALE
V
R
/V = ±2.5V
MIDSCALE
DD SS
FULL-SCALE
= 100kΩ
FULL-SCALE
AB
–100
–90
10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
Figure 29. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
Rev. A | Page 19 of 36
AD5124/AD5144/AD5144A
Data Sheet
600
500
400
300
200
100
0
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
1.0
0.8
0.6
0.4
0.2
0
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
100kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
10kΩ, V
= 2.3V
= 2.7V
= 3V
DD
DD
DD
DD
DD
DD
= 3.6V
= 5V
= 5.5V
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
0
1
2
3
4
5
RESISTOR DRIFT (ppm)
VOLTAGE (V)
Figure 33. Resistor Lifetime Drift
Figure 30. Incremental Wiper On Resistance vs. Positive Power Supply (VDD
)
0
10
10kΩ
V
V
= 5V ±10% AC
10kΩ + 0pF
DD
SS
100kΩ
= GND, V = 4V, V = GND
10kΩ + 75pF
A
B
9
–10
–20
–30
–40
–50
–60
–70
–80
–90
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0pF
100kΩ + 75pF
100kΩ + 150pF
100kΩ + 250pF
CODE = MIDSCALE
8
7
6
5
4
3
2
1
0
AD5144/
AD5144A
10
100
1k
10k
100k
1M
10M
0
0
20
10
40
20
60
30
80
40
100
50
120
FREQUENCY (Hz)
60 AD5124
CODE (Decimal)
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 31. Maximum Bandwidth vs. Code vs. Net Capacitance
0.8
0.020
0x80 TO 0x7F, 100kΩ
V
V
V
/V = ±2.5V
DD SS
0x80 TO 0x7F, 10kΩ
= V
A
B
DD
SS
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.015
0.010
0.005
0
= V
–0.005
–0.010
–0.015
–0.020
V
V
V
/V = ±2.5V
DD SS
= V
= V
A
DD
B
SS
CODE = HALF SCALE
–0.1
0
5
10
15
0
500
1000
1500
2000
TIME (µs)
TIME (ns)
Figure 32. Maximum Transition Glitch
Figure 35. Digital Feedthrough
Rev. A | Page 20 of 36
Data Sheet
AD5124/AD5144/AD5144A
0
7
6
5
4
3
2
1
0
10kΩ
SHUTDOWN MODE ENABLED
100kΩ
–20
–40
–60
–80
10kΩ
–100
100kΩ
–120
AD5144/
10
100
1k
10k
100k
1M
10M
0
0
50
25
100
50
150
75
200
100
250
125
AD5144A
AD5124
FREQUENCY (Hz)
CODE (Decimal)
Figure 36. Shutdown Isolation vs. Frequency
Figure 37. Theoretical Maximum Current vs. Code
Rev. A | Page 21 of 36
AD5124/AD5144/AD5144A
Data Sheet
TEST CIRCUITS
Figure 38 to Figure 42 define the test conditions used in the Specifications section.
NC
DUT
A
V
I
A
W
V+ = V ±10%
DD
W
V
∆
MS
V
A
B
PSRR (dB) = 20 LOG
DD
)
(
∆V
B
W
DD
V+
~
V
∆V
%
MS
MS
PSS (%/%) =
V
MS
∆V
%
DD
NC = NO CONNECT
Figure 41. Power Supply Sensitivity and
Figure 38. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Power Supply Rejection Ratio (PSS and PSRR)
0.1V
R
=
SW
I
DUT
B
SW
CODE = 0x00
W
+
–
DUT
V+ = V
DD
1LSB = V+/2
0.1V
I
SW
N
A
W
V+
V
SS
TO V
DD
B
A = NC
V
MS
Figure 39. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 42. Incremental On Resistance
NC
DUT
A
W
I
= V /R
W DD NOMINAL
V
W
B
V
R
= V
/I
MS1
W
MS1 W
NC = NO CONNECT
Figure 40. Wiper Resistance
Rev. A | Page 22 of 36
Data Sheet
AD5124/AD5144/AD5144A
THEORY OF OPERATION
The AD5124/AD5144/AD5144A digital programmable
potentiometers are designed to operate as true variable resistors
SERIAL DATA DIGITAL INTERFACE SELECTION, DIS
The AD5124/AD5144 LFSCP provides the flexibility of a selectable
interface. When the digital interface select (DIS) pin is tied low,
the SPI mode is engaged. When the DIS pin is tied high, the I2C
mode is engaged.
for analog signals within the terminal voltage range of VSS < VTERM
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad register
that allows unlimited changes of resistance settings. A secondary
register (the input register) can be used to preload the RDAC
register data.
<
SPI SERIAL DATA INTERFACE
The AD5124/AD5144 contain a 4-wire, SPI-compatible digital
SYNC
begins by bringing the
held low until the complete data-word is loaded from the SDI
pin. Data is loaded in at the SCLK falling edge transition, as
shown in Figure 6. When
interface (SDI,
, SDO, and SCLK). The write sequence
SYNC SYNC
The RDAC register can be programmed with any position setting
using the I2C or SPI interface (depending on the model). When
a desirable wiper position is found, this value can be stored in
the EEPROM memory. Thereafter, the wiper position is always
restored to that position for subsequent power-ups. The storing
of the EEPROM data takes approximately 15 ms; during this
time, the device is locked and does not acknowledge any new
command, preventing any changes from taking place.
line low. The
pin must be
SYNC
returns high, the serial data-
word is decoded according to the instructions in Table 20.
To minimize power consumption in the digital input buffers
when the part is enabled, operate all serial interface pins close
to the VLOGIC supply rails.
RDAC REGISTER AND EEPROM
SYNC
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5144/AD5144A, 256 taps), the wiper is
connected to half scale of the variable resistor. The RDAC register
is a standard logic register; there is no restriction on the number
of changes allowed.
Interruption
In a standalone write sequence for the AD5124/AD5144,
SYNC
the
instruction is decoded when
SYNC
line is kept low for 16 falling edges of SCLK, and the
SYNC
is pulled high. However, if
line is kept low for less than 16 falling edges of SCLK,
the
the input shift register content is ignored, and the write sequence is
considered invalid.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 14).
SDO Pin
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 14). Thereafter, the RDAC register
always sets at that position for any future on-off-on power
supply sequence. It is possible to read back data saved into the
EEPROM with Command 3 (see Table 14).
The serial data output pin (SDO) serves two purposes: to read back
the contents of the control, EEPROM, RDAC, and input registers
using Command 3 (see Table 14 and Table 20), and to connect the
AD5124/AD5144 in daisy-chain mode.
The SDO pin contains an internal open-drain output that needs an
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 20).
SYNC
external pull-up resistor. The SDO pin is enabled when
is
pulled low, and the data is clocked out of SDO on the rising
edge of SCLK, as shown in Figure 6 and Figure 7.
INPUT SHIFT REGISTER
For the AD5124/AD5144/AD5144A, the input shift register is
16 bits wide, as shown in Figure 4. The 16-bit word consists of
four control bits, followed by four address bits and by eight
data bits.
If the AD5124 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 14 and
Table 20.
Rev. A | Page 23 of 36
AD5124/AD5144/AD5144A
Data Sheet
Daisy-Chain Connection
To prevent data from mislocking (for example, due to noise) the
part includes an internal counter, if the SCLK falling edges count is
not a multiple of 8, the part ignores the command. A valid clock
Daisy chaining minimizes the number of port pins required from
the controlling IC. As shown in Figure 43, the SDO pin of one
package must be tied to the SDI pin of the next package. The clock
period may need to be increased because of the propagation
delay of the line between subsequent devices. When two AD5124/
AD5144 devices are daisy chained, 32 bits of data are required.
The first 16 bits are assigned to U2, and the second 16 bits are
SYNC
count is 16, 24, 32, 40, and so on. The counter resets when
returns high.
SYNC
assigned to U1, as shown in Figure 44. Keep the
until all 32 bits are clocked into their respective serial registers.
SYNC
pin low
The
pin is then pulled high to complete the operation.
V
V
LOGIC
R
LOGIC
R
AD5124/
AD5144
AD5124/
AD5144
P
P
2.2kΩ
2.2kΩ
SDI
SDO
U2
MOSI
SDI
U1
SDO
MICROCONTROLLER
MISO
SCLK
SS
SYNC
SCLK
SYNC
SCLK
Figure 43. Daisy-Chain Configuration
18
SCLK
1
2
16
17
32
SYNC
MOSI
DB15
DB0
DB0
DB15
DB15
DB0
INPUT WORD FOR U2
INPUT WORD FOR U1
INPUT WORD FOR U2
SDO_U1
DB0
DB15
UNDEFINED
Figure 44. Daisy-Chain Diagram
Rev. A | Page 24 of 36
Data Sheet
AD5124/AD5144/AD5144A
I2C SERIAL DATA INTERFACE
I2C ADDRESS
The AD5144/AD5144A have 2-wire, I2C-compatible serial
interfaces. These devices can be connected to an I2C bus as a
slave device, under the control of a master device. See Figure 5
for a timing diagram of a typical write sequence.
The AD5144/AD5144A each have two different device address
options available (see Table 12 and Table 13).
Table 12. 20-Lead TSSOP Device Address Selection
ADDR
7-Bit I2C Device Address
0101000
The AD5144/AD5144A support standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
VLOGIC
No connect1
0101010
GND
0101011
The 2-wire serial bus protocol operates as follows:
1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
Table 13. 24-Lead LFCSP Device Address Selection
ADDR0 Pin
ADDR1 Pin
7-Bit I2C Device Address
0100000
VLOGIC
VLOGIC
No connect1
GND
VLOGIC
No connect1
GND
VLOGIC
VLOGIC
No connect1
No connect1
No connect1
GND
0100010
0100011
0101000
0101010
0101011
0101100
0101110
W
and an R/ bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
VLOGIC
No connect1
GND
W
If the R/ bit is set high, the master reads from the slave
GND
GND
0101111
W
device. However, if the R/ bit is set low, the master writes
1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
Rev. A | Page 25 of 36
AD5124/AD5144/AD5144A
Data Sheet
Table 14. Reduced Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0] 1
Command
Number
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
X
X
X
X
X
X
X
X
X
NOP: do nothing.
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2
3
0
0
0
0
1
1
0
1
0
0
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
X
A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
1
D0
1
1
Data
EEPROM
RDAC
9
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
0
X
0
A1 A0
A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
10
14
15
0
X
X
X
A3
A1 A0
D0 Software shutdown
D0
0
1
Condition
Normal mode
Shutdown mode
1 X = don’t care.
Table 15. Reduced Address Bits Table
A3
A2
A1
X1
0
A0
X1
0
Channel
Stored Channel Memory
Not applicable
RDAC1
1
0
0
0
All channels
RDAC1
0
0
0
1
RDAC2
RDAC2
0
0
1
0
RDAC3
RDAC3
0
0
1
1
RDAC4
RDAC4
1 X = don’t care.
Rev. A | Page 26 of 36
Data Sheet
AD5124/AD5144/AD5144A
Low Wiper Resistance Feature
ADVANCED CONTROL MODES
The AD5124/AD5144/AD5144A include two commands to
reduce the wiper resistance between the terminals when the
devices achieve full scale or zero scale. These extra positions are
called bottom scale, BS, and top scale, TS. The resistance between
Terminal A and Terminal W at top scale is specified as RTS.
Similarly, the bottom scale resistance between Terminal B and
Terminal W is specified as RBS.
The AD5124/AD5144/AD5144A digital potentiometers include
a set of user programming features to address the wide number of
applications for these universal adjustment devices (see Table 20
and Table 22).
Key programming features include the following:
•
•
•
•
•
•
•
•
Input register
Linear gain setting mode
Low wiper resistance feature
Linear increment and decrement instructions
6 dB increment and decrement instructions
Burst mode (I2C only)
The contents of the RDAC registers are unchanged by entering
into these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13
(see Table 20); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 20).
Reset
Shutdown mode
Table 16 and Table 17 show the truth tables for the top scale
position and the bottom scale position, respectively, when the
potentiometer or linear gain setting mode is enabled.
Input Register
The AD5124/AD5144/AD5144A include one input register per
RDAC register. These registers allow preloading of the value for
the associated RDAC register. These registers can be written to
using Command 2 and read back from using Command 3 (see
Table 20).
Table 16. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
RAW
RAB
RWB
RAW
RWB
RAB
RTS
RAB
This feature allows a synchronous and asynchronous update of
one or all of the RDAC registers at the same time.
Table 17. Bottom Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
The transfer from the input register to the RDAC register is
RAW
RWB
RAW
RWB
done asynchronously by the
pin or synchronously by
LRDAC
RTS
RBS
RAB
RBS
Command 8 (see Table 20).
Linear Increment and Decrement Instructions
If new data is loaded into an RDAC register, this RDAC register
automatically overwrites the associated input register.
The increment and decrement commands (Command 4 and
Command 5 in Table 20) are useful for linear step adjustment
applications. These commands simplify microcontroller software
coding by allowing the controller to send an increment or
decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where
all wiper positions are changed at the same time.
Linear Gain Setting Mode
The patented architecture of the AD5124/AD5144/AD5144A
allows the independent control of each string resistor, RAW, and
RWB. To enable this feature, use Command 16 (see Table 20) to set
Bit D2 of the control register (see Table 22).
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, the W terminal.
For an increment command, executing Command 4 automatically
moves the wiper to the next RDAC position. This command
can be executed in a single channel or multiple channels.
This feature enables a second input and an RDAC register per
channel, as shown in Table 21, but the actual RDAC contents remain
unchanged. The same operations are valid for potentiometer and
linear gain setting modes. The EEPROM commands affect the
R
WB resistance only. The parts restores in potentiometer mode
after a reset or power-up.
Rev. A | Page 27 of 36
AD5124/AD5144/AD5144A
Data Sheet
±± dB Increment and Decrement Instructions
Shutdown Mode
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 20).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to go
to the full-scale position (see Table 18).
The AD5124/AD5144/AD5144A can be placed in shutdown mode
by executing the software shutdown command, Command 15
(see Table 20), and setting the LSB (D0) to 1. This feature places
the RDAC in a zero power consumption state where the device
operates in potentiometer mode, Terminal A is open circuited,
and the wiper, Terminal W, is connected to Terminal B; however, a
finite wiper resistance of 40 Ω is present. When the device is
configured in linear gain setting mode, the resistor addressed,
R
AW or RWB, is internally place at high impedance. Table 19 shows a
truth table depending on the device operating mode. The contents
of the RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 20 are supported while
in shutdown mode. Execute Command 15 (see Table 20) and set
the LSB (D0) to 0 to exit shutdown mode.
Incrementing the wiper position by +6 dB essentially doubles the
RDAC register value, whereas decrementing the wiper position
by −6 dB halves the register value. Internally, the AD5124/
AD5144/AD5144A use shift registers to shift the bits left and
right to achieve a 6 dB increment or decrement. These functions
are useful for various audio/video level adjustments, especially
for white LED brightness settings in which human visual responses
are more sensitive to large adjustments than to small adjustments.
Table 19. Shutdown Mode Truth Table
Linear Gain Setting Mode
Potentiometer Mode
RAW
RWB
RAW RWB
High impedance High impedance High impedance RBS
EEPROM OR RDAC REGISTER PROTECTION
Table 18. Detailed Left Shift and Right Shift Functions for
the 6 dB Step Increment and Decrement
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 22), which protects the RDAC
and EEPROM registers independently.
Left Shift (+6 dB/Step)
Right Shift (−6 dB/Step)
0000 0000
1111 1111
0000 0001
0111 1111
0000 0010
0011 1111
If the registers are protected by hardware, pull the
pin low
WP
pin is pulled
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
0001 1111
0000 1111
0000 0111
0000 0011
0000 0001
0000 0000
0000 0000
(only available in the LFCSP package). If the
WP
low when the part is executing a command, the protection is not
enabled until the command is completed (only available in the
LFCSP package).
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
Burst Mode (I2C Only)
LOAD RDAC INPUT REGISTER (LRDAC)
By enabling the burst mode, multiple data bytes can be sent to
the part consecutively. After the command byte, the part interprets
the following consecutive bytes as data bytes for the command.
LRDAC
software or hardware transfers data from the input
register to the RDAC register (and therefore updates the wiper
position). By default, the input register has the same value as the
RDAC register; therefore, only the input register that has been
updated using Command 2 is updated.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 22).
LRDAC
, Command 8, allows updating of a single RDAC
register or all of the channels at once (see Table 20). This is a
synchronous update.
Software
Reset
The AD5124/AD5144/AD5144A can be reset through software
by executing Command 14 (see Table 20) or through hardware
LRDAC
The hardware
is completely asynchronous and copies
the content of all the input registers into the associated RDAC
registers. If a command is being executed, any transition in
RESET
on the low pulse of the
pin. The reset command loads the
RDAC register with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
LRDAC
the
pin is ignored by the part to avoid data corruption.
RESET
RESET
Tie
to VDD if the
pin is not used.
Rev. A | Page 28 of 36
Data Sheet
AD5124/AD5144/AD5144A
Table 20. Advance Commands Operation Truth Table
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1
Data Bits[DB7:DB0]1
Command
Number
C3
0
C2
0
C1
0
C0
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
NOP: do nothing
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to RDAC
2
3
0
0
0
0
1
1
0
1
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to input
register
X
A2 A1 A0
X
X
X
X
X
X
D1 D0 Read back contents
D1
0
0
D0
0
1
Data
Input register
EEPROM
1
0
Control
register
1
1
RDAC
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
9
0
1
1
1
0
0
A1 A0
A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
Copy RDAC register to
EEPROM
10
11
0
1
1
0
1
0
1
0
0
0
0
0
Copy EEPROM into RDAC
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to EEPROM
12
1
0
0
1
A3 A2 A1 A0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
D0 Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
D0 Bottom scale
13
1
0
0
1
A3 A2 A1 A0
D0 = 1; enter
D0 = 0; exit
14
15
1
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Software reset
A3 A2 A1 A0
D0 Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16
1
1
0
1
X
X
X
X
X
X
X
X
D3 D2 D1 D0 Copy serial register data to
control register
1 X = don’t care.
Rev. A | Page 29 of 36
AD5124/AD5144/AD5144A
Data Sheet
Table 21. Address Bits
Potentiometer Mode
Input Register RDAC Register
Linear Gain Setting Mode
Stored RDAC
Memory
A3
1
0
A2
X1
0
A1
X1
0
A0
X1
0
Input Register
RDAC Register
All channels
RDAC1
All channels
RDAC1
All channels
RWB1
All channels
RWB1
Not applicable
RDAC1
0
0
1
0
0
0
0
1
Not applicable
RDAC2
Not applicable
RDAC2
RAW1
RWB2
RAW1
RWB2
Not applicable
RDAC2
0
0
1
0
0
1
1
0
Not applicable
RDAC3
Not applicable
RDAC3
RAW2
RWB3
RAW2
RWB3
Not applicable
RDAC3
0
0
1
0
1
1
0
1
Not applicable
RDAC4
Not applicable
RDAC4
RAW3
RWB4
RAW3
RWB4
Not applicable
RDAC4
0
1
1
1
Not applicable
Not applicable
RAW4
RAW4
Not applicable
1 X = don’t care.
Table 22. Control Register Bit Descriptions
Bit Name
Description
D0
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
D1
D2
D3
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Burst mode (I2C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Rev. A | Page 30 of 36
Data Sheet
AD5124/AD5144/AD5144A
RDAC ARCHITECTURE
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation— 8% Resistor Tolerance
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5124/AD5144 employ a
three-stage segmentation approach, as shown in Figure 45. The
AD5124/AD5144/AD5144A wiper switch is designed with the
transmission gate CMOS topology and with the gate voltage
derived from VDD and VSS.
The AD5124/AD5144/AD5144A operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating, or it can be tied to Terminal W, as shown
in Figure 46.
A
A
A
W
W
W
A
S
TS
B
B
B
R
R
H
H
Figure 46. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is 10 kꢀ or 100 kꢀ, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
R
M
R
M
R
L
W
R
L
AD5124:
7-BIT/8-BIT
ADDRESS
DECODER
R
R
M
D
128
From 0x00 to 0x7F (1)
From 0x00 to 0xFF (2)
R
WB (D)
RAB RW
RAB RW
R
H
M
AD5144/AD5144A:
R
H
S
BS
D
256
RWB (D)
B
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
Figure 45. AD5124/AD5144/AD5144A Simplified RDAC Circuit
R
AB is the end-to-end resistance.
RW is the wiper resistance.
Top Scale/Bottom Scale Architecture
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, RWA. RWA also
gives a maximum of 8% absolute resistance error. RWA starts at the
maximum resistance value and decreases as the data loaded into
the latch increases. The general equations for this operation are
In addition, the AD5124/AD5144/AD5144A include new
positions to reduce the resistance between terminals. These
positions are called bottom scale and top scale. At bottom scale,
the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB =
100 kΩ). At top scale, the resistance between Terminal A and
Terminal W is decreased by 1 LSB, and the total resistance is
reduced to 60 Ω (RAB = 100 kΩ).
AD5124:
128 D
128
R
AW (D)
RAB RW
RAB RW
From 0x00 to 0x7F (3)
From 0x00 to 0xFF (4)
AD5144/AD5144A:
256 D
256
R
AW (D)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
Rev. A | Page 31 of 36
AD5124/AD5144/AD5144A
Data Sheet
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
TERMINAL VOLTAGE OPERATING RANGE
The AD5124/AD5144/AD5144A are designed with internal ESD
diodes for protection. These diodes also set the voltage boundary
of the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
AD5124:
D
128
From 0x00 to 0x7F (5)
From 0x00 to 0xFF (6)
R
WB (D)
RAB RW
RAB RW
AD5144/AD5144A:
V
DD
D
256
RWB (D)
A
where:
W
B
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
V
SS
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B to the maximum continuous
current of 6 mA or to the pulse current specified in Table 7.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 48), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and
VA, VB, and VW. The order of powering VA, VB, VW, and digital
inputs is not important as long as they are powered after VSS,
VDD, and VLOGIC. Regardless of the power-up sequence and the
ramp rates of the power supplies, once VDD is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 47.
V
A
A
LAYOUT AND POWER SUPPLY BIASING
W
V
OUT
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 49 illustrates the basic supply bypassing configuration
for the AD5124/AD5144/AD5144A.
B
V
B
Figure 47. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
RWB(D)
R
AW (D)
RAB
VW (D)
VA
VB
(7)
RAB
V
V
V
V
LOGIC
DD
DD
LOGIC
+
+
+
C3
C1
C5
0.1µF
C6
10µF
where:
10µF
0.1µF
AD5124/
AD5144/
AD5144A
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
C4
10µF
C2
0.1µF
V
V
SS
SS
Operation of the digital potentiometer in the divider mode results
in a more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent mainly on the
ratio of the internal resistors, RAW and RWB, and not the absolute
values. Therefore, the temperature drift reduces to 5 ppm/°C.
GND
Figure 49. Power Supply Bypassing
Rev. A | Page 32 of 36
Data Sheet
AD5124/AD5144/AD5144A
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
18
0.50
BSC
1
6
EXPOSED
PAD
2.20
2.10 SQ
2.00
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 50. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 51. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. A | Page 33 of 36
AD5124/AD5144/AD5144A
Data Sheet
ORDERING GUIDE
Model1, 2
RAB (kΩ)
10
100
10
100
10
100
10
100
10
100
10
Resolution
128
128
128
128
Interface
SPI/I2C
SPI/I2C
SPI
SPI
SPI
Temperature Range Package Description
Package Option
CP-24-10
CP-24-10
RU-20
RU-20
RU-20
AD5124BCPZ10-RL7
AD5124BCPZ100-RL7
AD5124BRUZ10
AD5124BRUZ100
AD5124BRUZ10-RL7
AD5124BRUZ100-RL7
AD5144BCPZ10-RL7
AD5144BCPZ100-RL7
AD5144BRUZ10
AD5144BRUZ100
AD5144BRUZ10-RL7
AD5144BRUZ100-RL7
EVAL-AD5144DBZ
AD5144ABRUZ10
AD5144ABRUZ100
AD5144ABRUZ10-RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
Evaluation Board
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
20-lead TSSOP
128
128
SPI
RU-20
256
256
256
256
256
256
SPI/I2C
SPI/I2C
SPI
CP-24-10
CP-24-10
RU-20
RU-20
RU-20
SPI
SPI
SPI
100
RU-20
10
100
10
256
256
256
256
I2C
I2C
I2C
I2C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
RU-20
RU-20
RU-20
RU-20
AD5144ABRUZ100-RL7 100
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options.
Rev. A | Page 34 of 36
Data Sheet
NOTES
AD5124/AD5144/AD5144A
Rev. A | Page 35 of 36
AD5124/AD5144/AD5144A
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10877-0-12/12(A)
Rev. A | Page 36 of 36
相关型号：
AD5144BRUZ100-RL7
The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.
ADI
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