AD5160BRJZ10-RL7 [ADI]
256-Position SPI-Compatible Digital Potentiometer; 256位SPI兼容数字电位计
| 型号： | AD5160BRJZ10-RL7 |
| 厂家： | 
ADI |
| 描述： | 256-Position SPI-Compatible Digital Potentiometer |
| 文件： | 总16页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256-Position SPI-Compatible
Digital Potentiometer
AD5160
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
DD
256-position
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI-compatible interface
A
CS
SPI INTERFACE
SDI
Power-on preset to midscale
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 45 ppm/°C
Low power, IDD = 8 μA
W
B
CLK
WIPER
REGISTER
Wide operating temperature: –40°C to +125°C
Evaluation board available
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
PIN CONFIGURATION
1
2
3
4
W
8
7
6
5
A
V
AD5160
B
DD
GND
CLK
CS
SDI
TOP VIEW
(Not to Scale)
Figure 2.
GENERAL DESCRIPTION
The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers1 or variable resistors but with
enhanced resolution, solid-state reliability, and superior low
temperature coefficient performance.
The wiper settings are controllable through an SPI-compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 μA allows for usage in portable battery-operated
applications.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
AD5160
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 12
SPI Interface .................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor......................................... 14
Programming the Potentiometer Divider............................... 15
SPI-Compatible 3-Wire Serial Bus........................................... 15
ESD Protection ........................................................................... 15
Power-Up Sequence ................................................................... 15
Layout and Power Supply Bypassing ....................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 kΩ Version.................................. 3
10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4
Timing Characteristics—All Versions....................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
5/09—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 16
1/09—Rev. 0 to Rev. A
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 1 ............................................................................ 3
Changes to Resistor Noise Voltage Density Parameter,
Table 1 ................................................................................................ 3
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 2 ............................................................................ 4
Changes to Resistor Noise Voltage Density Parameter,
Table 2 ................................................................................................ 4
Added Endnote to Table 3............................................................... 5
Changes to Table 4............................................................................ 6
Changes to the Rheostat Operation Section............................... 14
Deleted Terminal Voltage Operating Range Section and
Figure 41, Renumbered Figures Sequentially ............................. 13
Changes to Figure 40 and Figure 41............................................. 15
Changes to Ordering Guide .......................................................... 16
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 16
AD5160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ꢀ1%, or 3 V ꢀ1%ꢁ VA = +VDDꢁ VB = 1 Vꢁ –41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.
Table 1.
Parameter
Symbol Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1.5 ±±.1
+1.5
+2±
12±
LSB
LSB
%
ppm/°C
Ω
−4
±±.ꢀ5 +4
−2±
VAB = VDD, wiper = no connect
45
5±
Potentiometer Divider Mode
Specifications apply to all VRs
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
−1.5 ±±.1
−1.5 ±±.6
15
+1.5
+1.5
LSB
LSB
ppm/°C
LSB
LSB
Code = ±x8±
Code = ±xFF
Code = ±x±±
−6
±
−2.5
+2
±
+6
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A, Capacitance B6
Capacitance W6
Common-Mode Leakage
DIGITAL INPUTS
VA, VB, VW
CA,B
CW
GND
VDD
V
f = 1 MHz, measured to GND, code = ±x8±
f = 1 MHz, measured to GND, code = ±x8±
VA = VB = VDD/2
45
6±
1
pF
pF
nA
ICM
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
μA
pF
±.8
VDD = 3 V
VDD = 3 V
VIN = ± V or 5 V
±.6
±1
CIL
5
3
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipationꢀ
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
±.2
V
μA
mW
VIH = 5 V or VIL = ± V
VIH = 5 V or VIL = ± V, VDD = 5 V
∆VDD = +5 V ± 1±%, code = midscale
PSS
±±.±2 ±±.±5 %/%
BW_5K
THDW
tS
RAB = 5 kΩ, code = ±x8±
VA = 1 V rms, VB = ± V, f = 1 kHz
VA = 5 V, VB = ± V, ±1 LSB error band
RWB = 2.5 kΩ
1.2
±.±5
1
MHz
%
μs
Resistor Noise Voltage Density
eN_WB
6
nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
± V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. B | Page 3 of 16
AD5160
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ꢀ1%, or 3 V ꢀ1%ꢁ VA = VDDꢁ VB = 1 Vꢁ −41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.
Table 2.
Parameter
Symbol Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2
−15
±±.1
±±.25
+1
+2
+15
LSB
LSB
%
∆RAB/∆T VAB = VDD
,
45
5±
ppm/°C
Wiper = no connect
VDD = 5 V
Specifications apply to all VRs
Wiper Resistance
Potentiometer Divider Mode
Resolution
RW
12±
Ω
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
Coefficient
DNL
INL
∆VW/∆T
−1
−1
±±.1
±±.3
15
+1
+1
LSB
LSB
ppm/°C
Code = ±x8±
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = ±xFF
Code = ±x±±
−3
±
−1
1
±
3
LSB
LSB
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance A, Capacitance B6
f = 1 MHz, measured to GND, code =
±x8±
f = 1 MHz, measured to GND, code =
±x8±
45
6±
1
Capacitance W6
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS
VA = VB = VDD/2
nA
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
μA
pF
±.8
VDD = 3 V
VDD = 3 V
VIN = ± V or 5 V
±.6
±1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipationꢀ
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
±.2
V
μA
mW
VIH = 5 V or VIL = ± V
VIH = 5 V or VIL = ± V, VDD = 5 V
∆VDD = +5 V ± 1±%, code = midscale
3
PSS
±±.±2
±±.±5 %/%
BW
THDW
RAB = 1± kΩ/5± kΩ/1±± kΩ, Code = ±x8±
VA = 1 V rms, VB = ± V, f = 1 kHz, RAB
1± kΩ
6±±/1±±/4±
±.±5
kHz
%
Total Harmonic Distortion
=
VW Settling Time (1± kΩ/5± kΩ/1±± kΩ)
Resistor Noise Voltage Density
tS
VA = 5 V, VB = ± V,
±1 LSB error band
RWB = 5 kΩ
2
9
μs
eN_WB
nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
± V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. B | Page 4 of 16
AD5160
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = +5V ꢀ1%, or +3V ꢀ1%ꢁ VA = VDDꢁ VB = 1 Vꢁ –41°C < TA < +ꢀ25°Cꢁ unless otherwise noted.
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS1, 2
Symbol
Conditions
Min
Typ1
Max
25
Unit
Specifications apply to all parts
Clock Frequency
Input Clock Pulse Width
Data Setup Time
fCLK
tCH, tCL
tDS
MHz
ns
ns
Clock level high or low
2±
5
Data Hold Time
tDH
5
ns
CS Setup Time
tCSS
15
4±
±
ns
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
tCSW
tCSH±
tCSH1
ns
ns
±
ns
1 See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (1±% to 9±% of 3 V) and timed from a
voltage level of 1.5 V.
2 Guaranteed by design and not subject to production test.
Rev. B | Page 5 of 16
AD5160
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VDD
VA, VB, VW to GND
Maximum Current IMAX
IWB, IWA Pulsed
IWB, IWA Continuous
5 kΩ, 10 kΩ
1
20 mA
ESD CAUTION
4.7 mA
50 kΩ
100 kΩ
0.95 mA
0.48 mA
0 V to +7 V
Digital Inputs and Output Voltage to GND
Temperature
Operating Temperature Range
−40°C to +125°C
150°C
−65°C to +150°C
Maximum Junction Temperature (TJMAX
Storage Temperature
Thermal Resistance (SOT-23 Package)2
)
θJA Thermal Impedance
θJC Thermal Impedance
206ºC/W
91°C/W
Reflow Soldering (Pb-Free)
Peak Temperature
260°C
Time at Peak Temperature
10 sec to 40 sec
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and applied
voltage across any two of the A, B, and W terminals at a given resistance.
2 Package power dissipation = (TJMAX − TA)/θJA
.
Rev. B | Page 6 of 16
AD5160
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
W
8
7
6
5
A
V
AD5160
B
DD
GND
CLK
CS
SDI
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
Description
1
W
W Terminal.
2
3
4
5
VDD
GND
CLK
SDI
CS
B
Positive Power Supply.
Digital Ground.
Serial Clock Input. Positive edge triggered.
Serial Data Input.
6
Chip Select Input, Active Low. When CS returns high, data loads into the DAC register.
7
8
B Terminal.
A Terminal.
A
Rev. B | Page 7 of 16
AD5160
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
5V
3V
–40°C
+25°C
+85°C
+125°C
0.8
0.6
0.6
0.4
0.2
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
0
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 4. R-INL vs. Code vs. Supply Voltages
Figure 7. DNL vs. Code, VDD = 5 V
1.0
0.8
1.0
0.8
0.6
5V
3V
5V
3V
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 5. R-DNL vs. Code vs. Supply Voltages
Figure 8. INL vs. Code vs. Supply Voltages
1.0
0.8
1.0
0.8
_
40°C
5V
3V
+25°C
+85°C
+125°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
256
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 6. INL vs. Code, VDD = 5 V
Figure 9. DNL vs. Code vs. Supply Voltages
Rev. B | Page 8 of 16
AD5160
1.0
0.8
2.5
2.0
1.5
1.0
0.5
–40
+25°C
+85°C
°C
0.6
+125°C
0.4
V
V
= 5.5V
= 2.7V
DD
0.2
0
DD
–0.2
–0.4
–0.6
–0.8
–1.0
0
–40
0
40
80
120
0
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 13. Zero-Scale Error vs. Temperature
Figure 10. R-INL vs. Code, VDD = 5 V
1.0
0.8
10
_
40°C
+25°C
+85°C
+125°C
0.6
0.4
0.2
V
= 5.5V
DD
0
1
–0.2
–0.4
–0.6
V
= 2.7V
DD
–0.8
–1.0
0.1
–40
0
32
64
96
128
160
192
224
256
0
40
80
120
CODE (Decimal)
TEMPERATURE (°C)
Figure 11. R-DNL vs. Code, VDD = 5 V
Figure 14. Supply Current vs. Temperature
2.5
2.0
1.5
1.0
70
60
50
40
30
20
10
0
V
V
= 2.7V
= 5.5V
DD
DD
V
= 5V
DD
0.5
0
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Shutdown Current vs. Temperature
Figure 12. Full-Scale Error vs. Temperature
Rev. B | Page 9 of 16
AD5160
200
150
100
50
REF LEVEL
0.000dB
0
/DIV
6.000dB
MARKER 510 634.725Hz
MAG (A/R) –9.049dB
0x80
–6
0x40
–12
0x20
0x10
–18
–24
–30
–36
–42
–48
–54
–60
0x08
0x04
0x02
0x01
0
–50
0
32
64
96
128
160
192
224
256
CODE (Decimal)
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
160
140
120
100
80
REF LEVEL
0.000dB
0
/DIV
6.000dB
MARKER 100 885.289Hz
MAG (A/R) –9.014dB
0x80
–6
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
60
0x08
40
0x04
0x02
0x01
20
0
–20
0
32
64
96
128
160
192
224
256
CODE (Decimal)
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
REF LEVEL
0.000dB
0
/DIV
6.000dB
MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB
REF LEVEL
0.000dB
0
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
0x80
0x80
–6
–6
0x40
0x20
0x40
0x20
–12
–12
–18
–24
–30
–36
–42
–48
–54
–60
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x10
0x08
0x04
0x02
0x01
0x02
0x01
1k
START 1 000.000Hz
10k
100k
1M
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Rev. B | Page 10 of 16
AD5160
REF LEVEL
–5.000dB
/DIV
0.500dB
–5.5
5kΩ – 1.026 MHz
10kΩ – 511 MHz
50kΩ – 101 MHz
100kΩ – 54 MHz
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–10.5
1
VW
CLK
R = 50kΩ
R = 5kΩ
2
R = 10kΩ
R = 100kΩ
Ch 1 200mV
B
Ch 2 5.00 V
B
M 100ns A CH2 3.00 V
W
W
10k
100k
1M
10M
START 1 000.000Hz
STOP 1 000 000.000Hz
Figure 22. –3 dB Bandwidth @ Code = 0x80
Figure 25. Digital Feedthrough
60
40
20
0
CODE = 0x80, V = V , V = 0V
DD
A
B
V
V
= 5V
= 0V
A
B
1
VW
CS
PSRR @ V = 3V DC ± 10% p-p AC
DD
2
PSRR @ V = 5V DC ± 10% p-p AC
Ch 1 100mV
B
Ch 2 5.00 V
B
M 200ns A CH1 152mV
W
DD
W
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 26. Midscale Glitch, Code 0x80 to Code 0x7F
Figure 23. PSRR vs. Frequency
900
V
= 5V
DD
800
700
600
500
400
300
V
V
= 5V
= 0V
A
B
1
VW
CS
CODE = 0x55
CODE = 0xFF
2
200
100
0
Ch 1
5.00V
B
Ch 2 5.00 V
B
M 200ns A CH1 3.00 V
W
W
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 24. IDD vs. Frequency
Figure 27. Large Signal Settling Time, Code 0xFF to Code 0x00
Rev. B | Page 11 of 16
AD5160
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
5V
DUT
A
V+ = V
DD
1LSB = V+/2
OP279
N
V
OUT
V
W
IN
V+
W
B
OFFSET
GND
V
MS
A
DUT
B
OFFSET
BIAS
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 33. Test Circuit for Noninverting Gain
NO CONNECT
DUT
A
+15V
W
I
W
V
IN
A
DUT
W
AD8610
–15V
V
OUT
OFFSET
GND
B
B
V
2.5V
MS
Figure 34. Test Circuit for Gain vs. Frequency
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
0.1V
R
=
SW
I
SW
DUT
DUT
CODE = 0x00
I
= V /R
NOMINAL
DD
W
A
W
V
W
W
V
MS2
B
0.1V
I
SW
B
V
R
= [V
– V
]/I
MS2
W
MS1
W
MS1
V
TO V
DD
SS
Figure 30. Test Circuit for Wiper Resistance
Figure 35. Test Circuit for Incremental On Resistance
NC
V
A
V+ = V
10%
PSRR (dB) = 20 LOG
DD
ΔV
ΔV
MS
DD
I
(
)
V
A
B
CM
DUT
GND
DD
V
DD
W
A
B
%
ΔV
ΔV
MS
W
V+
PSS (%/%) =
V
%
SS
DD
V
CM
V
MS
NC NC = NO CONNECT
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 36. Test Circuit for Common-Mode Leakage Current
A
B
DUT
5V
W
V
IN
OP279
V
OUT
OFFSET
GND
OFFSET
BIAS
Figure 32. Test Circuit for Inverting Gain
Rev. B | Page 12 of 16
AD5160
SPI INTERFACE
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Table 6. Serial Data-Word Format
SDI
CLK
CS
B7
D7
MSB
27
B6
B5
B4
B3
B2
B1
B0
D0
LSB
20
0
1
D6
D5
D4
D3
D2
D1
RDAC REGISTER LOAD
0
1
0
VOUT
Figure 37. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT
)
1
0
1
SDI
(DATA IN)
Dx
Dx
tDS
tCH
tCS1
tCH
CLK
0
tCSH1
tCL
tCSHO
tCSS
1
0
CS
tCSW
tS
VDD
VOUT
±1LSB
0
Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT
)
Rev. B | Page 13 of 16
AD5160
THEORY OF OPERATION
The AD5160 is a 256-position digitally controlled variable
resistor (VR) device.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
D
256
R
WB (D) =
×RAB +RW
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
R
AB is the end-to-end resistance.
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
final two or three digits of the model number as listed in the
Ordering Guide section determine the nominal resistance value,
for example, in model AD5160BRJZ10, the 10 represents 10 kΩ;
and in AD5160BRJZ50, the 50 represents 50 kΩ.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings.
Table 7. Codes and Corresponding RWB Resistance
D (Dec.)
RWB (Ω)
9961
5060
99
Output State
255
128
1
Full Scale (RAB − 1 LSB + RW)
Midscale
1 LSB
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 60 Ω
wiper contact resistance, such connection yields a minimum of
60 Ω resistance between Terminal W and Terminal B.
0
60
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
60 Ω is present. Take care to limit the current flow between W
and B in this state to a maximum pulse current of no more than
20 mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
The second connection is the first tap point, which corresponds
to 99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for Data 0x01.
The third connection is the next tap point, representing 138 Ω
(2 × 39 Ω + 60 Ω) for Data 0x02, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at 9961 Ω (RAB − 1 LSB + RW). Figure 39
shows a simplified diagram of the equivalent RDAC circuit
where the last resistor string is not accessed; therefore, there is
1 LSB less of the nominal resistance at full scale in addition to
the wiper resistance.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance (RWA). When
these terminals are used, the B terminal can be opened. Setting
the resistance value for RWA starts at a maximum value of
resistance and decreases as the data loaded in the latch increases
in value. The general equation for this operation is
A
256 − D
256
R
WA (D) =
×RAB + RW
(2)
RS
For RAB = 10 kΩ and the B terminal is open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
D7
D6
D5
D4
D3
D2
D1
D0
RS
RS
Table 8. Codes and Corresponding RWA Resistance
W
D (Dec.)
RWA (Ω)
Output State
Full Scale
Midscale
1 LSB
255
128
1
99
RDAC
5060
9961
10,060
LATCH
RS
AND
B
DECODER
0
Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to 30ꢀ. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Figure 39. Equivalent RDAC Circuit
Rev. B | Page 14 of 16
AD5160
PROGRAMMING THE POTENTIOMETER DIVIDER
ESD PROTECTION
Voltage Output Operation
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures are shown in Figure 40 and
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
CS
Figure 41. This applies to SDI, CLK, and , which are the
digital input pins.
340Ω
LOGIC
GND
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by
the 256 positions of the potentiometer divider. The general
equation defining the output voltage at VW with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B is
Figure 40. ESD Protection of Digital Pins
A,B,W
GND
Figure 41. ESD Protection of Resistor Terminals
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals, it is important to power VDD/GND
before applying any voltage to the A, B, and W terminals;
otherwise, the diode forward biases such that VDD is powered
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD,
digital inputs, and then VA/B/W. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
they are powered after VDD/GND.
D
256
256 − D
256
VW (D) =
VA
+
VB
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as
R
WB (D)
256
R
WA (D)
256
VW (D) =
VA
+
VB
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors (RWA and RWB) and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. Keep the leads to the inputs as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Bypass supply
leads to the device with disc or chip ceramic capacitors of
0.01 μF to 0.1 μF. To minimize any transient disturbance and
low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors at the supplies (see Figure 42). To
minimize the ground bounce, join the digital ground remotely
to the analog ground at a single point.
SPI-COMPATIBLE 3-WIRE SERIAL BUS
The AD5160 contains a 3-wire SPI-compatible digital interface
CS
(SDI, , and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 6.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
CS
flip-flop or other suitable means. When
is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 37).
V
V
DD
DD
+
C3
C1
10μF
0.1μF
AD5160
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
GND
CS
internal RDAC register when the
Extra MSB bits are ignored.
line returns to logic high.
Figure 42. Power Supply Bypassing
Rev. B | Page 15 of 16
AD5160
OUTLINE DIMENSIONS
3.00
2.90
2.80
8
1
7
6
3
5
4
3.00
2.80
2.60
1.70
1.60
1.50
2
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
0.22 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.60
0.45
0.30
0.15 MAX
0.05 MIN
8°
4°
0°
SEATING
PLANE
0.60
BSC
0.38 MAX
0.22 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 43. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
RAB (Ω)
5 k
5 k
10 k
10 k
50 k
50 k
100 k
100 k
Temperature
Package Description
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
Evaluation Board
Package Option
Branding
D6Q
D6Q
D09
D09
D8J
D8J
D0B
D0B
AD5160BRJZ5-R22
AD5160BRJZ5-RL72
AD5160BRJZ10-R22
AD5160BRJZ10-RL72
AD5160BRJZ50-R22
AD5160BRJZ50-RL72
AD5160BRJZ100-R22
AD5160BRJZ100-RL72
AD5160EVAL3
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
1 The AD5160 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
2 Z = RoHS Compliant Part.
3 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03434-0-5/09(B)
Rev. B | Page 16 of 16
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