AD5165 [ADI]
256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer; 256位，超低功耗1.8 V逻辑电平数字电位计
| 型号： | AD5165 |
| 厂家： | 
ADI |
| 描述： | 256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer |
| 文件： | 总16页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256-Position, Ultralow Power
1.8 V Logic-Level Digital Potentiometer
AD5165
FEATURES
Ultralow standby power IDD = 50 nA typical
FUNCTIONAL BLOCK DIAGRAM
V
DD
256-position
End-to-end resistance 100 kΩ
Logic high voltage 1.8 V
Power supply 2.7 V to 5.5 V
Low temperature coefficient 35 ppm/°C
Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package
Simple 3-wire digital interface
A
CS
3-WIRE
INTERFACE
SDI
W
B
CLK
WIPER
REGISTER
Wide operating temperature −40°C to +125°C
Pin-to-pin compatible to AD5160 with CS inverted
GND
APPLICATIONS
Figure 1.
Battery-operated electronics adjustment
Remote utilities meter adjustment
Mechanical potentiometer replacement
Transducer circuit adjustment
Automotive electronics adjustment
Gain control and offset adjustment
System calibration
PIN CONFIGURATION
1
2
3
4
W
8
7
6
5
A
V
AD5165
TOP VIEW
(Not to Scale)
B
DD
CS
GND
CLK
SDI
VCXO adjustment
Figure 2.
GENERAL OVERVIEW
The AD5165 provides a compact 2.9 mm × 2.8 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance. The AD5165’s supply voltage requirement is 2.7 V
to 5.5 V, but its logic voltage requirement is 1.8 V to VDD. The
AD5165 consumes very low quiescent power during standby
mode and is ideal for battery-operated applications.
TYPICAL APPLICATION
5V
V
= 1.8V MIN
OH
V
DD
3.3V
V
A
AD5165
WIDE TERMINAL
V
W
VOLTAGE RANGE:
DIGITAL
CONTROL
LOGIC OR
MICRO
CS
V
B
0V < V ,V ,V < 5V
A B W
CLK
SDI
Wiper settings are controlled through a simple 3-wire interface.
The interface is similar to the SPI® digital interface except for the
inverted chip-select function that minimizes logic power con-
sumption in the idling state. The resistance between the wiper
and either endpoint of the fixed resistor varies linearly with
respect to the digital code transferred into the wiper register.
GND
Figure 3.
Note:
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 50 nA typical standby power allows use in battery-
operated portable or remote utility device applications.
The terms digital potentiometer, RDAC, and VR are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5165
TABLE OF CONTENTS
3-Wire Serial Bus Digital Interface .......................................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Evaluation Board........................................................................ 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Electrical Characteristics—100 kΩ Version .................................. 3
Absolute Maximum Ratings............................................................ 5
Pin Configuration and Functional Descriptions.......................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 11
3-Wire Digital Interface................................................................. 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor ......................................... 13
Programming the Potentiometer Divider............................... 14
REVISION HISTORY
4/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD5165
ELECTRICAL CHARACTERISTICS—100 kΩ VERSION
VDD = 5 V 10ꢀ, or 3 V 10ꢀ% VA = VDD% VB = 0 V% –40°C < TA < +125°C% unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB/RAB
(∆RAB/RAB)/∆Tx106
RW
RWB, VA = no connect
RWB, VA = no connect
TA = 2ꢀ°C
−1
−2
−20
0.1
0.2ꢀ
+1
+2
+20
LSB
LSB
%
ppm/°C
Ω
V
AB = VDD, wiper = no connect
3ꢀ
8ꢀ/ꢀ0
VDD = 2.7 V/ꢀ.ꢀ V
1ꢀ0/120
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
DNL
INL
(∆VW/VW )/∆Tx106
−1
−1
0.1
0.3
1ꢀ
+1
+1
LSB
LSB
ppm/°C
Code = 0x80
Coefficient
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−0.ꢀ
0
−0.3
0.1
0
0.ꢀ
LSB
LSB
RESISTOR TERMINALS
Voltage Rangeꢀ
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
90
9ꢀ
1
Capacitance6 W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VA = VB = VDD/2
nA
VIH
VIL
CIL
VDD = 2.7 V to ꢀ.ꢀ V
VDD = 2.7 V to ꢀ.ꢀ V
1.8
2.7
V
V
pF
Input Logic Low
Input Capacitance6
0.6
ꢀ
POWER SUPPLIES
Power Supply Range
Supply Current
VDD RANGE
IDD
ꢀ.ꢀ
1
V
Digital inputs = 0 V or VDD
0.0ꢀ
10
ꢀ00
µA
µA
µA
µW
%/%
VDD = 2.7 V, digital inputs = 1.8 V
VDD = ꢀ V, digital inputs = 1.8 V
Digital inputs = 0 V or VDD
VDD = +ꢀ V 10%,
Code = Midscale
Power Dissipation7
Power Supply Sensitivity
PDISS
PSS
ꢀ.ꢀ
0.00ꢀ
0.001
DYNAMIC CHARACTERISTICS6, 8
Bandwidth −3 dB
BW
THDW
tS
Code = 0x80
VA =1 V rms, VB = 0 V, f = 1 kHz,
VA = ꢀ V, VB = 0 V,
1 LSB error band
ꢀꢀ
0.0ꢀ
2
kHz
%
µs
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
eN_WB
RWB = ꢀ0 kΩ
28
nV/√Hz
1 Typical specifications represent average readings at +2ꢀ°C and VDD = ꢀ V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
ꢀ Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = ꢀ V.
Rev. 0 | Page 3 of 16
AD5165
TIMING CHARACTERISTICS—100 kΩ VERSION
VDD = +5 V 10ꢀ, or +3 V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
3-WIRE INTERFACE TIMING CHARACTERISTICS2, 3, 4 (specifications apply to all parts)
Clock Frequency
Input Clock Pulse Width
Data Setup Time
fCLK= 1/( tCH+ tCL)
tCH, tCL
tDS
2ꢀ
MHz
ns
ns
Clock level high or low
20
ꢀ
Data Hold Time
tDH
ꢀ
ns
CS Setup Time
tCSS
1ꢀ
40
0
0
10
ns
ns
ns
ns
CS Low Pulse Width
CLK Fall to CS Rise Hold Time
CLK Fall to CS Fall Hold Time
CS Fall to Clock Rise Setup
tCSW
tCSH0
tCSH1
tCS1
ns
1 Typical specifications represent average readings at +2ꢀ°C and VDD = ꢀ V.
2 Guaranteed by design and not subject to production test.
3 All dynamic characteristics use VDD = ꢀ V.
4 See Figure 34 and Figure 3ꢀ for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.ꢀ V.
Rev. 0 | Page 4 of 16
AD5165
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.1, 2
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only% functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Value
VDD to GND
VA, VB, VW to GND
Maximum Current
–0.3 V to +7 V
VDD
I
WB, IWA Pulsed
20 mA
IWB Continuous (RWB ≤ 1 kΩ, A open)2
IWA Continuous (RWA ≤ 1 kΩ, B open)2
Digital Inputs and Output Voltage to GND
Operating Temperature Range
ꢀ mA
ꢀ mA
0 V to +7 V
–40°C to +12ꢀ°C
1ꢀ0°C
Maximum Junction Temperature (TJMAX
)
Storage Temperature
Lead Temperature (Soldering, 10 – 30 sec)
Thermal Resistance2 θJA: TSOT-8
–6ꢀ°C to +1ꢀ0°C
24ꢀ°C
200°C/W
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX − TA)/θJA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢀ of 16
AD5165
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
1
2
3
4
W
8
7
6
5
A
V
AD5165
TOP VIEW
(Not to Scale)
B
DD
CS
GND
CLK
SDI
Figure 4.
Table 4.
Pin
Name
Description
1
2
3
4
ꢀ
6
7
W
Wiper terminal. GND ≤ VA ≤ VDD.
Positive Power Supply.
Digital Ground.
Serial Clock Input. Positive-edge triggered.
Serial Data Input (data loads MSB first).
VDD
GND
CLK
SDI
CS
Chip Select Input, active high. When CS returns low, data is loaded into the wiper register.
B terminal. GND ≤ VA ≤ VDD.
B
8
A
A terminal. GND ≤ VA ≤ VDD.
Rev. 0 | Page 6 of 16
AD5165
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.5
0.4
–40°C
+25°C
+85°C
+125°C
5.5V
2.7V
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
0
0
32
64
96
128
160
192
224
256
256
256
0
0
0
32
64
96
128
160
192
224
256
256
256
CODE (Decimal)
CODE (Decimal)
Figure 5. R-INL vs. Code vs. Supply Voltages
Figure 8. DNL vs. Code vs. Temperature, VDD = 5 V
0.5
0.4
0.5
0.4
5.5V
2.7V
5.5V
2.7V
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
32
64
96
128
160
192
224
32
64
96
128
160
192
224
CODE (Decimal)
CODE (Decimal)
Figure 6. R-DNL vs. Code vs. Supply Voltages
Figure 9. INL vs. Code vs. Supply Voltages
0.5
0.4
0.5
0.4
5.5V
2.7V
–40°C
+25°C
+85°C
+125°C
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
32
64
96
128
160
192
224
32
64
96
128
160
192
224
CODE (Decimal)
CODE (Decimal)
Figure 7. INL vs. Code vs. Temperature , VDD = 5 V
Figure 10. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 7 of 16
AD5165
0.5
0.4
0.5
0.4
–40°C
+25°C
+85°C
+125°C
0.3
0.3
0.2
0.2
ZSE @ V = 5.5V
DD
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
–0.5
ZSE @ V = 2.7V
DD
–0.5
0
32
64
96
128
160
192
224
256
–40
–20
0
20
40
60
80
100
120
CODE (Decimal)
TEMPERATURE (°C)
Figure 11. R-INL vs. Code vs. Temperature, VDD = 5 V
Figure 14. Zero-Scale Error vs. Temperature
0.5
0.4
0.5
0.4
–40°C
+25°C
+85°C
+125°C
0.3
0.3
0.2
0.2
I
@ V = 5.5V
DD
DD
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
I
@ V = 2.7V
DD
DD
0
32
64
96
128
160
192
224
256
–40
–20
0
20
40
60
80
100
120
CODE (Decimal)
TEMPERATURE (°C)
Figure 12. R-DNL vs. Code vs. Temperature, VDD = 5 V
Figure 15. Supply Current vs. Temperature
0.5
0.4
10000
1000
100
10
0.3
0.2
FSE @ V = 5.5V
DD
0.1
V
= V = 5V
A
DD
0
V
= V = 2.7V
A
DD
–0.1
–0.2
–0.3
–0.4
–0.5
FSE @ V = 2.7V
DD
1
0.1
0.01
–40
–20
0
20
40
60
80
100
120
0
1
2
3
4
5
TEMPERATURE (°C)
V
(0) (V)
IH
Figure 13. Full-Scale Error vs. Temperature
Figure 16. Supply Current vs. Digital Input Voltage
Rev. 0 | Page 8 of 16
AD5165
1000
100
10
REF LEVEL
0.000dB
0
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
0x80
–6
V
= V = 5V
A
DD
0x40
0x20
–12
V
= V = 2.7V
A
DD
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x02
0x01
1
0.1
0.01
0
1
2
3
4
5
V
(1MHz) (V)
IH
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 17. Supply Current vs. Digital Input Voltage
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
REF LEVEL
–5.000dB
/DIV
0.500dB
20
15
–5.5
100kΩ – 54kHz
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–10.5
10
5
0
–5
–10
–15
–20
R = 100kΩ
0
32
64
96
128
160
192
224
256
CODE (Decimal)
10k
10M
STOP 1 000 000.000Hz
START 1 000.000Hz
Figure 21. –3 dB Bandwidth @ Code = 0x80
Figure 18. Rheostat Mode Tempco ∆RWB/∆T vs. Code
80
8
6
CODE = 80 , V = V , V = 0V
DD
H
A
B
60
40
20
0
4
PSRR @ V = 5V DC ± 10% p-p AC
DD
PSRR @ V = 3V DC ± 10% p-p AC
DD
2
0
–2
–4
–6
–8
100
1k
10k
100k
1M
0
32
64
96
128
160
192
224
256
FREQUENCY (Hz)
CODE (Decimal)
Figure 22. PSRR vs. Frequency
Figure 19. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Rev. 0 | Page 9 of 16
AD5165
800
700
600
500
400
300
200
100
V
= 5V
V
V
= 5V
= 0V
DD
A
B
1
2
VW
CS
CODE 55
H
H
Ch 1 100mV
B
Ch 2 5.00 V
B
M 200ns A CH1 152mV
W
W
CODE FF
Figure 26. Midscale Glitch, Code 0x80–0x7F
0
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 23. IDD vs. Frequency
1
2
VW
CS
Ch 1 200mV
B
Ch 2 5.00 V
B
M 100ns A CH2 3.00 V
W
W
Figure 24. Large Signal Settling Time, Code 0xFF–0x00
1
VW
CLK
2
Ch 1 200mV
B
Ch 2 5.00 V
B
M 100ns A CH2 3.00 V
W
W
Figure 25. Digital Feedthrough
Rev. 0 | Page 10 of 16
AD5165
TEST CIRCUITS
Figure 27 to Figure 33 illustrate the test circuits that define the test conditions used in the product specification tables.
V+ = V
DUT
W
DUT
W
DD
1LSB = V+/2
+15V
N
A
B
A
B
V
IN
V+
AD8610
–15V
V
OUT
OFFSET
GND
V
MS
2.5V
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
Figure 31. Test Circuit for Gain vs. Frequency
0.1V
NO CONNECT
DUT
R
=
SW
I
SW
CODE = 0x00
DUT
I
W
A
W
W
B
0.1V
I
SW
B
V
MS
GND TO V
DD
Figure 32. Test Circuit for Incremental ON Resistance
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
NC
DUT
I
= V /R
DD NOMINAL
W
A
B
DUT
V
W
W
A
B
I
CM
V
MS2
V
DD
W
R
= [V
– V ]/I
MS2
W
MS1
W
GND
V
MS1
V
CM
NC NC = NO CONNECT
Figure 33. Test Circuit for Common-Mode Leakage Current
Figure 29. Test Circuit for Wiper Resistance
V
A
V+ = V
10%
PSRR (dB) = 20 LOG
DD
∆
V
MS
DD
(
)
∆V
V
DD
A
B
%
%
∆V
MS
DD
W
V+
PSS (%/%) =
∆V
V
MS
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Rev. 0 | Page 11 of 16
AD5165
3-WIRE DIGITAL INTERFACE
Note that in the AD5165 data is loaded MSB first.
Table 5. AD5165 Serial Data-Word Format
B7
D7
MSB
27
B6
B5
B4
B3
B2
B1
B0
D0
LSB
20
D6
Dꢀ
D4
D3
D2
D1
1
0
1
D7 D6
D5 D4 D3 D2
D1 D0
SDI
CLK
CS
0
1
RDAC REGISTER LOAD
0
1
0
VOUT
Figure 34. 3-Wire Digital Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT
)
1
0
1
SDI
(DATA IN)
Dx
Dx
tDS
tDH
tCS1
tCH
CLK
0
tCSH1
tCL
tCSHO
tCSS
1
0
CS
tCSW
tS
V
DD
0
VOUT
±1LSB
Figure 35. 3-Wire Digital Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT
)
Rev. 0 | Page 12 of 16
AD5165
THEORY OF OPERATION
The AD5165 is a 256-position digitally controlled variable
resistor (VR) device.
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
AB is the end-to-end resistance.
W is the wiper resistance contributed by the on resistance of
the internal switch.
PROGRAMMING THE VARIABLE RESISTOR
R
R
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 100 kΩ. The nominal resistance (RAB) of the VR
has 256 contact points accessed by the wiper terminal, plus the
B terminal contact. The 8-bit data in the RDAC latch is decoded
to select one of the 256 possible settings.
In summary, if RAB = 100 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 6. Codes and Corresponding RWB Resistance
A
A
A
D (Dec.)
RWB (Ω)
99,710
ꢀ0,100
490
Output State
W
W
W
2ꢀꢀ
128
1
Full scale (RAB – 1 LSB + RW)
Midscale
1 LSB
B
B
B
0
100
Zero scale (wiper contact resistance)
Figure 36. Rheostat Mode Configuration
Note that, in the zero-scale condition, a finite wiper resistance
of 100 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Assuming that a 100 kΩ part is used, the wiper’s first connec-
tion starts at the B terminal for data 0x00. Because there is a
50 Ω wiper contact resistance, such a connection yields a mini-
mum of 100 Ω (2 × 50 Ω) resistance between terminals W and
B. The second connection is the first tap point, which corres-
ponds to 490 Ω (RWB = RAB/256 + 2 × RW = 390 Ω + 2 × 50 Ω)
for data 0x01. The third connection is the next tap point,
representing 880 Ω (2 × 390 Ω + 2 × 50 Ω) for data 0x02, and
so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 100,100 Ω
(RAB + 2 × RW).
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
A
R
S
256 − D
256
RWA(D) =
× RAB + 2× RW
(2)
R
R
D7
D6
D5
D4
D3
D2
D1
D0
S
For RAB = 100 kΩ with the B terminal open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
S
W
Table 7. Codes and Corresponding RWA Resistance
D (Dec.)
RWA (Ω)
Output State
Full scale
Midscale
1 LSB
2ꢀꢀ
128
1
490
ꢀ0,100
99, 710
100,100
R
RDAC
S
LATCH
AND
DECODER
B
0
Zero scale
Typical device-to-device matching is process-lot dependent
and may vary by up to 20ꢀ. Because the resistance element
is processed in thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
Figure 37. AD5165 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
D
256
RWB (D) =
× RAB + 2× RW
(1)
Rev. 0 | Page 13 of 16
AD5165
The data setup and data hold times in the specifications table
determine the valid timing requirements. The AD5165 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic low.
Extra MSB bits are ignored.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDI, CLK,
and CS.
V
I
A
W
V
O
340Ω
B
LOGIC
Figure 38. Potentiometer Mode Configuration
GND
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminals A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to terminals A and B is
Figure 39. ESD Protection of Digital Pins
A, B, W
GND
Figure 40. ESD Protection of Resistor Terminals
D
256
256 − D
256
VW (D) =
VA +
VB
(3)
TERMINAL VOLTAGE OPERATING RANGE
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
The AD5165 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Supply signals present on terminals A, B, and W that
exceed VDD or GND are clamped by the internal forward-biased
diodes, as shown in Figure 41.
R
WB (D)
RAB
RWA(D)
RAB
(4)
VW (D) =
VA +
VB
V
DD
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
A
W
B
GND
3-WIRE SERIAL BUS DIGITAL INTERFACE
Figure 41. Maximum Terminal Voltages Set by VDD and GND
The AD5165 contains a 3-wire digital interface (SDI, CS, and
CLK). The 8-bit serial word must be loaded MSB first. The
format of the word is shown in Table 5.
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power VDD/GND before applying any voltage to terminals A, B,
and W% otherwise, the diode is forward biased such that VDD is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, and VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is high, the clock
loads data into the serial register on each positive clock edge,
as shown in Figure 34.
Rev. 0 | Page 14 of 16
AD5165
EVALUATION BOARD
LAYOUT AND POWER SUPPLY BYPASSING
An evaluation board, along with all necessary software, is
available to program the AD5165 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 43, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disk or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
V
V
DD
DD
+
C3
10
C1
0.1µF
Figure 43. AD5165 Evaluation Board Software
µ
F
AD5165
The AD5165 starts at midscale upon power-up. To increment
or decrement the resistance, the user may move the scroll bars
on the left. To write any specific value, the user should use the
bit pattern in the upper screen and click the Run button. The
format of writing data to the device is shown in Figure 32.
GND
Figure 42. Power Supply Bypassing
Rev. 0 | Page 1ꢀ of 16
AD5165
OUTLINE DIMENSIONS
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
0.90
0.87
0.84
1.00 MAX
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.10 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-193BA
Figure 44. 8-Lead Thin Small Outline Transistor Package [Thin SOT-23]
(UJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5165BUJZ100-R21
AD5165BUJZ100-R71
AD5165EVAL
RAB (Ω)
100 k
Temperature
Package Description
Thin SOT-23
Package Option
Quantity on Reel
Branding
D3N
–40°C to +125°C
–40°C to +125°C
UJ-8
UJ-8
250
100 k
Thin SOT-23
3,000
D3N
Evaluation Board
1 Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04749–0–4/04(0)
Rev. 0 | Page 16 of 16
相关型号：
AD5170BRM10-R2
IC 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.9 MM, MO-187BA, MSOP-10, Digital Potentiometer
ADI
©2020 ICPDF网 联系我们和版权申明