AD5201BRMZ10 [ADI]
256-Position and 33-Position Digital Potentiometers; 256位和33位的数字电位器
| 型号： | AD5201BRMZ10 |
| 厂家： | 
ADI |
| 描述： | 256-Position and 33-Position Digital Potentiometers |
| 文件： | 总15页 (文件大小：1043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256-Position and 33-Position
Digital Potentiometers
a
AD5200/AD5201
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AD5200—256-Position
AD5201—33-Position
10 kꢀ, 50 kꢀ
AD5200/AD5201
V
V
SS
DD
A
3-Wire SPI-Compatible Serial Data Input
Single Supply 2.7 V to 5.5 V or
Dual Supply ꢁ2.7 V for AC or Bipolar Operations
Internal Power-On Midscale Preset
CS
W
B
CLK
SER
REG
8/6 RDAC
REG
SDI
Dx
APPLICATIONS
SHDN
GND
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
PWR-ON
PRESET
GENERAL DESCRIPTION
has a nominal temperature coefficient of 500 ppm/°C. The VR
has a VR latch that holds its programmed resistance value. The
VR latch is updated from an SPI-compatible serial-to-parallel
shift register that is loaded from a standard 3-wire serial-input
digital interface. Eight data bits for the AD5200 and six data
bits for the AD5201 make up the data word that is clocked into
the serial input register. The internal preset forces the wiper to
the midscale position by loading 80H and 10H into AD5200 and
AD5201 VR latches respectively. The SHDN pin forces the
resistor to an end-to-end open-circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When SHDN is returned to logic high,
the previous latch setting puts the wiper in the same resistance
setting prior to shutdown. The digital interface is still active dur-
ing shutdown so that code changes can be made that will produce
a new wiper position when the device is returned from shutdown.
The AD5200 and AD5201 are programmable resistor devices,
with 256 positions and 33 positions respectively, that can be digi-
tally controlled through a 3-wire SPI serial interface. The terms
programmable resistor, variable resistor (VR), and RDAC are
commonly used interchangeably to refer to digital potentiometers.
These devices perform the same electronic adjustment function
as a potentiometer or variable resistor. Both AD5200/AD5201
contain a single variable resistor in the compact
MSOP
package. Each device contains a fixed wiper resistance at the
wiper contact that taps the programmable resistance at a point
determined by a digital code. The code is loaded in the serial
input register. The resistance between the wiper and either end
point of the programmable resistor varies linearly with respect to
the digital code transferred into the VR latch. Each variable
resistor offers a completely programmable value of resistance,
between the A terminal and the wiper, or the B terminal and the
wiper. The fixed A-to-B terminal resistance of 10 kΩ or 50 kΩ
All parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
781/461-3113
www.analog.com
2012
© Analog Devices, Inc.,
Fax:
AD5200/AD5201–SPECIFICATIONS
(VDD = 5 V ꢁ 10%, or 3 V ꢁ 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
–40ꢂC < T < +85ꢂC unless otherwise noted.)
AD5200 ELECTRICAL CHARACTERISTICS
A
Parameter
Symbol
Conditions
Min Typ1 Max
Unit
DCCHARACTERISTICSRHEOSTATMODE
2
ResistorDifferentialNonlinearity
R-DNL
R-INL
∆RAB
RWB, VA = No Connect
RWB, VA = No Connect
TA = 25°C
–1
–2
–30
0.25 +1
0.5 +2
LSB
LSB
%
2
ResistorIntegralNonlinearity
3
NominalResistorTolerance
+30
ResistanceTemperatureCoefficient
WiperResistance
R
RW
AB/∆T
VAB = VDD, Wiper = No Connect
VDD = 5 V
500
50
ppm/°C
Ω
100
DCCHARACTERISTICSPOTENTIOMETERDIVIDERMODE(SpecificationsapplytoallVRs.)
Resolution
DifferentialNonlinearity
IntegralNonlinearity
N
DNL
INL
8
–1
–2
Bits
LSB
LSB
4
1/4 +1
1/2 +2
4
VoltageDividerTemperatureCoefficient
Full-ScaleError
Zero-ScaleError
∆VW/∆T
VWFSE
VWZSE
Code = 80 H
Code = FF H
Code = 00 H
5
ppm/°C
LSB
LSB
–1.5 –0.5
0
0
+0.5 +1.5
RESISTORTERMINALS
VoltageRange 5
VA, B, W
CA, B
CW
IDD_SD
ICM
VSS
VDD
V
Capacitance 6 A,B
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
VDD = 5.5 V
45
60
0.01
1
pF
pF
µA
nA
H
H
Capacitance 6 W
ShutdownSupplyCurrent
Common-ModeLeakage
7
5
VA = VB = VDD/2
DIGITALINPUTSANDOUTPUTS
InputLogicHigh
InputLogicLow
InputLogicHigh
InputLogicLow
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
0.8
VDD = 3 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VIN = 0 V or 5 V
0.6
1
InputCurrent
InputCapacitance
6
CIL
5
POWERSUPPLIES
LogicSupply
VLOGIC
VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
2.7
–0.3
2.3
5.5
5.5
2.7
40
40
0.2
V
V
V
µA
µA
mW
PowerSingle-SupplyRange
PowerDual-SupplyRange
PositiveSupplyCurrent
NegativeSupplyCurrent
PowerDissipation 8
VSS = 0 V
VIH = +5 V or VIL = 0 V
VSS = –5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V
15
15
PowerSupplySensitivity
PSS
∆VDD = +5 V 10%, Code = Midscale
–0.01 0.001 +0.01 %/%
6,9
DYNAMICCHARACTERISTICS
Bandwidth–3dB
BW_10 kΩ
BW_50 kΩ
THDW
tS
RAB = 10 kΩ, Code = 80 H
RAB = 50 kΩ, Code = 80 H
VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ
VA = 5 V, VB = 0 V, 1 LSB Error Band
RWB = 5 kΩ, RS = 0
600
100
0.003
2/9
kHz
kHz
%
µs
nV√Hz
TotalHarmonicDistortion
VW Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
eN_WB
9
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,
VSS = –2.7 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the A terminal. A terminal is open-circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 5 V, VSS = 0 V.
Specifications subject to change without notice.
REV. D
–2–
AD5200/AD5201
(VDD = 5 V ꢁ 10%, or 3 V ꢁ 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
–40ꢂC < T < +85ꢂC unless otherwise noted.)
AD5201 ELECTRICAL CHARACTERISTICS
A
Parameter
Symbol
Conditions
Min Typ1 Max
Unit
DCCHARACTERISTICSRHEOSTATMODE
2
ResistorDifferentialNonlinearity
R-DNL
R-INL
∆RAB
RWB, VA = No Connect
RWB, VA = No Connect
TA = 25°C
–0.5
–1
–30
0.05 +0.5
0.1 +1
+30
LSB
LSB
%
2
ResistorIntegralNonlinearity
3
NominalResistorTolerance
ResistanceTemperatureCoefficient
WiperResistance
R
RW
AB/∆T
VAB = VDD, Wiper = No Connect
VDD = 5 V
500
50
ppm/°C
Ω
100
DCCHARACTERISTICSPOTENTIOMETERDIVIDERMODE(SpecificationsapplytoallVRs.)
Resolution4
DifferentialNonlinearity
IntegralNonlinearity
N
DNL
INL
6
–0.5
–1
Bits
LSB
LSB
5
0.01 +0.5
0.02 +1
5
VoltageDividerTemperatureCoefficient
Full-ScaleError
Zero-ScaleError
∆VW/∆T
VWFSE
VWZSE
Code = 10 H
Code = 20 H
Code = 00 H
5
ppm/°C
LSB
LSB
–1/2 –1/4
0
0
+1/4 +1/2
RESISTORTERMINALS
VoltageRange 6
VA, B, W
CA, B
CW
IDD_SD
ICM
VSS
VDD
V
Capacitance 7 A,B
f = 1 MHz, Measured to GND, Code = 10
f = 1 MHz, Measured to GND, Code = 10
VDD = 5.5 V
45
60
0.01
1
pF
pF
µA
nA
H
H
Capacitance 7 W
ShutdownSupplyCurrent
Common-ModeLeakage
8
5
VA = VB = VDD/2
DIGITALINPUTSANDOUTPUTS
InputLogicHigh
InputLogicLow
InputLogicHigh
InputLogicLow
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
0.8
VDD = 3 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VIN = 0 V or 5 V
0.6
1
InputCurrent
InputCapacitance
7
CIL
5
POWERSUPPLIES
LogicSupply
VLOGIC
VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
2.7
–0.3
2.3
5.5
5.5
2.7
40
40
0.2
V
V
V
µA
µA
mW
PowerSingle-SupplyRange
PowerDual-SupplyRange
PositiveSupplyCurrent
NegativeSupplyCurrent
PowerDissipation 9
VSS = 0 V
VIH = +5 V or VIL = 0 V
VSS = –5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V
15
15
PowerSupplySensitivity
PSS
∆VDD = +5 V 10%
–0.01 0.001 +0.01 %/%
7,10
DYNAMICCHARACTERISTICS
Bandwidth–3dB
BW_10 kΩ
BW_50 kΩ
THDW
tS
RAB = 10 kΩ, Code = 10 H
RAB = 50 kΩ, Code = 10 H
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ
VA = 5 V, VB = 0 V, 1 LSB Error Band
RWB = 5 kΩ, RS = 0
600
100
0.003
2/9
kHz
kHz
%
µs
nV√Hz
TotalHarmonicDistortion
VW Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
eN_WB
9
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,
VSS = –2.7 V.
3 VAB = VDD, Wiper (VW) = No connect.
4 Six bits are needed for 33 positions even though it is not a 64-position device.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions.
6 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
7 Guaranteed by design and not subject to production test.
8 Measured at the A terminal. A terminal is open-circuited in shutdown mode.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V, VSS = 0 V.
Specifications subject to change without notice.
REV. D
–3–
AD5200/AD5201–SPECIFICATIONS
(VDD = 5 V ꢁ 10%, or 3 V ꢁ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40ꢂC < TA < +85ꢂC
unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS Setup Time
t
tDS
tDH
tCSS
tCSW
tCSH0
tCSH1
tCS1
CH, tCL
Clock Level High or Low
20
5
5
15
40
0
ns
ns
ns
ns
ns
ns
ns
ns
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
0
10
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2Guaranteed by design and not subject to production test.
3See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using VLOGIC = 5 V.
Specifications subject to change without notice.
1
SDI
D7
D6
D5
D4
D3
D2
D1
D0
0
1
CLK
0
1
DAC REGISTER LOAD
CS
0
1
VOUT
0
Figure 1a. AD5200 Timing Diagram
1
SDI
D5
D4
D3
D2
D1
D0
0
1
CLK
0
1
DAC REGISTER LOAD
CS
0
1
VOUT
0
Figure 1b. AD5201 Timing Diagram
1
SDI
(DATA IN)
Dx
Dx
tDS
0
1
tDH
tCH
tCS1
CLK
0
1
0
tCSH0
tCL
tCSH1
tCSS
tCSW
tS
CS
V
DD
VOUT
0
ꢃ1LSB
Figure 1c. Detail Timing Diagram
–4–
AD5200/AD5201
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted)
Pin
Name
Description
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
1
2
B
VSS
B Terminal.
V
V
DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V
SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
Negative Power Supply, specified for opera-
tion from 0 V to –2.7 V.
Ground.
Chip Select Input, Active Low. When CS
returns high, data will be loaded into the
DAC register.
Serial Data Input.
Serial Clock Input, positive edge triggered.
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors of
RDAC to temporary infinite.
Positive Power Supply (Sum of VDD + VSS
≤ 5.5 V).
Wiper Terminal.
A Terminal.
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA2
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ Max) . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
3
4
GND
CS
5
6
7
SDI
CLK
SHDN
Thermal Resistance θ
. . . . . . . . . . . . . 200°C/W
JA, MSOP
Package Power Dissipation = (TJ Max – TA)/θJA
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
8
VDD
9
10
W
A
2Max current is bounded by the maximum current handling of the switches,
maximum power dissipation of the package, and maximum applied voltage across
any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31
and TPC 32 for detail.
PIN CONFIGURATION
1
2
3
4
5
10
9
B
A
W
V
V
SS
AD5200/
AD5201
TOP VIEW
(Not to Scale)
8
GND
DD
7
CS
SHDN
6
SDI
CLK
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–5–
AD5200/AD5201–Typical Performance Characteristics
0.20
0.15
0.10
0.05
0.12
0.10
0.08
V
= 2.7V, V = 0V
SS
DD
V
= 5.5V, V = 0V
SS
DD
V
V
= +2.7V
DD
SS
= –2.7V
0.06
0.04
0.00
ꢄ0.05
ꢄ0.10
0.02
0.00
V
= +2.7V, V = –2.7V
SS
DD
V
= 2.7V, V = 0V
DD
SS
ꢄ0.15
ꢄ0.20
V
= 5.5V, V = 0V
SS
DD
–0.02
0
32
64
96
128
160
192
224
256
0
4
8
12
16
20
24
28
32
CODE – Decimal
CODE – Decimal
TPC 1. AD5200 10 kΩ RDNL vs. Code
TPC 4. AD5201 10 kΩ RINL vs. Code
0.10
0.05
0.03
0.02
V
= 2.7V, V = 0V
SS
DD
V
= 5.5V, V = 0V
SS
DD
V
= 2.7V, V = 0V
SS
DD
0.00
0.01
0.00
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.01
–0.02
–0.03
V
= +2.7V, V = –2.7V
SS
DD
V
= 5.5V, V = 0V
SS
DD
V
= +2.7V, V = –2.7V
SS
DD
0
4
8
12
16
20
24
28
32
0
32
64
96
128
160
192
224
256
CODE – Decimal
CODE – Decimal
TPC 2. AD5201 10 kΩ RDNL vs. Code
TPC 5. AD5200 10 kΩ DNL vs. Code
0.020
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
0.015
0.010
V
= 2.7V, V = 0V
SS
DD
V
= 5.5V, V = 0V
SS
DD
V
= +2.7V, V = –2.7V
SS
DD
0.005
V
= 5.5V, V = 0V
SS
DD
0.000
–0.005
–0.010
V
= 2.7V, V = 0V
SS
V
= +2.7V, V = –2.7V
DD
DD
SS
0
4
8
12
16
20
24
28
32
0
32
64
96
128
160
192
224
256
CODE – Decimal
CODE – Decimal
TPC 6. AD5201 10 kΩ DNL vs. Code
TPC 3. AD5200 10 kΩ RINL vs. Code
REV. D
–6–
AD5200/AD5201
0.3
0.2
20
18
V
V
= V
SS
IL
= V
IH
DD
V = 5.5V
DD
V
= 5.5V, V = 0V
DD
SS
16
14
0.1
0.0
12
10
8
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 2.7V
DD
6
4
2
0
V
= +2.7V, V = –2.7V
SS
DD
V
= 2.7V, V = 0V
SS
DD
0
32
64
96
128
160
192
224
256
–40
–20
0
20
40
60
80
100
CODE – Decimal
TEMPERATURE – ꢂC
TPC 7. AD5200 10 kΩ INL vs. Code
TPC 10. Supply Current vs. Temperature
0.020
0.015
0.010
0.005
0.000
14
V
= +2.7V, V = –2.7V
SS
V
= 5.5V
DD
DD
12
10
8
V
= 5.5V, V = 0V
SS
DD
6
4
2
–0.005
–0.010
0
V
= 2.7V, V = 0V
SS
DD
–
2
–40
0
4
8
12
16
20
24
28
32
–20
0
20
40
60
80
100
CODE – Decimal
TEMPERATURE – ꢂC
TPC 8. AD5201 10 kΩ INL vs. Code
TPC 11. Shutdown Current vs. Temperature
160
10
1.0
SEE TEST CIRCUIT 13
A
I
@ V /V = 5V/0V
T = 25ꢂC
DD
DD SS
140
120
V
= 2.7V
DD
I
@ V /V = ꢁ2.5V
DD SS
DD
100
80
0.1
60
40
V
= 5.5V
DD
I
@ V /V = ꢁ2.5V
DD SS
SS
0.01
0.001
I
@ V /V = 3V/0V
DD SS
DD
20
0
0
1
2
3
4
5
6
0.0
1.0
2.0
3.0
4.0
5.0
V
– V
V
– V
SUPPLY
IH
TPC 12. Wiper ON Resistance vs. V SUPPLY
TPC 9. Supply Current vs. Logic Input Voltage
REV. D
–7–
AD5200/AD5201
6
0
500
450
400
350
300
CODE FF
H
80
H
H
H
H
H
–6
–12
–18
40
20
10
08
–24
–30
–36
–42
–48
–54
250
200
150
100
I
@ V /V
= ꢁ2.5V
= ꢁ2.5V
SS
DD SS
I
@ V /V
04
DD
DD SS
H
H
02
01
I
@ V /V = 5V/0V
DD SS
DD
H
I
@ V /V = 3V/0V
DD SS
DD
50
0
1M
1k
10k
100k
1M
10M
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 13. AD5200 10 kΩ Supply Current vs. Clock Frequency
TPC 16. AD5200 10 kΩ Gain vs. Frequency vs. Code
500
6
0
CODE 55
H
450
400
80
40
20
10
H
H
H
H
–6
–12
–18
350
300
I
@ V /V
DD SS
= ꢁ2.5V
= ꢁ2.5V
SS
250
200
150
–24
–30
–36
–42
–48
–54
I
@ V /V
DD SS
DD
08
04
H
H
I
@ V /V = 5V/0V
DD SS
DD
02
01
H
100
50
I
@ V /V = 3V/0V
DD SS
DD
H
0
1M
10M
1M
10k
100k
FREQUENCY – Hz
1k
10k
100k
FREQUENCY – Hz
TPC 14. AD5200 10 kΩ Supply Current vs. Clock Frequency
TPC 17. AD5200 50 kΩ Gain vs. Frequency vs. Code
80
6
0
CODE = 80 , V = V , V = 0V
H
A
DD
B
10
H
+PSRR @ V
DD
= 5V DC ꢁ10% p-p AC
–6
–12
–18
60
40
20
0
8
4
2
H
H
H
–24
–30
–36
–42
–48
–54
+PSRR @ V
= 3V DC ꢁ10% p-p AC
= 3V DC ꢁ10% p-p AC
DD
1
H
–PSRR @ V
DD
100
1M
1k
10k
100k
1M
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 15. Power Supply Rejection Ratio vs. Frequency
TPC 18. AD5201 10 kΩ Gain vs. Frequency vs. Code
–8–
AD5200/AD5201
6
0
12
6
SEE TEST CIRCUIT 10
CODE = 80
H
10
V
= 5V
H
DD
= 25ꢂC
–6
–12
–18
0
T
A
10kꢀ
8
H
–6
4
50kꢀ
H
–12
2
H
–24
–30
–36
–42
–48
–54
–18
–24
–30
–36
–42
–48
1
H
1M
1k
10k
100k
10
100
1M
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 19. AD5201 50 kΩ Gain vs. Frequency vs. Code
TPC 22. Normalized Gain Flatness vs. Frequency
12
12
6
SEE TEST CIRCUIT 10
6
CODE = 10
H
V
= 5V
10kꢀ
DD
0
0
T = 25ꢂC
A
–6
–6
50kꢀ
10kꢀ
–12
–12
50kꢀ
–18
–24
–30
–36
–42
–48
–18
–24
–30
V
V
R
= 100mV rms
IN
–36
–42
–48
= 5V
DD
= 1Mꢀ
L
10
100
1M
1M
1k
10k
100k
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 23. AD5201 Normalized Gain Flatness vs. Frequency
TPC 20. AD5200 –3 dB Bandwidth
12
6
10kꢀ
0
–6
50kꢀ
V
W
–12
(20mV/DIV)
–18
–24
–30
–36
–42
–48
V
V
R
= 100mV rms
IN
CS
(5V/DIV)
= 5V
DD
= 1Mꢀ
L
1M
1k
10k
100k
FREQUENCY – Hz
TPC 21. AD5201 –3 dB Bandwidth
TPC 24. One Position Step Change at Half Scale
–9–
AD5200/AD5201
3500
3000
2500
OUTPUT
(2V/DIV)
2000
1500
1000
INPUT
(5V/DIV)
500
0
ꢄ500
0
32
64
96
128
160
192
224
256
CODE – Decimal
TPC 25. Large Signal Settling Time
TPC 28. AD5200 ∆RWB/∆T Rheostat Mode Temperature
Coefficient
3000
2500
2000
V
1500
1000
OUT
(20mV/DIV)
500
0
–500
0
4
8
12
16
20
24
28
32
CODE – Decimal
TPC 26. Digital Feedthrough vs. Time
TPC 29. AD5201 Potentiometer Mode Temperature
Coefficient
4000
3500
3000
2500
2000
50
40
30
20
1500
1000
10
0
500
0
–10
ꢄ500
0
32
64
96
128
160
192
224
256
–20
CODE – Decimal
0
4
8
12
16
20
24
28
32
CODE – Decimal
TPC 27. AD5200 ∆VWB/∆T Potentiometer Mode
Temperature Coefficient
TPC 30. AD5201 ∆VWB/∆T Potentiometer Mode Tempco
–10–
AD5200/AD5201
100.0
10.0
1.0
Table I. AD5200 Serial-Data Word Format
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
LSB
20
MSB
27
R
R
= 10kꢀ
AB
Table II. AD5201 Serial-Data Word Format
= 50kꢀ
AB
B5*
D5*
MSB
25
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
LSB
20
0.1
0
32
64
96
128
192
224
256
160
CODE – Decimal
TPC 31. AD5200 IMAX vs. Code
100.0
10.0
1.0
*Six data bits are needed for 33 positions.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ and 50 kΩ. The final two
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10 and 50 kΩ = 50. The nominal resistance
(RAB) of AD5200 has 256 contact points accessed by the wiper
terminal. The 8-bit data word in the RDAC latch of AD5200 is
decoded to select one of the 256 possible settings. In both parts,
the wiper’s first connection starts at the B terminal for data 00H.
This B-terminal connection has a wiper contact resistance of
50 Ω as long as valid VDD/VSS is applied, regardless of the nominal
resistance. For a 10 kΩ part, the second connection of AD5200 is
the first tap point with 89 Ω [RWB = RAB/255 + RW = 39 Ω + 50 Ω]
for data 01H. The third connection is the next tap point representing
78 + 50 = 128 Ω for data 02H. Due to its unique internal structure,
AD5201 has 5-bit + 1 resolution, but needs a 6-bit data word to
achieve the full 33 steps resolution. The 6-bit data word in the
RDAC latch is decoded to select one of the 33 possible settings.
Data 34 to 63 will automatically be equal to Position 33. The
wiper 00H connection of AD5201 gives 50 Ω. Similarly, for a
10 kΩ part, the first tap point of AD5201 yields 363 Ω for
data 01H, 675 Ω for data 02H. For both AD5200 and AD5201,
each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached. Figures 2a and 2b show
the simplified diagrams of the equivalent RDAC circuits.
R
R
= 10kꢀ
= 50kꢀ
AB
AB
0.1
16
28
0
4
8
12
20
24
32
CODE – Decimal
TPC 32. AD5201 IMAX vs. Code
OPERATION
The AD5200/AD5201 provide 255 and 33 positions digitally-
controlled variable resistor (VR) devices. Changing the
programmed VR settings is accomplished by clocking in an 8-bit
serial data word for AD5200, and a 6-bit serial data word for
AD5201, into the SDI (Serial Data Input) pins. Table I provides
the serial register data word format. The AD5200/AD5201 are
preset to a midscale internally during power-on condition. In
addition, the AD5200/AD5201 contain power shutdown
SHDN pins that place the RDAC in a zero power consump-
tion state where the immediate switches next to Terminals A and
B are open-circuited. Meanwhile, the wiper W is connected to B
terminal, resulting in only leakage current consumption in the VR
structure. During shutdown, the VR latch contents are maintained
when the RDAC is inactive. When the part is returned from
shutdown, the stored VR setting will be applied to the RDAC.
–11–
AD5200/AD5201
A
Note D in AD5200 is between 0 to 255 for 256 positions. On
the other hand, D in AD5201 is between 0 to 32 so that 33
positions can be achieved due to the slight internal structure
difference, Figure 2b.
SHDN
SHDN
SW
D7
D6
D5
D4
D3
D2
D1
D0
N
SW
2
ꢄ1
ꢄ2
Again if RAB = 10 kΩ and A terminal can be opened or tied to
W, the following output resistance between W to B will be set
for the following RDAC latch codes:
R
N
SW
2
AD5200 Wiper-to-B Resistance
W
SW
SW
1
R
R
D
(DEC)
RWB
(ꢀ)
R
AB
R
N
Output State
0
2
–1
RDAC
LATCH &
DECODER
255
128
1
10050
5070
89
Full-Scale (RAB + RW)
Midscale
1 LSB
DIGITAL CIRCUITRY
OMITTED FOR CLARITY
B
Figure 2a. AD5200 Equivalent RDAC Circuit. 255 positions
0
50
Zero-Scale (Wiper Contact Resistance)
N
can be achieved up to Switch SW 2
.
–1
AD5201 Wiper-to-B Resistance
A
SHDN
SW
SHDN
D
RWB
(DEC)
(ꢀ)
Output State
N
SW
2
32
16
1
10050
5050
363
Full-Scale (RAB + RW)
Midscale
1 LSB
N
N
R
R
SW
2
2
ꢄ1
ꢄ2
D5
D4
D3
D2
D1
D0
0
50
Zero-Scale (Wiper Contact Resistance)
SW
Note that in the zero-scale condition a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switch contact.
W
SW
SW
R
R
1
R
AB
N
R
0
RDAC
2
LATCH &
DECODER
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
Terminal A also produces a digitally controlled resistance RWA
DIGITAL CIRCUITRY
OMITTED FOR CLARITY
B
.
When these terminals are used, the B terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in
the latch is increased in value. The general equation for this
operation is:
Figure 2b. AD5201 Equivalent RDAC Circuit. Unlike AD5200,
N
33 positions can be achieved all the way to Switch SW 2
.
The general equation determining the digitally programmed
output resistance between W and B is:
D
255
255 − D
(
)
for AD5200
for AD5201
(1)
(2)
RWB D =
RAB + 50 Ω
( )
for AD5200
(3)
RWA D =
RAB + 50Ω
( )
255
D
RWB D =
RAB + 50 Ω
( )
32
32 − D
(
)
where:
for AD5201
(4)
RWA D =
RAB + 50Ω
( )
32
D
is the decimal equivalent of the data contained in
RDAC latch.
Similarly, D in AD5200 is between 0 to 255, whereas D in
AD5201 is between 0 to 32.
RAB is the nominal end-to-end resistance.
For RAB = 10 kΩ and B terminal is opened or tied to the wiper
W, the following output resistance between W and A will be set
for the following RDAC latch codes:
RW is the wiper resistance contributed by the on-resistance
of the internal switch.
–12–
AD5200/AD5201
AD5200 Wiper-to-A Resistance
RWA
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors and not
the absolute values; therefore, the drift reduces to 15 ppm/°C.
D
(DEC)
(ꢀ)
Output State
255
128
1
50
Full-Scale (RW)
Midscale
1 LSB
DIGITAL INTERFACING
5030
10011
10050
The AD5200/AD5201 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK), CS, and
serial data input (SDI). The positive-edge-sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means.
Figure 3 shows more detail of the internal digital circuitry. When
CS is low, the clock loads data into the serial register on each
positive clock edge (see Table III).
0
Zero-Scale (RAB + RW)
AD5201 Wiper-to-A Resistance
RWA
D
(DEC)
(ꢀ)
Output State
32
16
1
50
Full-Scale (RW)
Midscale
1 LSB
5050
9738
10050
0
Zero-Scale (RAB + RW)
V
V
SS
DD
AD5200/AD5201
A
The tolerance of the nominal resistance can be 30% due to
process lot dependance. If users apply the RDAC in rheostat
(variable resistance) mode, they should be aware of such specifi-
cation of tolerance. The change in RAB with temperature has a
500 ppm/°C temperature coefficient.
CS
W
B
CLK
SER
REG
Dx
RDAC
REG
8/6
SDI
SHDN
GND
PWR-ON
PRESET
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt-
age at A to B.
Figure 3. Block Diagram
Table III. Input Logic Control Truth Table
CLK CS SHDN
Register Activity
Unlike the polarity of VDD – VSS, which must be positive, volt-
age across A–B, W–A, and W–B can be at either polarity.
L
P
X
X
X
L
L
P
H
H
H
H
H
H
L
No SR effect.
Shift one bit in from the SDI pin.
Load SR data into RDAC latch.
No operation.
Open circuit on A terminal and short
circuit between W to B terminals.
If ignoring the effects of the wiper resistance for an approxima-
tion, connecting A terminal to 5 V and B terminal to ground
produces an output voltage at the wiper which can be any value
starting at almost zero to almost full scale with the minor devia-
tion contributed by the wiper resistance. Each LSB of voltage is
equal to the voltage applied across Terminal AB divided by the
2N-1 and 2N position resolution of the potentiometer divider for
AD5200 and AD5201 respectively. The general equation defin-
ing the output voltage with respect to ground for any valid input
voltage applied to Terminals A and B is:
NOTE
P = positive edge, X = don’t care, SR = shift register.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 4. Applies to
digital input pins CS, SDI, SHDN, CLK.
D
255
340ꢀ
for AD5200
for AD5201
(5)
(6)
VW D =
VAB + VB
LOGIC
( )
D
32
V
SS
VW D =
VAB + VB
( )
Figure 4. ESD Protection of Digital Pins
where D in AD5200 is between 0 to 255 and D in AD5201 is
between 0 to 32.
A,B,W
For more accurate calculation, including the effects of wiper
resistance, VW can be found as:
V
SS
Figure 5. ESD Protection of Resistor Terminals
RWB
D
RWA
D
( )
( )
(7)
VW D =
VA
+
VB
( )
RAB
RAB
where RWB(D) and RWA(D) can be obtained from Equations
1 to 4.
–13–
AD5200/AD5201
TEST CIRCUITS
Figures 6 to 14 define the test conditions used in the product
specification table.
5V
OP279
V
OUT
V
IN
DUT
A
V+ = V
1 LSB = V+/2
DD
W
N
OFFSET
GND
W
V+
A
DUT
B
B
V
MS
OFFSET BIAS
Figure 6. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 11. Noninverting Gain Test Circuit
NO CONNECT
DUT
+15V
A
I
W
W
A
V
IN
W
OP42
V
OUT
B
OFFSET
GND
B
2.5V
V
MS
–15V
Figure 7. Resistor Position Nonlinearity Error
(RheostatOperation;R-INL, R-DNL)
Figure 12. Gain vs. Frequency Test Circuit
0.1V
R
=
SW
DUT
B
I
SW
DUT
CODE = OO
H
W
I
= V /R
NOMINAL
W
DD
V
A
MS2
V
+
W
W
I
SW
0.1V
–
B
V
R
MS1
V
TO V
DD
SS
= [V
MS1
– V ]/I
W
MS2
W
Figure 8. Wiper Resistance Test Circuit
Figure 13. Incremental ON Resistance Test Circuit
NC
V
A
V
DUT
DD
I
A
B
CM
W
V
DD
A
B
V+ = V ꢁ10%
V+
DD
W
ꢆV
ꢆV
V
MS
DD
GND
SS
V
CM
PSRR (dB) = 20 LOG
V
ꢆV
ꢆV
%
MS
MS
PSS (%/%) =
NC
NC = NO CONNECT
%
DD
Figure 9. Power Supply Sensitivity Test Circuit
(PSS, PSRR)
Figure 14. Common-Mode Leakage Current Test Circuit
A
DUT B
5V
W
V
IN
OP279
V
OUT
OFFSET
GND
OFFSET BIAS
Figure 10. Inverting Gain Test Circuit
–14–
AD5200/AD5201
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 15. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Full Reel
Qty.
Branding
Information
Model1
RES kΩ
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
AD5200BRMZ10
256 10
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
50
1,000
50
1,000
50
1,000
50
DLA
DLA
D8T
AD5200BRMZ10-REEL7 256 10
AD5200BRMZ50 256 50
AD5200BRMZ50-REEL7 256 50
AD5201BRMZ10
AD5201BRMZ10-REEL7 33
AD5201BRMZ50 33
D8T
33
10
10
50
50
DMA
DMA
DMB
DMB
AD5201BRMZ50-REEL7 33
1,000
1 Z = RoHS Compliant Part.
REVISION HISTORY
12/12—Rev. C to Rev. D
Changes to Ordering Guide...........................................................15
6/12—Rev. B to Rev. C
Removed Digital Potentiometer Selection Guide .......................15
Updated Outline Dimensions........................................................15
Changes to Ordering Guide...........................................................15
8/01—Rev. A to Rev. B
Edits to ORDERING GUIDE ..........................................................5
2/01—Rev. 0 to Rev. A
Edits to ORDERING GUIDE ..........................................................5
Edits to ABSOLUTE MAXIMUM RATINGS...............................5
TPCs 31 and 32 added....................................................................11
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02188-0-12/12(D)
REV. D
–15–
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