AD5206BRUZ50-REEL7_技术文档

4-/6-Channel

Digital Potentiometers

AD5204/AD5206

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

256 positions

AD5204

V

DD

CS

Multiple independently programmable channels

AD5204—4-channel

AD5206—6-channel

A1

W1

B1

CLK

D7

D0

EN

RDAC

LATCH

1

ADDR

DEC

A2

A1

A0

Potentiometer replacement

DO

SDO

R

Terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ

3-wire SPI-compatible serial data input

+2.7 V to +5.5 V single-supply operation; 2.7 V dual-supply

operation

D7

SER

REG

A4

D7

D0

Power-on midscale preset

W4

RDAC

LATCH

4

DI

D0

SDI

B4

APPLICATIONS

SHDN

8

Mechanical potentiometer replacement

Instrumentation: gain, offset adjustment

Programmable voltage-to-current conversion

Programmable filters, delays, time constants

Line impedance matching

V

R

SS

POWER-ON

PRESET

PR

GND

Figure 1.

AD5206

V

CS

DD

GENERAL DESCRIPTION

A1

W1

B1

CLK

D7

D0

The AD5204/AD5206 provide 4-/6-channel, 256-position

digitally controlled variable resistor (VR) devices. These

devices perform the same electronic adjustment function as a

potentiometer or variable resistor. Each channel of the AD5204/

AD5206 contains a fixed resistor with a wiper contact that taps

the fixed resistor value at a point determined by a digital code

loaded into the SPI-compatible serial-input register. The

resistance between the wiper and either endpoint of the fixed

resistor varies linearly with respect to the digital code transferred

into the VR latch. The variable resistor offers a completely

programmable value of resistance between the A terminal and

the wiper or the B terminal and the wiper. The fixed A-to-B

terminal resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal

temperature coefficient of 700 ppm/°C.

EN

RDAC

LATCH

1

ADDR

DEC

A2

A1

A0

R

D7

SER

REG

A6

W6

B6

D7

D0

RDAC

LATCH

6

DI

D0

SDI

8

R

POWER-ON

PRESET

GND

V

SS

Figure 2.

PR

An optional reset ( ) pin forces all the AD5204 wipers to the

midscale position by loading 0x80 into the VR latch.

Each VR has its own VR latch that holds its programmed

resistance value. These VR latches are updated from an internal

serial-to-parallel shift register that is loaded from a standard

3-wire serial-input digital interface. Eleven data bits make up

the data-word clocked into the serial input register. The first

three bits are decoded to determine which VR latch is loaded

The AD5204/AD5206 are available in the 24-lead surface-

mount SOIC, TSSOP, and PDIP packages. The AD5204 is also

available in a 32-lead, 5 mm × 5 mm LFCSP package. All parts are

guaranteed to operate over the extended industrial temperature

range of −40°C to +85°C. For additional single-, dual-, and quad-

channel devices, see the AD8400/AD8402/AD8403 data sheets.

CS

with the last eight bits of the data-word when the

strobe is

returned to logic high. A serial data output pin at the opposite

end of the serial register (AD5204 only) allows simple daisy

chaining in multiple VR applications without requiring

additional external decoding logic.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5204/AD5206

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ........................................... 10

Operation......................................................................................... 12

Programming the Variable Resistor............................................. 13

Rheostat Operation.................................................................... 13

Programming the Potentiometer Divider................................... 14

Voltage Output Operation......................................................... 14

Digital Interfacing .......................................................................... 15

Test Circuits..................................................................................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Diagrams.............................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

REVISION HISTORY

7/10—Rev. B to Rev. C

11/07—Rev. 0 to Rev. A

Changes to Digital Input and Output Voltage to GND

Parameter, Table 2............................................................................. 6

Changes to Ordering Guide .......................................................... 18

Updated Format..................................................................Universal

Added 32-Lead LFCSP Package .......................................Universal

Changed R_BAto R_AB............................................................Universal

Changes to Absolute Maximum Ratings........................................6

Changes to Operation Section...................................................... 12

Updated Outline Dimensions....................................................... 17

Changes to Ordering Guide.......................................................... 18

5/09—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Absolute Maximum Ratings....................................... 6

Changes to Figure 7.......................................................................... 8

Changes to Table 4............................................................................ 8

9/99—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD5204/AD5206

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 5 V 10% or 3 V 10%, V_SS= 0 V, V_A= V_DD, V_B= 0 V, −40°C < T_A< +85°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS RHEOSTAT MODE²

Resistor Differential NL³

Resistor Nonlinearity Error³

Nominal Resistor Tolerance⁴

Resistance Temperature Coefficient

Nominal Resistance Match

R-DNL

R-INL

ΔR_AB

ΔR_AB/ΔT

ΔR/R_AB

R_WB, V_A= no connect

T_A= 2ꢀ°C

−1

−2

−30

0.2ꢀ

0.ꢀ

+1

+2

+30

LSB

%

ppm/°C

%

V_AB= V_DD, wiper = no connect

700

0.2ꢀ

Channel 1 to Channel 2, Channel 3, and

Channel 4, or to Channel ꢀ and Channel 6;

V_AB= V_DD

1.ꢀ

Wiper Resistance

R_W

I_W= 1 V/R, V_DD= ꢀ V

ꢀ0

100

Ω

DC CHARACTERISTICS POTENTIOMETER

DIVIDER MODE²

Resolution

N

8

Bits

Differential Nonlinearity^ꢀ

Integral Nonlinearity^ꢀ

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

ΔV_W/ΔT

V_WFSE

V_WZSE

−1

−2

0.2ꢀ

0.ꢀ

1ꢀ

−1

1

+1

+2

LSB

ppm/°C

LSB

Code = 0x40

Code = 0x7F

Code = 0x00

−2

0

2

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁶

Capacitance⁷Ax, Bx

Capacitance⁷Wx

Shutdown Current⁸

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Output Logic High

Output Logic Low

Input Current

Input Capacitance⁷

V_A, V_B, V_W

C_A, C_B

C_W

I_{A_SD}

I_CM

V_SS

V_DD

V

f = 1 MHz, measured to GND, code = 0x40

4ꢀ

60

0.01

1

pF

μA

nA

ꢀ

V_A= V_B= V_W= 0, V_DD= +2.7 V, V_SS= −2.ꢀ V

V_IH

V_IL

V_OH

V_OL

I_IL

V_DD= ꢀ V/3 V

R_PULL–UP= 1 kΩ to ꢀ V

I_OL= 1.6 mA, V_LOGIC= ꢀ V

V_IN= 0 V or ꢀ V

2.4/2.1

4.9

V

μA

pF

0.8/0.6

0.4

1

C_IL

ꢀ

POWER SUPPLIES

Power Single-Supply Range

Power Dual-Supply Range

Positive Supply Current

Negative Supply Current

Power Dissipation⁹

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS^{7, 10}

Bandwidth −3 dB

V_DDrange

V_DD/V_SSrange

I_DD

I_SS

P_DISS

PSS

V_SS= 0 V

2.7

2.3

ꢀ.ꢀ

2.7

60

0.3

V

μA

mW

%/%

V_IH= ꢀ V or V_IL= 0 V

V_SS= −2.ꢀ V, V_DD= +2.7 V

V_IH= ꢀ V or V_IL= 0 V

ΔV_DD= ꢀ V 10%

12

0.0002 0.00ꢀ

BW_10K

BW_ꢀ0K

BW_100K

THD_W

t_S

e_{N_WB}

R_AB= 10 kΩ

R_AB= ꢀ0 kΩ

R_AB= 100 kΩ

V_A= 1.414 V rms, V_B= 0 V dc, f = 1 kHz

V_A= ꢀ V, V_B= 0 V, 1 LSB error band

R_WB= ꢀ kΩ, f = 1 kHz, PR = 0

721

137

69

0.004

2/9/18

9

kHz

%

μs

nV/√Hz

Total Harmonic Distortion

VW Settling Time (10 kΩ/ꢀ0 kΩ/100 kΩ)

Resistor Noise Voltage

Rev. C | Page 3 of 20

AD5204/AD5206

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

INTERFACE TIMING CHARACTERISTICS^{7, 11, 12}

Input Clock Pulse Width

Data Setup Time

Data Hold Time

CLK-to-SDO Propagation Delay¹³

t_CH, t_CL

t_DS

t_DH

t_PD

t_CSS

Clock level high or low

20

ꢀ

ns

R_L= 2 kΩ , C_L< 20 pF

1

1ꢀ0

CS Setup Time

1ꢀ

40

90

0

CS High Pulse Width

t_CSW

t_RS

t_CSH0

t_CSH1

t_CS1

Reset Pulse Width

CLK Fall to CS Fall Setup

CLK Fall to CS Rise Hold Time

CS Rise to Clock Rise Setup

0

10

¹Typicals represent average readings at 2ꢀ°C and V_DD= ꢀ V.

²Applies to all VRs.

³Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.

I

_W= V_DD/R for both V_DD= 3 V and V_DD= ꢀ V.

⁴V_AB= V_DD, wiper (V_W) = no connect.

^ꢀINL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of 1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.

⁶Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.

⁷Guaranteed by design and not subject to production test.

⁸Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

⁹P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

¹⁰All dynamic characteristics use V_DD= ꢀ V.

¹¹Applies to all parts.

¹²See the timing diagrams (Figure 3 to Figure ꢀ) for the location of the measured values. All input control voltages are specified with t_R= t_F= 2.ꢀ ns (10% to 90% of 3 V)

and timed from a voltage level of 1.ꢀ V. Switching characteristics are measured using both V_DD= 3 V and V_DD= ꢀ V.

¹³The propagation delay depends on the values of V_DD, R_L, and C_L(see the Operation section).

Rev. C | Page 4 of 20

AD5204/AD5206

TIMING DIAGRAMS

1

0

1

0

1

0

SDI

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

CLK

RDAC LATCH LOAD

CS

V

DD

0V

V

OUT

Figure 3. Timing Diagram

1

0

SDI

(DATA IN)

Ax OR Dx

t_DS

t_DH

1

0

SDO

(DATA OUT)

Ax OR Dx

t_{PD_MAX}

t_CS1

t_CH

1

0

CLK

CS

t_CSH0

t_CSH1

t_CL

t_CSS

1

0

t_CSW

t_S

V

±1 LSB

DD

V

OUT

±1 LSB ERROR BAND

0V

Figure 4. Detailed Timing Diagram

t_RS

1

PR

0

t_S

V

DD

V

OUT

±1 LSB

0V

±1 LSB ERROR BAND

Figure 5. AD5204 Preset Timing Diagram

Rev. C | Page ꢀ of 20

AD5204/AD5206

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 2.

Parameter

V_DDto GND

V_SSto GND

V_DDto V_SS

Rating

−0.3 V to +7 V

0 V to −7 V

7 V

V_A, V_B, V_Wto GND

I_A, I_B, I_W

Pulsed¹

V_SS, V_DD

ESD CAUTION

20 mA

Continuous

10 kΩ End-to-End Resistance

ꢀ0 kΩ and 100 kΩ End-to-End

Resistance

11 mA

2.ꢀ mA

Digital Input and Output Voltage

to GND

−0.3 V to (V_DD+ 0.3 V) or 7 V

(whichever is less)

Operating Temperature Range

Maximum Junction Temperature

(T_Jmax)

−40°C to +8ꢀ°C

1ꢀ0°C

Storage Temperature

Reflow Soldering

−6ꢀ°C to +1ꢀ0°C

Peak Temperature

260°C

Time at Peak Temperature

Package Power Dissipation

Thermal Resistance, θ_JA

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

2

PDIP (N-24-1)

SOIC (RW-24)

TSSOP (RU-24)

LFCSP (CP-32-3)

63°C/W

ꢀ2°C/W

ꢀ0°C/W

32.ꢀ°C/W

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Thermal resistance (JEDEC 4-layer (2S2P) board). Paddle soldered to board.

Rev. C | Page 6 of 20

AD5204/AD5206

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC

1

2

3

4

5

6

7

8

9

24 B4

23 W4

22 A4

21 B2

20 W2

19 A2

NC

GND

CS

AD5204

TOP VIEW

(Not to Scale)

PR

V

DD

18

A1

SHDN

SDI

17 W1

16 B1

15 A3

14 W3

13 B3

CLK

SDO 10

11

V

SS

NC 12

NC = NO CONNECT

Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration

Table 3. AD5204 SOIC/TSSOP/PDIP Pin Function Descriptions

Pin No. Name Description

1, 2, 12

3

4

NC

GND

CS

Not Connected.

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address

bits, and then it is loaded into the target RDAC latch.

ꢀ

PR

Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.

6

7

V_DD

SHDN

SDI

CLK

SDO

V_SS

B3

W3

A3

Positive Power Supply. This pin is specified for operation at both 3 V and ꢀ V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.

8

Serial Data Input. Data is input MSB first.

9

Serial Clock Input. This pin is positive edge triggered.

10

11

13

14

1ꢀ

16

17

18

19

20

21

22

23

24

Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Terminal B RDAC 3.

Wiper RDAC 3. Address = 010₂.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 000₂.

Terminal A RDAC 1.

B1

W1

A1

A2

Terminal A RDAC 2.

W2

B2

A4

W4

B4

Wiper RDAC 2. Address = 001₂.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 011₂.

Terminal B RDAC 4.

Rev. C | Page 7 of 20

AD5204/AD5206

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

NC

PIN 1

INDICATOR

23 NC

22 NC

21 NC

20 B4

19 W4

18 A4

NC

B3

AD5204

TOP VIEW

(Not to Scale)

W3

A3

NC

17

9

10 11 12 13 14 15 16

NOTES

1. NC = NO CONNECT.

2. THE LFCSP PACKAGE HAS AN EXPOSED

PADDLE THAT SHOULD BE CONNECTED TO

GND AND THE ASSOCIATED PCB

GROUND PLATE.

Figure 7. AD5204 LFCSP Pin Configuration

Table 4. AD5204 LFCSP Pin Function Descriptions

Pin No. Name Description

1

V_SS

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Not Connected.

2 to ꢀ, 9, NC

16, 17,

21 to 24

6

B3

Terminal B RDAC 3.

7

8

W3

A3

B1

W1

A1

A2

W2

B2

A4

W4

B4

GND

CS

Wiper RDAC 3. Address = 010₂.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 000₂.

Terminal A RDAC 1.

Terminal A RDAC 2.

Wiper RDAC 2. Address = 001₂.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 011₂.

Terminal B RDAC 4.

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address

bits, and then it is loaded into the target RDAC latch.

10

11

12

13

14

1ꢀ

18

19

20

2ꢀ

26

27

28

29

30

31

32

PR

Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.

V_DD

SHDN

SDI

CLK

SDO

Positive Power Supply. This pin is specified for operation at both 3 V and ꢀ V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Terminal A Open-Circuit Shutdown (Active Low Input). This pin controlsVR 1 through VR 4.

Serial Data Input. Data is input MSB first.

Serial Clock Input. This pin is positive edge triggered.

Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.

Rev. C | Page 8 of 20

AD5204/AD5206

A6

W6

1

2

3

4

5

6

7

8

9

24 B4

23 W4

22 A4

21 B2

20 W2

19 A2

B6

GND

CS

AD5206

TOP VIEW

(Not to Scale)

V

DD

18

A1

SDI

17 W1

16 B1

15 A3

14 W3

13 B3

CLK

V

SS

B5 10

W5 11

A5 12

NC = NO CONNECT

Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration

Table 5. AD5206 Pin Function Descriptions

Pin No.

Name

Description

1

2

3

4

ꢀ

A6

W6

B6

GND

CS

Terminal A RDAC 6.

Wiper RDAC 6. Address = 101₂.

Terminal B RDAC 6.

Ground.

Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the

address bits, and then it is loaded into the target RDAC latch.

6

7

8

9

V_DD

SDI

CLK

V_SS

Bꢀ

Wꢀ

Aꢀ

B3

W3

A3

B1

W1

A1

A2

W2

B2

Positive Power Supply. This pin is specified for operation at both 3 V and ꢀ V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Serial Data Input. Data is input MSB first.

Serial Clock Input. This pin is positive edge triggered.

Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |V_DD| + |V_SS| < ꢀ.ꢀ V.

Terminal B RDAC ꢀ.

Wiper RDAC ꢀ. Address = 100₂.

Terminal A RDAC ꢀ.

Terminal B RDAC 3.

Wiper RDAC 3. Address = 010₂.

Terminal A RDAC 3.

Terminal B RDAC 1.

Wiper RDAC 1. Address = 000₂.

Terminal A RDAC 1.

Terminal A RDAC 2.

Wiper RDAC 2. Address = 001₂.

Terminal B RDAC 2.

Terminal A RDAC 4.

Wiper RDAC 4. Address = 011₂.

Terminal B RDAC 4.

10

11

12

13

14

1ꢀ

16

17

18

19

20

21

22

23

24

A4

W4

B4

Rev. C | Page 9 of 20

AD5204/AD5206

TYPICAL PERFORMANCE CHARACTERISTICS

120

110

V

/V = 2.7V/0V

DD SS

100

90

80

70

60

50

40

30

10kΩ

0

V

= ±2.7V

= –2.7V

= 100mV rms

–2

DD

SS

A

–4

DATA = 0x80

50kΩ

V

A

V

/V = 5.5V/0V

DD SS

100kΩ

V

/V = ±2.7V

DD SS

OP42

–3.0 –2.0 –1.0

0

1.0

2.0

3.0

4.0

5.0

6.0

1k

10k

100k

FREQUENCY (Hz)

1M

COMMON MODE (V)

Figure 9. Incremental On Resistance of the Wiper vs. Voltage

Figure 12. −3 dB Bandwidth vs. Terminal Resistance,

2.7 V Dual-Supply Operation

–5.99

0

DATA = 0x80

DATA = 0x40

–6.00

–6.01

–6.02

–6.03

–6.04

–6.05

–6.06

–6.07

–6

–12

–18

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

10kΩ

–24

–30

–36

–42

–48

50kΩ

V

= +2.7V

= –2.7V

= 100mV rms

DATA = 0x80

= 25°C

DD

SS

100kΩ

A

DATA = 0x02

DATA = 0x01

T

A

V

A

V

A

V

= +2.7V

= –2.7V

DD

SS

OP42

–54

–60

–6.08

–6.09

= 100mV rms

= 25°C

A

V

= 0V

B

T

100

1k

10k

FREQUENCY (Hz)

100k

1k

10k

100k

FREQUENCY (Hz)

1M

Figure 10. Gain Flatness vs. Frequency

Figure 13. Bandwidth vs. Code, 10 kΩ Version

0

DATA = 0x80

DATA = 0x40

–6

–12

–18

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

DATA = 0x02

10kΩ

0

–2

–4

V

= 2.7V

= 0V

= 100mV rms

–24

–30

–36

–42

–48

DD

SS

A

DATA = 0x80

= 25°C

50kΩ

T

A

2.7V

100kΩ

DATA = 0x01

V

OP42

V

= +2.7V

= –2.7V

A

DD

SS

+1.5V

OP42

–54

–60

= 100mV rms

A

T

= 25°C

1k

10k

100k

1M

1k

10k

100k

FREQUENCY (Hz)

1M

FREQUENCY (Hz)

Figure 11. −3 dB Bandwidth vs. Terminal Resistance,

2.7 V Single-Supply Operation

Figure 14. Bandwidth vs. Code, 50 kΩ Version

Rev. C | Page 10 of 20

AD5204/AD5206

0

–6

8

7

6

5

4

3

2

1

0

T

= 25°C

A

DATA = 0x80

DATA = 0x40

–12

–18

–24

–30

DATA = 0x20

DATA = 0x10

DATA = 0x08

DATA = 0x04

DATA = 0x02

DATA = 0x01

I

, V /V = 5.5V/0V, DATA = 0x55

DD DD SS

I

, V /V = ±2.7V, DATA = 0x55

SS DD SS

I

, V /V = 5V/0V, DATA = 0xFF

DD DD SS

–36

–42

I

, V /V = ±2.7V, DATA = 0xFF

SS DD SS

I

, V /V = 2.7V/0V, DATA = 0xFF

DD DD SS

–48

–54

–60

V

= +2.7V

= –2.7V

A

DD

SS

I

, V /V = ±2.7V/0V, DATA = 0x55

DD DD SS

OP42

= 100mV rms

A

T

= 25°C

1k

10k

100k

FREQUENCY (Hz)

1M

10k

100k

FREQUENCY (Hz)

1M

10M

100k

Figure 15. Bandwidth vs. Code, 100 kΩ Version

Figure 18. Supply Current vs. Clock Frequency

2.5

2.0

1.5

1.0

0.5

0

60

50

40

30

20

10

0

T

= 25°C

A

V

= –3.0V ± 10%

SS

V

= 5.0V ± 10%

DD

SINGLE SUPPLY

V

= V

DD

SS

DUAL SUPPLY

= 0V

V

SS

V

DD

= 3.0V ± 10%

1

2

3

4

5

6

10

100

1k

FREQUENCY (Hz)

10k

SUPPLY VOLTAGE V (V)

DD

Figure 16. Digital Input Trip Point vs. Supply Voltage

Figure 19. Power Supply Rejection vs. Frequency

100

10

1

0.1

I

AT V /V = ±2.7V

DD SS

SS

T

= 25°C

A

V

= +2.7V

= –2.7V

DD

SS

T

= 25°C

A

R

= 10kΩ

AB

I

AT V /V = 5.5V/0V

DD SS

DD

1

0.01

I

AT V /V = ±2.7V

DD SS

NONINVERTING TEST CIRCUIT

INVERTING TEST CIRCUIT

DD

0.1

0.001

0.01

0.001

I

AT V /V = 2.7V/0V

DD SS

DD

0.0001

0

1

2

3

4

5

6

10

100

1k

10k

INCREMENTAL INPUT LOGIC VOLTAGE (V)

FREQUENCY (Hz)

Figure 17. Supply Current vs. Input Logic Voltage

Figure 20. Total Harmonic Distortion Plus Noise vs. Frequency

Rev. C | Page 11 of 20

AD5204/AD5206

OPERATION

connected to terminals Bx, resulting in only leakage currents

being consumed in the VR structure. In shutdown mode, the

VR latch settings are maintained so that the VR settings return

to their previous resistance values when the device is returned

to operational mode from power shutdown.

The AD5204 provides a 4-channel, 256-position digitally

controlled VR device, and the AD5206 provides a 6-channel,

256-position digitally controlled VR device. Changing the pro-

grammed VR settings is accomplished by clocking an 11-bit

serial data-word into the SDI pin. The format of this data-word

is three address bits, MSB first, followed by eight data bits, MSB

first. Table 6 provides the serial register data-word format.

Ax

R

S

SHDN

R

S

Table 6. Serial Data-Word Format

D7

D6

D5

D4

D3

D2

D1

D0

Address

Data

R

S

B10 B9 B8

B7

B6 B5 B4 B3 B2 B1 B0

A2

A1 A0

D7

D6 Dꢀ D4 D3 D2 D1 D0

MSB

2¹⁰

LSB MSB

2⁸2⁷

LSB

2⁰

Wx

See Table 10 for the AD5204/AD5206 address assignments to

decode the location of the VR latch receiving the serial register

data in Bit B7 through Bit B0. The VR outputs can be changed

one at a time in random sequence. The AD5204 presets to

RDAC

LATCH

AND

R

S

Bx

DECODER

PR

midscale by asserting the

pin, simplifying fault condition

recovery at power up. Both parts have an internal power-on

preset that places the wiper in a preset midscale condition at

power on. In addition, the AD5204 contains a power shutdown pin

Figure 21. AD5204/AD5206 Equivalent RDAC Circuit

SHDN

(

) that places the RDAC in a zero power consumption

state, where terminals Ax are open circuited and wipers Wx are

Rev. C | Page 12 of 20

AD5204/AD5206

PROGRAMMING THE VARIABLE RESISTOR

In the zero-scale condition, a finite total wiper resistance of 45 Ω

is present. Regardless of which setting the part is operating in,

care should be taken to limit the current between Terminal A to

Terminal B, Wiper W to Terminal A, and Wiper W to Terminal

B, to the maximum continuous current of 5.65 mA(10 kΩ) or

1.35 mA(50 kΩ and 100 kΩ) or pulse current of 20 mA.

Otherwise, degradation or possible destruction of the internal

switch contact, can occur.

RHEOSTAT OPERATION

The nominal resistance of the RDAC between Terminal A and

Terminal B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ.

The last digits of the part number determine the nominal

resistance value; for example, 10 kΩ = 10 and 100 kΩ = 100.

The nominal resistance (R_AB) of the VR has 256 contact points

accessed by the wiper terminal, plus Terminal B contact. The

8-bit data-word in the RDAC latch is decoded to select one of

the 256 possible settings. The first connection of the wiper starts

at Terminal B for the 0x00 data. This Terminal B connection has a

wiper contact resistance of 45 Ω. The second connection (for a

10 kΩ part) is the first tap point, located at 84 Ω [= R_AB(nominal

resistance)/256 + R_W= 84 Ω + 45 Ω] for the 0x01 data. The

third connection is the next tap point, representing 78 + 45 =

123 Ω for the 0x02 data. Each LSB data value increase moves

the wiper up the resistor ladder until the last tap point is

reached at 10,006 Ω. The wiper does not directly connect to

Terminal A. See Figure 21 for a simplified diagram of the

equivalent RDAC circuit.

Like the mechanical potentiometer that the RDAC replaces,

the RDAC is completely symmetrical. The resistance between

Wiper W and Terminal A produces a digitally controlled

resistance, R_WA. When these terminals are used, Terminal B

should be tied to the wiper. Setting the resistance value for R_WA

starts at a maximum value of resistance and decreases as the

data loaded to the latch is increased in value. The general

transfer equation for this operation is

R

_WA(Dx) = (256 − Dx)/256 × R_AB+ R_W

where Dx is the data contained in the 8-bit RDACx latch, and

_ABis the nominal end-to-end resistance.

(2)

R

The general transfer equation determining the digitally

programmed output resistance between the Wx and Bx

terminals is

For example, when V_A= 0 V and Terminal B is tied to Wiper W,

the output resistance values outlined in Table 8 are set for the

RDAC latch codes.

R

_WB(Dx) = (Dx)/256 × R_AB+ R_W

where Dx is the data contained in the 8-bit RDACx latch, and

_ABis the nominal end-to-end resistance.

(1)

Table 8. Output Resistance Values for the RDAC Latch Codes—

V_A= 0 V and Terminal B Tied to Wiper W

R

D (DEC)

R_WA(Ω)

Output State

For example, when V_B= 0 V and Terminal A is open circuited, the

output resistance values are set as outlined in Table 7 for the

RDAC latch codes (applies to the 10 kꢀ potentiometer).

2ꢀꢀ

128

1

84

Full scale

Midscale (PR = 0 condition)

1 LSB

ꢀ04ꢀ

10006

1004ꢀ

0

Zero scale

Table 7. Output Resistance Values for the RDAC Latch Codes—

V_B= 0 V and Terminal A = Open Circuited

The typical distribution of R_ABfrom channel to channel matches

to within 1%. However, device-to-device matching is process

lot dependent, having a 30% variation. The change in R_ABin

terms of temperature has a 700 ppm/°C temperature coefficient.

D (Dec)

R_WB(Ω)

10006

ꢀ04ꢀ

84

Output State

2ꢀꢀ

128

1

Full scale

Midscale (PR = 0 condition)

1 LSB

0

4ꢀ

Zero scale (wiper contact resistance)

Rev. C | Page 13 of 20

AD5204/AD5206

PROGRAMMING THE POTENTIOMETER DIVIDER

V

VOLTAGE OUTPUT OPERATION

CS

DD

A1

W1

B1

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal.

For example, connecting Terminal A to 5 V and Terminal B to

ground produces an output voltage at the wiper that can be any

value from 0 V up to 1 LSB less than +5 V. Each LSB of voltage

is equal to the voltage applied across Terminal A and Terminal B

divided by the 256-position resolution of the potentiometer

divider. The general equation defining the output voltage with

respect to ground for any given input voltage applied to

Terminal A and Terminal B is

CLK

D7

D0

EN

RDAC

LATCH

1

A2

A1

A0

D7

ADDR

DEC

DO

SDO*

R

AD5204/AD5206

SER

REG

A4/A6

W4/W6

B4/B6

D7

SDI

DI

D0

RDAC

LATCH

4/6

V

_W(Dx) = Dx/256 × V_AB+ V_B

(3)

8

D0

Operation of the digital potentiometer in the divider mode

results in more accurate operation over temperature. In this

mode, the output voltage is dependent on the ratio of the

internal resistors, not the absolute value; therefore, the drift

improves to 15 ppm/°C.

R

SHDN*

*AD5204 ONLY

DGND

PR

Figure 22. Block Diagram

Rev. C | Page 14 of 20

AD5204/AD5206

DIGITAL INTERFACING

The AD5204/AD5206 each contain a standard 3-wire serial

input control interface. The three inputs are clock (CLK), chip

Table 10. Address Decode Table

A2

A1

A0

Latch Decoded

CS

select input ( ), and serial data input (SDI). The positive-

0

RDAC 1

edge-sensitive CLK input requires clean transitions to avoid

clocking incorrect data into the serial input register. Standard

logic families work well. If mechanical switches are used for

product evaluation, they should be debounced by a flip-flop or

by other suitable means. Figure 22 shows more detail of the

0

1

RDAC 2

0

1

0

RDAC 3

0

1

RDAC 4

1

0

1

RDAC ꢀ ADꢀ206 only

RDAC 6 ADꢀ206 only

CS

internal digital circuitry. When

is taken active low, the clock

The data setup and data hold times in the specification table

determine the data valid time requirements. The last 11 bits of

loads data into the serial register on each positive clock edge

(see Table 9). When using a positive (V_DD) and negative (V_SS)

supply voltage, the logic levels are still referenced to digital

ground (GND).

CS

the data-word entered into the serial register are held when

CS

returns high. When

goes high, the address decoder is gated,

enabling one of four or six positive-edge-triggered RDAC

latches (see Figure 23 for details).

The serial data output (SDO) pin contains an open-drain

n-channel FET. This output requires a pull-up resistor to transfer

data to the SDI pin of the next package. The pull-up resistor

termination voltage can be larger than the V_DDsupply of the

AD5204. For example, the AD5204 can operate at V_DD= 3.3 V,

and the pull-up for the interface to the next device can be set at

5 V. This allows for daisy chaining several RDACs from a

single-processor serial data line.

AD5204/AD5206

RDAC 1

RDAC 2

CS

ADDR

DECODE

RDAC 4/

RDAC 6

CLK

SERIAL

REGISTER

SDI

Figure 23. Equivalent Input Control Logic

If a pull-up resistor is used to connect the SDI pin of the

next device in the series, the clock period must be increased.

Capacitive loading at the daisy-chain node (where SDO and

SDI are connected) between the devices must be accounted for

to successfully transfer data. When daisy chaining is used, the

The target RDAC latch is loaded with the last eight bits of the

serial data-word, completing one DAC update. Four separate

8-bit data-words must be clocked in to change all four VR

settings.

SHDN

CS

should be kept low until all the bits of every package are

CS

SDO

clocked into their respective serial registers, ensuring that the

address bits and data bits are in the proper decoding locations.

This requires 22 bits of address and data complying to the data-

word format outlined in Table 6 if two AD5204 4-channel RDACs

SERIAL

REGISTER

D

Q

SDI

GND

CK RS

CLK

PR

SHDN

are daisy-chained. During shutdown (

), the SDO output

Figure 24. Detail SDO Output Schematic of the AD5204

pin is forced to the off (logic high state) position to disable power

dissipation in the pull-up resistor. See Figure 24 for the equivalent

SDO output circuit schematic.

CS

All digital pins ( , SDI, SDO,

protected with a series input resistor and a parallel Zener ESD

structure (see Figure 25).

PR SHDN

, , and CLK) are

Table 9. Input Logic Control Truth Table¹

CS PR SHDN

CLK

Register Activity

L

H

No SR effect; enables SDO pin.

P

Shift one bit in from the SDI pin. The

11^thbit entered is shifted out of the

SDO pin.

X

P

H

Load SR data into the RDAC latch

based on A2, A1, A0 decode (Table 10).

X

H

X

H

L

H

No operation.

Sets all RDAC latches to midscale;

wiper centered and SDO latch

cleared.

X

H

P

H

L

Latches all RDAC latches to 0x80.

Open circuits all A resistor terminals,

connects Wiper W to Terminal B, and

turns off the SDO output transistor.

¹P = positive edge, X = don’t care, SR = shift register.

Rev. C | Page 1ꢀ of 20

AD5204/AD5206

TEST CIRCUITS

V

A

V

340kΩ

DD

V+ = V ± 10%

DD

V+

W

LOGIC

~

∆V

MS

PSRR (dB) = 20 log

(

)

B

DD

V

MS

∆V

%

MS

V

PSS (%/%) =

SS

%

DD

Figure 25. ESD Protection of Digital Pins

Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)

A

B

DUT

IN

5V

OP279

W

A, B, W

V

OUT

OFFSET

GND

OFFSET BIAS

V

SS

Figure 26. ESD Protection of Resistor Terminals

Figure 31. Inverting Programmable Gain Test Circuit

5V

V

OUT

OP279

B

DUT

V+ = V

DD

1LSB = V+/256

V

IN

W

A

W

V+

A

OFFSET

GND

B

V

DUT

OFFSET BIAS

MS

Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)

Figure 32. Noninverting Programmable Gain Test Circuit

NO CONNECT

DUT

A

+15V

I

W

A

V

IN

W

DUT

V

OP42

OUT

B

OFFSET

GND

V

MS

2.5V

–15V

Figure 28. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 33. Gain vs. Frequency Test Circuit

0.1V

R

=

SW

DUT

I

SW

I

MS

CODE = 0x00

I

=

1V/R

W

NOMINAL

V+

V

DD

W

DUT

A

W

V

– [V

+ I (R II R )]

AW BW

W2

W1

W

+

V

B

R

=

W

0.1V

V+

I

SW

W

–

WHERE V = V

W1 MS

WHEN I = 0

W

B

AND V

= V WHEN I = 1/R

W2

MS

W

V

MS

V

TO V

DD

SS

Figure 29. Wiper Resistance Test Circuit

Figure 34. Incremental On-Resistance Test Circuit

Rev. C | Page 16 of 20

AD5204/AD5206

OUTLINE DIMENSIONS

1.280 (32.51)

1.250 (31.75)

1.230 (31.24)

24

1

13

12

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-24-1)

Dimensions shown in inches and (millimeters)

15.60 (0.6142)

15.20 (0.5984)

24

1

13

12

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.2

5 (0.0098)

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)ꢀ

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-24)

Dimensions shown in millimeters and (inches)

Rev. C | Page 17 of 20

AD5204/AD5206

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

(BOTTOM VIEW)

3.45

3.30 SQ

3.15

TOP

VIEW

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

1.00

0.85

0.80

0.30

0.23

0.18

SECTION OF THIS DATA SHEET.

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

AD5204BN10

AD5204BR10

AD5204BR10-REEL

AD5204BRZ10

kΩ

10

50

Temperature Range

−40°C to +85°C

Package Description

Package Option

N-24-1

RW-24

24-Lead Plastic Dual In-Line Package [PDIP]

24-Lead Standard Small Outline Package [SOIC_W]

24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

32-Lead Frame Chip Scale Package [LFCSP_VQ]

24-Lead Plastic Dual In-Line Package [PDIP]

24-Lead Standard Small Outline Package [SOIC_W]

AD5204BRZ10-REEL

AD5204BRU10

RW-24

AD5204BRU10-REEL7

AD5204BRUZ10

AD5204BRUZ10-REEL7

AD5204BCPZ10-REEL

AD5204BCPZ10-REEL7

AD5204BN50

AD5204BR50

AD5204BR50-REEL

AD5204BRZ50

CP-32-3

N-24-1

RW-24

Rev. C | Page 18 of 20

AD5204/AD5206

Model^{1, 2}

kΩ

50

Temperature Range

−40°C to +85°C

Package Description

Package Option

AD5204BRZ50-REEL

AD5204BRU50

24-Lead Standard Small Outline Package [SOIC_W]

RW-24

24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

AD5204BRU50-REEL

AD5204BRU50-REEL7

AD5204BRUZ50

AD5204BRUZ50-REEL7

AD5204BN100

AD5204BR100

AD5204BR100-REEL

AD5204BRZ100

AD5204BRZ100-REEL

AD5204BRU100

AD5204BRU100-REEL7

AD5204BRUZ100

AD5204BRUZ100-R7

AD5206BN10

AD5206BR10

AD5206BR10-REEL

AD5206BRZ10

AD5206BRZ10-REEL

AD5206BRU10

AD5206BRU10-REEL7

AD5206BRUZ10

AD5206BRUZ10-RL7

AD5206BN50

AD5206BR50

AD5206BR50-REEL

AD5206BRZ50

50

100

10

50

24-Lead Plastic Dual In-Line Package [PDIP]

N-24-1

RW-24

24-Lead Standard Small Outline Package [SOIC_W]

24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

24-Lead Plastic Dual In-Line Package [PDIP]

N-24-1

RW-24

24-Lead Standard Small Outline Package [SOIC_W]

24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

24-Lead Plastic Dual In-Line Package [PDIP]

N-24-1

RW-24

N-24-1

RW-24

24-Lead Standard Small Outline Package [SOIC_W]

24-Lead Plastic Dual In-Line Package [PDIP]

24-Lead Standard Small Outline Package [SOIC_W]

24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

AD5206BRU50

AD5206BRU50-REEL

AD5206BRU50-REEL7

AD5206BRUZ50

AD5206BRUZ50-REEL7

AD5206BN100

AD5206BR100

AD5206BR100-REEL

AD5206BRZ100

AD5206BRU100

AD5206BRU100-REEL7

AD5206BRUZ100

AD5206BRUZ100-RL7

50

100

¹The AD5204/AD5206 each contains 5,925 transistors. Die size is 92 mil × 114 mil, or 10,488 sq. mil.

²Z = RoHS Compliant Part.

Rev. C | Page 19 of 20

AD5204/AD5206

NOTES

registered trademarks are the property of their respective owners.

D06884-0-7/10(C)

Rev. C | Page 20 of 20


型号：	AD5206BRUZ50-REEL7
厂家：	ADI
描述：	4-/6-Channel Digital Potentiometers 4- / 6通道数字电位器电位器
文件：	总20页 (文件大小：371K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5206BRUZ50-REEL7 [ADI]

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AD5206_15

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AD5207BRU10-REEL7

AD5207BRU10-REEL7

AD5207BRU100-REEL7

AD5207BRU100-REEL7