AD5233BRUZ100-R7 [ADI]
Nonvolatile, Quad, 64-Position Digital Potentiometer;
| 型号： | AD5233BRUZ100-R7 |
| 厂家： | 
ADI |
| 描述： | Nonvolatile, Quad, 64-Position Digital Potentiometer |
| 文件： | 总33页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nonvolatile Memory, Quad
64-Position Digital Potentiometer
AD5233
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Nonvolatile memory stores wiper setting
4-channel independent programmable
64-position resolution
Power-on refreshed with EEMEM settings
EEMEM restore time: 140 μs typical
AD5233
V
DD
ADDR
DECODE
RDAC1
REGISTER
CS
CLK
SDI
A1
W1
SDI SERIAL
INTERFACE
B1
EEMEM1
SDO
SDO
RDAC1
RDAC2
RDAC3
RDAC4
Full monotonic operation
WP
RDAC2
REGISTER
EEMEM
CONTROL
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined 6 dB/step log taper increment/decrement
instructions
SPI-compatible serial interface with readback function
2.7 V to 5.5 V single supply or 2.5 V dual supply
11 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, TA = 55°C
A2
RDY
W2
B2
11 BYTES
USER EEMEM
EEMEM2
RDAC3
REGISTER
DIGITAL
OUTPUT
BUFFER
O1
O2
A3
W3
2
B3
EEMEM3
DIGITAL 5
REGISTER
RDAC4
REGISTER
A4
PR
W4
APPLICATIONS
B4
EEMEM5
EEMEM4
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
GND
V
SS
Figure 1.
Sensor calibration
GENERAL DESCRIPTION
The AD5233 is a quad-channel nonvolatile memory,1 digitally
controlled potentiometer2 with a 64-step resolution. The device
performs the same electronic adjustment function as a mechanical
potentiometer with enhanced resolution, solid-state reliability,
and remote controllability. The AD5233 has versatile program-
ming using a serial peripheral interface (SPI) for 16 modes of
operation and adjustment, including scratchpad programming,
memory storing and restoring, increment/decrement, 6 dꢀ/step
log taper adjustment, wiper setting readback, and extra EEMEM
for user-defined information such as memory data for other
components, look-up tables, or system identification
information.
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC register, which sets the
resistance between Terminal W to Terminal A and Terminal W
to Terminal ꢀ. This setting can be stored into the EEMEM and
is transferred automatically to the RDAC register during system
power-on.
The EEMEM content can be restored dynamically or through
PR
WP
external
strobing. A
function protects EEMEM contents.
To simplify the programming, independent or simultaneous
increment or decrement commands can be used to move the
RDAC wiper up or down, one step at a time. For logarithmic
6 dꢀ step changes in wiper settings, the left or right bit shift
command can be used to double or halve the RDAC wiper
setting.
The AD5233 is available in a thin 24-lead TSSOP package. The
part is guaranteed to operate over the extended industrial
temperature range of −40°C to +85°C.
1 The terms nonvolatile memory and EEMEM are used interchangeably.
2 The terms digital potentiometer and RDAC are used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
AD5233* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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SOFTWARE AND SYSTEMS REQUIREMENTS
• Digital Potentiometer Linux Driver
EVALUATION KITS
• AD5233 Evaluation Kit
DESIGN RESOURCES
• AD5233 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-1291: Digital Potentiometers: Frequently Asked
Questions
DISCUSSIONS
View all AD5233 EngineerZone Discussions.
• AN-580: Programmable Oscillator Uses Digital
Potentiometers
• AN-582: Resolution Enhancements of Digital
Potentiometers with Multiple Devices
SAMPLE AND BUY
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• AN-686: Implementing an I2C® Reset
Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AD5233: Nonvolatile Memory, Quad 64-Position
Potentiometers Data Sheet
User Guides
• UG-350: Evaluation Board for the AD5233 Digital
Potentiometer
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AD5233
TABLE OF CONTENTS
Features .............................................................................................. 1
RDAC Structure.......................................................................... 20
Programming the Variable Resistor......................................... 20
Programming the Potentiometer Divider............................... 21
Programming Examples............................................................ 21
Flash/EEMEM Reliability.......................................................... 22
Applications Information.............................................................. 23
ꢀipolar Operation from Dual Supplies.................................... 23
Gain Control Compensation .................................................... 23
High Voltage Operation ............................................................ 23
DAC.............................................................................................. 23
ꢀipolar Programmable Gain Amplifier................................... 24
Programmable Low-Pass Filter ................................................ 24
Programmable State-Variable Filter......................................... 25
Programmable Oscillator .......................................................... 26
Programmable Voltage Source with ꢀoosted Output ........... 26
Programmable Current Source ................................................ 27
Programmable ꢀidirectional Current Source......................... 27
Resistance Scaling ...................................................................... 27
Doubling the Resolution ........................................................... 28
Applications....................................................................................... 1
Functional ꢀlock Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ
Versions.......................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 13
Theory of Operation ...................................................................... 15
Scratchpad and EEMEM Programming.................................. 15
ꢀasic Operation .......................................................................... 15
EEMEM Protection.................................................................... 16
Digital Input/Output Configuration........................................ 16
Serial Data Interface................................................................... 16
Daisy-Chain Operation ............................................................. 17
Terminal Voltage Operation Range ......................................... 17
Power-Up Sequence ................................................................... 17
Latched Digital Outputs ............................................................ 17
Advanced Control Modes ......................................................... 19
REVISION HISTORY
Resistance Tolerance, Drift, and Temperature Mismatch
Considerations............................................................................ 28
RDAC Circuit Simulation Model............................................. 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
7/04—Rev. 0 to Rev. A
Format updated .................................................................. Universal
Changes to Features, General Description, and ꢀlock
5/08—Rev. A to Rev. B
Changes to Features...........................................................................1
Changes to Table 1.............................................................................3
Changes Figure 3 ...............................................................................6
Changes to Absolute Maximum Ratings Section..........................7
Changes to Figure 17 and Figure 18..............................................11
Changes to Programmable Oscillator Section.............................26
Changes to Ordering Guide ...........................................................29
Diagram ..............................................................................................1
Changes to Specifications.................................................................3
Replaced Timing Diagrams..............................................................6
Changes to Absolute Maximum Ratings........................................7
Changes to Pin Function Descriptions...........................................8
Replaced Figure 11 ............................................................................9
Added Test Circuit (Figure 36)......................................................13
Changes to Theory of Operation...................................................14
Changes to Applications.................................................................22
Updated Outline Dimensions........................................................28
Changes to Ordering Guide...........................................................28
3/02—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD5233
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 3 V 10% or 5 V 10%, VSS = 0 V, VA = VDD, Vꢀ = 0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS,
RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB/RAB
(∆RWB/RWB)/∆T × 106
RWB, VA = NC, monotonic
RWB, VA = NC
D = 0x3F
−0.5
−0.5
−40
0.1
0.1
+0.5
+0.5
+20
LSB
LSB
%
ppm/°C
Ω
600
15
RW
IW = 100 μA, code = half scale
100
DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE
Resolution
N
6
Bits
Differential Nonlinearity3
Integral Nonlinearity3
Voltage Divider Temperature
Coefficient
DNL
INL
Monotonic
−0.5
−0.5
+0.1
+0.1
15
+0.5
+0.5
LSB
LSB
ppm/°C
(∆VW/VW)/∆T × 106
Code = half scale
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = full scale
Code = zero scale
−1.5
0
0
1.5
% FS
% FS
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance A, Capacitance B5
VA, VB, VW
CA, CB
VSS
VDD
V
pF
f = 1 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
35
Capacitance W5
CW
ICM
35
pF
Common-Mode Leakage Current5, 6
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VW = VDD/2
0.015
1
μA
VIH
With respect to GND, VDD = 5 V
With respect to GND, VDD = 3 V
With respect to GND,
VDD = 2.5 V, VSS = −2.5 V
2.4
2.1
2.0
V
V
V
Input Logic Low
VIL
With respect to GND, VDD = 5 V
With respect to GND, VDD = 3 V
With respect to GND,
VDD = 2.5 V, VSS = −2.5 V
0.8
0.6
0.5
V
V
V
Output Logic High (SDO, RDY)
Output Logic Low
VOH
VOL
RPULL-UP = 2.2 kΩ to 5 V
(see Figure 35)
IOL = 1.6 mA, VLOGIC = 5 V
(see Figure 35)
4.9
V
V
0.4
2.5
Input Current
Input Capacitance5
Output Current5
IIL
CIL
IO1, IO2
VIN = 0 V or VDD
μA
pF
mA
4
50
VDD = 5 V, VSS = 0 V, TA = 25°C,
sourcing only
VDD = 2.5 V, VSS = 0 V, TA = 25°C,
sourcing only
7
mA
Rev. B | Page 3 of 32
AD5233
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
VDD
VDD/VSS
IDD
VSS = 0 V
2.7
2.5
5.5
2.75
10
10
V
V
μA
μA
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND,
VDD = 2.5 V, VSS = −2.5 V
3.5
0.55
ISS
EEMEM Store Mode Current
IDD (store)
VIH = VDD or VIL = GND,
40
mA
VSS = 0, ISS ≈ 0
ISS (store)
IDD (restore)
VDD = 2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND,
−40
3
mA
mA
EEMEM Restore Mode Current7
0.3
9
VSS = GND, ISS ≈ 0
ISS (restore)
PDISS
PSS
VDD = 2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
∆VDD = 5 V 10%
−0.3
−3
0.018
0.002
−9
0.05
0.01
mA
mW
%/%
Power Dissipation8
Power Supply Sensitivity5
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
BW
THDW
−3 dB, RAB = 10 kΩ/50 kΩ/100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
630/135/66
0.04
kHz
%
Total Harmonic Distortion
VA = 1 V rms, VB = 0 V, f = 1 kHz,
0.015
%
R
AB = 50 kΩ, 100 kΩ
VW Settling Time
tS
VA = VDD, VB = 0 V,
0.6/2.2/3.8
μs
VW = 0.50% error band,
Code 0x000 to Code 0x200
for RAB = 10 kΩ/50 kΩ/100 kΩ
Resistor Noise Voltage
eN_WB
CT
RWB = 5 kΩ, f = 1 kHz
9
−1
nV/√Hz
nV/sec
Crosstalk (CW1/CW2
)
VA = VDD, VB = 0 V, measure VW
with adjacent RDAC making
the full-scale code change
Analog Crosstalk (CW1/CW2)
CTA
VDD = VA1 = +2.5 V,
−86/−73/−68
dB
VSS = VB1 = −2.5 V,
measure VW1 with VW2 = 5 V p-p
@ f = 10 kHz, Code 1 = 0x20,
Code 2 = 0x3F, RAB = 10 kΩ/
50 kΩ/100 kΩ
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW > 50 μA @ VDD = 2.7 V for the RAB = 10 kΩ version, IW > 50 μA for the
RAB = 50 kΩ, and IW > 25 μA for the RAB = 100 kΩ version (see Figure 25).
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output ADC. VA = VDD and VB = VSS. DNL specification limits of
−1 LSB minimum are guaranteed monotonic operating conditions (see Figure 26).
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from Terminal B and Terminal W to a common-mode bias level of VDD/2.
7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To
minimize power dissipation, a NOP instruction should be issued immediately after Instruction 1 (0x1).
8 Power dissipation is calculated by PDISS = (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = 2.5 V and VSS = −2.5 V.
Rev. B | Page 4 of 32
AD5233
TIMING CHARACTERISTICS
VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING CHARACTERISTICS2, 3
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC
CS Setup Time
)
t1
t2
20
10
1
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
t3
t4, t5
t6
t7
Clock level high or low
From positive CLK transition
From positive CLK transition
10
5
5
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4
CLK to SDO Data Hold Time
CS High Pulse Width5
t8
40
50
50
t9
t10
t11
t12
t13
t14
t15
t16
RPULL-UP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
0
10
4
CS High to CS High5
RDY Rise to CS Fall
0
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM6
0.1
25
0.15
Applies to Instruction 0x2, Instruction 0x3,
and Instruction 0x9
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY
Endurance7
t17
10
50
ns
ns
μs
μs
tPRW
tPRESP
tEEMEM1
Not shown in timing diagram
PR pulsed low to refresh wiper positions
RAB = 10 kΩ
70
140
100
kCycles
Years
Data Retention8
100
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See the timing diagrams (Figure 2 and Figure 3) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
5 Valid for commands that do not activate the RDY pin.
6
PR
The RDY pin is low only for Command 2, Command 3, Command 8, Command 9, Command 10, and the hardware pulse: CMD_8 > 1 ms; CMD_9, CMD_10 > 0.12 ms;
CMD_2, CMD_3 > 20 ms. Device operation at TA = −40°C and VDD < 3 V extends the save time to 35 ms.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.
Rev. B | Page 5 of 32
AD5233
CPHA = 1
CS
t12
t3
t13
t1
t2
CLK
CPOL = 1
B15
t4
B0
t17
t5
t7
t6
HIGH OR
LOW
HIGH OR LOW
B15
(MSB)
B0
(LSB)
SDI
t10
t9
t11
t8
SDO
B15
(MSB)
B0
(LSB)
B16*
t15
t14
t16
RDY
*EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2. CPHA = 1 Timing Diagram
CPHA = 0
CS
t12
t1
t13
t3
t2
CLK
CPOL = 0
t5
B15
t4
B0
t17
t6
HIGH
OR LOW
HIGH
OR LOW
B15
(MSB)
B0
(LSB)
SDI
SDO
RDY
t11
t10
t8
t9
B15
(MSB OUT)
B0
(LSB)
*
t7
t14
t15
t16
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 3. CPHA = 0 Timing Diagram
Rev. B | Page 6 of 32
AD5233
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
–0.3 V to +7 V
+0.3 V to −7 V
7 V
VA, VB, VW to GND
VSS − 0.3 V to VDD + 0.3 V
IA, IB, IW
Pulsed1
ESD CAUTION
20 mA
Continuous
2 mA
Digital Inputs and Output Voltage to GND
Operating Temperature Range2
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Reflow Soldering
−0.3 V to VDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Peak Temperature
Time at Peak Temperature
Thermal Resistance Junction-to-Ambient, θJA
Package Power Dissipation
260°C
20 sec to 40 sec
50°C/W
3
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Includes programming of nonvolatile memory.
3 Thermal Resistance (JEDEC 4-layer (2S2P) board).
Rev. B | Page 7 of 32
AD5233
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
24
23
22
21
20
19
18
O1
CLK
SDI
O2
2
RDY
CS
3
4
SDO
GND
PR
AD5233
5
WP
TOP VIEW
(Not to Scale)
V
6
V
SS
DD
7
A1
W1
B1
A2
W2
B2
A4
8
17 W4
16 B4
15 A3
14 W3
13 B3
9
10
11
12
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
O1
Nonvolatile Digital Output 1. Address (O1) = 0x4, the data bit position is D0; defaults to Logic 1 initially.
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on positive CLK edges. MSB loaded first.
CLK
SDI
SDO
Serial Data Output Pin. Serves readback and daisy-chain functions.
Command 9 and Command 10 activate the SDO output for the readback function, delayed by 16 or 17 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 16 or 17 clock pulses,
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy-
chaining multiple devices.
Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5
6
GND
VSS
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
40 mA for 25 ms when storing data to EEMEM.
7
8
9
A1
W1
B1
Terminal A of RDAC1.
Wiper Terminal of RDAC1, Address (RDAC1) = 0x0.
Terminal B of RDAC1.
10
11
12
13
14
15
16
17
18
19
20
A2
W2
B2
Terminal A of RDAC2.
Wiper Terminal of RDAC2, Address (RDAC2) = 0x1.
Terminal B of RDAC2.
Terminal B of RDAC3.
Wiper Terminal of RDAC3, Address (RDAC3) = 0x2.
Terminal A of RDAC3.
Terminal B of RDAC4.
Wiper Terminal of RDAC4, Address (RDAC4) = 0x3.
Terminal A of RDAC4.
B3
W3
A3
B4
W4
A4
VDD
WP
Positive Power Supply Pin.
Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe
and Instruction 1 and Instruction 8, and refreshes the RDAC register from EEMEM. Execute a NOP instruction
before returning to WP high. Tie WP to VDD if not used.
21
PR
Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 0x20 until EEMEM is loaded with a new value by the user. PR is activated at
the Logic 1 transition. Tie PR to VDD if not used.
22
23
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to Logic 1.
RDY
Ready. Active-high open-drain output. Identifies completion of Software Instruction 2, Software Instruction 3,
Software Instruction 8, Software Instruction 9, Software Instruction 10, and Hardware Instruction PR.
24
O2
Nonvolatile Digital Output 2. Address (O2) = 0x4, the data bit position is D1; defaults to Logic 1 initially.
Rev. B | Page 8 of 32
AD5233
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
0.05
0
0.20
T
T
T
= +25°C
= –40°C
= +85°C
A
A
A
T
T
T
= +25°C
= –40°C
= +85°C
A
A
A
0.15
0.10
0.05
0
V
= 5V, V = 0V
SS
DD
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
0
16
32
48
64
0
16
32
48
64
CODE (Decimal)
CODE (Decimal)
Figure 5. INL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ
Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ
0.20
3000
T
T
T
= +25°C
= –40°C
= +85°C
V
T
= 5V, V = 0V
SS
A
A
A
DD
= –40°C TO +85°C
A
0.15
0.10
0.05
0
2500
2000
1500
1000
500
–0.05
–0.10
–0.15
–0.20
0
0
16
32
48
64
0
16
32
CODE (Decimal)
48
64
CODE (Decimal)
Figure 6. DNL Error vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ
Figure 9. (∆RWB/RWB)/∆T × 106
0.20
300
200
100
0
T
T
T
= +25°C
= –40°C
= +85°C
V
T
V
V
= 5.5V, V = 0V
SS
= –40°C TO +85°C
= 2V
= 0V
A
A
A
DD
A
0.15
0.10
0.05
0
A
B
V
= 5V, V = 0V
SS
DD
–0.05
–0.10
–0.15
–0.20
0
16
32
48
64
0
16
32
CODE (Decimal)
48
64
CODE (Decimal)
Figure 10. (∆VW/VW)/∆T × 106 vs. Code, RAB = 10 kΩ
Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ
Rev. B | Page 9 of 32
AD5233
3
0
80
60
40
20
V
V
@ V = ±2.5V
SS
DD
= 1V rms
V
= 2.7V, V = 0V
SS
DD
= 25°C
A
T
A
D = MIDSCALE
f
= 66kHz
–3dB
–3
–6
–9
–12
f
= 600kHz, R
= 10kΩ
AB
–3dB
f
= 132kHz, R
= 50kΩ
AB
–3dB
0
0
1k
10k
100k
1M
16
32
CODE (Decimal)
48
64
FREQUENCY (Hz)
Figure 11. Wiper On Resistance vs. Code
Figure 14. −3 dB Bandwidth vs. Resistance (Using the Circuit
Shown in Figure 31)
0.05
0.04
0.03
0.02
0.01
0
4
3
2
R
= 10kΩ
AB
I
@ V /V = 5V/0V
DD SS
DD
1
R
= 50kΩ
AB
I
@ V /V = 5V/0V
DD SS
SS
R
= 100kΩ
AB
0
I
@ V /V = 2.7V/0V
DD SS
V
V
/V = ±2.5V
DD SS
DD
I
@ V /V = 2.7V/0V
DD SS
= 1V rms
SS
A
–1
–40
10
100
1k
FREQUENCY (Hz)
10k
100k
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 15. Total Harmonic Distortion + Noise vs. Frequency
Figure 12. IDD vs. Temperature, RAB = 10 kΩ
0
0.30
0.25
0.20
0.15
0.10
0.05
V
V
= 5V
= 5V
DD
SS
CODE 0x20
FULL SCALE
–6
0x10
0x08
–12
–18
–24
–30
–36
–42
MIDSCALE
ZERO SCALE
0x04
0x02
0x01
0
0
100
1k
10k
100k
1M
10M
2
4
6
8
10
12
FREQUENCY (Hz)
CLOCK FREQUENCY (MHz)
Figure 16. Gain vs. Frequency vs. Code, RAB = 10 Ω ( Figure 31)
Figure 13. IDD vs. Clock Frequency, RAB = 10 kΩ
Rev. B | Page 10 of 32
AD5233
0
–6
CODE 0x20
V
V
V
= 5V
= 2.25V
= 0V
DD
A
B
0x10
0x08
V
A
–12
–18
–24
–30
–36
–42
V
W
0x04
0x02
EXPECTED
VALUE
MIDSCALE
0.5V/
DIV
0x01
100µs/DIV
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 20. Power-On Reset, VA = 2.25 V, VB = 0 V,
Code = 101010
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 31)
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
0
V
V
= V = 5V
A
DD
SS
CODE 0x20
–6
= V = 0V
B
CODE = 0x20 TO 0x1F
0x10
–12
0x08
–18
0x04
–24
0x02
–30
0x01
–36
–42
100
0
50
100 150 200 250 300 350 400 450 511
TIME (µs)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ ( Figure 31)
Figure 21. Midscale Glitch Energy, Code 0x20 to Code 0x1F
80
R
= 100kΩ
AB
70
60
50
40
30
20
10
0
5V/DIV
R
= 50kΩ
AB
CS
R
= 10kΩ
AB
5V/DIV
CLK
5V/DIV
SDI
V
V
= 5V ±100mV AC
= 0V, V = 5V, V = 0V
MEASURED AT V WITH CODE = 0x200
DD
SS
A
B
W
I
DD
20mA/
DIV
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
4ms/DIV
Figure 19. PSRR vs. Frequency
Figure 22. IDD vs. Time When Storing Data to EEMEM
Rev. B | Page 11 of 32
AD5233
100
10
V
T
= V = OPEN
B
= 25°C
A
A
5V/DIV
CS
CLK
SDI
5V/DIV
5V/DIV
R
= 10kΩ
AB
1
R
= 50kΩ
AB
I
*
DD
2mA/DIV
0.1
0.01
R
= 100kΩ
AB
4ms/DIV
*SUPPLY CURRENT RETURNS TO MINIMUM POWER
CONSUMPTION, IF INSTRUCTION 0 (NOP) IS EXECUTED
IMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM).
0
8
16
24
32
40
48
56
64
CODE (Decimal)
Figure 23. IDD vs. Time When Reading Data from EEMEM
Figure 24. IWB_MAX vs. Code
Rev. B | Page 12 of 32
AD5233
TEST CIRCUITS
Figure 25 to Figure 35 define the test conditions used in the specifications.
NC
A
DUT
B
DUT
A
I
W
5V
W
W
V
IN
B
OP279
V
OUT
OFFSET
GND
V
MS
OFFSET BIAS
NC = NO CONNECT
Figure 25. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 29. Inverting Gain
5V
OP279
V
OUT
V
IN
DUT
A
V+ = V
DD
1LSB = V+/2
N
W
W
OFFSET
GND
V+
A
DUT
B
B
V
MS
OFFSET BIAS
Figure 30. Noninverting Gain
Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL)
+15V
A
DUT
I
W
W
V
IN
A
DUT
V
W
W
OP42
B
V
OUT
V
MS2
OFFSET
GND
B
R
= [V
MS1
– V
]/I
MS2
2.5V
W
W
V
MS1
–15V
Figure 31. Gain vs. Frequency
Figure 27. Wiper Resistance
0.1V
R
=
SW
I
DUT
B
SW
V
A
CODE = 0x00
W
V+ = V ±10%
DD
+
–
ΔV
MS
0.1V
V
A
B
PSRR (dB) = 20 log
DD
I
(ΔV )
SW
W
DD
V+
ΔV
ΔV
%
MS
PSS (%/%) =
V
V
BIAS
MS
%
A = NC
DD
Figure 32. Incremental On Resistance
Figure 28. Power Supply Sensitivity (PSS, PSRR)
Rev. B | Page 13 of 32
AD5233
NC
200µA
I
OL
A
V
I
DD
CM
DUT
W
TO OUTPUT
PIN
V
(MIN)
OH
OR
V
GND
SS
B
C
50pF
V
L
CM
V
(MAX)
OL
NC
NC = NO CONNECT
200µA
I
OH
Figure 35. Load Circuit for Measuring VOH and VOL; the Diode Bridge Test
Circuit Is Equivalent to the Application Circuit with RPULL-UP of 2.2 kΩ
Figure 33. Common-Mode Leakage Current
V
DD
A1
A2
RDAC1
W1
RDAC2
W2
V
IN
NC
V
OUT
B1
B2
V
OUT
V
C
= 20 log
SS
NC = NO CONNECT
TA
(
)
V
IN
Figure 34. Analog Crosstalk
Rev. B | Page 14 of 32
AD5233
THEORY OF OPERATION
SCRATCHPAD AND EEMEM PROGRAMMING
The AD5233 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratchpad
register is loaded with all 0, the wiper is connected to Terminal
ꢀ of the variable resistor. The scratchpad register is a standard
logic register with no restriction on the number of changes
allowed, but the EEMEM registers have a program erase/write
cycle limitation (see the Flash/EEMEM Reliability section).
remain within the terminal voltage range of VSS < VTERM < VDD
The basic voltage range is limited to VDD − VSS < 5.5 V. The
digital potentiometer wiper position is determined by the
RDAC register contents.
.
The RDAC register acts as a scratchpad register, allowing as
many value changes as necessary to place the potentiometer
wiper in the correct position. The scratchpad register can be
programmed with any position value using the standard SPI
serial interface mode by loading the complete representative
data-word. Once a desirable position is found, this value can be
stored in an EEMEM register. Thereafter, the wiper position is
always restored to that position for subsequent power-up.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11,
Address A1, Address A0, and the desired wiper position
data. When the proper wiper position is determined, the
user can load the serial data input register with Instruction 2,
which stores the wiper position data in the EEMEM register.
After 25 ms, the wiper position is permanently stored in the
nonvolatile memory location. Table 5 provides a programming
example listing the sequence of serial data input (SDI) words
with the serial data output appearing at the SDO pin in
hexadecimal format.
The EEMEM data storing process takes approximately 25 ms;
during this time, the shift register is locked, preventing any
changes from taking place. The RDY pin pulses low to indicate
the completion of this EEMEM storage.
The following instructions facilitate the user’s programming
needs (see Table 7 for details):
0 = Do nothing.
Table 5. Set and Store RDAC Data to EEMEM Register
1 = Restore EEMEM contents to RDAC.
2 = Store RDAC setting to EEMEM.
3 = Store RDAC setting or user data to EEMEM.
4 = Decrement 6 dꢀ.
SDI
SDO
Action
0xB010 0xXXXX Writes Data 0x10 to the RDAC1 register,
Wiper W1 moves to ¼ full-scale position.
0x20XX 0xB010 Stores RDAC1 register content into the
EEMEM1 register.
5 = Decrement all 6 dꢀ.
At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the EEMEM
register. The factory-preset EEMEM value is midscale, but it
can be changed by the user thereafter.
6 = Decrement one step.
7 = Decrement all one step.
8 = Reset EEMEM contents to RDACs.
9 = Read EEMEM contents from SDO.
10 = Read RDAC wiper setting from SDO.
11 = Write data to RDAC.
During operation, the scratchpad (RDAC) register can be
refreshed with the EEMEM register data with Instruction 1 or
Instruction 8. The RDAC register can also be refreshed with the
PR
EEMEM register data under hardware control by pulsing the
PR
pin. The
pulse first sets the wiper at midscale when brought
12 = Increment 6 dꢀ.
to Logic 0, and then, on the positive transition to Logic 1, it
reloads the RDAC wiper register with the contents of EEMEM.
13 = Increment all 6 dꢀ.
14 = Increment one step.
Many additional advanced programming commands are
available to simplify the variable resistor adjustment process
(see Table 7). For example, the wiper position can be changed
one step at a time using the increment/decrement instruction or
by 6 dꢀ with the shift left/right instruction. Once an increment,
decrement, or shift instruction has been loaded into the shift
15 = Increment all one step.
CS
register, subsequent
strobes can repeat this command.
A serial data output SDO pin is available for daisy-chaining and
for readout of the internal register contents.
Rev. B | Page 15 of 32
AD5233
PR
WP
EEMEM PROTECTION
VALID
COMMAND
WP
The write protect (
) pin disables any changes to the
COMMAND
PROCESSOR
AND ADDRESS
DECODE
5V
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
COUNTER
PR
WP
and the
hardware EEMEM protection feature. To disable
recommended to execute a NOP instruction before returning
WP
pulse. Therefore,
can be used to provide a
R
PULL-UP
(FOR DAISY
CHAIN ONLY)
CLK
SERIAL
REGISTER
WP
, it is
SDO
GND
to Logic 1.
CS
DIGITAL INPUT/OUTPUT CONFIGURATION
SDI
AD5233
Figure 36. Equivalent Digital Input-Output Logic
All digital inputs are ESD-protected, high input impedance
that can be driven directly from most digital sources. Active at
The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
PR
WP
Logic 0,
and
must be tied to VDD if they are not used.
No internal pull-up resistors are present on any digital input
pins. ꢀecause the device can be detached from the driving
source once it is programmed, adding pull-up resistance on
the digital input pins is a good way to avoid falsely triggering
the floating pins in a noisy environment.
CS
chip select ( ) is in Logic 1. The SPI interface can be used
in two slave modes: CPHA = 1, CPOL = 1 and CPHA = 0,
CPOL = 0. CPHA and CPOL refer to the control bits that
dictate SPI timing in the following MicroConverters® and
microprocessors: ADuC812, ADuC824, M68HC11, and
MC68HC16R1/MC68HC916R1. ESD protection of the
digital inputs is shown in Figure 37 and Figure 38.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. Use a
resistor in the range of 1 kΩ to 10 kΩ to balance the power
and switching speed trade-off.
V
DD
SERIAL DATA INTERFACE
INPUT
300Ω
The AD5233 contains a 4-wire SPI-compatible digital interface
LOGIC
PINS
CS
(SDI, SDO, , and CLK). It uses a 16-bit serial data-word
loaded MSꢀ first. The format of the SPI-compatible word is
CS
shown in Table 6. The chip-select
pin must be held low until
CS
the complete data-word is loaded into the SDI pin. When
GND
returns high, the serial data-word is decoded according to the
instructions in Table 7. The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are
the values that are loaded into the decoded register. To program
RDAC1 to RDAC4, only the 6 LSꢀ data bits are used.
Figure 37. Equivalent ESD Digital Input Protection
V
DD
INPUT
300Ω
WP
The AD5233 has an internal counter that counts a multiple
of 16 bits (a frame) for proper operation. For example, the
AD5233 works with a 32-bit word, but it cannot work properly
with a 15-bit or 17-bit word. In addition, the AD5233 has a
GND
CS
subtle feature that, if
is pulsed without CLK and SDI, the
WP
Figure 38. Equivalent
Input Protection
part repeats the previous command (except during power-up).
As a result, care must be taken to ensure that no excessive noise
CS
exists in the CLK or line that might alter the effective number-
of-bits pattern. Also, to prevent data from locking incorrectly
(due to noise, for example), the counter resets, if the count is
CS
not a multiple of four when
goes high.
Rev. B | Page 16 of 32
AD5233
The ground pin of the AD5233 device is used primarily as a
DAISY-CHAIN OPERATION
digital ground reference, which needs to be tied to the PCꢀ’s
common ground. The digital input control signals to the
AD5233 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
The serial data output (SDO) pin serves two purposes. It can
be used to read the contents of the wiper setting and EEMEM
values using Instruction 10 and Instruction 9, respectively.
The remaining instructions (0 to 8, 11 to 15) are valid for
daisy-chaining multiple devices in simultaneous operations.
Daisy-chaining minimizes the number of port pins required
from the controlling IC (Figure 39). The SDO pin contains an
open-drain N-channel FET that requires a pull-up resistor, if
this function is used. As shown in Figure 39, users need to tie
the SDO pin of one package to the SDI pin of the next package.
voltage range of the three terminals extends from VSS to VDD
,
regardless of the digital input level.
POWER-UP SEQUENCE
ꢀecause there are diodes to limit the voltage compliance at
Terminal A, Terminal ꢀ, and Terminal W (see Figure 40), it is
important to power on VDD/VSS first before applying any voltage
to Terminal A, Terminal ꢀ, and Terminal W. Other wise, the
diode is forward-biased such that VDD/VSS are powered unin-
tentionally. For example, applying 5 V across the A and ꢀ
terminals prior to VDD causes the VDD terminal to exhibit 4.3 V.
It is not destructive to the device, but it might affect the rest of
the system. The ideal power-up sequence is GND, VDD, VSS,
digital inputs, and VA/Vꢀ/VW. The order of powering VA, Vꢀ,
VW, and digital inputs is not important as long as they are
powered after VDD/VSS.
Users might need to increase the clock period, because the
pull-up resistor and the capacitive loading at the SDO to SDI
interface might require an additional time delay between
subsequent packages. When two AD5233s are daisy-chained,
32 bits of data is required. The first 16 bits go to U2 and the
CS
second 16 bits go to U1.
should be kept low until all 32 bits
CS
are clocked into their respective serial registers.
is then
pulled high to complete the operation.
+V
AD5233
R
2kΩ
AD5233
P
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on preset
remains effective, which restores the EEMEM values to the
RDAC registers.
MICRO-
CONTROLLER
SDI
SDO
SDI
U1 SDO
U2
CS
CLK
CLK
CS
LATCHED DIGITAL OUTPUTS
A pair of digital outputs, O1 and O2, is available on the AD5233.
These outputs provide a nonvolatile Logic 0 or Logic 1 setting.
O1 and O2 are standard CMOS logic outputs, shown in Figure 41.
These outputs are ideal to replace the functions often provided
by DIP switches. In addition, they can be used to drive other
standard CMOS logic-controlled parts that need an occasional
setting change. Pin O1 and Pin O2 default to Logic 1, and they
can drive up to 50 mA of load at 5 V/25°C.
Figure 39. Daisy-Chain Configuration Using SDO
TERMINAL VOLTAGE OPERATION RANGE
The AD5233’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal ꢀ, and Terminal W that exceed VDD or VSS are clamped
by the internal forward-biased diodes (see Figure 40).
V
V
DD
DD
OUTPUTS
A
O1 AND O2
PINS
W
B
GND
Figure 41. Logic Output O1 and Logic Output O2
V
SS
Figure 40. Maximum Terminal Voltages Set by VDD and VSS
Rev. B | Page 17 of 32
AD5233
In Table 6, C0 to C3 are command bits, A3 to A0 are address bits, D0 to D5 are data bits that are applicable to the RDAC wiper register,
and D0 to D7 are applicable to the EEMEM register.
Table 6. 16-Bit Serial Data-Word
MSB
Instruction Byte
LSB
A0
Data Byte
RDAC
EEMEM
C3
C3
C2
C2
C1
C1
C0
C0
0
0
A1
A1
X
X
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
A3
A2
A0
D7
D6
Command instruction codes are defined in Table 7.
Table 7. Instruction/Operation Truth Table1, 2, 3
Instruction Byte 0
Data Byte 0
B16
C3
0
B8
B7
B6
D6
X
B5
B4
D4
X
B3
D3
X
B2
B1
B0
Inst.
No.
C2
C1
C0
A3 A2 A1 A0 D7
D5
D2
D1
D0
Operation
0
0
0
0
X
0
X
0
X
X
X
X
X
X
X
X
NOP: Do nothing. See Table 14 for
programming example.
1
0
0
0
1
A1
A0
X
X
X
X
X
X
X
Restore EEMEM contents to the RDAC
register. This command leaves the device
in read program power state. To return
the part to the idle state, perform NOP
instruction 0. See Table 14.
2
0
0
0
0
1
1
0
1
0
0
A1
A1
A0
A0
X
X
X
X
X
X
X
X
Store wiper setting: Store RDAC (ADDR)
setting to EEMEM. See Table 13.
34
A3
A2
D7
D6
D5
D4
D3
D2
D1
D0
Store contents of Serial Register Data
Byte 0 (total eight bits) to EEMEM
(ADDR). See Table 16.
45
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
X
0
X
X
0
X
0
X
X
A1
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Decrement 6 dB: right-shift contents of
RDAC register, stop at all 0s.
55
65
75
8
Decrement all 6 dB: right-shift contents
of all RDAC registers, stop at all 0s.
A1
X
A0
X
Decrement content of RDAC register
by 1, stop at all 0s.
Decrement contents of all the RDAC
registers by 1, stop at all 0s.
X
X
Reset: refresh all RDACs with their
corresponding EEMEM previously
stored values.
9
1
0
0
1
A3
A2
A1
A0
X
X
X
X
X
X
X
X
Read content of EEMEM (ADDR) from
SDO output in the next frame. See
Table 17.
10
11
1
1
0
0
1
1
0
1
0
0
0
0
A1
A1
A0
A0
X
X
X
X
X
X
X
X
X
X
Read RDAC wiper setting from SDO
output in the next frame. See Table 18.
D5
D4
D3
D2
D1
D0
Write contents of Serial Register Data
Byte 0 (total six bits) to RDAC. See
Table 12.
125
1
1
0
0
0
0
A1
A0
X
X
X
X
X
X
X
X
Increment 6 dB: Left-shift contents of
RDAC register, stop at all 1s. See
Table 15.
135
145
1
1
1
1
0
1
1
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Increment all 6 dB: left-shift contents of
RDAC registers, stop at all 1s.
A1
A0
Increment contents of the RDAC
register by 1, stop at all 1s. See
Table 13.
155
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
Increment contents of all RDAC
registers by 1, stop at all 1s.
1 The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, see details of these instructions for proper usage.
2 The RDAC register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvolatile EEMEM register.
3 Execution of these operations takes place when the strobe returns to Logic 1.
CS
4 Instruction 3 writes one data byte (eight bits of data) to EEMEM. In the case of Address 0, Address 1, Address 2, and Address 3, only the last six bits are valid for wiper
position setting.
5 The increment, decrement, and shift instructions ignore the contents of the Shift Register Data Byte 0.
Rev. B | Page 18 of 32
AD5233
data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.
ADVANCED CONTROL MODES
The AD5233 digital potentiometer includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
The right-shift 4 and 5 instructions are ideal only if the LSꢀ is
0 (ideal logarithmic = no error). If the LSꢀ is a 1, the right-shift
function generates a linear half-LSꢀ error, which translates to
a number-of-bits-dependent logarithmic error, as shown in
Figure 42. The plot shows the error of the odd numbers of bits
for the AD5233.
Key programming features include
•
•
Scratchpad programming to any desirable values
Nonvolatile memory storage of the scratchpad RDAC
register value in the EEMEM register
•
•
•
Increment and decrement instructions for the RDAC
wiper register
Left- and right-bit shift of the RDAC wiper register to
achieve 6 dꢀ level changes
Table 8. Detail Left-Shift and Right-Shift Functions for
6 dB Step Increment and Decrement
Left-Shift
(+6 dB/Step)
Right-Shift
(–6 dB/Step)
Eleven extra bytes of user-addressable nonvolatile memory
00 0000
00 0001
00 0010
00 0100
00 1000
01 0000
10 0000
11 1111
11 1111
11 1111
01 1111
00 1111
00 0111
00 0011
00 0001
00 0000
00 0000
00 0000
Linear Increment and Decrement Instructions
The increment and decrement instructions (14, 15, 6, and 7)
are useful for linear step-adjustment applications. These com-
mands simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device.
For an increment command, executing Instruction 14 with
the proper address automatically moves the wiper to the next
resistance segment position. Instruction 15 performs the same
function, except that the address does not need to be specified.
All RDACs are changed at the same time.
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of log error [20 × log10 (error/
code)] for the AD5233. For example, Code 3 log error = 20 ×
log10 (0.5/3) = −15.56 dꢀ, which is the worst-case scenario. The
plot of log error is more significant at the lower codes.
0
Logarithmic Taper Mode Adjustment
Four programming instructions produce logarithmic taper
increment and decrement of the wiper. These settings are
activated by the 6 dꢀ increment and 6 dꢀ decrement instruc-
tions (12, 13, 4, and 5). For example, starting at zero scale,
executing the increment Instruction 12 seven times moves
the wiper in 6 dꢀ per step from 0% to full scale, RAꢀ. The 6 dꢀ
increment instruction doubles the value of the RDAC register
contents each time the command is executed. When the wiper
position is near the maximum setting, the last 6 dꢀ increment
instruction causes the wiper to go to the full-scale 6310 code
position. Further 6 dꢀ per increment instructions do not
change the wiper position beyond its full scale.
–10
–20
–15.56dB @ CODE 3
–30
–40
The 6 dꢀ step increments and 6 dꢀ step decrements are achieved
by shifting the bit internally to the left or right, respectively.
The following information explains the nonideal 6 dꢀ step
adjustment under certain conditions. Table 8 illustrates the
operation of the shifting function on the RDAC register data
bits. Each table row represents a successive shift operation.
Note that the left-shift 12 and 13 instructions were modified
such that, if the data in the RDAC register is equal to zero and
the data is shifted left, the RDAC register is then set to Code 1.
Similarly, if the data in the RDAC register is greater than or
equal to midscale and the data is shifted left, then the
–50
0
5
10 15 20 25 30 35 40 45 50 55 60 65
CODE (Decimal)
Figure 42. Plot of Log Error Conformance for Odd Numbers of Bits Only (Even
Numbers of Bits are Ideal)
Rev. B | Page 19 of 32
AD5233
SW
A
Using Additional Internal Nonvolatile EEMEM
A
The AD5233 contains additional user EEMEM registers for
storing any 8-bit data. Table 9 provides an address map of the
internal storage registers shown in the functional block diagram
as EEMEM1, EEMEM2, and 11 bytes of user EEMEM.
N
SW(2 – 1)
W
R
S
RDAC
WIPER
N
SW(2 – 2)
REGISTER
AND
Table 9. EEMEM Address Map
DECODER
EEMEM Number Address
EEMEM Content
RDAC11, 2
RDAC21, 2
RDAC31, 2
RDAC41, 2
O1 and O23
USER14
USER2
…
USER10
USER11
SW
(1)
R
R
S
1
2
3
4
5
6
7
…
15
16
0000
0001
0010
0011
0100
0101
0110
…
S
SW
(0)
N
R
= R /2
S
AB
DIGITAL
SW
B
CIRCUITRY
OMITTED FOR
CLARITY
B
Figure 43. Equivalent RDAC Structure
1110
1111
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
1 RDAC data stored in the EEMEM location is transferred to the RDAC register
at power-on, or when Instruction 1, Instruction 8, and are executed.
The nominal resistance of the RDAC between Terminal A
and Terminal ꢀ, RAꢀ, is available with 10 kΩ, 50 kΩ, and 100 kΩ
with 64 positions (6-bit resolution). The final digit(s) of the part
number determine the nominal resistance value, for example,
10 = 10 kΩ; 50 = 50 kΩ; 100 = 100 kΩ.
PR
2 Execution of Instruction 1 leaves the device in the read mode power
consumption state. After the last Instruction 1 is executed, the user
should perform a NOP, Instruction 0, to return the device to the low
power idling state.
3 O1 and O2 data stored in EEMEM locations is transferred to the corresponding
digital register at power-on, or when Instruction 1 and Instruction 8 are
executed.
The 6-bit data-word in the RDAC latch is decoded to select
one of the 64 possible settings. The following discussion
describes the calculation of resistance (RWꢀ) at different codes
of a 10 kΩ part. For VDD = 5 V, the wiper’s first connection
starts at Terminal ꢀ for Data 0x00. RWꢀ(0) is 15 Ω because of
the wiper resistance and because it is independent of the nominal
resistance. The second connection is the first tap point, where
4 USERx are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 8-bit information using Instruction 3 and
Instruction 9, respectively.
RDAC STRUCTURE
The patent-pending RDAC contains multiple strings of equal
resistor segments, with an array of analog switches that act as
the wiper connection. The number of positions is the resolution
of the device. The AD5233 has 64 connection points, allowing it
to provide better than 1.5% set ability resolution. Figure 43
shows an equivalent structure of the connections between the
three terminals of the RDAC. The SWA and SWꢀ are always on,
while the switches, SW(0) to SW(2N−1), are on, one at a time,
depending on the resistance position decoded from the data
bits. ꢀecause the switch is not ideal, there is a 15 Ω wiper
resistance, RW. Wiper resistance is a function of supply voltage
and temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if an accurate
prediction of the output resistance is needed.
R
Wꢀ(1) becomes 156 Ω + 15 Ω = 171 Ω for Data 0x01. The third
connection is the next tap point, representing RWꢀ(2) = 321 Ω +
15 Ω = 327 Ω for Data 0x02, and so on. Each LSꢀ data value
increase moves the wiper up the resistor ladder until the last
tap point is reached at RWꢀ(63) = 9858 Ω. See Figure 43 for a
simplified diagram of the equivalent RDAC circuit. When RWꢀ
is used, Terminal A can be left floating or tied to the wiper.
100
R
R
WB
WA
75
50
25
0
0
16
32
48
64
CODE (Decimal)
Figure 44. RWA(D) and RWB(D) vs. Decimal Code
Rev. B | Page 20 of 32
AD5233
The general equation that determines the programmed output
resistance between W and ꢀ is
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
D
64
The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to
the input voltages applied to Terminal A and Terminal ꢀ. For
example, connecting Terminal A to 5 V and Terminal ꢀ to
ground produces an output voltage at the wiper that can be
any value from 0 V to 5 V. Each LSꢀ of voltage is equal to the
voltage applied across Terminal A and Terminal ꢀ divided
by the 2N position resolution of the potentiometer divider.
R
WB (D) = ×RAB + RW
(1)
where:
D is the decimal equivalent of the data contained in the RDAC
register.
RAB is the nominal resistance between Terminal A and Terminal ꢀ.
RW is the wiper resistance.
For example, the output resistance values in Table 10 are set for
ꢀecause AD5233 can also be supplied by dual supplies, the
general equation defining the output voltage at VW with respect
to ground for any given input voltages applied to the A and ꢀ
terminals is
the given RDAC latch codes with VDD = 5 V (applies to RAꢀ
10 kΩ digital potentiometers).
=
Table 10. RWB(D) at Selected Codes for RAB = 10 kΩ
D (Decimal) RWB(D) (Ω) Output State
D
64
VW (D) = ×VAB +VB
(3)
63
32
1
9858
5015
171
15
Full scale
Midscale
1 LSB
Equation 3 assumes that VW is buffered so that the effect of
wiper resistance is minimized. Operation of the digital potenti-
ometer in divider mode results in more accurate operation over
temperature. Here, the output voltage is dependent on the ratio
of the internal resistors and not the absolute value; therefore,
the drift improves to 15 ppm/°C. There is no voltage polarity
restriction among the A, ꢀ, and W terminals as long as the
terminal voltage (VTERM) stays within VSS < VTERM < VDD.
0
Zero scale (wiper contact resistor)
Note that in the zero-scale condition a finite wiper resistance of
15 Ω is present. Care should be taken to limit the current flow
between W and ꢀ in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Like the mechanical potentiometer that the RDAC replaces, the
AD5233 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, RWA . Figure 44 shows the symmetrical
programmability of the various terminal connections. When
PROGRAMMING EXAMPLES
The following programming examples illustrate a typical
sequence of events for various features of the AD5233. See
Table 7 for the instructions and data-word format. The
instruction numbers, addresses, and data appearing at the
SDI and SDO pins are in hexadecimal format.
RWA is used, Terminal ꢀ can be left floating or tied to the wiper.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value.
Table 12. Scratchpad Programming
SDI
SDO
Action
The general transfer equation for this operation is
0xB010
0xXXXX
Writes Data 0x10 into RDAC register,
Wiper W1 moves to ¼ full-scale position.
64 − D
64
RWA (D) =
× RAB + RW
(2)
Table 13. Incrementing RDAC1 Followed by Storing the
Wiper Setting to EEMEM1
For example, the output resistance values in Table 11 are set for
the RDAC latch codes with VDD = 5 V (applies to RAꢀ = 10 kΩ
digital potentiometers).
SDI
SDO
Action
0xB010
0xXXXX
Writes Data 0x10 into RDAC register,
Wiper W1 moves to ¼ full-scale
position.
Table 11. RWA(D) at Selected Codes for RAB = 10 kΩ
D (Decimal)
RWA(D) (Ω)
Output State
Full scale
Midscale
1 LSB
0xE0XX
0xE0XX
0xB010
0xE0XX
Increments the RDAC register by one
to 0x11.
Increments the RDAC register by one
to 0x12. Continues until desired wiper
position is reached.
63
32
1
171
5015
9858
0
10015
Zero scale
0x20XX
0xXXXX
Stores the RDAC register data into
EEMEM1. Optionally tie WP to GND to
protect EEMEM values.
Channel-to-channel RAꢀ matching is better than 1%. The
change in RAꢀ with temperature has a 600 ppm/°C temperature
coefficient.
Rev. B | Page 21 of 32
AD5233
The EEMEM1 value for RDAC1 can be restored by power-on,
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of the following
four independent, sequential events:
PR
by strobing the
pin, or by programming, as shown in Table 14.
Table 14. Restoring the EEMEM1 Value to the
RDAC1 Register
•
•
•
•
Initial page erase sequence
Read/verify sequence
ꢀyte program sequence
Second read/verify sequence
SDI
SDO
Action
0x10XX
0xXXXX
Restores the EEMEM1 value to the
RDAC1 register.
0x00XX
0x10XX
NOP. Recommended step to minimize
power consumption.
During reliability qualification, Flash/EE memory is cycled
from 0x00 to 0x3F until a first fail is recorded, signifying the
endurance limit of the on-chip Flash/EE memory.
Table 15. Using Left-Shift by One to Increment 6 dB Step
SDI
SDO
Action
As indicated in the Specifications section, the AD5233
Flash/EE memory endurance qualification has been carried
out in accordance with JEDEC Specification A117 over the
industrial temperature range of −40°C to +85°C. The results
allow the specification of a minimum endurance figure over
supply and temperature of 100,000 cycles, with an endurance
figure of 700,000 cycles being typical of operation at 25°C.
0xC0XX
0xXXXX
Moves the wiper to double the present
data contained in the RDAC1 register.
Table 16. Storing Additional User Data in EEMEM
SDI
SDO
Action
0x35AA
0xXXXX
Stores Data 0xAA in the extra EEMEM6
location, USER1. (Allowable to address
in 11 locations with a maximum of
eight bits of data.)
Stores Data 0x55 in the extra EEMEM7
location USER2. (Allowable to address
in 11 locations with a maximum of
eight bits of data.)
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the AD5233 has
been qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 55°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its full specified retention lifetime every time the
Flash/EE memory is reprogrammed. It should also be noted
that retention lifetime, based on an activation energy of 0.6 eV,
derates with TJ as shown in Figure 45. For example, the data is
retained for 100 years at 55°C operation, but reduces to 15 years
at 85°C operation. ꢀeyond these limits, the part must be
reprogrammed so that the data can be restored.
0x3655
0x35AA
Table 17. Reading Back Data from Memory Locations
SDI
SDO
Action
0x95XX
0xXXXX
Prepares data read from USER1 EEMEM
location.
0x00XX
0x95AA
NOP Instruction 0 sends a 16-bit word
out of SDO, where the last eight bits
contain the contents of the USER1
location. The NOP command ensures
that the device returns to the idle
power dissipation state.
300
Table 18. Reading Back Wiper Settings
SDI SDO Action
250
200
0xB020 0xXXXX Writes RDAC1 to midscale.
0xC0XX 0xB020 Doubles RDAC1 from midscale to full scale
(left-shift instruction).
150
0xA0XX 0xC0XX Prepares reading the wiper setting from the
RDAC1 register.
ANALOG DEVICES
TYPICAL PERFORMANCE
AT T = 55°C
J
0xXXXX 0xA03F Reads back full-scale value from SDO.
100
50
0
FLASH/EEMEM RELIABILITY
The Flash/EE memory array on the AD5233 is fully qualified
for two key Flash/EE memory characteristics, Flash/EE memory
cycling endurance, and Flash/EE memory data retention.
40
50
60
70
80
90
100
110
T
JUNCTION TEMPERATURE (°C)
J
Figure 45. Flash/EE Memory Data Retention
Rev. B | Page 22 of 32
AD5233
APPLICATIONS INFORMATION
As a result, one can use the previous relationship and scale C2
as if R2 were at its maximum value. Doing this might over-
compensate and compromise the performance when R2 is
set at low values. On the other hand, it avoids the ringing or
oscillation at the worst case. For critical applications, C2 should
be found empirically to suit the need. In general, C2 in the
range of picofarads is usually adequate for the compensation.
BIPOLAR OPERATION FROM DUAL SUPPLIES
The AD5233 can be operated from dual supplies 2.5 V, which
enables control of ground-referenced ac signals or bipolar opera-
tion. AC signals as high as VDD/VSS can be applied directly
across Terminal A and Terminal ꢀ with output taken from
Terminal W. See Figure 46 for a typical circuit connection.
+2.5V
Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.
SS
CS
V
DD
V
DD
SCLK
CLK
SDI
MICRO-
CONVERTER
A
MOSI
±
2.5V p-p
±1.25V p-p
GND
W
B
HIGH VOLTAGE OPERATION
The digital potentiometer can be placed directly in the feedback
or input path of an op amp for gain control, provided that the
voltage across Terminal A and Terminal ꢀ, Terminal W and
Terminal A, or Terminal W and Terminal ꢀ does not exceed
|5 V|. When high voltage gain is needed, users should set a
fixed gain in an op amp operated at high voltage and let the
digital potentiometer control the adjustable input. Figure 48
shows a simple implementation.
GND
AD5233
V
SS
D = MIDSCALE
–2.5V
Figure 46. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION
A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 47.
C
C2
10pF
R
2R
R2
100kΩ
15V
B
A
R1
33.2kΩ
W
5V
–
+
V+
A2
V
O
C1
35pF
A
V
U1
O
V–
W
AD5233
0 TO 15V
V
B
i
Figure 47. Typical Noninverting Gain Amplifier
Figure 48. 5 V Voltage Span Control
When RDAC ꢀ terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a 0 for the
1/bO term with 20 dꢀ/dec, while a typical op amp GꢀP has
−20 dꢀ/dec characteristics. A large R2 and finite C1 can cause
this zero’s frequency to fall well below the crossover frequency.
Therefore, the rate of closure becomes 40 dꢀ/dec, and the
system as a 0° phase margin at the crossover frequency. The
output can ring or oscillate if an input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values; this is equivalent to a stop change at
the input.
Similarly, a compensation capacitor, C, might be needed to
dampen the potential ringing when the digital potentiometer
changes steps. This effect is prominent when stray capacitance
at the inverted node is augmented by a large feedback resistor.
Usually, a capacitor (C) of a few picofarads, is adequate to combat
the problem.
DAC
Figure 49 shows a unipolar 8-bit DAC using the AD5233. The
buffer is needed to drive various loads.
5V
AD5233
Depending on the op amp GꢀP, reducing the feedback
resistor might extend the zero’s frequency far enough to
overcome the problem. A better approach is to include a
compensation capacitor, C2, to cancel the effect caused by
C1. Optimum compensation occurs when R1 × C1 = R2 ×
C2. This is not an option because of the variation of R2.
1
U1
5V
3
V
V
IN OUT
A
B
W
V+
V
AD8601
V–
GND
O
2
AD1582
A1
Figure 49. Unipolar 8-Bit DAC
Rev. B | Page 23 of 32
AD5233
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
PROGRAMMABLE LOW-PASS FILTER
There are several ways to achieve bipolar gain. Figure 50 shows
one versatile implementation. Digital potentiometer, U1, sets
the adjustment range; therefore, the wiper voltage, VW2, can be
programmed between Vi and −KVi at a given U2 setting.
The AD5233 digital potentiometer can be used to construct a
second-order Sallen-Key low-pass filter, as shown in Figure 51.
C1
+2.5V
V
DD
R1
R2
U2
A2
A
B
A
B
V+
AD8601
V–
V+
OP2177
V–
V
i
AD5233
W2
B2
V
O
V
O
W
W
R
R
R2
R1
C
A2
U1
V
SS
B1
A1
C2
–2.5V
–KV
V
i
i
W1
V
DD
GANGED
TOGETHER
U1
V+
OP2177
Figure 51. Sallen-Key Low-Pass Filter
AD5233
V–
The design equations are
A1
V
SS
2
VO
Vi
ωO
ωO
Q
=
(6)
Figure 50. Bipolar Programmable Gain Amplifier
S2 +
S + ωO
2
Configuring A2 as a noninverting amplifier yields a linear
transfer function:
1
ωO
=
(7)
(8)
VO
Vi
R2
R1
D2
64
⎛
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
R1× R2 ×C1×C2
= 1 +
×
×(1 + K) − K
(4)
⎜
1
1
Q =
+
where:
R1× C1 R2 ×C2
K is the ratio of RWꢀ/RWA that is set by U1.
D is the decimal equivalent of the input code.
where:
Q is the Q factor.
VO is the resonant frequency.
R1 and R2 are RWꢀ1 and RWꢀ2, respectively.
In the simpler (and much more usual) case where K is 1, a
pair of matched resistors can replace U1. Equation 4 can be
simplified to
To achieve maximal flat bandwidth where Q is 0.707, let C1
be twice the size of C2 and let R1 equal R2. Users can first
select convenient values for the capacitors and then gang and
move R1 and R2 together to adjust the −3 dꢀ corner frequency.
Instruction 5, Instruction 7, Instruction 13, and Instruction 15
of the AD5233 make these changes simple to implement.
VO
Vi
2D
64
R2
R1
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
⎠
2
= 1+
×
−1
(5)
⎜
Table 19 shows the result of adjusting D with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 64-step resolution.
Table 19. Result of Bipolar Gain Amplifier
D
R1 = ∞, R2 = 0 R1 = R2
R2 = 9 × R1
0
−1
−0.5
0
0.5
0.968
−2
−1
0
−10
−5
0
16
32
48
63
1
5
1.937
9.680
Rev. B | Page 24 of 32
AD5233
Figure 53 shows the measured filter response at the band-pass
output as a function of the RDAC2 and RDAC3 settings, which
produce a range of center frequencies from 2 kHz to 20 kHz.
The filter gain response at the band-pass output is shown in
Figure 54. At a center frequency of 2 kHz, the gain is adjusted
over the −20 dꢀ to +20 dꢀ range, determined by RDAC1.
Circuit Q is adjusted by RDAC4 and RDAC1. Suitable op amps
for this application are OP4177, AD8604, OP279, and AD824.
40
PROGRAMMABLE STATE-VARIABLE FILTER
One of the standard circuits used to generate a low-pass, high-
pass, or band-pass filter is the state-variable active filter. The
AD5233 digital potentiometer allows full programmability
of the frequency, the gain, and the Q of the filter outputs.
Figure 52 shows a filter circuit using a 2.5 V virtual ground,
which allows a 2.5 V peak input and output swing. RDAC2
and RDAC3 set the low-pass, high-pass, and band-pass cutoff
and center frequencies, respectively. RDAC2 and RDAC3
should be programmed with the same data (as with ganged
potentiometers) to maintain the best Circuit Q.
–16
20k
20
0
RDAC4
R2
*
B
10kΩ
R1
10kΩ
V
IN
0.01µF
0.01µF
A3
RDAC1
A1
B
–20
–40
–60
–80
B
A2
B
RDAC2
A3
RDAC3
2.5V
LOW-PASS
BAND-PASS
HIGH-PASS
OP279 × 2
Figure 52. Programmable Stable-Variable Filter
20
100
1k
FREQUENCY (Hz)
10k
100k 200k
The transfer function of the band-pass filter is
Figure 53. Programmed Center Frequency Band-Pass Response
ωO
AO
S
VBP
Vi
Q
40
=
(9)
–19.01
2.0k
ωO
S2 +
S + ωO
2
Q
20
where AO is the gain.
0
For RWꢀ2(D2) = RWꢀ3(D3), R1 = R2, and C1 = C2:
1
–20
–40
–60
–80
ωO
=
(10)
RWB2C1
RWB1
RWA1
AO =
(11)
(12)
RWA4 RWB1
Q =
×
RWB4
R1
20
100
1k
FREQUENCY (Hz)
10k
100k 200k
Figure 54. Programmed Amplitude Band-Pass Response
Rev. B | Page 25 of 32
AD5233
digital potentiometer, with R and R´ set to 8.06 kΩ, 4.05 kΩ,
and 670 Ω, oscillation occurs at 8.8 kHz, 17.6 kHz, and
102 kHz, respectively (see Figure 56).
PROGRAMMABLE OSCILLATOR
In a classic Wien-bridge oscillator, shown in Figure 55, the
Wien network (R, R´, C, C´) provides positive feedback, while
R1 and R2 provide negative feedback. At the resonant frequency,
fO, the overall phase shift is zero, and the positive feedback
causes the circuit to oscillate. If the op amp is chosen with a
relatively high gain bandwidth product, the frequency response
of the op amp can be neglected.
1V/DIV
R = 8.06kΩ
f = 8.8kHz
1V/DIV
FREQUENCY
ADJUSTMENT
C'
R'
R = 4.05kΩ
f = 17.6kHz
2.2nF
10kΩ
VP
A
B
B
R
10kΩ
C
2.2nF
+2.5V
W
R = 670Ω
f = 102kHz
1V/DIV
W
A
V+
U1
OP1177
V–
V
O
Figure 56. Programmable Oscillation
R = R' = R2B = 1/4 AD5233
D1 = D2 = 1N4148
–2.5V
In both circuits (shown in Figure 51 and Figure 55), the
frequency tuning requires that both RDACs be adjusted to
the same settings. ꢀecause the two channels might be adjusted
one at a time, an intermediate state occurs that might not be
acceptable for some applications. Of course, the increment/
decrement all instructions (5, 7, 13, and 15) can be used.
Different devices can also be used in daisy-chain mode so that
parts can be programmed to the same setting simultaneously.
VN
R2A
2.1kΩ D1
R2B
10kΩ
D2
B
A
R1
1kΩ
W
AMPLITUDE
ADJUSTMENT
Figure 55. Programmable Oscillator with Amplitude Control
With R = R´, C = C´, and R2 = R2A||(R2ꢀ + RDIODE), the
oscillation frequency is
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
1
RC
1
ωO
=
or fO
=
(13)
(14)
(15)
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 57).
2πRC
where R is equal to RWA such that
64 − D
64
R =
RAB
V
V
OUT
IN
R
BIAS
AD5233
2N7002
At resonance, setting
C
C
SIGNAL
I
L
U2
A
B
W
R2
R1
V+
AD8601
V–
= 2
LD
balances the bridge. In practice, R2/R1 should be set slightly
larger than 2 to ensure that the oscillation can start. On the
other hand, the alternate turn-on of the diodes, D1 and D2,
ensures that R1/R2 is smaller than 2 momentarily and,
therefore, stabilizes the oscillation.
Figure 57. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-
channel FET N1. N1 power handling must be adequate to
dissipate (Vi − VO) × IL power. This circuit can source a
maximum of 100 mA with a 5 V supply.
Once the frequency is set, the oscillation amplitude can be
turned on by R2ꢀ, because
2
3
VO = ID R2B +VD
(16)
For precision applications, a voltage reference such as ADR421,
ADR03, or ADR370 can be applied at Terminal A of the digital
potentiometer.
where VO, ID, and VD are interdependent variables.
With proper selection of R2ꢀ, an equilibrium is reached such
that VO converges. R2ꢀ can be in series with a discrete resistor
to increase the amplitude, but the total resistance cannot be too
large or it saturates the output. In this configuration, R2ꢀ can be
adjusted from minimum to full scale with amplitude varied
from 0.6 V to 0.9 V. Using 2.2 nF for C and C´, 10 kΩ dual
Rev. B | Page 26 of 32
AD5233
PROGRAMMABLE CURRENT SOURCE
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
A programmable current source can be implemented with the
circuit shown in Figure 58.
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be
used (see Figure 59).
+5V
2
U1
R1
R2
V
S
0 TO (2.048 + V )
L
150kΩ
15kΩ
6
3
SLEEP OUTPUT
REF191
B
C1
C1
10pF
1µF
W
GND
4
+15V
V+
R
102Ω
A
S
–
+5V
V+
OP2177
–
AD5233
+2.5V
A
V–
+
R2B
50Ω
+15V
V+
A2
OP1177
U2
–2.048V TOV
L
+
+
AD5233
V–
–15V
V
L
B W
R
100Ω
V
L
OP2177
V–
L
–5V
I
R1
150kΩ
R2A
14.95kΩ
L
–
R
L
–2.5V
500Ω
A1
–15V
Figure 58. Programmable Current Source
I
L
REF191 is a unique low supply headroom precision reference
that can deliver the 20 mA needed at 2.048 V. The load current
is simply the voltage across Terminal ꢀ to Terminal W of the
digital potentiometer divided by RS.
Figure 59. Programmable Bidirectional Current Source
If the resistors are matched, the load current is
(
R2A + R2B
)
R1
R2B
The circuit is simple, but be aware that there are two issues.
First, dual-supply op amps are ideal, because the ground
potential of REF191 can swing from −2.048 V at zero scale
to VL at full scale of the potentiometer setting. Although the
circuit works under single supply, the programmable resolution
of the system is reduced. Second, the voltage compliance at VL
is limited to 2.5 V or equivalently a 125 Ω load. If higher voltage
compliance is needed, users can consider digital potentiometers
AD5260, AD5280, and AD7376. Figure 58 shows an alternative
circuit for high voltage compliance.
IL
=
×VW
(17)
R2ꢀ, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current-driving capability.
In this circuit, OP2177 delivers 5 mA in both directions, and
the voltage compliance approaches 15 V. Without C1, it can be
shown that the output impedance is
R1' × R2B (R1+ R2A)
ZO
=
(18)
R1× R2'−R1'(R2A + R2B)
ZO can be infinite if the R1´ and R2´ resistors match precisely
with R1 and R2A + R2ꢀ, respectively. On the other hand, ZO can
be negative if the resistors are not matched. As a result, C1 in
the range of 1 pF to 10 pF is needed to prevent oscillation from
the negative impedance.
To achieve higher current, such as when driving a high power
LED, the user can replace the U1 with an LDO, reduce RS, and
add a resistor in series with the AD5233’s A terminal. This
limits the potentiometer’s current and enhances the current
adjustment resolution.
RESISTANCE SCALING
AD5233 offers 10 kΩ, 50 kΩ, and 100 kΩ nominal resistance.
Users who need lower resistance but want to maintain the
number of adjustment steps can parallel multiple devices. For
example, Figure 60 shows a simple scheme of paralleling two
AD5233 channels. To adjust half the resistance linearly per step,
users need to program both devices concurrently with the same
settings.
V
DD
A1
B1
A2
B2
W1
W2
LD
Figure 60. Reduce Resistance by Half with Linear Adjustment Characteristics
Rev. B | Page 27 of 32
AD5233
In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 61, a proportionately lower voltage appears at
Terminal A to Terminal ꢀ. This translates into a finer degree of
precision because the step size at Terminal W is smaller.
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE MISMATCH CONSIDERATIONS
In a rheostat mode operation such as gain control (see Figure 64),
the tolerance mismatch between the digital potentiometer and
the discrete resistor can cause repeatability issues among various
systems. ꢀecause of the inherent matching of the silicon process,
it is practical to apply the dual- or multiple-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
all nonideal parameters become less sensitive to the system
variations.
V
DD
R3
A
W
R2
R1
B
0
Figure 61. Lowering the Nominal Resistance
The voltage can be found as follows:
(RAB || R2 )
R3 + RAB || R2 64
D
(19)
VW (D) =
×
× VDD
R2
B
A
W
Figure 60 and Figure 61 show that the digital potentiometer
steps change linearly. On the other hand, log taper adjustment
is usually preferred in applications such as audio control.
Figure 62 shows another type of resistance scaling. In this
configuration, the smaller the R2 with respect to R1, the
more the pseudo log taper characteristic of the circuit behaves.
C1
R1*
–
AD8601
V
O
+
V
i
U1
*REPLACED WITH ANOTHER
CHANNEL OF RDAC
V
i
A
V
Figure 64. Linear Gain Control with Tracking Resistance Tolerance
and Temperature Coefficient
O
R1
B
W
R2
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external load
dominate the ac characteristics of the RDACs. Configured as
a potentiometer divider, the −3 dꢀ bandwidth of the AD5233
(10 kΩ resistor) measures 370 kHz at half scale. Figure 14
provides the large signal bode plot characteristics. A parasitic
simulation model is shown in Figure 65.
Figure 62. Resistor Scaling with Pseudo Log Adjustment Characteristics
DOUBLING THE RESOLUTION
ꢀorrowing from Analog Devices’ patented RDAC segmentation
technique, the user can configure three channels of AD5233, as
shown in Figure 63. ꢀy paralleling a discrete resistor, RP (RP =
RAB/64), with RDAC3, the user can double the resolution of
AD5233 from 6 bits to 12 bits. One might think that moving
RDAC1 and RDAC2 together would form the coarse 6-bit
resolution, and then moving RDAC3 would form the finer
6-bit resolution. As a result, the effective resolution would
become 12 bits. However, the precision of this circuit remains
only 6-bit accurate and the programming can be complicated.
RDAC
10kΩ
A
B
C
C
B
A
35pF
35pF
C
W
35pF
W
V
A
Figure 65. RDAC Circuit Simulation Model for RDAC = 10 kΩ
A1
The following code provides a macromodel net list for the
10 kΩ RDAC:
RDAC1
A3
B1
RDAC3
W3
R
Listing I. spice model net list
P
.PARAM D = 64, RDAC = 10E3
*
.SUBCKT DPOT (A, W, B)
*
A2
RDAC2
B2
B3
CA
RWA
CW
RWB
CB
*
A
A
W
W
B
0
W
0
B
0
35E-12
{(1-D/64)* RDAC + 15}
35-12
{D/64 * RDAC + 15}
35E-12
Figure 63. Doubling AD5233 from 6 Bits to 12 Bits
.ENDS DPOT
Rev. B | Page 28 of 32
AD5233
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 66. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Description
RAB
(kΩ)
No. of
Channels
Temperature
Range
Package
Option
Ordering
Quantity
Model
Branding1
5233B10
5233B10
5233B10
5233B10
5233B50
5233B50
5233B50
5233B50
5233B100
5233B100
5233B100
5233B100
AD5233BRU10
4
4
4
4
4
4
4
4
4
4
4
4
10
10
10
10
50
50
50
50
100
100
100
100
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
AD5233BRU10-REEL7
AD5233BRUZ102
AD5233BRUZ10-R72
AD5233BRU50
AD5233BRU50-REEL7
AD5233BRUZ502
AD5233BRUZ50-R72
AD5233BRU100
AD5233BRU100-REEL7
AD5233BRUZ1002
AD5233BRUZ100-R72
1,000
1 Line 1 contains the model number. Line 2 contains the Analog Devices logo followed by the end-to-end resistance value. Line 3 contains the date code, YWW or
#YWW, for RoHS compliant parts.
2 Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
AD5233
NOTES
Rev. B | Page 30 of 32
AD5233
NOTES
Rev. B | Page 31 of 32
AD5233
NOTES
Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent
Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02794-0-5/08(B)
Rev. B | Page 32 of 32
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