AD5243BRM100-R2 [ADI]
IC 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer;
| 型号： | AD5243BRM100-R2 |
| 厂家： | 
ADI |
| 描述： | IC 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer 光电二极管 转换器 电阻器 |
| 文件： | 总16页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 256-Position I2C
Digital Potentiometer
Preliminary Technical Data
AD5243/AD5248
applications.
FEATURES
2-Channel, 256-position
All parts are guaranteed to operate over the extended
automotive temperature range of -40°C to +125°C.
End-to-end resistance 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) Package
Full read/write of wiper register
FUNCTIONAL BLOCK DIAGRAMS
Power-on preset to midscale
VDD
Extra package address decode pins AD0 and AD1(AD5248)
Single supply +2.7 V to +5.5 V
Low temperature coefficient 35 ppm/°C
Low power, IDD = 5 µA
A1
SCL
SDA
I2C INTERFACE
W1
Wide operating temperature –40°C to +125°C
Evaluation board available
B1
WIPER
REGISTER
1
A2
APPLICATIONS
WIPER
REGISTER
2
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
W2
B2
RF amplifier biasing
GND
Automotive electronics adjustment
Gain control and offset adjustment
Figure 1. AD5243
W1
B1
W2
B2
GENERAL OVERVIEW
The AD5243 & AD5248 provide a compact 3x4.9mm packaged
solution for dual 256 position adjustment applications. These
devices perform the same electronic adjustment function as a 3-
terminal mechanical potentiometer (AD5243) or a 2-terminal
variable resistor (AD5248). Available in four different end-to-
end resistance values (2.5k, 10k, 50k, 100k ) these low
temperature coefficient devices are ideal for high accuracy and
stability variable resistance adjustments. The wiper settings are
controllable through the I2C compatible digital interface. The
AD5248 has extra package address decode pins AD0 & AD1
allowing multiple parts to share the same I2C 2-wire bus on a
PCB.
VDD
RDAC
RDAC
REGISTER 2
REGISTER 1
GND
AD0
ADDRESS
DECODE
AD1
8
SDA
SCL
SERIAL INPUT
REGISTER
Figure 2. AD5248
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
The resistance between the wiper and either end point of the
fixed resistor varies linearly with respect to the digital code
transferred into the RDAC latch1.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Operating from a 2.7 to 5.5 volt power supply and consuming
less than 5µA allows for usage in portable battery operated
Rev. PrE5/12/03
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5243/AD5248
Preliminary Technical Data
TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ Version................................... 3
Level Shifting for Bidirectional Interface................................ 12
ESD Protection ........................................................................... 12
Terminal Voltage Operating Range.......................................... 12
Power-Up Sequence ................................................................... 13
Layout and Power Supply Bypassing ....................................... 13
Pin Configuration and Function Descriptions........................... 14
Pin Configuration ...................................................................... 14
Pin Function Descriptions ........................................................ 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
ESD Caution................................................................................ 15
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions
............................................................................................................. 5
Absolute Maximum Ratings1 .......................................................... 5
Typical Performance Characteristics ............................................. 6
Test Circuits....................................................................................... 7
I2C Interface....................................................................................... 8
Operation......................................................................................... 10
Programming the Variable Resistor ......................................... 10
Programming the Potentiometer Divider............................... 11
I2C Compatible 2-Wire Serial Bus............................................ 11
REVISION HISTORY
Revision 0: Initial Version
Rev. PrE 5/12/03 | Page 2 of 16
AD5243/AD5248
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION
(VDD = 5 V 10%, or 3 V 10%ꢀ VA = +VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
–1.8
–5
–30
0.2
0.ꢀ5 +5
+1.8
LSB
LSB
%
ppm/°C
Ω
+30
VAB = VDD, Wiper = no connect
35
50
120
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1.5
–1.5
0.1
0.6
15
–2.5
+2
+1.5
+1.5
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
–6
0
0
+6
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
45
60
Capacitance6 W
CW
pF
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
IDD_SD
ICM
VDD = 5.5 V
VA = VB = VDD/2
0.01
1
1
µA
nA
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
0.8
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
0.6
1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation8
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
5
0.2
V
µA
mW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
3
Power Supply Sensitivity
PSS
∆VDD = +5 V 10%,
Code = Midscale
0.02
0.05 %/%
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB
BW_5K
THDW
tS
RAB = 2.5 kΩ, Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA= 5 V, VB = 0 V, 1 LSB error
band
2.4
0.05
1
MHz
%
µs
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
eN_WB
RWB = 2.5 kΩ, RS = 0
4.5
nV/√Hz
Rev. PrE 5/12/03 | Page 3 of 16
AD5243/AD5248
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = 5 V 10%, or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
–1
–2
–30
0.1
0.25
+1
+2
+30
LSB
LSB
%
∆RAB/∆T
35
50
ppm/°C
Wiper Resistance
RW
VDD = 5 V
120
Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1
–1
0.1
0.3
15
–1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
–3
0
0
3
Zero-Scale Error
1
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to
GND, Code = 0x80
f = 1 MHz, measured to
GND, Code = 0x80
45
60
Capacitance6 W
CW
pF
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
IDD_SD
ICM
VDD = 5.5 V
VA = VB = VDD/2
0.01
1
1
µA
nA
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
0.8
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
0.6
1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation8
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
5
0.2
V
µA
mW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V,
3
V
DD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V 10%,
Code = Midscale
0.02
0.05 %/%
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = 5 V, VB = 0 V,
1 LSB error band
RWB = 5 kΩ, RS = 0
600/100/40
kHz
%
Total Harmonic Distortion
THDW
tS
0.05
2
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
µs
eN_WB
9
nV/√Hz
Rev. PrE 5/12/03 | Page 4 of 16
AD5243/AD5248
Preliminary Technical Data
TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V 10%, or +3V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 3.
Parameter
Symbol
Conditions
Min Typ1 Max Unit
I2C INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
400
kHz
µs
µs
1.3
0.6
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
t5
t6
tꢀ
t8
t9
t10
1.3
0.6
0.6
µs
µs
µs
µs
ns
ns
ns
µs
50
0.9
100
0.6
300
300
NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagrams for locations of measured values.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4.
Stresses above those listed under Absolute Maximum Ratings
Parameter
VDD to GND
VA, VB, VW to GND
Value
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
–0.3 V to +ꢀ V
VDD
1
IMAX
20 mA
Digital Inputs and Output Voltage to GND 0 V to +ꢀ V
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
–40°C to +125°C
)
150°C
–65°C to +150°C
300°C
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
230°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA
.
Rev. PrE 5/12/03 | Page 5 of 16
AD5243/AD5248
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Rev. PrE 5/12/03 | Page 6 of 16
AD5243/AD5248
Preliminary Technical Data
TEST CIRCUITS
Figure 3 to Figure 11 illustrate the test circuits that define the
test conditions used in the product specification tables.
5V
OP279
V
DUT
A
V+ = V
DD
1LSB = V+/2
OUT
N
V
IN
W
W
V+
OFFSET
GND
B
A
DUT
B
V
MS
OFFSET
BIAS
Figure 3. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 8. Test Circuit for Noninverting Gain
NO CONNECT
DUT
A
+15V
I
W
W
A
V
DUT
IN
W
AD8610
–15V
V
OUT
OFFSET
GND
B
B
V
MS
2.5V
Figure 9. Test Circuit for Gain vs. Frequency
Figure 4. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
0.1V
SW
R
=
SW
I
DUT
DUT
CODE = 0x00
I
= V /R
NOMINAL
DD
W
W
A
V
W
W
V
MS2
B
0.1V
I
SW
B
V
R
= [V
– V
]/I
MS2
W
MS1
W
MS1
V
TO V
DD
SS
Figure 5. Test Circuit for Wiper Resistance
Figure 10. Test Circuit for Incremental ON Resistance
V
A
NC
V+ = V
PSRR (dB) = 20 LOG
10%
DD
∆V
∆V
MS
DD
(
)
V
DD
A
I
V
A
B
%
CM
∆V
∆V
DUT
GND
DD
MS
W
V+
W
PSS (%/%) =
%
DD
B
V
SS
V
V
MS
CM
NC NC = NO CONNECT
Figure 6. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 11. Test Circuit for Common-Mode Leakage current
A
B
DUT
5V
W
V
IN
OP279
V
OUT
OFFSET
GND
OFFSET
BIAS
Figure 7. Test Circuit for Inverting Gain
Rev. PrE 5/12/03 | Page ꢀ of 16
AD5243/AD5248
I2C INTERFACE
Preliminary Technical Data
Table 5. Write Mode
AD5243
S
0
1
1
0
1
1
1
1
W
A
A0 SD
A0 SD
X
X
X
X
X
X
X
X
A
A
Dꢀ D6 D5 D4 D3 D2 D1 D0
Data Byte
A
A
P
P
Slave Address Byte
Instruction Byte
AD5248
S
0
0
1
1
AD1 AD0 W
A
X
X
X
X
Dꢀ D6 D5 D4 D3 D2 D1 D0
Data Byte
Slave Address Byte
Instruction Byte
Table 6. Read Mode
AD5243
S
0
1
0
1
1
1
1
R
R
A
A
Dꢀ D6 D5 D4 D3 D2 D1 D0
Data Byte
A
A
P
P
Slave Address Byte
AD5248
S
0
1
0
1
1
AD1 AD0
Dꢀ D6 D5 D4 D3 D2 D1 D0
Data Byte
Slave Address Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
A0 = RDAC sub address select bit
SD = Shutdown connects wiper to B terminal and open
circuits A terminal. It does not change contents of wiper
register.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits
W
= Write
R = Read
Rev. PrE 5/12/03 | Page 8 of 16
AD5243/AD5248
Preliminary Technical Data
t2
t8
t9
SCL
t6
t7
t5
t10
t2
t3
t4
t9
t8
SDA
t1
P
S
S
P
Figure 12. I2C Interface Detailed Timing Diagram
1
9
1
9
1
9
SCL
SDA
0
1
0
1
1
1
1
R/W
A0
SD
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5243
ACK BY
AD5243
ACK BY
AD5243
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
STOP BY
START BY
MASTER
DATA BYTE
MASTER
Figure 13. Writing to the RDAC Register – AD5243
1
9
1
9
1
9
SCL
SDA
0
1
0
1
1
AD1 AD0 R/W
A0
SD
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5248
ACK BY
AD5248
ACK BY
AD5248
FRAME 1
FRAME 2
INSTRUCTION BYTE
FRAME 3
STOP BY
START BY
MASTER
SLAVE ADDRESS BYTE
DATA BYTE
MASTER
Figure 14. Writing to the RDAC Register – AD5248
1
9
1
9
SCL
0
1
0
1
1
1
1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
SDA
ACK BY
AD5243
NO ACK
BY MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
START BY
MASTER
STOP BY
MASTER
Figure 15. Reading Data from a Previously Selected RDAC Register in Write Mode – AD5243
1
9
1
9
SCL
SDA
0
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5248
NO ACK
BY MASTER
STOP BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
START BY
MASTER
Figure 16 Reading Data from a Previously Selected RDAC Register in Write Mode – AD5248
Rev. PrE 5/12/03 | Page 9 of 16
AD5243/AD5248
OPERATION
Preliminary Technical Data
The AD5243/48 is a 256-position digitally controlled variable
resistor (VR) device.
D
R
WB (D) =
×RAB +RW
(1)
256
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB will be set for the
indicated RDAC latch codes.
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 kΩ = 10ꢀ 50 kΩ = 50. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings. Assume a 10 kΩ part is used, the wiper’s first
Table 7. Codes and Corresponding RWB Resistance
D (Dec.)
RWB (Ω)
9,961
5,060
99
Output State
255
128
1
Full Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
0
60
Zero Scale (Wiper Contact Resistance)
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such connection yields a
minimum of 60 Ω resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for data 0x01.
The third connection is the next tap point, representing 138 Ω
(2 × 39 Ω + 60 Ω) for data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 9961 Ω (RAB – 1 LSB + RW). Figure 17 shows
a simplified diagram of the equivalent RDAC circuit where the
last resistor string will not be accessedꢀ therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.
Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
A
256 − D
256
SD BIT
RS
R
WA (D) =
×RAB + RW
(2)
D7
D6
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA will be set for the indicated
RDAC latch codes.
RS
D5
D4
D3
D2
RS
D1
D0
W
Table 8. Codes and Corresponding RWA Resistance
RDAC
D (Dec.)
RWA (Ω)
Output State
Full Scale
Midscale
1 LSB
LATCH
RS
AND
B
255
128
1
99
DECODER
5,060
9,961
10,060
0
Zero Scale
Figure 17. AD5243/48 Equivalent RDAC Circuit
Typical device to device matching is process lot dependent and
may vary by up to 30%. Since the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
The general equation determining the digitally programmed
output resistance between W and B is
Rev. PrE 5/12/03 | Page 10 of 16
AD5243/AD5248
Preliminary Technical Data
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC sub
address select bit. A logic low will select channel-1 and a
logic high will select channel-2.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
The second MSB, SD, is a shutdown bit. A logic high
causes an open circuit at terminal A while shorting the
wiper to terminal B. This operation yields almost 0 Ω in
rheostat mode or 0 V in potentiometer mode. It is
important to note that the shutdown operation does not
disturb the contents of the register. When brought out of
shutdown, the previous setting will be applied to the
RDAC. Also, during shutdown, new settings can be
programmed. When the part is returned from shutdown,
the corresponding VR setting will be applied to the RDAC.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
The remainder of the bits in the instruction byte are don’t
cares(see Table 5).
D
256
256 − D
256
VW (D) =
VA
+
VB
(3)
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 5).
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
RWB (D)
RAB
RWA (D)
RAB
VW (D) =
VA +
VB
(4)
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses(a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 15 and Figure 16).
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
Note that the channel of interest is the one that is
previously selected in the Write Mode. In the case where
users need to read the RDAC values of both channels, they
need to program the first channel in the Write Mode and
then change to the Read Mode to read the first channel
value. After that, they need to change back to the Write
Mode with the second channel selected and read the
second channel value in the Read Mode again. It is not
necessary for users to issue the Frame 3 data byte in the
write mode for subsequent readback operation. Users
should refer to Figure 15 for the programming format.
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 13). The
following byte is the slave address byte, which consists of
W
the slave address followed by an R/ bit (this bit
determines whether data will be read from or written to
the slave device). The AD5243 has a fixed slave address
byte whereas the AD5248 has two configurable address bits
AD0 and AD1 (see Table 5).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
W
its serial register. If the R/ bit is high, the master will read
W
from the slave device. On the other hand, if the R/ bit is
low, the master will write to the slave device.
Rev. PrE 5/12/03 | Page 11 of 16
AD5243/AD5248
Preliminary Technical Data
4. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 13) In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 15 and Figure
16).
FETs such as the FDV301N.
V
= 3.3V
V
5V
=
DD1
DD2
R
R
R
R
P
P
P
P
G
S
D
SDA1
SCL1
SDA2
SCL2
G
M1
S
D
M2
3.3V
5V
2
AD5243
E PROM
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output will update on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new slave address, instruction, and data
byte. Similarly, a repeated read function of the RDAC is also
allowed.
Figure 19. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 20 and Figure 21.
This applies to the digital input pins SDA, SCL, and AD0.
340Ω
LOGIC
Multiple Devices on One Bus(applies only to AD5248)
V
SS
Figure 18 shows four AD5248 devices on the same serial bus.
Each has a different slave address since the states of their AD0
and AD1 pins are different. This allows each device on the bus
to be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
Figure 20. ESD Protection of Digital Pins
A,B,W
V
SS
+5V
Figure 21. ESD Protection of Resistor Terminals
Rp
Rp
SDA
SCL
TERMINAL VOLTAGE OPERATING RANGE
MASTER
The AD5243/48 VDD and GND power supply defines the
boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on terminals A,
B, and W that exceed VDD or GND will be clamped by the
internal forward biased diodes (see Figure 22).
+5V
+5 V
+5V
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
AD0
AD5248
AD0
AD5248
AD0
AD5248
AD0
AD5248
Figure 18. Multiple AD5248 Devices on One I2C Bus
V
DD
A
W
B
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E2PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional
V
SS
Figure 22. Maximum Terminal Voltages Set by VDD and VSS
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E2PROM. Figure 19
shows one of the implementations. M1 and M2 can be any
N-channel signal FETs, or if VDD falls below 2.5 V, low threshold
Rev. PrE 5/12/03 | Page 12 of 16
AD5243/AD5248
Preliminary Technical Data
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 23). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 22), it is important to power
VDD/GND before applying any voltage to terminals A, B, and Wꢀ
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
V
V
DD
DD
+
10 F
C3
C1
0.1 F
µ
µ
AD5243
LAYOUT AND POWER SUPPLY BYPASSING
GND
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Figure 23. Power Supply Bypassing
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
Rev. PrE 5/12/03 | Page 13 of 16
AD5243/AD5248
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Table 9.
Pin Name Description
1
2
3
4
5
B1
A1
W1
B2
10
9
1
2
3
4
5
6
ꢀ
8
9
10
B1
B1 Terminal.
A1
A1 Terminal.
8
W2
GND
A2
SDA
SCL
W2
GND
VDD
SCL
SDA
A2
W2 Terminal.
7
Digital Ground.
VDD
6
Positive Power Supply.
Serial Clock Input. Positive edge triggered.
Serial Data Input/Output.
A2 Terminal.
Figure 24.- AD5243 Pin Configuration
B2
B2 Terminal.
W2
W2 Terminal.
Table 10.
Pin Name Description
1
2
3
4
5
B1
W1
B2
10
9
AD0
1
2
B1
B1 Terminal.
8
W2
GND
AD1
SDA
SCL
AD0
Programmable address bit 0 for multiple
package decoding.
7
VDD
6
3
4
5
6
ꢀ
8
W2
W2 Terminal
GND
VDD
Digital Ground.
Figure 25. – AD5243 Pin Configuration
Positive Power Supply..
Serial Clock Input. Positive edge triggered.
Serial Data Input/Output.
SCL
SDA
AD1
Programmable address bit 1 for multiple
package decoding.
9
B2
B2 Terminal.
W1 Terminal.
10
W1
Rev. PrE 5/12/03 | Page 14 of 16
AD5243/AD5248
Preliminary Technical Data
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.23
0.20
0.17
0.80
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 26. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB (Ω)
2.5k
Temperature
Package Description
MSOP-10
Package Option
Branding
D0L
AD5243BRM2.5-R2
AD5243BRM2.5-RLꢀ
AD5243BRM10-R2
AD5243BRM10-RLꢀ
AD5243BRM50-R2
AD5243BRM50-RLꢀ
AD5243BRM100-R2
AD5243BRM100-RLꢀ
AD5243EVAL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
2.5k
MSOP-10
D0L
10k
MSOP-10
D0M
D0M
D0N
10k
MSOP-10
50k
MSOP-10
50k
MSOP-10
D0N
100k
100k
See Note 1
MSOP-10
D0P
MSOP-10
D0P
Evaluation Board
Model
RAB (Ω)
2.5k
Temperature
Package Description
MSOP-10
Package Option
RM-10
Branding
D1F
AD5248BRM2.5-R2
AD5248BRM2.5-RLꢀ
AD5248BRM10-R2
AD5248BRM10-RLꢀ
AD5248BRM50-R2
AD5248BRM50-RLꢀ
AD5248BRM100-R2
AD5248BRM100-RLꢀ
AD5248EVAL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
2.5k
MSOP-10
RM-10
D1F
10k
MSOP-10
RM-10
D1G
D1G
D1H
D1H
D1J
10k
MSOP-10
RM-10
50k
MSOP-10
RM-10
50k
MSOP-10
RM-10
100k
100k
See Note 1
MSOP-10
RM-10
MSOP-10
RM-10
D1J
Evaluation Board
1The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5243/48 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2,358 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE 5/12/03 | Page 15 of 16
AD5243/AD5248
NOTES
Preliminary Technical Data
Rev. PrE 5/12/03 | Page 16 of 16
相关型号：
AD5243BRM2.5-R2
IC 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer
ADI
AD5243BRM50-R2
IC 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer
ADI
©2020 ICPDF网 联系我们和版权申明