AD5245BRJZ100-R2_技术文档

256-Position I²C^®-Compatible

Digital Potentiometer

AD5245

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

256-position

DD

End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Compact SOT-23-8 (2.9 mm × 3 mm) package

Fast settling time: t_S= 5 µs typ on power-up

Full read/write of wiper register

Power-on preset to midscale

Extra package address decode pin AD0

A

SCL

I²C INTERFACE

SDA

W

B

AD0

WIPER

REGISTER

Computer software replaces µC in factory programming

applications

POR

Single supply: 2.7 V to 5.5 V

GND

Low temperature coefficient 45 ppm/°C

Low power: I_DD= 8 µA

Figure 1.

Wide operating temperature: –40°C to +125°C

Evaluation board available

PIN CONFIGURATION

APPLICATIONS

Mechanical potentiometer replacement in new designs

LCD panel V_COMadjustment

1

2

3

4

W

8

7

6

5

A

V

AD5245

TOP VIEW

(Not to Scale)

B

DD

GND

SCL

AD0

SDA

LCD panel brightness and contrast control

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

Figure 2.

RF amplifier biasing

Automotive electronics adjustment

Gain control and offset adjustment

GENERAL DESCRIPTION

The AD5245 provides a compact 2.9 mm × 3 mm packaged

solution for 256-position adjustment applications. These

devices perform the same electronic adjustment function as

mechanical potentiometers or variable resistors, with enhanced

resolution, solid-state reliability, and superior low temperature

coefficient performance.

Operating from a 2.7 V to 5.5 V power supply and consuming

less than 8 µA allows usage in portable battery-operated

applications.

Note that the terms digital potentiometer, VR, and RDAC are

used interchangeably.

The wiper settings are controllable through an I²C-compatible

digital interface, which can also be used to read back the wiper

register content. AD0 can be used to place up to two devices on

the same bus. Command bits are available to reset the wiper

position to midscale or to shut down the device into a state of

zero power consumption.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5245

TABLE OF CONTENTS

Features .............................................................................................. 1

Test Circuits..................................................................................... 12

Theory of Operation ...................................................................... 13

Programming the Variable Resistor......................................... 13

Programming the Potentiometer Divider............................... 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 14

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board........................................................................ 15

I²C Interface .................................................................................... 16

I²C-Compatible 2-Wire Serial Bus........................................... 16

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Electrical Characteristics................................................................. 3

5 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4

Timing Characteristics..................................................................... 5

5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

Added Figure 37 ............................................................................ 14

Changes to Equation 4.................................................................. 14

Deleted Readback RDAC Value Section .................................... 14

Deleted Level Shifting for Bidirectional Interface Section ...... 14

Moved ESD Protection Section to Page ..................................... 14

Changes to Figure 38 and Figure 39............................................ 14

Moved Terminal Voltage Operating Range Section to Page.... 14

Changes to Figure 40..................................................................... 14

Moved Power-Up Sequence Section to Page ............................. 14

Moved Layout and Power Supply Bypassing Section to Page . 15

Added Constant Bias to Retain Resistance Setting Section..... 15

Added Figure 42 ............................................................................ 15

Added Evaluation Board Section ................................................ 15

Added Figure 43 ............................................................................ 15

Moved I²C Interface Section to Page........................................... 16

Changes to I2C Compatible 2-Wire Serial Bus Section ........... 16

Moved Table 5 and Table 6 to Page ............................................. 17

(Renumbered as Table 8 and Table 9)

1/06—Rev. A to Rev. B

Changes to Table 3........................................................................... 5

Changes to Ordering Guide .........................................................19

3/04—Rev. 0 to Rev. A

Updated Format................................................................ Universal

Changes to Features......................................................................... 1

Changes to Applications ................................................................. 1

Changes to Figure 1......................................................................... 1

Changes to Electrical Characteristics—5 kΩ Version ................ 3

Changes to Electrical Characteristics—10 kΩ, 50 kΩ,

and 100 kΩ Versions ....................................................................... 4

Changes to Timing Characteristics............................................... 5

Changes to Absolute Maximum Ratings...................................... 6

Moved ESD Caution to Page.......................................................... 6

Changes to Pin Configuration and Function Descriptions ....... 7

Changes to Figures 22 and 23 ......................................................11

Moved Figure 25 to Figure 26 ......................................................11

Moved Figure 26 to Figure 27 ......................................................11

Moved Figure 27 to Figure 25 ......................................................11

Deleted Figures 31 and 32 ............................................................12

Changes to Figure 32, Figure 33 and Figure 34 .........................12

Changes to Rheostat Operation Section.....................................13

Added Figure 35.............................................................................13

Changes to Equation 1 and Equation 2 ......................................13

Changes to Table 6 and Table 7....................................................13

Moved Figure 36, Figure 37, and Figure 38 to Page.................. 17

(Renumbered as Figure 44, Figure 45, and Figure 46)

Moved Multiply Devices on One Bus Section to Page ............. 18

Updated Ordering Guide ............................................................. 19

Updated Outline Dimensions...................................................... 19

Moved I²C Disclaimer to Page..................................................... 20

5/03—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5245

ELECTRICAL CHARACTERISTICS

5 kΩ VERSION

V_DD= 5 V 10ꢀ or 3 V 10ꢀ, V_A= V_DD, V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

+1.5

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB

R_WB, V_A= no connect

T_A= 25°C

–1.5

–4

–30

0.1

LSB

%

ppm/°C

Ω

0.ꢀ5 +4

+30

120

(∆R_AB/R_AB)/∆T × 10⁶V_AB= V_DD, wiper = no connect

45

50

R_W

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

–1.5

0.1

0.6

15

–2.5

2

+1.5

LSB

ppm/°C

LSB

(∆V_W/V_W)/∆T × 10⁶

V_WFSE

V_WZSE

Code = 0x80

Code = 0xFF

Code = 0x00

–6

0

6

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

f = 1 MHz, measured to GND,

code = 0x80

Capacitance A, B⁶

90

pF

f = 1 MHz, measured to GND,

code = 0x80

V_DD= 5.5 V

Capacitance W⁶

C_W

I_{A_SD}

I_CM

95

0.01

1

pF

µA

nA

Shutdown Supply Current^ꢀ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

1

V_A= V_B= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

5

POWER SUPPLIES

Power Supply Range

Supply Current

V_{DD RANGE}

I_DD

P_DISS

2.ꢀ

5.5

8

44

V

µA

µW

V_IH= 5 V or V_IL= 0 V

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

V_DD= +5 V 10%, code = midscale

3

Power Dissipation⁸

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS^{6, 9}

Bandwidth –3 dB

Total Harmonic Distortion

V_WSettling Time

PSS

0.02

0.05 %/%

BW_5K

THD_W

t_S

R_AB= 5 kΩ, code = 0x80

1.2

0.1

1

MHz

%

µs

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 5 V, V_B= 0 V, 1 LSB error band

R_WB= 2.5 kΩ, R_S= 0

Resistor Noise Voltage Density

e_{N_WB}

6

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

^ꢀMeasured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁹All dynamic characteristics use V_DD= 5 V.

Rev. B | Page 3 of 20

AD5245

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

V_DD= 5 V 10ꢀ or 3 V 10ꢀ, V_A= V_DD, V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB

R_WB, V_A= no connect

T_A= 25°C

–1

–2

–30

0.1

0.25

+1

+2

+30

LSB

%

ppm/°C

Ω

(∆R_AB/R_AB)/∆T × 10⁶V_AB= V_DD, wiper = no connect

45

50

R_WV_DD= 5 V

120

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity⁴

Integral Nonlinearity⁴

DNL

INL

–1

0.1

0.3

15

–1

1

+1

LSB

ppm/°C

LSB

Voltage Divider Temperature Coefficient (∆V_W/V_W)/∆T × 10⁶

Code = 0x80

Code = 0xFF

Code = 0x00

Full-Scale Error

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_WFSE

V_WZSE

–3

0

3

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance A, B⁶

f = 1 MHz, measured to GND,

code = 0x80

f = 1 MHz, measured to GND,

code = 0x80

90

95

Capacitance W⁶

C_W

pF

Shutdown Supply Current

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

I_{A_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

0.01

1

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

5

3

POWER SUPPLIES

Power Supply Range

Supply Current

Power Dissipation^ꢀ

V_{DD RANGE}

I_DD

P_DISS

2.ꢀ

5.5

8

44

V

µA

µW

V_IH= 5 V or V_IL= 0 V

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

Power Supply Sensitivity

PSS

V_DD= 5 V 10%,

code = midscale

0.02

0.05 %/%

DYNAMIC CHARACTERISTICS^{6, 8}

Bandwidth –3 dB

BW

R_AB= 10 kΩ/50 kΩ/100 kΩ,

code = 0x80

V_A= 1 V rms, V_B= 0 V, f = 1 kHz,

R_AB= 10 kΩ

V_A= 5 V, V_B= 0 V,

1 LSB error band

R_WB= 5 kΩ, R_S= 0

600/100/40

kHz

%

Total Harmonic Distortion

THD_W

t_S

0.1

2

V_WSettling Time (10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage Density

µs

e_{N_WB}

9

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

^ꢀP_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁸All dynamic characteristics use V_DD= 5 V.

Rev. B | Page 4 of 20

AD5245

TIMING CHARACTERISTICS

5 KΩ, 10 KΩ, 50 KΩ, 100 KΩ VERSIONS

V_DD= 5 V 10ꢀ or 3 V 10ꢀ, V_A= V_DD, V_B= 0 V, –40°C < T_A< +125°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Conditions

Min

Typ¹

Max

400

Unit

I²C INTERFACE TIMING CHARACTERISTICS^{2, 3, 4}(Specifications Apply to All Parts)

SCL Clock Frequency

t_BUFBus Free Time Between STOP and START

t_HD;STAHold Time (Repeated START)

f_SCL

t₁

t₂

kHz

µs

1.3

0.6

After this period, the first clock

pulse is generated.

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time for Repeated START Condition

t_HD;DATData Hold Time

t_SU;DATData Setup Time

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSetup Time for STOP Condition

t₃

t₄

t₅

t₆

t_ꢀ

t₈

t₉

t₁₀

1.3

0.6

µs

ns

µs

0.9

100

0.6

300

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Guaranteed by design and not subject to production test.

³See timing diagram (Figure 44) for locations of measured values.

⁴Standard I²C mode operation guaranteed by design.

Rev. B | Page 5 of 20

AD5245

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Value

V_DDto GND

V_A, V_B, V_Wto GND

Terminal Current, A to B, A to W, B to W¹

–0.3 V to +ꢀ V

V_DD

Pulsed

Continuous

20 mA

5 mA

Digital Inputs and Output Voltage to GND

Operating Temperature Range

0 V to ꢀ V

–40°C to +125°C

150°C

Maximum Junction Temperature (T_JMAX

)

Storage Temperature Range

Lead Temperature (Soldering, 10 sec)

Thermal Resistance²θ_JA: SOT-23-8

–65°C to +150°C

245°C

230°C/W

¹Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 6 of 20

AD5245

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

W

8

7

6

5

A

V

AD5245

TOP VIEW

(Not to Scale)

B

DD

GND

SCL

AD0

SDA

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic

Description

1

2

3

4

5

6

ꢀ

8

W

W Terminal. GND ≤ V_W≤ V_DD.

Positive Power Supply.

Digital Ground.

Serial Clock Input. Positive edge triggered. Pull-up resistor required.

Serial Data Input/Output. Pull-up resistor required.

Programmable Address Bit 0 for Two-Device Decoding.

B Terminal. GND ≤ V_B≤ V_DD.

V_DD

GND

SCL

SDA

AD0

B

A

A Terminal. GND ≤ V_A≤ V_DD.

Rev. B | Page ꢀ of 20

AD5245

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

–40°C

+25°C

+85°C

+125°C

5V

0.8

3V

0.6

0.4

0.2

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 4. R-INL vs. Code vs. Supply Voltages

Figure 7. DNL vs. Code vs. Temperature, V_DD= 5 V

1.0

0.8

1.0

0.8

5V

3V

5V

3V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 5. R-DNL vs. Code vs. Supply Voltages

Figure 8. INL vs. Code vs. Supply Voltages

1.0

0.8

1.0

0.8

–40°C

+25°C

+85°C

+125°C

5V

3V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–0.2

–0.4

–0.6

–0.8

–1.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 6. INL vs. Code vs. Temperature, V_DD= 5 V

Figure 9. DNL vs. Code vs. Supply Voltages

Rev. B | Page 8 of 20

AD5245

1.0

0.8

2.5

2.0

1.5

1.0

0.5

–40

+25°C

+85°C

°C

+125°C

0.6

0.4

0.2

V

= 5.5V

DD

0

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 2.7V

DD

0

–40

0

40

TEMPERATURE (°C)

80

120

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 10. R-INL vs. Code vs. Temperature, V_DD= 5 V

Figure 13. Zero-Scale Error vs. Temperature

1.0

0.8

10

–40°C

+25°C

+85°C

+125°C

0.6

0.4

0.2

V

= 5.5V

DD

0

1

–0.2

–0.4

–0.6

–0.8

–1.0

= 2.7V

DD

0.1

0

32

64

96

128

160

192

224

256

–40

0

40

TEMPERATURE (°C)

80

120

CODE (Decimal)

Figure 11. R-DNL vs. Code vs. Temperature, V_DD= 5 V

Figure 14. Supply Current vs. Temperature

2.5

2.0

1.5

1.0

70

60

50

40

30

20

10

0

V

= 2.7V

= 5.5V

DD

V

= 5V

DD

0.5

0

–40

0

40

80

120

–40

0

40

TEMPERATURE (°C)

80

120

TEMPERATURE (°C)

Figure 12. Full-Scale Error vs. Temperature

Figure 15. Shutdown Current vs. Temperature

Rev. B | Page 9 of 20

AD5245

REF LEVEL

0.000dB

/DIV

6.000dB

MARKER 510 634.725Hz

MAG (A/R) –9.049dB

200

0

0x80

–6

150

100

50

0x40

–12

0x20

0x10

–18

–24

–30

–36

–42

–48

–54

–60

0x08

0x04

0x02

0x01

0

–50

0

32

64

96

128

160

192

224

256

1k

START 1 000.000Hz

10k

100k

1M

CODE (Decimal)

STOP 1 000 000.000Hz

Figure 16. Rheostat Mode Tempco ∆R_WB/∆T vs. Code

Figure 19. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

REF LEVEL

0.000dB

0

/DIV

6.000dB

MARKER 100 885.289Hz

MAG (A/R) –9.014dB

160

140

120

100

80

0x80

–6

0x40

0x20

0x10

0x08

–12

–18

–24

–30

–36

–42

–48

–54

–60

60

0x04

0x02

0x01

40

20

0

–20

0

32

64

96

128

160

192

224

256

1k

START 1 000.000Hz

10k

100k

1M

CODE (Decimal)

STOP 1 000 000.000Hz

Figure 20. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

Figure 17. Potentiometer Mode Tempco ∆V_WB/∆T vs. Code

REF LEVEL

0.000dB

0

/DIV

6.000dB

MARKER 54 089.173Hz

MAG (A/R) –9.052dB

REF LEVEL

0.000dB

0

/DIV

6.000dB

MARKER 1 000 000.000Hz

MAG (A/R) –8.918dB

0x80

–6

0x80

–6

0x40

0x20

–12

0x40

0x20

–12

–18

–24

–30

–36

–42

–48

–54

–60

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x10

0x08

0x04

0x02

0x01

0x02

0x01

1k

START 1 000.000Hz

10k

100k

1M

1k

START 1 000.000Hz

10k

100k

1M

STOP 1 000 000.000Hz

Figure 21. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

Figure 18. Gain vs. Frequency vs. Code, R_AB= 5 kΩ

Rev. B | Page 10 of 20

AD5245

REF LEVEL

–5.000dB

/DIV

0.500dB

–5.5

5kΩ – 1.026MHz

10kΩ – 511kHz

50kΩ – 101kHz

100kΩ – 54kHz

–6.0

–6.5

–7.0

–7.5

–8.0

–8.5

–9.0

–9.5

–10.0

–10.5

1

VW

R = 50kΩ

R = 5kΩ

SCL

R = 10kΩ

R = 100kΩ

2

Ch 1 200mV

B

Ch 2 5.00 V

B

M 100ns A CH2 3.00 V

W

10k

100k

1M

10M

START 1 000.000Hz

STOP 1 000 000.000Hz

Figure 22. –3 dB Bandwidth @ Code = 0x80

Figure 25. Large Signal Settling Time, Code 0xFF ≥ 0x00

60

40

20

0

CODE = 0x80, V = V , V = 0V

A

DD

B

V

= 5V

= 0V

A

B

PSRR @ V

= 3V DC ±10% p-p AC

DD

1

VW

SCL

2

PSRR @ V

= 5V DC ±10% p-p AC

DD

Ch 1 100mV

B

Ch 2 5.00 V

B

M 200ns A CH1 152mV

W

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 26. Digital Feedthrough

Figure 23. PSRR vs. Frequency

900

V

= 5V

DD

800

700

600

500

400

300

V

= 5V

= 0V

A

B

1

VW

CODE = 0x55

CODE = 0xFF

SCL

200

100

0

2

Ch 1 5.00V

B

Ch 2 5.00 V

B

M 200ns A CH1 3.00 V

W

10k

100k

1M

FREQUENCY (Hz)

10M

Figure 27. Midscale Glitch, Code 0x80 ≥ 0x7F

Figure 24. I_DDvs. Frequency

Rev. B | Page 11 of 20

AD5245

TEST CIRCUITS

Figure 28 to Figure 34 illustrate the test circuits that define the test conditions used in the product specification tables (Table 1 through Table 3).

V+ = V

DD

1LSB = V+/2

DUT

W

DUT

+15V

N

A

B

A

W

AD8610

V

IN

V+

V

OUT

B

OFFSET

GND

V

MS

–15V

2.5V

Figure 32. Test Circuit for Gain vs. Frequency

Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error

(INL, DNL)

NO CONNECT

DUT

0.1V

R

=

SW

I

SW

DUT

I

W

A

CODE = 0x00

W

B

0.1V

I

B

SW

V

MS

GND TO V

DD

Figure 29. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 33. Test Circuit for Incremental On Resistance

NC

DUT

I

= V /R

DD NOMINAL

DUT

W

A

B

I

CM

V

A

B

W

V

DD

W

V

MS2

R

= [V

MS1

– V

]/I

GND

W

MS2

W

V

CM

V

MS1

NC NC = NO CONNECT

Figure 34. Test Circuit for Common-Mode Leakage Current

Figure 30. Test Circuit for Wiper Resistance

V

A

V+ = V ±10%

DD

∆V

MS

PSRR (dB) = 20 log

(

)

V

DD

A

B

%

∆V

MS

W

V+

PSS (%/%) =

%

DD

V

MS

Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

Rev. B | Page 12 of 20

AD5245

THEORY OF OPERATION

The AD5245 is a 256-position digitally controlled variable

resistor (VR) device.

The general equation determining the digitally programmed

output resistance between W and B is

D

256

An internal power-on preset places the wiper at midscale

during power-on, which simplifies the fault condition recovery

at power-up.

R

_WB(D) =

×R_AB+2×R_W

(1)

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

R_ABis the end-to-end resistance.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminals A and

B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal

resistance (R_AB) of the VR has 256 contact points accessed by

the wiper terminal, plus the B terminal contact. The 8-bit data

in the RDAC latch is decoded to select one of the 256 possible

settings.

R_Wis the wiper resistance contributed by the on resistance of

the internal switch.

In summary, if R_AB= 10 kΩ and the A terminal is open

circuited, then the following output resistance R_WBis set for the

indicated RDAC latch codes.

Table 6. Codes and Corresponding R_WBResistance

A

D (Dec.)

R_WB(Ω)

9,961

5,060

139

Output State

W

255

128

1

Full Scale (R_AB– 1 LSB + R_W)

Midscale

1 LSB

B

Figure 35. Rheostat Mode Configuration

0

100

Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of

100 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of

no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

Assuming that a 10 kΩ part is used, the wiper’s first connection

starts at the B terminal for Data 0x00. Because there is a 50 Ω

wiper contact resistance, such a connection yields a minimum

of 100 Ω (2 × 50 Ω) resistance between Terminals W and B. The

second connection is the first tap point, which corresponds to

139 Ω (R_WB= R_AB/256 + 2 × R_W= 39 Ω + 2 × 50 Ω) for Data 0x01.

The third connection is the next tap point, representing 178 Ω

(2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so on. Each LSB data

value increase moves the wiper up the resistor ladder until the

last tap point is reached at 10,100 Ω (R_AB+ 2 × R_W).

Similar to the mechanical potentiometer, the resistance of the

RDAC between the Wiper W and Terminal A also produces a

digitally controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

A

R

S

256 − D

256

R_WA(D) =

×R_AB+2×R_W

(2)

R

D7

D6

D5

D4

D3

D2

D1

D0

S

For R_AB= 10 kΩ and the B terminal open circuited, the

following output resistance R_WAis set for the indicated RDAC

latch codes.

S

W

Table 7. Codes and Corresponding R_WAResistance

D (Dec.)

R_WA(Ω)

Output State

Full Scale

Midscale

1 LSB

255

128

1

139

R

RDAC

S

5,060

9,961

10,060

LATCH

AND

DECODER

B

0

Zero Scale

Typical device-to-device matching is process lot dependent and

can vary by up to 30ꢀ. Because the resistance element is

processed in thin film technology, the change in R_ABwith

temperature has a very low 45 ppm/°C temperature coefficient.

Figure 36. AD5245 Equivalent RDAC Circuit

Rev. B | Page 13 of 20

AD5245

PROGRAMMING THE POTENTIOMETER DIVIDER

TERMINAL VOLTAGE OPERATING RANGE

Voltage Output Operation

The AD5245 V_DDand GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on Terminals A, B, and W that

exceed V_DDor GND are clamped by the internal forward-biased

diodes (see Figure 40).

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

A to B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

V

DD

A

V

I

W

B

A

B

W

V

O

GND

Figure 40. Maximum Terminal Voltages Set by V_DDand GND

Figure 37. Potentiometer Mode Configuration

POWER-UP SEQUENCE

If ignoring the effect of the wiper resistance for approximation,

then connecting the A terminal to 5 V and the B terminal to

ground produces an output voltage at the wiper-to-B starting at

0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal A and B divided by the 256

positions of the potentiometer divider. The general equation

defining the output voltage at V_Wwith respect to ground for any

valid input voltage applied to Terminals A and B is

Because the ESD protection diodes limit the voltage compliance

at Terminals A, B, and W (see Figure 40), it is important to

power V_DDand GND before applying any voltage to Terminals

A, B, and W; otherwise, the diode is forward biased such that

V_DDis powered unintentionally and can affect the rest of the

user’s circuit. The ideal power-up sequence is in the following

order: GND, V_DD, digital inputs, and then V_A, V_B, and V_W. The

relative order of powering V_A, V_B, V_W, and the digital inputs is

not important as long as they are powered after V_DDand GND.

D

256

256 − D

256

V_W(D) =

V_A+

V_B

(3)

LAYOUT AND POWER SUPPLY BYPASSING

A more accurate calculation, which includes the effect of wiper

resistance, V_W, is

It is good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

R

_WB(D)

R_AB

R

_WA(D)

R_AB

V_W(D) =

V_A+

V_B

(4)

Similarly, it is also good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to

the device should be bypassed with disk or chip ceramic

capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum

or electrolytic capacitors should also be applied at the supplies

to minimize any transient disturbance and low frequency ripple

(see Figure 41). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors, R_WAand R_WB, not the absolute

values. Therefore, the temperature drift reduces to 15 ppm/°C.

ESD PROTECTION

All digital inputs are protected with a series of input resistors and

parallel Zener ESD structures, shown in Figure 38 and Figure 39.

This applies to the digital input pins SDA, SCL, and AD0.

340Ω

V

DD

LOGIC

+

C3

C1

10µF

0.1µF

AD5245

GND

Figure 38. ESD Protection of Digital Pins

GND

A, B, W

GND

Figure 41. Power Supply Bypassing

Figure 39. ESD Protection of Resistor Terminals

Rev. B | Page 14 of 20

AD5245

Although the resistance setting of the AD5245 is lost when the

battery needs replacement, such events occur rather infrequently

so that this inconvenience is justified by the lower cost and

smaller size offered by the AD5245. If total power is lost, then

the user should be provided with a means to adjust the setting

accordingly.

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the

additional cost for the EEMEM, the AD5245 can be considered

a low cost alternative by maintaining a constant bias to retain

the wiper setting. The AD5245 is designed specifically with low

power in mind, which allows low power consumption even in

battery-operated systems. Figure 42 demonstrates the power

consumption from a 3.4 V, 450 mA-hr Li-Ion cell phone battery

that is connected to the AD5245. The measurement over time

shows that the device draws approximately 1.3 µA and

EVALUATION BOARD

An evaluation board, along with all necessary software, is

available to program the AD5245 from any PC running

Windows® 98/2000/XP. The graphical user interface, as shown

in Figure 43, is straightforward and easy to use. More detailed

information is available in the user manual, which is provided

with the board.

consumes negligible power. Over a course of 30 days, the

battery is depleted by less than 2ꢀ, the majority of which is due

to the intrinsic leakage current of the battery itself.

110%

T

= 25°C

A

108%

106%

104%

102%

100%

98%

96%

94%

92%

Figure 43. AD5245 Evaluation Board Software

90%

0

5

10

15

20

25

30

The AD5245 starts at midscale upon power-up. To increment or

decrement the resistance, the user can simply move the scroll-

bars on the left. To write a specific value, the user should use the

bit pattern in the upper screen and click the Run button. The

format of writing data to the device is shown in Table 8. To read

the data from the device, the user can simply click the Read

button. The format of the read bits is shown in Table 9.

DAYS

Figure 42. Battery Operating Life Depletion

This demonstrates that constantly biasing the potentiometer

can be a practical approach. Most portable devices do not

require the removal of batteries for charging.

Rev. B | Page 15 of 20

AD5245

I²C INTERFACE

I²C-COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I²C serial bus protocol operates as follows:

3. After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Figure 45).

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high (see Figure 45). The next byte

is the slave address byte, which consists of the 7-bit slave

4. In read mode, the data byte follows immediately after the

acknowledgment of the slave address byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (a slight difference with write mode, in which eight

data bits are followed by an acknowledge bit). Similarly, the

transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of

SCL (see Figure 46).

W

address followed by an R/ bit (this bit determines whether

data is read from or written to the slave device). The AD5245

has one configurable address bit, AD0 (see Table 8).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

5. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10^thclock pulse to establish a STOP

condition (see Figure 45). In read mode, the master issues a

no acknowledge for the ninth clock pulse (that is, the SDA

line remains high). The master then brings the SDA line low

before the 10^thclock pulse, which goes high to establish a

STOP condition (see Figure 46).

its serial register. If the R/ bit is high, the master reads

W

from the slave device. On the other hand, if the R/ bit is

W

low, the master writes to the slave device.

2. In write mode, the second byte is the instruction byte.

The first bit (MSB) of the instruction byte is a don’t care.

The second MSB, RS, is the midscale reset. A logic high on

this bit moves the wiper to the center tap, where R_WA= R_WB

This feature effectively overwrites the contents of the

.

register; therefore, when taken out of reset mode, the RDAC

remains at midscale.

A repeated write function gives the user flexibility to update

the RDAC output a number of times after addressing and

instructing the part only once. For example, after the RDAC

has acknowledged its slave address and instruction bytes in

the write mode, the RDAC output updates on each successive

byte. If different instructions are needed, then the write/read

mode has to start again with a new slave address, instruction,

and data byte. Similarly, a repeated read function of the

RDAC is also allowed.

The third MSB, SD, is a shutdown bit. A logic high causes an

open circuit at Terminal A while shorting the wiper to

Terminal B. This operation yields almost 0 Ω in rheostat mode

or 0 V in potentiometer mode. It is important to note that

the shutdown operation does not disturb the contents of the

register. When brought out of shutdown, the previous setting is

applied to the RDAC. Also during shutdown, new settings can

be programmed. When the part is returned from shutdown,

the corresponding VR setting is applied to the RDAC.

The remainder of the bits in the instruction byte are don’t

cares (see Table 8).

Rev. B | Page 16 of 20

AD5245

Table 8. Write Mode

S

0

1

0

1

0

AD0

W

A

X

RS SD

X

A

D7 D6 D5 D4 D3 D2 D1 D0

A P

Slave Address Byte

Instruction Byte

Data Byte

Table 9. Read Mode

S

0

1

0

1

0

AD0

R

A

D7

D6

D5

D4

D3

D2

D1

D0

A

P

Slave Address Byte

Data Byte

S = START condition

P = STOP condition

A = Acknowledge

X = Don’t care

R = Read

RS = Reset wiper to midscale 0x80

SD = Shutdown connects wiper to B terminal and open circuits

A terminal, but does not change contents of wiper register

Dꢀ, D6, D5, D4, D3, D2, D1, D0 = Data Bits

W

= Write

t₂

t₈

t₉

SCL

t₆

t₇

t₅

t₁₀

t₂

t₃

t₄

t₉

t₈

SDA

t₁

P

S

1

S

P

Figure 44. I²C Interface Detailed Timing Diagram

9

1

9

1

9

SCL

SDA

X

RS SD

X

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

AD0 R/W

ACK BY

AD5245

ACK BY

AD5245

ACK BY

AD5245

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

START BY

MASTER

Figure 45. Writing to the RDAC Register

1

9

1

9

SCL

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

AD0 R/W

SDA

ACK BY

AD5245

NO ACK

BY MASTER

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

RDAC REGISTER

START BY

MASTER

Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode

Rev. B | Page 1ꢀ of 20

AD5245

+5V

Multiple Devices on One Bus

R_P

Figure 47 shows two AD5245 devices on the same serial bus.

Each has a different slave address because the states of their

AD0 pins are different. This allows the RDAC within each

device to be written to or read from independently. The master

device’s output bus line drivers are open-drain pull-downs in a

fully I²C-compatible interface.

SDA

SCL

MASTER

+5V

SDA SCL

AD0

AD5245

Figure 47. Multiple AD5245 Devices on One I²C Bus

Rev. B | Page 18 of 20

AD5245

OUTLINE DIMENSIONS

2.90 BSC

8

1

7

2

6

3

5

4

1.60 BSC

2.80 BSC

PIN 1

INDICATOR

0.65 BSC

1.95

BSC

1.30

1.15

0.90

1.45 MAX

0.22

0.08

0.60

0.45

0.30

8°

4°

0°

0.38

0.22

0.15 MAX

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 48. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD5245BRJ5-R2

Temperature Range

Package Description

8-Lead SOT-23

Evaluation Board

Package Option Branding R_AB(Ω) Ordering Quantity

–40°C to +125°C

RJ-8

D0G

D0H

D0J

D0K

5 k

250

3,000

250

3,000

250

3,000

250

3,000

250

3,000

250

3,000

250

3,000

250

AD5245BRJ5-RLꢀ

AD5245BRJZ5-R2¹

AD5245BRJZ5-RLꢀ¹

AD5245BRJ10-R2

AD5245BRJ10-RLꢀ

AD5245BRJZ10-R2¹

AD5245BRJZ10-RLꢀ¹

AD5245BRJ50-R2

AD5245BRJ50-RLꢀ

AD5245BRJZ50-R2¹

AD5245BRJZ50-RLꢀ¹

AD5245BRJ100-R2

AD5245BRJ100-RLꢀ

AD5245BRJZ100-R2¹

AD5245BRJZ100-RLꢀ¹

AD5245EVAL²

10 k

50 k

100 k

3,000

¹Z = Pb-free part.

²The evaluation board is shipped with the 10 kΩ R_ABresistor option; however, the board is compatible with all available resistor value options.

Rev. B | Page 19 of 20

AD5245

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the

purchaser under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C

Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

C03436-0-1/06(B)

Rev. B | Page 20 of 20


型号：	AD5245BRJZ100-R2
厂家：	ADI
描述：	256-Position I2C-Compatible Digital Potentiometer 256位I2C兼容数字电位计转换器数字电位计电阻器光电二极管
文件：	总20页 (文件大小：687K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5245BRJZ100-R2 [ADI]

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