AD5247BKSZ10-2RL7_技术文档

128-Position I²C-Compatible

Digital Potentiometer

Data Sheet

AD5247

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

DD

128 positions

End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Ultracompact, SC70-6 (2 mm × 2.1 mm) package

I²C-compatible interface

A

SDA

SCL

2

I C INTERFACE

Full read/write of wiper register

W

Power-on preset to midscale

Single-supply 2.7 V to 5.5 V

WIPER

REGISTER

Rheostat mode temperature coefficient: 45 ppm/°C

Low power, I_DD= 0.9 µA at 3.3 V typical

Wide operating temperature range: −40°C to +125°C

B

GND

Figure 1.

APPLICATIONS

Mechanical potentiometer replacement in new designs

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

RF amplifier-biasing

LCD brightness and contrast adjustment

Automotive electronics adjustment

Gain control and offset adjustment

have three hard-coded slave address options available to allow

users access to three of these devices on one I²C bus (see Table 8

for a full list of slave address locations).

GENERAL DESCRIPTION

The AD5247 provides a compact, 2 mm × 2.1 mm, packaged

solution for 128-position adjustment applications. This device

performs the same electronic adjustment function as a mechanical

potentiometer or a variable resistor. Available in four different

end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ),

these low temperature coefficient devices are ideal for high

accuracy and stability variable resistance adjustments.

The wiper settings are controllable through the I²C-compatible

digital interface, which can also be used to read back the present

wiper register control word. The 10 kΩ and 100 kΩ options each

The resistance between the wiper and either end point of

the fixed resistor varies linearly with respect to the digital

code transferred into the RDAC latch. Note the terms digital

potentiometer, VR (variable resistor), and RDAC are used

interchangeably in this document.

Operating from a 2.7 V to 5.5 V power supply and consuming

0.9 µA (3.3 V) allows the AD5247 to be used in portable

battery-operated applications.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5247

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

I²C Interface .................................................................................... 13

Theory of Operation ...................................................................... 14

Programming the Variable Resistor......................................... 14

Programming the Potentiometer Divider............................... 15

I²C-Compatible 2-Wire Serial Bus........................................... 15

Level Shifting for Bidirectional Interface................................ 16

ESD Protection ........................................................................... 16

Terminal Voltage Operating Range ......................................... 16

Maximum Operating Current .................................................. 16

Power-Up Sequence ................................................................... 16

Layout and Power Supply Bypassing ....................................... 17

Constant Bias to Retain Resistance Setting............................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 kΩ Version.................................. 3

Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ

Versions.......................................................................................... 4

Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ

Versions.......................................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits..................................................................................... 12

REVISION HISTORY

5/12—Rev. E to Rev. F

3/07—Rev. A to Rev. B

Changes to Features and General Description Sections.............. 1

Changes to I_DDParameters, Table 1................................................ 3

Changes to I_DDParameters, Table 2................................................ 4

Changes to Figure 15........................................................................ 9

Changes to Figure 16...................................................................... 10

Removed Evaluation Board Section............................................. 17

Changes to Ordering Guide .......................................................... 18

Changes to General Description Section .......................................1

Added Table 8 ................................................................................. 13

Changes to I²C-Compatible 2-Wire Serial Bus Section ............ 15

Changes to Ordering Guide.......................................................... 18

7/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings section ..........................6

Changes to Ordering Guide.......................................................... 18

1/11—Rev. D to Rev. E

Change to Table 1, Added Output Logic Low .............................. 3

Change to Table 2, Added Output Logic Low .............................. 4

9/03—Revision 0: Initial Version

3/10—Rev. C to Rev. D

Changes to Table 9 and Table 10................................................... 14

10/09—Rev. B to Rev. C

Changes to Zero-Scale Error (10 kΩ) Parameter, Table 2........... 4

Changes to Ordering Guide .......................................................... 18

Rev. F | Page 2 of 20

Data Sheet

AD5247

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 kΩ VERSION

V_DD= 5 V ꢀ1% or 3 V ꢀ1%ꢁ V_A= V_DDꢁ −41°C < T_A< +ꢀ25°Cꢁ unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient³

Output Resistance

R-DNL

R-INL

∆R_AB

∆R_AB/∆T

R_WB

R_WB, V_A= no connect

−1.5

−4

−30

0.1

0.75

+1.5

+4

+30

LSB

%

ppm/°C

Ω

45

75

Code = 0x00

300

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

∆V_W/∆T

V_WFSE

V_WZSE

−1

0.1

0.2

15

−2

1

+1

LSB

ppm/°C

LSB

Code = 0x40

Code = 0x7F

Code = 0x00

−3

0

2

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_A,V_W

C_A

GND

V_DD

V

Capacitance A⁶

f = 1 MHz, measured to GND,

code = 0x40

f = 1 MHz, measured to GND,

code = 0x40

45

pF

Capacitance W⁶

C_W

I_CM

60

1

pF

nA

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

V_A= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

μA

pF

V

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

V_OL

5

Output Logic Low (SDA)

I_OL= 3 mA

I_OL= 6 mA

0.4

0.6

V

POWER SUPPLIES

Power Supply Range

Supply Current

V_{DD RANGE}

I_DD

2.7

5.5

7

5.2

2

V

V_DD= 5.5 V; V_IH= V_DDor V_IL= GND

V_DD= 5 V; V_IH= V_DDor V_IL= GND

V_DD= 3.3 V; V_IH= V_DDor V_IL= GND

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

3

2.5

0.9

μA

μW

Power Dissipation⁷

P_DISS

40

Power Supply Sensitivity

PSSR

V_DD= 5 V 10%,

code = midscale

0.003

0.05 %/%

DYNAMIC CHARACTERISTICS^{6, 8}

Bandwidth –3 dB

Total Harmonic Distortion

V_WSettling Time

BW_5 K

THD_W

t_S

R_AB= 5 kΩ, code = 0x40

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 5 V, 1 LSB error band

R_WB= 2.5 kΩ, R_S= 0 Ω

1.2

0.05

1

MHz

%

μs

Resistor Noise Voltage Density

e_{N_WB}

6

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, wiper (V_W) = no connect.

⁴INL and DNL are measured at V_W,with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic under operating conditions.

⁵Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

⁷P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁸All dynamic characteristics use V_DD= 5 V.

Rev. F | Page 3 of 20

AD5247

Data Sheet

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

V_DD= 5 V 10% or 3 V 10%, V_A= V_DD, −40°C < T_A< +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient³

Output Resistance

R-DNL

R-INL

∆R_AB

∆R_AB/∆T

R_WB

R_WB, V_A= no connect

−1

−2

−20

0.1

0.25

+1

+2

+20

LSB

%

ppm/°C

Ω

45

75

Code = 0x00

300

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Differential Nonlinearity⁴

DNL

INL

−1

0.1

0.2

15

+1

LSB

ppm/°C

LSB

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error (50 kΩ, 100 kΩ)

Zero-Scale Error (50 kΩ, 100 kΩ)

Full-Scale Error (10 kΩ)

∆V_W/∆T

V_WFSE

V_WZSE

V_WFSE

V_WZSE

Code = 0x40

Code = 0x7F

Code = 0x00

Code = 0x7F

V_DD= 4.5 V to 5.5 V, code = 0x00

V_DD= 2.7 V to 4.4 V, code = 0x00

−1

0

−2

0

−1

0

1

0

1

0.4

−0.5

0.5

Zero-Scale Error (10 kΩ)

0

1.2

RESISTOR TERMINALS

Voltage Range⁵

V_A,V_W

C_A

GND

V_DD

V

Capacitance A⁶

f = 1 MHz, measured to GND,

code = 0x40

f = 1 MHz, measured to GND,

code = 0x40

45

pF

Capacitance W⁶

C_W

I_CM

60

1

pF

nA

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁶

V_A= V_DD/2

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

V

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

V_OL

5

Output Logic Low (SDA)

I_OL= 3 mA

I_OL= 6 mA

0.4

0.6

V

POWER SUPPLIES

Power Supply Range

Supply Current

V_{DD RANGE}

I_DD

2.7

5.5

7

5.2

2

V

V_DD= 5.5 V; V_IH= V_DDor V_IL= GND

V_DD= 5 V; V_IH= V_DDor V_IL= GND

V_DD= 3.3 V; V_IH= V_DDor V_IL= GND

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

V_DD= 5 V 10%, code = midscale

3

2.5

0.9

µA

µW

Power Dissipation⁷

Power Supply Sensitivity

P_DISS

PSSR

40

0.01

0.02 %/%

Rev. F | Page 4 of 20

Data Sheet

AD5247

Parameter

DYNAMIC CHARACTERISTICS^{6, 8}

Symbol

Conditions

Min

Typ¹

Max

Unit

Bandwidth –3 dB

BW

R_AB= 10 kΩ/50 kΩ/100 kΩ,

code = 0x40

V_A=1 V rms, f = 1 kHz, R_AB= 10 kΩ

V_A= 5 V 1 LSB error band

R_WB= 5 kΩ, R_S= 0

600/100/40

kHz

%

µs

Total Harmonic Distortion

V_WSettling Time (10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage Density

THD_W

t_S

e_{N_WB}

0.05

2

9

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, wiper (V_W) = no connect.

⁴INL and DNL are measured at V_W,with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

⁶Guaranteed by design, not subject to production test.

⁷P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁸All dynamic characteristics use V_DD= 5 V.

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

V_DD= 5 V 10% or 3 V 10%, V_A= V_DD, −40°C < T_A< +125°C, unless otherwise noted.

Table 3.

Parameter^{1, 2, 3}

Symbol

Min

Typ ⁴

Max

Unit

kHz

µs

SCL Clock Frequency

Bus Free Time Between Stop and Start, t_BUF

Hold Time (Repeated Start), t_HD;STA

f_SCL

t₁

t₂

400

1.3

0.6

1.3

0.6

5

µs

Low Period of SCL Clock, t_LOW

High Period of SCL Clock, t_HIGH

Setup Time for Repeated Start Condition, t_SU;STA

Data Hold Time, t_HD;DAT

t₃

t₄

t₅

t₆

50

0.9

µs

Data Setup Time, t_SU;DAT

t₇

t₈

t₉

t₁₀

100

0.6

ns

µs

Fall Time of Both SDA and SCL Signals, t_F

Rise Time of Both SDA and SCL Signals, t_R

Setup Time for Stop Condition, t_SU;STO

300

¹Specifications apply to all parts.

²Guaranteed by design, not subject to production test.

³See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.

⁴Typical specifications represent average readings at 25°C and V_DD= 5 V.

⁵After this period, the first clock pulse is generated.

t₈

t₂

t₉

t₆

SCL

t₅

t₂

t₃

t₄

t₇

t₁₀

t₉

t₈

SDA

t₁

P

S

Figure 2. I²C Interface, Detailed Timing Diagram

Rev. F | Page 5 of 20

AD5247

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

V_DDto GND

V_A, V_Wto GND

–0.3 V to +7 V

V_DD

Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx

Pulsed¹

20 mA

ESD CAUTION

Continuous

5 mA

Digital Inputs and Output Voltage to GND

Operating Temperature Range

0 V to V_DD+ 0.3 V

–40°C to +125°C

150°C

–65°C to +150°C

340°C/W

Maximum Junction Temperature (T_JMAX

Storage Temperature Range

Thermal Resistance θ_JA²: (SC70-6)

Reflow Soldering Peak Temperature

SnPb

)

240°C

260°C

Pb-Free

¹Maximum terminal current is bounded by the maximum current handling

of the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA

.

Rev. F | Page 6 of 20

Data Sheet

AD5247

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

2

3

6

5

4

A

DD

AD5247

GND

SCL

W

TOP VIEW

(Not to Scale)

SDA

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

V_DD

GND

SCL

SDA

W

Positive Power Supply.

Digital Ground and B Termination Voltage.

Serial Clock Input; Positive Edge Triggered.

Serial Data Input/Output.

Terminal W.

A

Terminal A.

Rev. F | Page 7 of 20

AD5247

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.25

0.20

0.15

0.10

0.05

0

1.0

V = 2.7V

DD

T

R

= 25°C

–40°C

+25°C

+85°C

+125°C

A

0.8

R = 10kΩ

= 10kΩ

AB

0.6

V

= 2.7V

DD

0.4

0.2

T

= –40°C, +25°C, +85°C, +125°C

A

0

V

= 5.5V

DD

–0.05

–0.2

–0.10

–0.15

–0.20

–0.25

–0.4

–0.6

–0.8

–1.0

0

16

32

48

64

80

96

112

128

0

16

32

48

64

80

96

112

128

CODE (Decimal)

Figure 4. R-INL vs. Code vs. Supply Voltages

Figure 7. DNL vs. Code vs. Temperature

0.5

0.25

T

R

= 25°C

= 10kΩ

A

T

R

= 25°C

= 10kΩ

A

0.20

0.15

0.4

0.3

0.2

AB

0.10

0.05

V

= 2.7V

DD

V

= 2.7V

DD

0.1

0

–0.1

–0.2

V

= 5.5V

DD

–0.05

V

= 5.5V

DD

–0.10

–0.15

–0.20

–0.3

–0.4

–0.25

–0.5

0.25

16

32

48

64

80

96

112

16

32

48

64

80

96

112

CODE (Decimal)

Figure 8. INL vs. Code vs. Supply Voltages

Figure 5. R-DNL vs. Code vs. Supply Voltages

0.25

T

R

= 25°C

= 10kΩ

V

R

= 2.7V

T

= –40°C

= +25°C

= +85°C

= +125°C

A

DD

A

V

= 2.7V

= 5.5V

0.20

0.15

DD

0.20

0.15

= 10kΩ

AB

DD

T

= +25°C, +85°C, +125°C

0.10

0.05

0.10

0.05

A

V

= 2.7V

DD

0

–0.05

T

= –40°C

V

= 5.5V

A

DD

–0.10

–0.15

–0.20

–0.10

–0.15

–0.20

–0.25

16

32

48

64

80

96

112

16

32

48

64

80

96

112

CODE (Decimal)

Figure 9. DNL vs. Code vs. Supply Voltages

Figure 6. INL vs. Code vs. Temperature

Rev. F | Page 8 of 20

Data Sheet

AD5247

1.0

0.8

1.50

T

= –40°C

A

T

= +85°C

1.25

1.00

0.75

A

0.6

0.4

0.2

V

= 5.5V, V = 5.5V

A

DD

T

= +25°C

0

A

T

= +125°C

A

–0.2

0.50

–0.4

–0.6

T

= –40°C

= +25°C

= +85°C

= +125°C

A

0.25

0

V

= 2.7V, V = 2.7V

DD A

–0.8

–1.0

–40 –25 –10

5

20

35

50

65 80

95 110 125

0

16

32

48

64

80

96

112

128

TEMPERATURE (°C)

CODE (Decimal)

Figure 10. R-INL vs. Code vs. Temperature

Figure 13. Zero-Scale Error vs. Temperature

0.5

0.4

0.3

0.2

0.1

0

100

10

1

V

R

= 2.7V

= 10kΩ

DD

–40°C

+25°C

+85°C

+125°C

DIGITAL INPUTS = 0V

CODE = 0x40

AB

V = 5.5V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

–0.1

V

= 2.7V

DD

–0.2

–0.3

–0.4

–0.5

0.1

0.01

–40 –25 –10

0

16

32

48

CODE (Decimal)

64

80

96

112

128

5

20

35 50

65

80

95 110 125

TEMPERATURE (°C)

Figure 14. Supply Current vs. Temperature

Figure 11. R-DNL vs. Code vs. Temperature

100

90

80

70

60

50

40

30

20

10

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

5V

2.7V

V

= 5.5V, V = 5.5V

A

DD

V

= 2.7V, V = 2.7V

A

DD

I

R

= 200µA

= 10kΩ

WB

AB

0

1

9

17 25 33 41 49 57 65 73 81 89 97 105 113 121

CODE (Decimal)

–40 –25 –10

5

20 35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 12. Full-Scale Error vs. Temperature

Figure 15. ∆R_WB/∆T vs. Code

Rev. F | Page 9 of 20

AD5247

Data Sheet

0

–6

100

80

2.7V

5V

0x40

0x20

–12

–18

–24

–30

–36

–42

–48

–54

–60

60

0x10

0x08

0x04

0x02

0x01

40

20

0

–20

–40

–60

–80

V

R

= V

DD

= 10kΩ

A

AB

–100

1

1k

10k

100k

1M

10M

10 19 28 37 46 55 64 73 82 91 100 109 118 127

CODE (Decimal)

FREQUENCY (Hz)

Figure 16. ∆V_WB/∆T vs. Code

Figure 19. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

0

–6

0

–6

0x40

0x20

0x40

0x20

0x10

0x08

0x04

0x02

0x01

–12

–18

–24

–30

–36

–42

–48

–54

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

–60

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, R_AB= 5 kΩ

Figure 20. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

0

–6

0

–6

0x40

0x20

5kΩ

–12

–18

–24

–30

–36

–42

–48

–54

–12

–18

–24

–30

–36

–42

–48

–54

–60

10kΩ

0x10

0x08

0x04

100kΩ

50kΩ

0x02

0x01

–60

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 18. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

Figure 21. −3 dB Bandwidth @ Code = 0x80

Rev. F | Page 10 of 20

Data Sheet

AD5247

0.30

V

= 5.5V

= 5.0V

= 0V

DD

T

= 25°C

A-V

= 5.5V

A

T

= 25°C

DD

CODE = 0x55

A

R

= 10kΩ

AB

B

0.25

0.20

0.15

0.10

0.05

0

CODE 0x40 TO CODE 0x3F

B-V

= 5.5V

DD

CODE = 0x7F

C-V

= 2.7V

DD

CODE = 0x55

D-V

= 2.7V

DD

CODE = 0x7F

V

W

A

B

C

D

1k

10k

100k

FREQUENCY (Hz)

1M

200ns/DIV

Figure 22. I_DDvs. Frequency

Figure 25. Midscale Glitch, Code 0x40 to Code 0x3F

150

125

100

75

T

R

= 25°C

A

V

= 5.5V

= 5.0V

= 0V

T = 25°C

A

DD

= 50kΩ

AB

R

= 10kΩ

A

AB

B

CODE 0x00 TO CODE 0x7F

V

= 2.7V

DD

V

W

50

25

V

= 5.5V

64

DD

0

4µs/DIV

0

16

32

48

80

96

112

128

CODE (Decimal)

Figure 23. Wiper Resistance vs. Code vs. V_DD

Figure 26. Large Signal Settling Time

T

R

F

= 25°C

V

= 5.5V

= 5.0V

= 0V

A

DD

= 10kΩ

AB

A

B

= 100kHz

CLK

V

W

5V

0V

CLK

1µs/DIV

Figure 24. Digital Feedthrough

Rev. F | Page 11 of 20

AD5247

Data Sheet

TEST CIRCUITS

Figure 27 to Figure 32 define the test conditions used in the Specifications section.

V

A

V+ = V ± 10%

DD

DUT

A

V+ = V

DD

1LSB = V+/2

ΔV

%

MS

N

PSSR (%/%) =

V

DD

A

ΔV

DD

W

V+

B

V

MS

Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)

Figure 30. Power Supply Sensitivity (PSS, PSSR)

NO CONNECT

DUT

I

W

+15V

A

W

V

IN

W

B

OP27

–15V

V

OUT

B

V

MS

Figure 28. Resistor Position Nonlinearity Error (R-INL, R-DNL)

Figure 31. Gain vs. Frequency

NC

DUT

I

= V /R

DD NOMINAL

W

V

DD

A

I

A

B

V

CM

W

V

MS2

B

GND

V

CM

V

R

= [V

MS1

– V ]/I

MS2 W

MS1

W

NC

Figure 29. Wiper Resistance

Figure 32. Common-Mode Leakage Current

Rev. F | Page 12 of 20

Data Sheet

AD5247

I²C INTERFACE

The following abbreviations are used in this section:

W

= write

•

S = start condition

P = stop condition

A = acknowledge

X = don’t care

•

R = read

A6, A5, A4, A3, A2, A1, A0 = address bits

D6, D5, D4, D3, D2, D1, D0 = data bits

Table 6. Write Mode

A6 A5

S

A4

A3

A2

A1

A0

A

X

0

D6

D5

D4

D3

D2

D1

D0

A

P

W

R

Slave Address Byte

Data Byte

Table 7. Read Mode

A6 A5

S

A4

A3

A2

A1

D6

D4

D3

Slave Address Byte

Data Byte

1

9

1

9

1

SCL

A6

A5

A4

A3 A2

A1 A0

R/W

ACK

X

D6

D5 D4

D3 D2

D1 D0

SDA

ACK BY

AD5247

ACK BY

AD5247

FRAME 2

DATA BYTE

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

START BY

MASTER

Figure 33. Writing to the RDAC Register

1

9

1

0

9

SCL

A6 A5 A4

A3 A2 A1

A0

D6 D5

D4

D3 D2 D1

D0

R/W

S

ACK BY

AD5247

NO ACK BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

RDAC REGISTER

STOP BY

MASTER

START BY

MASTER

Figure 34. Reading from the RDAC Register

Table 8. I²C Slave Addresses

Slave Addresses

A6 A5 A4 A3 A2 A1 A0 Model

Slave Address

A6 A5 A4 A3 A2 A1 A0

Model

AD5247BKS5-R2

AD5247BKS5-RL7

AD5247BKSZ5-RL7

AD5247BKS10-R2

AD5247BKS10-RL7

AD5247BKSZ10-RL7

AD5247BKSZ10-1RL7

AD5247BKSZ10-2RL7

AD5247BKS50-R2

0

1

0

1

0

1

0

1

0

1

0

1

0

AD5247BKS50-RL7

AD5247BKSZ50-RL7

AD5247BKS100-R2

AD5247BKSZ100-R2

AD5247BKS100-RL7

AD5247BKSZ100-RL7

AD5247BKSZ100-1RL7

AD5247BKSZ100-2RL7

0

1

0

1

0

1

0

1

0

Rev. F | Page 13 of 20

AD5247

Data Sheet

THEORY OF OPERATION

The AD5247 is a 128-position, digitally-controlled variable

resistor (VR) device. An internal power-on preset places the

wiper at midscale during power-on, which simplifies the

default condition recovery at power-up.

The general equation determining the digitally programmed

output resistance between W and B is

D

R_WB(D) =

×R_AB+ 2×R_W

(1)

128

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

where:

D is the decimal equivalent of the binary code loaded in the

7-bit RDAC register.

The nominal resistance (R_AB) of the RDAC between Terminal A

and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The

final two or three digits of the part number determine the nominal

resistance value; for example, 10 kΩ = 10 and 50 kΩ = 50. The

R

_ABis the end-to-end resistance.

_Wis the wiper resistance contributed by the on resistance of

the internal switch.

R

_ABof the VR has 128 contact points accessed by the wiper

In summary, if R_AB= 10 kΩ and the Terminal A is open-circuited,

the output resistance R_WB, shown in Table 9, is set for the indicated

RDAC latch codes.

terminal, plus the B terminal contact. The 7-bit data in the

RDAC latch is decoded to select one of the 128 possible settings.

Assuming a 10 kΩ part is used, the wiper’s first connection starts

at the B terminal for Data 0x00. Because there is a 50 Ω wiper

contact resistance, such a connection yields a minimum of 100 Ω

(2 × 50 Ω) resistance between Terminal W and Terminal B. The

second connection is the first tap point, corresponding to 178 Ω

(R_WB= R_AB/128 + R_W= 78 Ω + 2 × 50 Ω) for Data 0x01. The third

connection is the next tap point, representing 256 Ω (2 × 78 Ω

+ 2 × 50 Ω) for Data 0x02, and so on. Each LSB data value increase

moves the wiper up the resistor ladder until the last tap point is

reached at 10,100 Ω (R_AB+ 2 × R_W).

Table 9. Codes and Corresponding R_WBResistance

D (Decimal)

R_WB(Ω)

10,072

5150

228

Output State

127

64

1

Full scale (R_AB+ 2 × R_W)

Midscale

1 LSB

0

150

Zero scale (wiper contact resistance)

Note that in the zero-scale condition, a finite resistance of

100 Ω between Terminal W and Terminal B is present. Care

should be taken to limit the current flow between W and B in

this state to a maximum pulse current of no more than 20 mA.

Otherwise, degradation or possible destruction of the internal

switch contact can occur.

Figure 35 shows a simplified diagram of the equivalent RDAC

circuit where the last resistor string is not accessed.

Ax

Similar to the mechanical potentiometer, the resistance of

the RDAC between Wiper W and Terminal A also produces a

digitally controlled complementary resistance, R_WA. When

these terminals are used, the Terminal B can be opened. Set the

resistance value for R_WAto start at a maximum value of resistance

and to decrease the data loaded in the latch increases in value.

The general equation for this operation is

R

D6

D5

D4

D3

D2

D1

D0

S

Wx

Bx

RDAC

128 − D

128

R_WA(D) =

×R_AB+ 2×R_W

(2)

LATCH

AND

DECODER

R

S

If R_AB= 10 kΩ and the B terminal is open-circuited, the output

resistance, R_WA, shown in Table 10, is set for the indicated RDAC

latch codes.

Figure 35. AD5247 Equivalent RDAC Circuit

Table 10. Codes and Corresponding R_WAResistance

D (Decimal)

R_WA(Ω)

Output State

Full scale

Midscale

1 LSB

127

64

1

228

5150

10,071

10,150

0

Zero scale

Typical device-to-device matching is process lot dependent

and can vary by up to 30%. Because the resistance element

is processed in thin film technology, the change in R_ABwith

temperature has a very low 45 ppm/°C temperature coefficient.

Rev. F | Page 14 of 20

Data Sheet

AD5247

The 2-wire I²C serial bus protocol operates as follows:

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

1. The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 33). The

following byte is the slave address byte, consisting of the

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A, proportional to the input voltage

at A-to-B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A-to-B, W-to-A, and W-to-B can be at

either polarity.

W

7-bit slave address followed by an R/ bit (this bit determines

whether data is read from or written to the slave device). The

slave, whose address corresponds to the transmitted address,

responds by pulling the SDA line low during the ninth clock

pulse (this is termed the acknowledge bit). At this stage, all

other devices on the bus remain idle while the selected

device waits for data to be written to or read from its serial

If ignoring the effect of the wiper resistance for approximation,

connecting the Terminal A to 5 V and the Terminal B to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage

applied across Terminal A and Terminal B divided by the 128

positions of the potentiometer divider. The general equation

defining the output voltage at V_Wwith respect to ground for any

valid input voltage applied to Terminal A and Terminal B is

W

register. If the R/ bit is high, the master reads from the

W

slave device. If the R/ bit is low, the master writes to the

slave device.

2. In write mode, after acknowledgement of the slave address

byte, the next byte is the data byte. Data is transmitted over

the serial bus in sequences of nine clock pulses (eight data

bits followed by an acknowledge bit). The transitions on

the SDA line must occur during the low period of SCL

and remain stable during the high period of SCL (see

Figure 33).

D

128

V_W(D) =

×V_A

(3)

A more accurate calculation that includes the effect of wiper

resistance, V_W, is

R_WB(D)

R_AB

V_W(D) =

×V_A

(4)

3. In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of

nine clock pulses (a slight difference from write mode,

where eight data bits are followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during

the high period of SCL (see Figure 34).

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

rheostat mode, divider mode makes the output voltage mainly on

the ratio of Internal Resistor R_WAto Internal Resistor R_WB, and

not the absolute values. Therefore, the temperature drift reduces

to 15 ppm/°C.

I²C-COMPATIBLE 2-WIRE SERIAL BUS

4. When all data bits have been read or written, a stop con-

dition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10^thclock pulse to establish a stop condition

(see Figure 33). In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA

line remains high). The master then brings the SDA line

low before the 10^thclock pulse, which goes high to establish

a stop condition (see Figure 34).

The first byte of the AD5247 is a slave address byte (see the I²C

W

Interface section). It has a 7-bit slave address and an R/ bit.

The 5 kΩ and 50 kΩ options support one 7-bit slave address

while the 10 kΩ and 100 kΩ options each have three hard-coded

slave address options available (see Table 8 for a full list of slave

address locations). The extra hard coded slave addresses on the

10 kΩ and 100 kΩ options allow users to employ up to three of

these devices on one I²C bus. The seven MSBs of the slave address

are followed by 0 for a write command or 1 to place the device

in read mode.

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing the part only

once. For example, after the RDAC has acknowledged its slave

address in the write mode, the RDAC output updates on each

successive byte. If different instructions are needed, the write/read

mode has to start again with a new slave address and data byte.

Similarly, a repeated read function of the RDAC is also allowed.

Rev. F | Page 15 of 20

AD5247

Data Sheet

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

MAXIMUM OPERATING CURRENT

While most legacy systems can be operated at one voltage, a

new component can be optimized at another voltage. When

two systems operate the same signal at two different voltages,

proper level shifting is needed. For instance, users can employ

a 3.3 V E²PROM to interface with a 5 V digital potentiometer. A

level shifting scheme is needed to enable a bidirectional commu-

nication so that the setting of the digital potentiometer can be

stored in and retrieved from the E²PROM. Figure 36 shows one

of the level-shifting implementations. M1 and M2 can be any

N-channel signal FETs, or if V_DDfalls below 2.5 V, M1 and M2

can be low threshold FETs such as the FDV301N.

At low code values, the user should be aware that, due to low

resistance values, the current through the RDAC might exceed

the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,

and the current through Terminal W and Terminal B is plotted

with respect to code. A line is also drawn denoting the 5 mA

current limit. Note that at low code values (particularly for the

5 kΩ and 10 kΩ options), the current level increases signifi-

cantly. Care should be taken to limit the current flow between

W and B in this state to a maximum continuous current of

5 mA and a maximum pulse current of no more than 20 mA.

Otherwise, degradation or possible destruction of the internal

switch contacts can occur.

V

= 3.3V

V

= 5V

DD1

DD2

100

R

P

G

S

D

SDA2

SDA1

SCL1

10

G

5mA CURRENT LIMIT

M1

S

D

SCL2

R

= 5kΩ

AB

M2

3.3V

5V

1

R

= 10kΩ

AB

2

AD5247

E PROM

R

= 50kΩ

AB

0.1

Figure 36. Level-Shifting for Operation at Different Potentials

R

= 100kΩ

ESD PROTECTION

AB

0.01

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures as shown in Figure 37. This applies

to digital input pins (SDA and SCL).

64

80

96

112

128

0

16

32

48

CODE (Decimal)

Figure 39. Maximum Operating Current

340Ω

SDA/

SCL

LOGIC

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminal A and Terminal W (see Figure 38), it is important

to power V_DD/GND before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that V_DDis powered unintentionally and can affect the rest of the

user’s circuit. The ideal power-up sequence is in the following

order: GND, V_DD, digital inputs, V_A, and V_W. The relative order

of powering V_Aand V_Wand the digital inputs is not important

as long as they are powered after V_DD/GND.

GND

Figure 37. ESD Protection of Digital Pins

TERMINAL VOLTAGE OPERATING RANGE

The AD5247 V_DDand GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer operation.

Supply signals present on Terminal A and Terminal W that exceed

_DDor GND are clamped by the internal forward biased diodes

(see Figure 38).

V

DD

A

W

GND

Figure 38. Maximum Terminal Voltages Set by V_DDand GND

Rev. F | Page 16 of 20

Data Sheet

AD5247

AD5247. The measurement over time shows that the device

LAYOUT AND POWER SUPPLY BYPASSING

draws approximately 1.3 µA and consumes negligible power.

Over a course of 30 days, the battery was depleted by less than

2%, the majority of which was due to the intrinsic leakage

current of the battery itself.

It is good practice to employ a compact, minimum lead-length

layout design. The leads to the inputs should be as direct as pos-

sible with minimum conductor length. Ground paths should

have low resistance and low inductance.

110%

Similarly, it is good practice to bypass the power supplies with

quality capacitors for optimum stability. Supply leads to the device

should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic

capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capaci-

tors should also be applied at the supplies to minimize any transient

disturbance and low frequency ripple (see Figure 40). Note that the

digital ground should also be joined remotely to the analog ground

at one point to minimize the ground bounce.

108%

T

= 25°C

A

106%

104%

102%

100%

98%

96%

94%

V

DD

C3

10µF

+

92%

C1

0.1µF

90%

AD5247

0

5

10

15

20

25

30

DAYS

Figure 41. Battery Operating Life Depletion

GND

This demonstrates that constantly biasing the potentiometer

is a practical approach. Most portable devices do not require

the removal of batteries for charging. Although the resistance

setting of the AD5247 is lost when the battery needs replace-

ment, such events occur rather infrequently. As a result, this

inconvenience is justified by the lower cost and smaller size

offered by the AD5247. If total power is lost, the user should

be provided with a means to adjust the setting accordingly.

Figure 40. Power Supply Bypassing

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the additional

cost for the EEMEM, the AD5247 can be considered a low cost

alternative because it maintains a constant bias to retain the

wiper setting. The AD5247 is specifically designed with low

power in mind, which allows low power consumption even in

battery-operated systems.

Figure 41 demonstrates the power consumption from a 3.4 V

450 mA/hr Li-Ion cell phone battery, which is connected to the

Rev. F | Page 17 of 20

AD5247

Data Sheet

OUTLINE DIMENSIONS

2.20

2.00

1.80

2.40

2.10

1.80

6

1

5

2

4

3

1.35

1.25

1.15

0.65 BSC

1.30 BSC

1.00

0.90

0.70

0.40

0.10

1.10

0.80

0.46

0.36

0.26

0.22

0.08

SEATING

PLANE

0.10 MAX

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 42. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

6-lead Thin Shrink Small OutlineTransistor Package [SC70] KS-6

Model¹

R_AB(kΩ) Temperature Range Package Description²

Branding

D96

D95

D5E

DAK

D97

D98

DAJ

DAL

AD5247BKSZ5-RL7

AD5247BKSZ10-RL7

AD5247BKSZ10-1RL7

AD5247BKSZ10-2RL7

AD5247BKSZ50-RL7

AD5247BKSZ100-R2

AD5247BKSZ100-RL7

AD5247BKSZ100-1RL7

AD5247BKSZ100-2RL7

EVAL-AD5247DBZ

5

–40°C to +125°C

10

50

6-lead Thin Shrink Small OutlineTransistor Package [SC70] KS-6

Evaluation Board

100

¹Z = RoHS compliant part.

²The evaluation board is shipped with the 10 kΩ R_ABresistor option; however, the board is compatible with all available resistor value options.

Rev. F | Page 18 of 20

Data Sheet

NOTES

AD5247

Rev. F | Page 19 of 20

AD5247

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D03876-0-5/12(F)

Rev. F | Page 20 of 20


型号：	AD5247BKSZ10-2RL7
厂家：	ADI
描述：	128-Position I2C-Compatible Digital Potentiometer 128位I2C兼容数字电位计数字电位计
文件：	总20页 (文件大小：489K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5247BKSZ10-2RL7 [ADI]

相关型号：

AD5247BKSZ10-RL7

AD5247BKSZ100-1RL7

AD5247BKSZ100-2RL7

AD5247BKSZ100-R2

AD5247BKSZ100-RL7

AD5247BKSZ5-RL7

AD5247BKSZ50-RL7

AD5247EVAL

AD5248

AD5248BRM10

AD5248BRM10-R2

AD5248BRM10-RL7