AD5248BRM100-RL7 [ADI]
Dual 256-Position I2C Compatible Digital Potentiometer; 双256位I2C兼容数字电位计型号: | AD5248BRM100-RL7 |
厂家: | ADI |
描述: | Dual 256-Position I2C Compatible Digital Potentiometer |
文件: | 总20页 (文件大小:1067K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual 256-Position I2C Compatible
Digital Potentiometer
AD5243/AD5248
FEATURES
2-channel, 256-position
FUNCTIONAL BLOCK DIAGRAMS
A1
W1
B1
A2
W2
B2
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typ on power-up
Full read/write of wiper register
Power-on preset to midscale
V
DD
WIPER
REGISTER 1
WIPER
REGISTER 2
Extra package address decode pins AD0 and AD1 (AD5248
only)
GND
Computer software replaces µC in factory programming
applications
Single supply: 2.7 V to 5.5 V
AD5243
SDA
SCL
PC INTERFACE
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA max
Figure 1. AD5243
Wide operating temperature: −40°C to +125°C
Evaluation board available
W1
B1
W2
B2
APPLICATIONS
Systems calibrations
V
DD
RDAC
REGISTER 1
RDAC
REGISTER 2
Electronics level settings
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
GND
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
AD0
AD1
ADDRESS
DECODE
AD5248
8
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
SDA
SCL
SERIAL INPUT
REGISTER
Figure 2. AD5248
GENERAL DESCRIPTION
The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm
packaged solution for dual 256-position adjustment applica-
tions. These devices perform the same electronic adjustment
function as a 3-terminal mechanical potentiometer (AD5243)
or a 2-terminal variable resistor (AD5248). Available in four
different end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ), these low temperature coefficient devices are ideal
for high accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C compatible
digital interface. The AD5248 has extra package address decode
pins AD0 and AD1, allowing multiple parts to share the same
I2C 2-wire bus on a PCB. The resistance between the wiper and
either endpoint of the fixed resistor varies linearly with respect
to the digital code transferred into the RDAC latch.1
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows for usage in portable battery-operated
applications.
For applications that program the AD5243/AD5258 at the
factory, Analog Devices offers device programming software
running on Windows® NT/2000/XP operating systems. This
software effectively replaces any external I2C controllers, which
in turn enhances users’ systems time-to-market. An AD5243/
AD5248 evaluation kit and software are available. The kit
includes a cable and instruction manual.
1The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5243/AD5248
TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ Version................................... 3
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 14
Constant Bias to Retain Resistance Setting............................. 15
Evaluation Board........................................................................ 15
I2C Interface .................................................................................... 16
I2C Compatible 2-Wire Serial Bus ........................................... 16
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—All Versions ........................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage.................... 13
Programming the Potentiometer Divider............................... 14
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5243/AD5248
ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION
VDD = 5 V 10ꢀ, or 3 V 10ꢀ% VA = +VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 27°C
−2
−6
−20
0.1
0.ꢀ7
+2
+6
+77
LSB
LSB
%
(∆RAB/RAB )/∆T VAB = VDD, wiper = no connect
RWB Code = 0x00, VDD = 7 V
37
160
ppm/°C
Ω
200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
Integral Nonlinearity
DNL
INL
−1.7
−2
0.1
0.6
+1.7
+2
LSB
LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T
Code = 0x80
17
ppm/°C
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−10
0
−2.7
2
0
10
LSB
LSB
RESISTOR TERMINALS
Voltage Range7
VA, VB, VW
CA, CB
CW
IA_SD
ICM
GND
VDD
V
Capacitance6 A, B
f = 1 MHz, measured to GND, Code = 0x80
f = 1 MHz, measured to GND, Code = 0x80
VDD = 7.7 V
47
60
0.01
1
pF
pF
µA
nA
Capacitance6 W
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
1
VA = VB = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = 7 V
VDD = 7 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
0.8
0.6
1
VIN = 0 V or 7 V
CIL
7
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS 9
VDD RANGE
IDD
PDISS
2.ꢀ
7.7
6
30
V
VIH = 7 V or VIL = 0 V
VIH = 7 V or VIL = 0 V, VDD = 7 V
VDD = 7 V 10%, Code = midscale
3.7
µA
µW
%/%
PSS
0.02
0.08
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
See notes at end of section.
BW_2.7 K
THDW
tS
Code = 0x80
4.8
0.1
1
MHz
%
µs
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 7 V, VB = 0 V, 1 LSB error band
RWB = 1.27 kΩ, RS = 0
eN_WB
3.2
nV/√Hz
Rev. 0 | Page 3 of 20
AD5243/AD5248
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V 10ꢀ, or 3 V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < 125°C% unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 27°C
−1
−2.7
−20
0.1
0.27
+1
+2.7
+20
LSB
LSB
%
(∆RAB/RAB )/∆T VAB = VDD, wiper = no connect
RWB Code = 0x00, VDD =7 V
37
160
ppm/°C
Ω
200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
Integral Nonlinearity4
DNL
INL
−1
−1
0.1
0.3
+1
+1
LSB
LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T
Code = 0x80
17
ppm/°C
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−2.7 −1
0
2.7
LSB
LSB
0
1
RESISTOR TERMINALS
Voltage Range7
Capacitance6 A, B
Capacitance6 W
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
Power Supply Sensitivity
VA, VB, VW
CA, CB
CW
IA_SD
ICM
GND
VDD
V
f = 1 MHz, measured to GND, Code = 0x80
f = 1 MHz, measured to GND, Code = 0x80
VDD = 7.7 V
47
60
0.01
1
pF
pF
µA
nA
1
VA = VB = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = 7 V
VDD = 7 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 7 V
CIL
7
VDD RANGE
IDD
PDISS
2.ꢀ
7.7
6
30
0.0
8
V
VIH = 7 V or VIL = 0 V
VIH = 7 V or VIL = 0 V, VDD = 7 V
VDD = 7 V 10%, Code = midscale
3.7
µA
µW
%/%
PSS
0.02
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
BW
RAB = 10 kΩ/70 kΩ/100 kΩ, Code = 0x80
600/100/4
0
kHz
Total Harmonic Distortion
VW Settling Time (10 kΩ/70 kΩ/100
kΩ)
THDW
tS
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ
VA = 7 V, VB = 0 V, 1 LSB error band
0.1
2
%
µs
Resistor Noise Voltage Density
eN_WB
RWB = 7 kΩ, RS = 0
9
nV/√Hz
See notes at end of section.
Rev. 0 | Page 4 of 20
AD5243/AD5248
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = 5V 10ꢀ, or 3V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ1 Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS10 (Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
0
1.3
0.6
400
kHz
µs
µs
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time11
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
t7
t6
tꢀ
t8
t9
t10
1.3
0.6
0.6
µs
µs
µs
µs
ns
ns
ns
µs
0.9
100
0.6
300
300
See notes at end of section.
NOTES
1 Typical specifications represent average readings at 27°C and VDD = 7 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
7 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 7 V.
10See timing diagrams for locations of measured values.
11The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Rev. 0 | Page 7 of 20
AD5243/AD5248
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only% functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Value
–0.3 V to +ꢀ V
VDD
20 mA
7 mA
0 V to ꢀ V
–40°C to +127°C
170°C
Maximum Junction Temperature (TJMAX
)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
–67°C to +170°C
300°C
230°C/W
1Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2Package power dissipation = (TJMAX − TA)/θJA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD5243/AD5248
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
1
2
3
4
5
10
9
10
9
W1
B2
W1
B1
A1
B1
AD0
W2
B2
8
8
W2
AD5243
TOP VIEW
A2
AD5248
TOP VIEW
AD1
SDA
SCL
7
7
GND
SDA
SCL
GND
6
6
V
V
DD
DD
Figure 3. AD5243 Pin Configuration
Figure 4. AD5248 Pin Configuration
Table 5. AD5243 Pin Function Descriptions
Table 6. AD5248 Pin Function Descriptions
Pin
No.
Pin
No.
Mnemonic Description
Mnemonic Description
1
B1
B1 Terminal.
1
B1
B1 Terminal.
2
3
4
7
A1
A1 Terminal.
W2 Terminal.
Digital Ground.
Positive Power Supply.
Serial Clock Input. Positive edge
triggered.
Serial Data Input/Output.
A2 Terminal.
B2 Terminal.
2
AD0
Programmable Address Bit 0 for Multiple
Package Decoding.
W2 Terminal.
Digital Ground.
Positive Power Supply.
Serial Clock Input. Positive edge
triggered.
Serial Data Input/Output.
Programmable Address Bit 1 for Multiple
Package Decoding.
B2 Terminal.
W1 Terminal.
W2
GND
VDD
SCL
3
4
7
6
W2
GND
VDD
6
SCL
ꢀ
8
9
10
SDA
A2
B2
ꢀ
8
SDA
AD1
W1
W1 Terminal.
9
10
B2
W1
Rev. 0 | Page ꢀ of 20
AD5243/AD5248
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
0.5
0.4
T
R
= 25°C
R
= 10kΩ
A
AB
= 10kΩ
AB
1.5
1.0
0.3
V
= 2.7V
DD
0.2
0.5
0.1
V
= 2.7V; T = –40°C, +25°C, +85°C, +125°C
A
DD
0
0
V
= 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
0
0
0
32
64
96
128
160
192
224
256
0
0
0
32
32
32
64
96
128
160
192
224
256
256
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. R-INL vs. Code vs. Supply Voltages
Figure 8. DNL vs. Code vs. Temperature
0.5
0.4
1.0
0.8
T
R
= 25°C
T
R
= 25°C
= 10kΩ
A
A
= 10kΩ
AB
AB
0.3
0.6
0.2
0.4
V
= 2.7V
DD
V
= 5.5V
0.1
0.2
DD
0
0
V
= 2.7V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5.5V
DD
32
64
96
128
160
192
224
256
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 6. R-DNL vs. Code vs. Supply Voltages
Figure 9. INL vs. Code vs. Supply Voltages
0.5
0.4
0.5
0.4
R
= 10kΩ
T
R
= 25°C
= 10kΩ
AB
A
AB
0.3
0.3
V
= 5.5V
DD
T
= –40°C, +25°C, +85°C, +125°C
A
0.2
0.2
0.1
0.1
V
= 2.7V
DD
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 5.5V
DD
V
= 2.7V
DD
T
= –40°C, +25°C, +85°C, +125°C
A
32
64
96
128
160
192
224
256
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 7. INL vs. Code vs. Temperature
Figure 10. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 8 of 20
AD5243/AD5248
2.0
1.5
4.50
3.75
3.00
2.25
1.50
0.75
0
R
= 10kΩ
R
= 10kΩ
AB
AB
V
= 2.7V
DD
= –40°C, +25°C, +85°C, +125°C
T
A
1.0
0.5
0
V
= 2.7V, V = 2.7V
A
DD
V
= 5.5V
DD
= –40°C, +25°C, +85°C, +125°C
–0.5
–1.0
–1.5
–2.0
T
A
V
= 5.5V, V = 5.0V
A
DD
0
32
64
96
128
160
192
224
256
–40 –25 –10
5
20
35
50
65
80
95 110 125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 11. R-INL vs. Code vs. Temperature
Figure 14. Zero-Scale Error vs. Temperature
0.5
0.4
10
R
= 10kΩ
AB
0.3
V
V
= 5V
DD
0.2
V
= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C
A
DD
0.1
0
1
–0.1
–0.2
–0.3
–0.4
–0.5
= 3V
DD
0.1
–40
0
32
64
96
128
160
192
224
256
–7
26
59
92
125
TEMPERATURE (°C)
CODE (DECIMAL)
Figure 12. R-DNL vs. Code vs. Temperature
Figure 15. Supply Current vs. Temperature
120
100
80
2.0
1.5
R
= 10kΩ
R
= 10kΩ
AB
AB
1.0
0.5
60
V
= 2.7V
DD
= –40°C TO +85°C, –40°C TO +125°C
T
A
0
V
= 5.5V, V = 5.0V
A
DD
40
V
= 5.5V
DD
= –40°C TO +85°C, –40°C TO +125°C
–0.5
–1.0
–1.5
–2.0
T
A
20
V
= 2.7V, V = 2.7V
A
DD
0
–20
0
32
64
96
128
160
192
224
256
–40 –25 –10
5
20
35
50
65
80
95 110 125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 13. Full-Scale Error vs. Temperature
Rev. 0 | Page 9 of 20
AD5243/AD5248
50
40
30
0
–6
R
= 10kΩ
AB
0x80
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
V
T
= 2.7V
DD
= –40°C TO +85°C, –40°C TO +125°C
20
10
A
0x08
0x04
0x02
0x01
0
–10
–20
–30
V
= 5.5V
DD
= –40°C TO +85°C, –40°C TO +125°C
T
A
0
32
64
96
128
160
192
224
256
1k
10k
100k
1M
CODE (DECIMAL)
FREQUENCY (Hz)
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
–6
0
–6
0x80
0x80
0x40
0x20
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x02
0x01
0x08
0x04
0x02 0x01
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 18. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
–6
0
–6
0x80
0x40
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
100kΩ
60kHz
50kΩ
0x20
0x10
0x08
0x04
120kHz
10kΩ
570kHz
2.5kΩ
2.2MHz
0x02
0x01
1k
10k
100k
FREQUENCY (Hz)
1M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 22. –3 dB Bandwidth @ Code = 0x80
Rev. 0 | Page 10 of 20
AD5243/AD5248
10
T
= 25°C
A
1
V
= 5.5V
DD
V
V
W2
0.1
0.01
V
= 2.7V
DD
W1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
Figure 26. Analog Crosstalk
Figure 23. IDD vs. Input Voltage
V
V
W
W
SCL
Figure 27. Midscale Glitch, Code 0x80 to 0x7F
Figure 24. Digital Feedthrough
V
W
V
V
W2
SCL
W1
Figure 28. Large Signal Settling Time
Figure 25. Digital Crosstalk
Rev. 0 | Page 11 of 20
AD5243/AD5248
TEST CIRCUITS
Figure 29 through Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables.
V+ = V
DUT
W
DUT
W
DD
1LSB = V+/2
+15V
N
A
B
A
B
V
IN
V+
AD8610
–15V
V
OUT
OFFSET
GND
V
MS
2.5V
Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
Figure 33. Test Circuit for Gain vs. Frequency
NO CONNECT
DUT
0.1V
R
=
SW
I
SW
CODE = 0x00
DUT
W
I
W
A
W
I
SW
0.1V
B
B
V
MS
V
TO V
DD
SS
Figure 30. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 34. Test Circuit for Incremental On Resistance
NC
DUT
I
= V /R
DD NOMINAL
W
A
B
DUT
V
W
W
A
B
I
CM
V
V
MS2
DD
W
R
= [V
– V
]/I
MS2 W
W
MS1
GND
V
MS1
V
CM
NC NC = NO CONNECT
Figure 31. Test Circuit for Wiper Resistance
Figure 35. Test Circuit for Common-Mode Leakage Current
V
A
V+ = V ± 10%
DD
∆V
∆V
MS
DUT
W
PSRR (dB) = 20 LOG
(
)
DD
∆V
∆V
%
%
A
B
MS
DD
∆V
PSS (%/%) =
DD
V+
V
MS
Figure 32. Test Circuit for Power Supply Sensitivity(PSS, PSSR)
Rev. 0 | Page 12 of 20
AD5243/AD5248
THEORY OF OPERATION
The AD5243/AD5248 are 256-position digitally controlled
variable resistor (VR) devices.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
D
256
R
WB (D) =
× RAB + 2× RW
(1)
where:
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB is the end-to-end resistance.
The nominal resistance of the RDAC between Terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
R
W is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
A
A
A
D (Dec)
RWB (Ω)
9,961
7,060
139
Output State
W
W
W
277
128
1
Full scale (RAB − 1 LSB + RW)
Midscale
1 LSB
B
B
B
Figure 36. Rheostat Mode Configuration
0
100
Zero scale (wiper contact resistance)
Note that, in the zero-scale condition, a finite wiper resistance
of 100 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
A
R
S
256 − D
256
R
RWA(D) =
× RAB + 2× RW
(2)
D7
D6
D5
D4
D3
D2
D1
D0
S
R
S
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
W
Table 8. Codes and Corresponding RWA Resistance
D (Dec)
RWA (Ω)
Output State
Full scale
Midscale
1 LSB
277
128
1
139
R
RDAC
S
7,060
9,961
10,060
LATCH
AND
DECODER
B
0
Zero scale
Figure 37. AD5243 Equivalent RDAC Circuit
Rev. 0 | Page 13 of 20
AD5243/AD5248
340Ω
Typical device-to-device matching is process lot dependent and
may vary by up to 30ꢀ. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
LOGIC
GND
Figure 39. ESD Protection of Digital Pins
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
A, B, W
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
GND
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 VDD and GND power supply defines the
boundary conditions for proper 3-terminal digital potentiome-
ter operation. Supply signals present on Terminals A, B, and W
that exceed VDD or GND are clamped by the internal forward
biased diodes (see Figure 41).
V
I
A
W
V
O
B
V
DD
Figure 38. Potentiometer Mode Configuration
A
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
W
B
GND
Figure 41. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 41), it is important to
power VDD/GND before applying any voltage to Terminals A, B,
and W% otherwise, the diode is forward biased such that VDD is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, and VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
D
256
256 − D
256
VW (D) =
VA +
VB
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
RWB (D)
RWA(D)
RAB
(4)
VW (D) =
VA +
VB
RAB
Operation of the digital potentiometer in the divider mode
results in a more accurate operation overtemperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
ESD PROTECTION
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disk or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDA, SCL, AD0,
and AD1 (AD5248 only).
Rev. 0 | Page 14 of 20
AD5243/AD5248
This demonstrates that constantly biasing the potentiometer is
not an impractical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5243/AD5248 is lost
when the battery needs replacement, such events occur rather
infrequently such that this inconvenience is justified by the
lower cost and smaller size offered by the AD5243/AD5248. If
and when total power is lost, the user should be provided with a
means to adjust the setting accordingly.
V
V
DD
DD
+
C3
10µF
C1
0.1µF
AD5243
GND
Figure 42. Power Supply Bypassing
EVALUATION BOARD
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
An evaluation board, along with all necessary software, is avail-
able to program the AD5243/AD5248 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown in
Figure 44, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
For users who desire nonvolatility but cannot justify the addi-
tional cost for the EEMEM, the AD5243/AD5248 may be
considered as low cost alternatives by maintaining a constant
bias to retain the wiper setting. The AD5243/AD5248 are
designed specifically with low power in mind, which allows low
power consumption even in battery-operated systems. The
graph in Figure 43 demonstrates the power consumption from a
3.4 V 450 mAhr Li-Ion cell phone battery, which is connected to
the AD5243/AD5248. The measurement over time shows that
the device draws approximately 1.3 µA and consumes negligible
power. Over a course of 30 days, the battery is depleted by less
than 2ꢀ, the majority of which is due to the intrinsic leakage
current of the battery itself.
110%
108%
T
= 25°C
A
106%
104%
102%
100%
98%
Figure 44. AD5243 Evaluation Board Software
96%
The AD5243/AD5248 start at midscale upon power-up. To
increment or decrement the resistance, the user may simply
move the scrollbars on the left. To write any specific value, the
user should use the bit pattern in the upper screen and press the
Run button. The format of writing data to the device is shown
in Table 9. To read the data out from the device, the user can
simply press the Read button. The format of the read bits is
shown in Table 10.
94%
92%
90%
0
5
10
15
20
25
30
DAYS
Figure 43. Battery Operating Life Depletion
Rev. 0 | Page 17 of 20
AD5243/AD5248
I2C INTERFACE
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 46). The
following byte is the slave address byte, which consists of
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, eight data
bits are followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 48 and Figure 49).
the slave address followed by an R/ bit (this bit deter-
W
mines whether data is read from or written to the slave
device). The AD5243 has a fixed slave address byte, while
the AD5248 has two configurable address bits AD0 and
AD1 (see Table 9).
Note that the channel of interest is the one that is previ-
ously selected in the write mode. In the case where users
need to read the RDAC values of both channels, they need
to program the first channel in the write mode and then
change to the read mode to read the first channel value.
After that, they need to change back to the write mode with
the second channel selected and read the second channel
value in the read mode again. It is not necessary for users
to issue the Frame 3 data byte in the write mode for subse-
quent readback operation. Users should refer to Figure 48
and Figure 49 for the programming format.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/ bit is high, the master reads
W
from the slave device. On the other hand, if the R/ bit is
W
low, the master writes to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A Logic Low selects Channel 1 and a
Logic High selects Channel 2.
4. After all data bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 46 and Figure 47). In read mode, the
master issues a no acknowledge for the ninth clock pulse
(that is, the SDA line remains high). The master then
brings the SDA line low before the tenth clock pulse, which
goes high to establish a STOP condition (see Figure 48 and
Figure 49).
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the previ-
ous setting is applied to the RDAC. Also, during shutdown,
new settings can be programmed. When the part is
returned from shutdown, the corresponding VR setting is
applied to the RDAC.
A repeated write function gives the user flexibility to
update the RDAC output a number of times after
The remainder of the bits in the instruction byte are don’t
care bits (see Table 9).
addressing and instructing the part only once. For example,
after the RDAC has acknowledged its slave address and
instruction bytes in the write mode, the RDAC output
updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a
new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46
and Figure 47).
Rev. 0 | Page 16 of 20
AD5243/AD5248
Table 9. Write Mode
AD5243
S
0
1
0
1
1
1
1
W
A
A0
SD
X
X
X
X
X
X
A
Dꢀ
D6
D7
D4
D3
D2
D1
D0
A
P
P
Slave Address Byte
Instruction Byte
Data Byte
AD5248
S
0
1
0
1
1
AD1 AD0
W
A
A0 SD
X
X
X
X
X
X
A
Dꢀ D6 D7 D4 D3 D2 D1 D0
Data Byte
A
Slave Address Byte
Instruction Byte
Table 10. Read Mode
AD5243
S
0
1
0
1
1
1
1
R
A
Dꢀ
D6
D7
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Data Byte
AD5248
S
0
1
0
1
1
AD1
AD0
R
A
Dꢀ
D6
D7
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Data Byte
LEGEND
S = Start condition.
P = Stop condition.
A = Acknowledge.
X = Don’t care.
R = Read.
A0 = RDAC subaddress select bit.
SD = Shutdown connects wiper to B terminal and
open circuits A terminal. It does not change contents
of wiper register.
W = Write.
AD0, AD1 = Package pin
Dꢀ, D6, D7, D4, D3, D2, D1, D0 = Data bits.
programmable address bits.
t2
t8
t6
t9
SCL
t10
t4
t7
t5
t2
t3
t9
t8
SDA
t1
P
S
S
P
Figure 45. I2C Interface Detailed Timing Diagram
1
0
9
1
9
1
9
SCL
SDA
1
0
1
1
1
1
R/W
A0 SD
X
X
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
ACK BY
AD5243
ACK BY
AD5243
ACK BY
AD5243
START BY
MASTER
STOP BY
MASTER
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
FRAME 1
SLAVE ADDRESS BYTE
Figure 46. Writing to the RDAC Register—AD5243
Rev. 0 | Page 1ꢀ of 20
AD5243/AD5248
1
9
1
9
1
9
SCL
0
1
0
1
1
AD1 AD0 R/W
A0 SD
X
X
X
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
SDA
ACK BY
AD5248
ACK BY
AD5248
ACK BY
AD5248
START BY
MASTER
STOP BY
MASTER
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
FRAME 1
SLAVE ADDRESS BYTE
Figure 47. Writing to the RDAC Register—AD5248
1
9
1
9
SCL
0
1
0
1
1
1
1
R/W
D7 D6 D5 D4 D3 D2 D1 D0
SDA
ACK BY
AD5243
NO ACK
BY MASTER
START BY
MASTER
FRAME 2
RDAC REGISTER
STOP BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243
1
0
9
1
9
SCL
SDA
1
0
1
1
AD1 AD0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
NO ACK
BY MASTER
ACK BY
AD5248
START BY
MASTER
FRAME 2
RDAC REGISTER
FRAME 1
SLAVE ADDRESS BYTE
STOP BY
MASTER
Figure 49. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248
Multiple Devices on One Bus (Applies Only to AD5248)
5V
R
R
P
P
Figure 50 shows four AD5248 devices on the same serial bus.
Each has a different slave address, because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C compatible interface.
SDA
SCL
MASTER
5V
5V
5V
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
AD0
AD0
AD0
AD0
AD5248
AD5248
AD5248
AD5248
Figure 50. Multiple AD5248 Devices on One I2C Bus
Rev. 0 | Page 18 of 20
AD5243/AD5248
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 51. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB
Temperature
Package Description
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Evaluation Board
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Package Option
Branding
D0L
D0L
D0M
D0M
D0N
D0N
D0P
D0P
AD7243BRM2.7
AD7243BRM2.7-RLꢀ
AD7243BRM10
AD7243BRM10-RLꢀ
AD7243BRM70
AD7243BRM70-RLꢀ
AD7243BRM100
AD7243BRM100-RLꢀ
AD7243EVAL
2.7 kΩ
2.7 kΩ
10 kΩ
10 kΩ
70 kΩ
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
70 kΩ
100 kΩ
100 kΩ
See Note 1
2.7 kΩ
2.7 kΩ
10 kΩ
10 kΩ
70 kΩ
70 kΩ
AD7248BRM2.7
AD7248BRM2.7-RLꢀ
AD7248BRM10
AD7248BRM10-RLꢀ
AD7248BRM70
AD7248BRM70-RLꢀ
AD7248BRM100
AD7248BRM100-RLꢀ
AD7248EVAL
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
−40°C to +127°C
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
D1F
D1F
D1G
D1G
D1H
D1H
D1J
100 kΩ
100 kΩ
See Note 1
D1J
Evaluation Board
1The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. 0 | Page 19 of 20
AD5243/AD5248
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04109–0–1/04(0)
Rev. 0 | Page 20 of 20
相关型号:
AD5248BRM2.5-R2
IC 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer
ADI
AD5248BRM50-R2
IC 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer
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