AD5251BRU100 [ADI]
Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers; 双64和256位I2C非易失性存储器数字电位器
| 型号： | AD5251BRU100 |
| 厂家： | 
ADI |
| 描述： | Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers |
| 文件： | 总28页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 64-and 256-Position I2C Nonvolatile
Memory Digital Potentiometers
AD5251/AD5252
White LED brightness adjustment
FEATURES
AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory1 stores wiper setting w/write protection
Power-on refreshed with EEMEM settings in 300 µs typ
EEMEM rewrite time = 540 µs typ
RF base station power amp bias control
Programmable gain and offset control
Programmable voltage-to-current conversion
Programmable power supply
Sensor calibrations
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information
I2C compatible serial interface
Direct read/write access of RDAC2 and EEMEM registers
Predefined linear increment/decrement commands
Predefined 6 dB step change commands
Synchronous or aysynchronous dual channel update
Wiper setting read back
FUNDAMENTAL BLOCK DIAGRAM
RDAC EEMEM
V
RDAC1
DD
A1
W1
B1
RDAC1
REGIS-
TER
EEMEM
POWER-ON
REFRESH
RAB
TOL
V
SS
DGND
WP
DATA
RDAC3
A3
W3
B3
SCL
SDA
RDAC3
REGIS-
TER
2
I C
SERIAL
INTERFACE
CONTROL
AD0
AD1
COMMAND
DECODE LOGIC
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply 2.25 V to 2.75 V
2 slave address decoding bits allow operation of 4 devices
100-year typical data retention TA = 55°C
Operating temperature –40°C to +85°C
ADDRESS
DECODE LOGIC
AD5251/
AD5252
POWER-
ON RESET
CONTROL LOGIC
Figure 1.
APPLICATIONS
1The terms nonvolatile memory and EEMEM are used interchangeably.
2The terms digital potentiometer and RDAC are used interchangeably.
Mechanical potentiometer replacement
General purpose DAC replacement
LCD panel VCOM adjustment
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.
GENERAL DESCRIPTION
The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem-
ory, digitally controlled potentiometers with 64/256 positions,
respectively. These devices perform the same electronic adjust-
ment functions as mechanical potentiometers, trimmers, and
variable resistors. The parts’ versatile programmability allows
multiple modes of operation, including read/write access in the
RDAC and EEMEM registers, increment/decrement of
resistance, resistance changes in 6 dB scales, wiper setting
readback, and extra EEMEM for storing user-defined infor-
mation such as memory data for other components, look-up
table, or system identification information.
The AD5251/AD5252 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update modes. The
increment and decrement functions allow stepwise linear
adjustments, while 6 dB step changes are equivalent to
doubling or halving the RDAC wiper setting. These functions
are useful for steep-slope nonlinear adjustments such as white
LED brightness and audio volume control. The parts have a
patented resistance tolerance storing function which enable the
user to access the EEMEM and obtain the absolute end-to-end
resistance values of the RDACs for precision applications.
The AD5251/AD5252 allow the host I2C controllers to write
any of the 64- or 256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
The AD5251/AD5252 are available in TSSOP-14 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can
operate over the –40°C to +85°C extended industrial
temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5251/AD5252
TABLE OF CONTENTS
Electrical Characteristics................................................................. 3
Interface Timing Characteristics................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Description .............................. 9
I2C Interface Timing Diagram.................................................... 9
I2C Interface General Description................................................ 10
I2C Interface Detail Description ................................................... 11
RDAC/EEMEM Write ............................................................... 11
I2C Compatible 2-Wire Serial Bus................................................ 15
Typical Performance Characteristics ........................................... 16
Operational Overview.................................................................... 20
Linear Increment and Decrement Commands ...................... 20
6 dB Adjustments (Doubling/Halving WIPER Setting)..... 20
Digital Input/Output Configuration........................................ 21
Multiple Devices on One Bus ................................................... 21
Terminal Voltage Operation Range ......................................... 21
Power-Up and Power-Down Sequences.................................. 21
Layout and Power Supply Biasing............................................ 22
Digital Potentiometer Operation ............................................. 22
Programmable Rheostat Operation......................................... 22
Programmable Potentiometer Operation ............................... 23
Applications..................................................................................... 24
LCD Panel Vcom Adjustment ..................................................... 24
Current-Sensing Amplifier ....................................................... 24
Adjustable High Power LED Driver ........................................ 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/04—Revision 0: Initial Version
Rev.0 | Page 2 of 28
AD5251/AD5252
ELECTRICAL CHARACTERISTICS
1 kΩ Version. VDD = 3 V 10% or 5 V 10%; VSS = 0 V or VDD/VSS
=
ꢀ.5 V 10%; VA = +VDD, VB = 0 V, –40°C < TA < +85°C, unless
otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution
Resistor Differential
Nonlinearity2
N
AD5251/AD5252
RWB, RWA = NC, VDD = 5.5 V, AD5251
6/8
+0.5
Bits
LSB
R-DNL
–0.5
0.2
RWB, RWA = NC, VDD = 5.5 V, AD5252
RWB, RWA = NC, VDD = 2.7 V, AD5251
RWB, RWA = NC, VDD = 2.7 V, AD5252
RWB, RWA = NC, VDD = 5.5 V, AD5251
RWB, RWA = NC, VDD = 5.5 V, AD5252
RWB, RWA = NC, VDD = 2.7 V, AD5251
RWB, RWA = NC, VDD = 2.7 V, AD5252
TA = 25°C
–1
0.25 +1
LSB
–0.75
–1.5
–0.5
–2
–1
–2
0.3
0.3
0.2
+0.75 LSB
+1.5
+0.5
+2
LSB
LSB
LSB
LSB
LSB
%
Resistor Nonlinearity2
R-INL
0.5
+2.5
+9
+4
+14
+30
Nominal Resistor Tolerance
∆RAB/RAB
–30
Resistance Temperature
Coefficent
Wiper Resistance
(∆RAB/RAB) × 106/∆T
RW
650
75
200
0.15
ppm/°C
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
130
300
Ω
Ω
%
Channel Resistance Matching
∆RAB1/∆RAB3
DC CHARACTERISTIC
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3
DNL
INL
AD5251
AD5252
AD5251
AD5252
–0.5
–1
–0.5
–2
0.1
0.25 +1
0.2
0.5
+0.5
LSB
LSB
LSB
LSB
Integral Nonlinearity3
+0.5
+2
Voltage Divider Temperature
Coefficent
Full-Scale Error
(∆VW/VW) × 106/∆T
VWFSE
Code = half scale
25
ppm/°C
LSB
LSB
Code = full scale, VDD = 5.5 V, AD5251
Code = full scale, VDD = 5.5 V, AD5252
Code = full scale, VDD = 2.7 V, AD5251
Code = full scale, VDD = 2.7 V, AD5252
Code = zero scale, VDD = 5.5 V, AD5251
Code = zero scale, VDD = 5.5 V, AD5252
Code = zero scale, VDD = 2.7 V, AD5251
Code = zero scale, VDD = 2.7 V, AD5252
–5
–16
−6
–23
0
0
0
0
–3
–11
–4
–16
3
11
4
15
0
0
0
LSB
0
5
16
6
20
LSB
LSB
LSB
LSB
Zero-Scale Error
VWZSE
LSB
RESISTOR TERMINALS
Voltage Range4
VA, VB, VW
CA, CB
VSS
VDD
V
pF
Capacitance5 Ax, Bx
f = 1 kHz, measured to GND,
Code = half scale
f = 1 kHz, measured to GND,
Code = half scale
85
95
Capacitance5 Wx
CW
pF
Common-Mode Leakage
Current
ICM
VIH
VA = VB = VDD/2
0.01
1
µA
DIGITAL INPUTS and OUTPUTS
Input Logic High
VDD = 5 V, VSS = 0 V
VDD/VSS = 2.7 V/0 V or VDD/VSS
VDD = 5V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD =5 V, VSS = 0 V
2.4
2.1
V
V
V
V
V
=
2.5 V
Input Logic Low
Output Logic High (SDA)
Output Logic Low (SDA)
VIL
VOH
VOL
0.8
0.4
4.9
Rev. 0 | Page 3 of 28
AD5251/AD5252
Parameter
Symbol
Conditions
WP
Min
Typ1
Max
Unit
IWP
5
µA
= VDD
Leakage Current
A0 Leakage Current
Input Leakage Current (Other
IA0
II
A0 = GND
VIN = 0 V or VDD
3
1
µA
µA
WP
than
Input Capacitance5
POWER SUPPLIES
and A0)
CI
5
pF
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
VDD
VDD/VSS
IDD
VSS = 0 V
2.7
2.25
5.5
2.75
15
–15
V
V
µA
µA
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = +2.5 V,
VSS = –2.5 V
5
–5
ISS
EEMEM Data Storing Mode
Current
IDD_STORE
VIH = VDD or VIL = GND
35
mA
mA
EEMEM Data Restoring Mode
IDD_RESTORE
VIH = VDD or VIL = GND
2.5
Current6
Power Dissipation7
PDISS
PSS
VIH = VDD = 5 V or VIL = GND
∆VDD = 5 V 10%
0.075 mW
0.025 %/%
Power Supply Sensitivity
−0.025 0.01
∆VDD = 3 V 10%
–0.04
0.02
0.04
%/%
DYNAMIC CHARACTERISTICS5, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Digital Crosstalk
BW
THD
tS
eN_WB
CT
RAB = 1 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V
4
MHz
%
µs
nV/√Hz
dB
0.05
0.2
3
RWB = 500 Ω, f = 1 kHz (thermal noise only)
VA = VDD, VB = 0 V, measure VW with
–80
adjacent RDAC making full-scale change
Analog Coupling
CAT
Signal input at A1 and measure the
output at W3, f = 1 kHz
–72
dB
1 Typical represents the average reading at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ
version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 4 of 28
AD5251/AD5252
10 kΩ, 50 kΩ, 100 kΩ Versions. VDD = +3 V 10% or + 5 V 10%. VSS = 0 V or VDD/VSS
=
ꢀ.5 V 10%. VA = +VDD, VB = 0 V,
–40°C < TA < +85°C, unless otherwise noted.
Table ꢀ.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution
N
AD5251/AD5252
6/8
+0.75
+1
+0.75
+2.5
+20
Bits
LSB
LSB
LSB
LSB
%
Resistor Differential NL2
R-DNL
RWB, RWA = NC, AD5251
RWB, RWA = NC, AD5252
RWB, RWA = NC, AD5251
RWB, RWA = NC, AD5252
TA = 25°C
−0.75
−1
−0.75
−2.5
−20
0.1
0.25
0.25
1
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance
Resistance Temperature
Coefficent
∆RAB/RAB
(∆RAB/RAB) × 106/∆T
650
ppm/°C
Wiper Resistance
RW
IW = 1 V/R, VDD = 5 V
IW = 1 V/R, VDD = 3 V
RAB = 10 kΩ, 50 kΩ
RAB = 100 kΩ
75
130
300
Ω
Ω
%
%
200
0.15
0.05
Channel Resistance Matching ∆RAB1/∆RAB2
DC CHARACTERISTICS
POTENTIOMETER DIVIDER
MODE
Differential Nonlinearity3
DNL
INL
AD5251
AD5252
AD5251
AD5252
−0.5
−1
−0.5
−1.5
0.1
0.3
0.15
0.5
+0.5
+1
+0.5
+1.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
3
Voltage Divider
Temperature Coefficent
Full-Scale Error
(∆VW/VW) × 106/∆T
VWFSE
Code = half scale
15
−0.3
−1
0.3
1.2
ppm/°C
LSB
LSB
LSB
LSB
Code = full scale, AD5251
Code = full scale, AD5252
Code = zero scale, AD5251
Code = zero scale, AD5252
−1
−3
0
0
0
1
3
Zero-Scale Error
VWZSE
0
RESISTOR TERMINALS
Voltage Range4
VA, VB, VW
CA, CB
VSS
VDD
V
pF
Capacitance5 Ax, Bx
f = 1 kHz, measured to GND,
Code = half scale
f = 1 kHz, measured to GND,
Code = half scale
85
Capacitance5 Wx
CW
ICM
95
pF
Common-Mode Leakage
Current
VA = VB = VDD/2
0.01
1
µA
DIGITAL INPUTS and OUTPUTS
Input Logic High
VIH
VIL
VDD =5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS
VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
2.4
2.1
V
V
V
V
V
V
µA
=
2.5 V
Input Logic Low
0.8
0.6
Output Logic High (SDA)
Output Logic Low (SDA)
VOH
VOL
IWP
4.9
0.4
5
WP
= VDD
Leakage Current
A0 Leakage Current
Input Leakage Current
IA0
A0 = GND
3
1
µA
WP
II
VIN = 0 V or VDD
µA
pF
(Other than
and A0)
Input Capacitance5
CI
5
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
2.7
5.5
V
Rev. 0 | Page 5 of 28
AD5251/AD5252
Parameter
Symbol
VDD/VSS
IDD
Conditions
Min
2.25
Typ1
Max
2.75
15
Unit
V
µA
µA
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = +2.5 V, VSS
= -2.5 V
5
−5
ISS
−15
EEMEM Data Storing Mode
Current
IDD_STORE
VIH = VDD or VIL = GND, TA = 0°C to 85°C
35
mA
mA
mW
EEMEM Data Restoring Mode
IDD_RESTORE
VIH = VDD or VIL = GND, TA = 0°C to 85°C
2.5
Current6
Power Dissipation7
PDISS
PSS
VIH = VDD = 5 V or VIL = GND
∆VDD = 5 V 10%
0.075
Power Supply Sensitivity
−0.005 +0.002
+0.005 %/%
∆VDD = 3 V 10%
−0.01
+0.002
+0.01
%/%
DYNAMIC CHARACTERISTICS5, 8
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
BW
THDW
tS
RAB = 10 kΩ/50 kΩ/100 kΩ
VA = 1 Vrms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V, RAB = 10 kΩ/50
kΩ/100 kΩ
400/80/40
0.05
1.5/7/14
kHz
%
µs
Resistor Noise Voltage
Digital Crosstalk
eN_WB
CT
10 kΩ/50 kΩ/100 kΩ, code = midscale,
f = 1 kHz (thermal noise only)
VA = VDD, VB = 0 V, Measure VW with
adjacent RDAC making full scale
change
9/20/29
-80
nV/√Hz
dB
Analog Coupling
CAT
Signal input at A1 and measure output
at W3, f = 1kHz
-72
dB
1 Typical represents the average reading at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ
version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 6 of 28
AD5251/AD5252
INTERFACE TIMING CHARACTERISTICS
Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are
specified with tR = tF = ꢀ.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured
using both VDD = 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts).
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INTERFACE TIMING
SCL Clock Frequency
tBUF Bus Free Time between STOP and
START
fSCL
t1
400
kHz
µs
1.3
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock pulse 0.6
is generated
µs
tLOW Low Period of SCL Clock
t3
t4
t5
t6
t7
t8
t9
t10
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
tHIGH High Period of SCL Clock
tSU;STA Setup Time For START Condition
tHD;DAT Data Hold Time
0.9
tSU;DAT Data Setup Time
100
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
EEMEM Data Storing Time
300
300
0.6
tEEMEM_STORE
tEEMEM_RESTORE1
26
300
ms
µs
EEMEM Data Restoring Time at
Power-On1
VDD rise time dependent. Measure
without decoupling capacitors at VDD
and VSS.
EEMEM Data Restoring Time Upon
tEEMEM_RESTORE2
VDD = 5 V
300
540
µs
µs
Restore Command or RESET Operation1
EEMEM Rewritable Time (delay time after tEEMEM_REWRITE
Power On or RESET before EEMEM can
be written)
FLASH/EE MEMORY RELIABILITY
Endurance2
Data Retention3
100
kCycles
Years
100
1 During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data
restoring time.
2 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
3 When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I2C interface at these pins conducts current of
about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
Rev. 0 | Page 7 of 28
AD5251/AD5252
ABSOLUTE MAXIMUM RATINGS
TA = ꢀ5°C, unless otherwise noted .
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
−0.3 V, +7 V
+0.3 V, −7 V
7 V
VA, VB, VW to GND
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A Open)1
VSS, VDD
20 mA
5 mA
5 mA
5 mA/ 500 µA/
100 µA/ 50 µA
IWA Continuous (RWA ≤ 1 kΩ, B Open)
IAB Continuous
1
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
(RAB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)
1
Digital Inputs and Output Voltage
to GND
0 V, 7 V
2 Package power dissipation = (TJMAX − TA)/θJA
.
Operating Temperature Range
Maximum Junction Temperature
−40°C to +85°C
150°C
(TJ MAX
)
Storage Temperature
Lead Temperature (Soldering,10 sec)
Vapor Phase (60 sec)
−65°C to +150°C
300°C
215°C
Infrared (15 sec)
TSSOP-14 Thermal Resistance2 θJA
220°C
136°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev.0 | Page 8 of 28
AD5251/AD5252
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
V
14
13
12
11
W3
DD
AD0
WP
W1
B1
B3
AD5251/
AD5252
A3
AD1
TOP VIEW
(Not to Scale)
10 DGND
9
8
A1
SCL
SDA
V
SS
Figure 2. AD5251/AD5252 in TSSOP-14
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or 2.7 V for dual supply,
where VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to
EEMEM.
2
3
4
5
6
7
AD0
WP
W1
B1
A1
SDA
I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
Write Protect, Active Low. VWP ≤ VDD + 0.3 V.
1
Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD
.
1
B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD
.
1
A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.
Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded
first. Open-drain MOSFET requires pull-up resistor.
8
9
VSS
Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS
+5.5 V. If VSS is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for
26 ms when storing data to EEMEM.
≤
SCL
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL
(VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.
≤
10
11
12
13
14
DGND
AD1
A3
B3
W3
Digital Ground. Connect to system analog ground at a single point.
I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
1
A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD
.
1
B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD
.
1
W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD
.
1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
I2C INTERFACE TIMING DIAGRAM
t6
t8
t9
SCL
t10
t5
t7
t4
t2
t3
t9
t8
t1
SDA
P
S
P
Figure 3. I2C Timing Diagram
Rev. 0 | Page 9 of 28
AD5251/AD5252
I2C INTERFACE GENERAL DESCRIPTION
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
SLAVE ADDRESS
(7-BIT)
INSTRUCTIONS
(8-BIT)
DATA
(8-BIT)
S
R/W
A
A
A/A
P
DATA TRANSFERRED
0 WRITE
(N BYTES + ACKNOWLEDGE)
Figure 4. I2C—Master Writing Data to Slave
SLAVE ADDRESS
(7-BIT)
DATA
(8-BIT)
DATA
(8-BIT)
S
R/W
A
A
A
P
DATA TRANSFERRED
1 READ
(N BYTES + ACKNOWLEDGE)
Figure 5. I2C—Master Reading Data from Slave
SLAVE ADDRESS
(7-BIT)
A/A
A/A
S
R/W
A
DATA
S
SLAVE ADDRESS
R/W
A
DATA
P
READ OR WRITE
(N BYTES +
ACKNOWLEDGE)
REPEATED START
READ
OR WRITE
(N BYTES +
ACKNOWLEDGE)
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
Figure 6. I2C—Combined Write/Read
Rev. 0 | Page 10 of 28
AD5251/AD5252
I2C INTERFACE DETAIL DESCRIPTION
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW
A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
S
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
0
EE/
RDAC
A
4
A
3
A
2
A
1
A
0
A
DATA
A/
A
P
SLAVE ADDRESS
INSTRUCTIONS
AND ADDRESS
(1 BYTE +
ACKNOWLEDGE)
0 WRITE
0 REG
Figure 7. Single Write Mode
A/
A
S
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
0
EE/
RDAC
A
4
A
3
A
2
A
1
A
0
A
RDAC1
DATA
A
RDAC3
DATA
P
RDAC SLAVE ADDRESS
RDAC INSTRUCTIONS
AND ADDRESS
(N BYTES +
ACKNOWLEDGE)
0 WRITE
0 REG
Figure 8. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/ = 0, CMD/
= 0, EE/
= 0)
RDAC
W
REG
A4
0
0
0
0
0
:
A3
0
0
0
0
0
:
A2
0
0
0
0
1
:
A1
0
0
1
1
0
:
A0
0
1
0
1
0
:
RDAC
Data Byte Description
Reserved
RDAC1
Reserved
RDAC3
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
Reserved
0
1
1
1
1
Reserved
RDAC/EEMEM WRITE
Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 7, and the
consecutive write operation is shown in Figure 8. In the
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
consecutive write operation, if the
is selected and the
RDAC
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
In a write operation to the EEMEM registers, the device disables
the I2C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See EEMEM Write-Acknowledge Polling.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
The addresses are shown in Table 7. The single and consecutive
write operations apply also to EEMEM write operations.
Rev. 0 | Page 11 of 28
AD5251/AD5252
Table 7. Addresses for Writing (Storing) RDAC Settings and
selected previously, readback starts with Address N, followed by
N + 1, and so on.
User-Defined Data to EEMEM Registers (R/ = 0,
W
CMD/
= 0, EE/
= 1)
REG
RDAC
Figure 10 illustrates a random RDAC or EEMEM read
operation. This operation lets users specify which RDAC or
EEMEM register is read by first issuing a dummy write
command to change the RDAC address pointer, and then
proceeding with the RDAC read operation at the new address
location.
A4
0
A3
0
A2
0
0
A1 A0
Data Byte Description
0
0
0
1
Reserved
Store RDAC1 setting to
EEMEM11
Reserved
Store RDAC3 setting to
EEMEM31
0
0
0
0
0
0
0
0
1
1
0
1
Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM (R/ = 1, CMD/ = 0,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Store user data to EEMEM4
Store user data to EEMEM5
Store user data to EEMEM6
Store user data to EEMEM7
Store user data to EEMEM8
Store user data to EEMEM9
Store user data to EEMEM10
Store user data to EEMEM11
Store user data to EEMEM12
Store user data to EEMEM13
Store user data to EEMEM14
Store user data to EEMEM15
W
REG
EE/
= 1)
RDAC
A4
0
A3
0
A2
0
A1
0
A0
0
Data Byte Description
Reserved
0
0
0
0
1
Read RDAC1 Setting from
EEMEM1
0
0
0
0
0
0
1
1
0
1
Reserved
Read RDAC3 Setting from
EEMEM3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Read user data from EEMEM4
Read user data from EEMEM5
Read user data from EEMEM6
Read user data from EEMEM7
Read user data from EEMEM8
Read user data from EEMEM9
Read user data from EEMEM10
Read user data from EEMEM11
Read user data from EEMEM12
Read user data from EEMEM13
Read user data from EEMEM14
Read user data from EEMEM15
1 User can store any of the 64 RDAC settings for AD5251 or any of the 256
RDAC settings for AD5252.
RDAC/EEMEM Read
The AD5251/AD5252 provide two different RDAC or EEMEM
read operations. For example, Figure 9 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected from
the previous operation. If RDAC_N, other than Address 0, is
S
0
1
0
1
1
A
D
1
A
D
0
1
A
RDAC1
EEMEM OR REGISTER DATA
A
RDAC3
EEMEM OR REGISTER DATA
P
A
RDAC SLAVE ADDRESS
(N BYTES + ACKNOWLEDGE)
1 READ
Figure 9. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register).
S
SLAVE ADDRESS
0
A
INSTRUCTION AND
ADDRESS
A
S
SLAVE ADDRESS
1
A
RDAC OR
EEMEM DATA
A/A
P
(N BYTES + ACKNOWLEDGE)
0 WRITE
REPEATED START
1 READ
Figure 10. RDAC or EEMEM Random Read
Rev. 0 | Page 12 of 28
AD5251/AD5252
RDAC/EEMEM Quick Commands
The AD5251/AD5252 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDAC-
to-EEMEM storing and restoring functions. The command
format is shown in Figure 11 and the command descriptions are
shown in Table 9.
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
2
AD1, AD0 = I C DEVICE ADDRESS BITS. MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0
R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
C3, C2, C1, C0 = COMMAND BITS
A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
S
0
1
0
1
1
A
D
1
A
D
0
0
A
CMD/
REG
C
3
C
2
C
1
C
0
A
2
A
1
A
0
A
P
RDAC SLAVE ADDRESS
0 WRITE
1 CMD
Figure 11. RDAC Quick Command Write (Dummy Write)
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/
= 1, A2 = 0)
REG
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
:
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
:
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
:
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
:
Command Description
NOP
Restore EEMEM (A1, A0) to RDAC (A1, A0)1
Store RDAC (A1, A0) to EEMEM (A1, A0)
Decrement RDAC (A1, A0) 6 dB
Decrement all RDACs 6 dB
Decrement RDAC (A1, A0) one step
Decrement all RDACs one step
Reset: Restore EEMEMs to all RDACs
Increment RDACs (A1, A0) 6 dB
Increment all RDACs 6 dB
Increment RDACs (A1, A0) one step
Increment all RDACs one step
Reserved
1
1
1
1
Reserved
1 This command leaves the device in the EEMEM read power state, which consumes power. Users should issue the NOP command to return the device to the idle state.
Table 10. Address Table for Reading Tolerance (CMD/
= 0, EE/
= 1, A4 = 1)
RDAC
REG
A4
0
:
A3
0
:
A2
0
:
A1
0
:
A0
0
:
Data Byte Description
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Reserved
Sign and 7-bit integer values of RDAC1 tolerance (read only)
8-bit decimal value of RDAC1 tolerance (read only)
Reserved
Reserved
Sign and 7-bit integer values of RDAC3 tolerance (read only)
8-bit decimal value of RDAC3 tolerance (read only)
Rev. 0 | Page 13 of 28
AD5251/AD5252
A
A
A
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
–6
D1
–7
D0
–8
6
5
4
3
2
1
0
–1
2
–2
2
–3
2
–4
2
–5
2
SIGN
SIGN
2
2
2
2
2
2
2
2
2
2
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 12. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)
RAB Tolerance Stored in Read-Only Memory
EEMEM Write-Acknowledge Polling
The AD5251/AD5252 feature patented RAB tolerances storage in
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of stored tolerance, which
is the average of RAB over all codes (see Figure 28), allows users
to predict RAB accurately. This feature is valuable for precision,
rheostat mode, and open-loop applications where knowledge of
absolute resistance is critical.
After each write operation to the EEMEM registers, an internal
write cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition
followed by the slave address + the write bit. If the I2C interface
responds with an ACK, the write cycle is complete and the
interface is ready to proceed with further operations. Other-
wise, I2C interface polling can be repeated until it succeeds.
Commands 2 and 7 also require acknowledge polling.
The stored tolerances reside in the read-only memory, and are
expressed as a percentage. The tolerance is stored in two
memory locations (see Table 10). The data format of the
tolerance is in sign magnitude binary form. An example is
shown in Figure 11. In the first memory location, the MSB is
designated for the sign (0 = + and 1= –) and the 7 LSBs are
designated for the integer portion of the tolerance. In the
second memory location, all eight data bits are designated for
the decimal portion of tolerance. As shown in Table 10 and
Figure 12 for example, if the rated RAB = 10 kΩ and the data
readback from Address 11000 shows 0001 1100 and Address
11001 shows 0000 1111, then RDAC0 tolerance can be
calculated as
EEMEM Write Protection
Setting the
pin to a logic LOW after EEMEM programming
WP
protects the memory and RDAC registers from future write
operations. In this mode, the EEMEM and RDAC read
operations operate as normal. When write protection is
enabled, Command 1 (Restore from EEMEM to RDAC) and
Command 7 (Reset) function normally to allow RDAC settings
to be refreshed from the EEMEM to the RDAC registers.
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06% and therefore
RAB_ACTUAL = 12.806 kΩ
Rev. 0 | Page 14 of 28
AD5251/AD5252
I2C COMPATIBLE 2-WIRE SERIAL BUS
1
9
1
9
1
9
SCL
0
1
0
1
1
AD1 AD0 R/W
X
X
X
X
X
X
X
X
D6 D5 D4 D3 D2 D1
D7
D0
SDA
ACK. BY
AD525x
ACK. BY
AD525x
ACK. BY
AD525x
START BY
MASTER
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
Figure 13. General I2C Write Pattern
1
9
1
9
SCL
D1 D0
NO ACK. BY
0
1
0
1
1
AD1
AD0
R/W
D7 D6 D5 D4 D3 D2
SDA
ACK. BY
AD525x
MASTER
STOP BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
START BY
MASTER
Figure 14. General I2C Read Pattern
addresses of the EEMEM and RDAC registers, (see Figure
7 and Figure 8). When MSB = 1 or when in CMD mode,
the four bits following MSB are C3 to C1, which
The first byte of the AD5251/AD5252 is a slave address byte
(see Figure 12 and Figure 13). It has a 7-bit slave address and an
W
R/ bit. The 5 MSBs of the slave address are 01011, and the
correspond to 12 predefined EEMEM controls and quick
commands; there also are four factory reserved commands.
The 3 LSBs—A2, A1, and A0—are four addresses, but only
001 and 011 are used for RDAC1 and RDAC3, respectively
(see Figure 10). After acknowledging the instruction byte,
the last byte in the write mode is the data byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 13).
following 2 LSBs are determined by the states of the AD1 and
AD0 pins. AD1 and AD0 allow the user to place up to four
parts on one bus.
AD5251/AD5252 can be controlled via an I2C compatible serial
bus, and are connected to this bus as slave devices. The 2-wire
I2C serial bus protocol (see Figure 13 and Figure 14) follows:
1. The master initiates a data transfer by establishing a start
condition, such that SDA goes from high to low while SCL
is high (see Figure 13). The following byte is the slave
address byte, which consists of the 5 MSBs of a slave
address defined as 01011. The next two bits are AD1 and
AD0, I2C device address bits. Depending on the states of
their AD1 and AD0 bits, four parts can be addressed on
3. In current read mode, the RDAC0 data byte immediately
follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on (there is a slight difference in write mode, where
the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit). Similarly, the
W
the same bus. The last LSB, the R/ bit, determines
whether data is read from or written to the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 14). Another reading method, random
read method, is shown in Figure 10.
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop
condition (see Figure 13). In read mode, the master issues a
no acknowledge for the ninth clock pulse, i.e., the SDA line
remains high. The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
stop condition (see Figure 14).
2. In the write mode (except when restoring EEMEM to the
RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/
. MSB = 1 enables CMD, the command
REG
instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/
,
RDAC
is true only when MSB = 0 or is in general writing mode.
EE enables the EEMEM register and REG enables the
RDAC register. The 5 LSBs, A4 to A0, designate the
Rev.0 | Page 15 of 28
AD5251/AD5252
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.8
T
= –40°C, +25°C, +85°C, +125°C
A
T
= –40°C, +25°C, +85°C, +125°C
0.6
0.4
0.6
A
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 15. R-INL vs. Code
Figure 18. DNL vs. Code
10
8
1.0
0.8
T
= –40°C, +25°C, +85°C, +125°C
A
I
@ V = +5.5V
DD
DD
6
0.6
4
0.4
2
0.2
I
@ V = +2.7V
DD
DD
0
0
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
I
@ V = +2.7V, V = –2.7V
DD SS
SS
–40
–20
0
20
40
60
80
100
120
0
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 16. R-DNL vs. Code
Figure 19. Supply Current vs. Temperature
1.0
0.8
10
T
= –40°C, +25°C, +85°C, +125°C
A
V
= 5.5V
DD
0.6
1
0.1
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0.01
V
= 2.7V
DD
0.001
0.0001
0
32
64
96
128
160
192
224
256
0
1
2
3
4
5
6
CODE (Decimal)
DIGITAL INPUT VOLTAGE (V)
Figure 17. INL vs. Code
Figure 20. Supply Current vs. Digital Input Voltage, TA = 25°C
Rev.0 | Page 16 of 28
AD5251/AD5252
240
220
200
180
160
140
120
100
80
30
25
20
15
10
5
DATA = 0x00
V
= 5V
= –40°C/+85°C
DD
T
A
V
T
= 2.7V
= 25°C
DD
V
V
= V
A
B
DD
= 0V
A
V
T
= 5.5V
= 25°C
DD
A
60
40
20
0
0
0
1
2
3
4
5
6
0
32
64
96
128
160
192
224
256
V
(V)
CODE (Decimal)
BIAS
Figure 24. AD5252 Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 21. Wiper Resistance vs. VBIAS
6
4
0
0xFF
–6
0x80
0x40
–12
0x20
–18
–24
–30
–36
–42
–48
–54
–60
0x10
2
0
0x08
0x04
0x02
–2
–4
–6
0x01
0x00
–40
–20
0
20
40
60
80
100
120
10
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 22. Change of RAB vs. Temperature
Figure 25. AD5252 Gain vs. Frequency vs. Code, RAB = 1 kΩ
0
90
0xFF
0x80
V
= 5V
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
DD
= –40°C/+85°C
80
70
60
50
40
30
20
10
0
T
A
V
V
= V
A
B
DD
= 0V
0x40
0x20
0x10
0x08
0x04
0x01
0x00
0x02
0
32
64
96
128
160
192
224
256
10
100
1k
10k
100k
1M
10M
CODE (Decimal)
FREQUENCY (Hz)
Figure 23. AD5252 Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 26. AD5252 Gain vs. Frequency vs. Code, RAB = 10 kΩ
Rev. 0 | Page 17 of 28
AD5251/AD5252
0
–6
1.2
1.0
0.8
0.6
0.4
0.2
0
0xFF
0x80
T
= 25°C
= 5.5V
A
–12
–18
–24
–30
–36
–42
–48
0x40
0x20
V
0x10
0x08
0x04
DD
0x01
0x00
V
= 2.7V
DD
0x02
–54
–60
1
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
CLOCK FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. Supply Current vs. Digital Input Clock Frequency
Figure 27. AD5252 Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
CLK
0x80
0x40
0xFF
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
VDD = 5V
0x20
0x10
0x08
0x04
0x02
0x01
V
W
DIGITAL FEEDTHROUGH
0x00
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 31. Clock Feedthrough and Midscale Transition Glitch
Figure 28. AD5252 Gain vs. Frequency vs. Code, RAB = 100 kΩ
100
80
V
= 5.5V
DD
100kΩ
60
VDD
(NO DE-
COUPLING
CAPS)
40
10kΩ
RESTORE RDAC1
SETTING TO 0x3F
20
MIDSCALE
PRESET
1kΩ
VWB1
(0x3F
0
STORED
IN EEMEM)
RESTORE RDAC3
SETTING TO 0x3F
–20
–40
–60
–80
–100
50k
Ω
MIDSCALE
PRESET
VWB3
(0x3F
STORED
IN EEMEM)
VDD = VA1 = VA3 = 3.3V
GND = VB1 = VB3
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 29. AD5252 ꢀRAB vs. Code, TA = 25°C
Figure 32 .tEEMEM_RESTORE
Rev. 0 | Page 18 of 28
AD5251/AD5252
6
5
4
3
2
1
0
6
5
4
3
2
1
0
R
= 1k
Ω
R
= 1k
Ω
AB
AB
V
T
= V = OPEN
B
= 25°C
V
T
= V = OPEN
A B
A
= 25°C
A
A
R
= 10k
Ω
R
= 10kΩ
AB
AB
R
= 50k
16
Ω
R
= 50k
64
Ω
AB
AB
R
= 100k
Ω
R
= 100k
Ω
AB
AB
0
8
24
32
40
48
56
64
0
32
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 33. AD5251 IWBmax vs. Code
Figure 34. AD5252 IWBmax vs. Code
Rev. 0 | Page 19 of 28
AD5251/AD5252
OPERATIONAL OVERVIEW
Table 11. AD5ꢀ51/AD5ꢀ5ꢀ Quick Commands
Commmand Description
The AD5251/AD5252 are dual-channel digital potentiometers
in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64 and 256 linear
resistance step adjustments. The AD5251/AD5252 employ
double-gate CMOS EEPROM technology that allows resistance
settings and user-defined data to be stored in the EEMEM
registers. The EEMEM is nonvolatile, such that settings remain
when power is removed. The RDAC wiper settings are restored
from the non-volatile memory settings during device power-up
and can also be restored at any time during operation.
0
1
NOP
Restore EEMEM content to RDAC. User should
issue NOP immediately after this command to
conserve power.
2
3
4
Store RDAC register setting to EEMEM.
Decrement RDAC 6 dB (shift data bits right).
Decrement all RDACs 6 dB (shift all data bits
right).
5
6
7
8
Decrement RDAC one step.
The AD5251/AD5252 resistor wiper positions are determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
device’s serial I2C interface. The format of the data-words and
the commands to program the RDAC registers are discussed in
the I2C Interface Detail Description section.
Decrement all RDACs one step.
Reset EEMEM contents to all RDACs.
Increment RDAC 6 dB (shift data bits left).
Increment All RDACs 6 dB (shift all data bits left).
Increment RDAC one step.
9
10
11
12–15
Increment all RDACs one step.
Reserved.
The four RDAC registers have corresponding EEMEM memory
locations that provide nonvolatile storage of resistor wiper
position settings. The AD5251/AD5252 provide commands to
store the RDAC register contents to their respective EEMEM
memory locations. During subsequent power-on sequences, the
RDAC registers are automatically loaded with the stored value.
LINEAR INCREMENT AND DECREMENT
COMMANDS
The increment and decrement commands (10, 11, 5, and 6) are
useful for linear step adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the AD5251/AD5252. The adjustments can be directed to an
individual RDAC or to all four RDACs.
Whenever the EEMEM write operation is enabled, the device
activates the internal charge pump and raises the EEMEM cell
gate bias voltage to a high level, essentially erasing the current
content in the EEMEM register and allowing subsequent stor-
age of the new content. Saving data to an EEMEM register con-
sumes about 35 mA of current and lasts about 26 ms. Because
of charge pump operation, all RDAC channels may experience
noise coupling during the EEMEM writing operation.
6 dB ADꢀUSTMENTS (DOUBLING/HALVING
WIPER SETTING)
The AD5251/AD5252 accommodates 6 dB adjustments of the
RDAC wiper positions by shifting the register contents to
left/right for increment/decrement operations, respectively.
Commands 3, 4, 8, and 9 can be used to increment or
decrement the wiper positions in 6 dB steps synchronously or
asynchronously.
The EEMEM restore time in power-up or during operation is
about 300 µs. Note that the power up EEMEM refresh time
depends on how fast VDD reaches its final value. As a result, any
supply voltage decoupling capacitors limit the EEMEM restore
time during power-up. Figure 32 shows the power up profile
where VDD, without any decoupling capacitors connected to it,
is applied with a digital signal. The device initially resets the
measured RDACs to midscale before reaching their final values
during EEMEM restoration.
Incrementing the wiper position by +6 dB is essentially
doubling the RDAC register value, while decrementing by
–6 dB is halving the register content. Internally, the
AD5251/AD5252 use shift registers to shift the bits left and
right to achieve a 6 dB increment or decrement. The
maximum number of adjustments is nine and eight steps for
increment from zero scale and decrement from full scale,
respectively. These functions are useful for various audio/video
level adjustments, especially for white LED brightness settings
where human visual responses are more sensitive to large than
small adjustments.
In addition, users should issue a NOP Command 0 immediately
after using Command 1 to restore the EEMEM setting to
RDAC, to minimize supply current dissipation. Directly reading
user data from EEMEM does not require similar NOP
command execution.
In addition to the movement of data between RDAC registers
and EEMEM memory, the AD5251/AD5252 provide other
shortcut commands that facilitate the users’ programming
needs, as shown in Table 11.
Rev. 0 | Page 20 of 28
AD5251/AD5252
Table 1ꢀ. Multiple Devices Addressing
DIGITAL INPUT/OUTPUT CONFIGURATION
AD1
AD0
Device Addressed
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
0
0
1
1
0
1
0
1
U1
U2
U3
U4
other hand, SCL and
are digital inputs for which pull-up
WP
resistors are recommended to minimize the MOSFETs cross
conduction current when the driving signals are lower than
VDD. SCL and
Figure 35 and Figure 36.
have ESD protection diodes, as shown in
WP
+5V
R
R
P
P
can be permanently tied to VDD without a pull-up resistor if
WP
the write-protect feature is not used. If
is left floating, an
SDA
SCL
WP
MASTER
internal current source pulls it low to enable write-protect. In
applications where the device is not being programmed on a
frequent basis, this allows the part to default to write-protect
after any one-time factory programming or field calibration
without the use of an on board pull-down resistor. Because
there are protection diodes on all these inputs, their signal levels
must not be greater than VDD to prevent forward biasing of the
diodes.
V
V
V
DD
DD
DD
SDA SCL
SDA SCL
SDA SCL
SDA SCL
AD1
AD1
AD1
AD1
U1
U2
U3
U4
AD0
AD0
AD0
AD0
Figure 37. Multiple AD5251/AD5252s on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
V
DD
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundary of the
terminal operating voltages. Positive signals present on
Terminal A, B, or W that exceed VDD are clamped by the
forward biased diode. Similarly, negative signals on Terminal A,
B, or W that are more negative than VSS are also clamped (see
Figure 38). In practice, users should not operate VAB, VWA, and
VWB to be higher than the voltage across VDD to VSS, but VAB,
VWA, and VWB have no polarity constraint.
SCL
GND
V
DD
Figure 35. SCL Digital Input
V
DD
A
W
B
INPUTS
WP
V
SS
Figure 38. Maximum Terminal Voltages Set by VDD and VSS
GND
WP
Figure 36. Equivalent
Digital Input
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power-on VDD/VSS before applying any voltage to Terminals A,
B, and W. Otherwise, the diodes are forward-biased such that
VDD/VSS are powered unintentionally and may affect the rest of
the user’s circuit. Similarly, VDD/VSS should be powered down
last. The ideal power-up sequence is in the following order:
GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of
powering VA, VB, VW, and the digital inputs is not important, as
long as they are powered after VDD/VSS.
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252s to be
operated on one I2C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
is shown in Table 12 and Figure 37. In I2C programming, each
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Rev. 0 | Page 21 of 28
AD5251/AD5252
SW
A
LAYOUT AND POWER SUPPLY BIASING
A
X
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
N
SW(2 –1)
W
X
R
S
RDAC
WIPER
N
SW(2 –2)
REGISTER
AND
DECODER
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 µF to 10 µF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 39 illustrates the basic
supply bypassing configuration for the AD5251/AD5252.
SW(1)
SW(0)
R
R
S
S
N
R
= R /2
AB
S
DIGITAL
SW
B
AD5251/AD5252
CIRCUITRY
OMITTED FOR
CLARITY
B
X
V
DD
V
DD
+
C1
C3
C4
Figure 40. Equivalent RDAC Structure
10µF
0.1µF
0.1µF
+
C2
10µF
V
SS
V
SS
GND
PROGRAMMABLE RHEOSTAT OPERATION
If either the W-to-B or W-to-A terminal is used as a variable
resistor, the unused terminal can be opened or shorted with W;
such operation is called rheostat mode (see Figure 41). The
resistance tolerance can range 20%.
Figure 39. Power Supply Bypassing
The ground pin of the AD5251/AD5252 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5251/AD5252 ground terminal should be joined
remotely to the common ground (see Figure 39).
A
A
A
W
W
W
B
B
B
DIGITAL POTENTIOMETER OPERATION
Figure 41. Rheostat Mode Configuration
The structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of resistor segments, with an array of analog
switches acting as the wiper connection to the resistor array.
The number of points is the resolution of the device. For
example, the AD5251/AD5252 emulates 64 or 256 connection
points with 64 or 256 equal resistance, RS, allowing it to provide
better than 1.5%/0.4% settability resolution.
The nominal resistance of the AD5251/AD5252 has 64 or 256
contact points accessed by the wiper terminal, plus the
B terminal contact. The 6-or 8-bit data-word in the RDAC
register is decoded to select one of the 64 or 256 settings. The
wiper’s first connection starts at the B terminal for Data 0x00.
This B-terminal connection has a wiper contact resistance, RW,
of 75 Ω, regardless of the nominal resistance. The second
connection (the AD5251 10 kΩ part) is the first tap point where
RWB = 231 Ω (RWB = RAB/64 + RW = 156 Ω + 75 Ω) for Data
0x01, and so on. Each LSB data value increase moves the wiper
up the resistor ladder until the last tap point is reached at
RWB = 9893 Ω. See Figure 40 for a simplified diagram of the
equivalent RDAC circuit.
Figure 40 provides an equivalent diagram of the connections
between the three terminals that make up one channel of the
RDAC. Switches SWA and SWB are always ON, while one of
switches SW(0) to SW(2N–1) is ON one at a time, depending on
the setting decoded from the data bit. Because the switches are
nonideal, there is a 75 Ω wiper resistance, RW. Wiper resistance
is a function of supply voltage and temperature; lower supply
voltages and higher temperatures result in higher wiper
resistances. Consideration of wiper resistance dynamics is
important in applications where accurate prediction of output
resistance is required.
The general equation that determines the digitally programmed
output resistance between W and B, is
AD5251: RWB(D) = (D/64) × RAB + 75 Ω
AD5252: RWB(D) = (D/256) × RAB + 75 Ω
(1)
(2)
Where D is the decimal equivalent data contained in the RDAC
latch and RAB is the nominal end-to-end resistance.
Rev. 0 | Page 22 of 28
AD5251/AD5252
100
75
50
25
0
PROGRAMMABLE POTENTIOMETER OPERATION
R
R
WB
WA
If all three terminals are used, the operation is called potenti-
ometer mode and the most common configuration is the
voltage divider operation (see Figure 43).
V
I
A
V
C
W
B
Figure 43. Potentiometer Mode Configuration
If the wiper resistance is ignored, the transfer function is simply
0
16
32
48
63
D
64
D (Code in Decimal)
AD5251: VW
AD5252: VW
=
=
×VAB +VB
(5)
(6)
Figure 42. AD5251 RWA(D) and RWB(D) vs. Decimal Code
D
256
×VAB +VB
Table 13. RWB vs. Codes; RAB = 10 kΩ, A Terminal = Open
D (DEC)
RWB (Ω)
9918
5075
231
Output State
A more accurate calculation, which includes the wiper
resistance effect, yields
63
32
1
Full scale
Midscale
1 LSB
D
RAB + RW
2N
0
75
Zero scale (wiper resistance)
VW (D) =
VA
(7)
RAB +2RW
Note that in the zero-scale condition, a 75 Ω finite wiper
resistance is present. Care should be taken to limit the current
conduction between W and B in this state to no more than
5 mA continuous for a total resistance of 1 kΩ, or a 20 mA
pulse, to avoid degradation or possible destruction of the
internal switch contact.
Where 2N is the number of steps. Unlike in rheostat mode
operation where the tolerance is high, potentiometer mode
operation yields an almost ratiometric function of D/2N with a
relatively small error contributed by the RW terms. Therefore,
the tolerance effect is almost cancelled. Similarly, the
ratiometric adjustment also reduces the temperature coefficient
effect to 50 ppm/°C, except at low value codes where RW
dominates.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value
(see Figure 40). The general equation for this operation is
Potentiometer mode operations include other applications such
as op amp input, feedback resistor networks, and other voltage
scaling applications. The A, W, and B terminals can in fact be
input or output terminals, provided |VA|, |VW|, and |VB| do not
exceed VDD to VSS.
AD5251: RWA(D) = [(64 – D)/64] × RAB + 75 Ω
AD5252: RWA(D) = [(256 – D)/256] × RAB + 75 Ω
(3)
(4)
Table 14. RWA vs. Codes; AD5ꢀ51, RAB=10 kΩ, B Terminal
Open
D (DEC)
RWA (Ω)
Output State
Full scale
Midscale
1 LSB
63
32
1
231
5075
9918
10075
0
Zero scale
The typical distribution of RAB from channel-to-channel
matches about 0.15% within a given device. On the other
hand, device-to-device matching is process-lot dependent with
20% tolerance.
Rev. 0 | Page 23 of 28
AD5251/AD5252
U1
RDAC1
10kΩ
APPLICATIONS
LCD PANEL VCOM ADꢀUSTMENT
V
1
B
Large LCD panels usually require an adjustable VCOM voltage
centered around 6 V to 8 V with 1 V swing and small steps
adjustment. This example represents common DAC appli-
cations where the window of adjustments is small and centered
at any level. High voltage and high resolution DACs can be used
but it is far more cost-effective to use low voltage digital
potentiometers with level shifting, such as the AD5251 or
AD5252, to achieve the objective.
+5V
U2
R
SENSE
0.1kΩ
V+
AD8628
V–
V
AD5252
O
B
VREF
V
2
RDAC3
10kΩ
Assume a VCOM voltage requirement of 6 V 1 V with a 20 mV
step adjustment, as shown in Figure 44. The AD5252 can be
configured in voltage divider mode with an op amp gain. With
20% tolerance accounted for by the AD5252, this circuit can
still be adjusted from 5 V to 7 V with an 8 mV/step in the
worst case.
Figure 45. Current-Sensing Amplifier.
ADꢀUSTABLE HIGH POWER LED DRIVER
Figure 46 shows a circuit that can drive three to four high power
LEDs. The ADP1610 is an adjustable boost regulator that
provides adequate headroom and current for the LEDs. Because
its FB pin voltage is 1.2 V, the digital potentiometer AD5252
and the op amp form an average gain of 12 feedback networks
that servo the sensing and feedback voltages. As a result, the
voltage across RSET is regulated around 0.1 V, depending on the
AD5252’s setting. An adjustable LED current is
+14.4V
R1
350k
±1%
U1
AD5252
+14.4V
V
+5V
DD
R2
10k
U2
6V ± 1V
V+
V–
±20%
V
COM
VR
B
SET
ILED
=
(9)
RSET
R3
18.5k
C1
2.2p
RSET should be small to conserve power but large enough to
limit the maximum LED current. R3 should also be used in
parallel with the AD5252 to limit the LED current within an
achievable range.
R5
1k
R4
6k
Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V 1 V Application.
+5V
C2
10µF
U2
R4
13.5kΩ
L1
10µF
IN
CURRENT-SENSING AMPLIFIER
D1
ADP1610
/SD
V
SW
PWM
The dual channel, synchronous update, and channel-to-channel
resistance matching characteristics make the AD5251/AD5252
suitable for current sensing applications, such as LED
brightness control. In the circuit shown in Figure 45, when
RDAC1 and RDAC3 are programmed to the same settings, it
can be shown that
OUT
C3
10µF
FB
COMP
SS
D1
D2
D3
R
O
100kΩ
RT GND
C
C
390pF
C
SS
10nF
C8
0.1µF
+5V
D
Vo =
(
V2 −V1
)
+VREF
(8)
U3
2N − D
V+
AD8591
V–
As a result, the current through a sense resistor connected
R
SET
0.25kΩ
between V1 and V2 can be known. The programmability of this
circuit makes it adaptable to systems that require different sen-
sitivities. If the op amp has very low offset and low bias current,
the major source of error comes from the digital potentiometer
channel-to-channel resistance mismatch, which is typically
0.15%. The circuit accuracy is about 9 bits, which is adequate
for LED control and other general purpose applications.
U1
AD5252
U1
W
B
A
10kΩ
R2
1.1kΩ
R1
100Ω
R3
200Ω
Figure 46. High Power Adjustable LED Driver
Rev. 0 | Page 24 of 28
AD5251/AD5252
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range (°C)
Package
Option
Full Container
Quantity
Model
Step RAB (kΩ)
Package Description
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Evaluation Board
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Branding1
B1
B1
B10
B10
B50
B50
B100
B100
AD5251BRU1
64
1
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
96
1,000
96
1,000
96
1,000
96
AD5251BRU1-RL7
AD5251BRU10
AD5251BRU10-RL7
AD5251BRU50
AD5251BRU50-RL7
AD5251BRU100
AD5251BRU100-RL7
AD5251EVAL
64
1
64
64
64
64
64
64
64
10
10
50
50
100
100
10
1
1,000
1
AD5252BRU1
256
256
256
256
256
256
256
256
256
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
−40 to +85
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
96
1,000
96
1,000
96
1,000
96
B1
B1
AD5252BRU1-RL7
AD5252BRU10
AD5252BRU10-RL7
AD5252BRU50
AD5252BRU50-RL7
AD5252BRU100
AD5252BRU100-RL7
AD5252EVAL
1
10
10
50
50
100
100
10
B10
B10
B50
B50
B100
B100
1,000
1
Evaluation Board
1 In the package marking, Line 1 shows the part number; Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, B50 = 50 kΩ, and B100 = 100 kΩ;
Line 3 shows the date code in YYWW.
Rev.0 | Page 25 of 28
AD5251/AD5252
NOTES
Rev. 0 | Page 26 of 28
AD5251/AD5252
NOTES
Rev. 0 | Page 27 of 28
AD5251/AD5252
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© ꢀ004 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective owners.
D038ꢀ3-0-6/04(0)
Rev. 0 | Page 28 of 28
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