AD5292SRUZ-20-EP_技术文档

1024-Position, Digital Potentiometer with

Maximum 1ꢀ ꢁ-ꢂoleranꢃe ꢄrror anꢅ 20-ꢂP Memorꢆ

Data Sheet

AD5292-ꢄP

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

RESET

DD

Single-channel, 1024-position resolution

20 kΩ nominal resistance

Maximum 1ꢀ nominal resistor tolerance error (resistor

performance mode)

20-times programmable wiper memory

Rheostat mode temperature coefficient: 35 ppm/°C

Voltage divider temperature coefficient: 5 ppm/°C

+9 V to +33 V single-supply operation

9 V to 16.5 V dual-supply operation

SPI-compatible serial interface

POWER-ON

RESET

AD5292-EP

V

LOGIC

RDAC

REGISTER

SCLK

SYNC

A

DATA

SERIAL

INTERFACE

W

OTP

MEMORY

BLOCK

DIN

B

Wiper setting readback

SDO

Power-on refreshed from 20-TP memory

RDY

ENHANCED PRODUCT FEATURES

V

EXT_CAP

GND

SS

Supports defense and aerospace applications (AQEC)

Temperature range: −55°C to +125°C

Controlled manufacturing baseline

1 assembly/test site

Figure 1.

1 fabrication site

Enhanced product change notification

Qualification data available on request

APPLICATIONS

Mechanical potentiometer replacement

Instrumentation: gain and offset adjustment

Programmable voltage-to-current conversion

Programmable filters, delays, and time constants

Programmable power supply

Low resolution DAC replacement

Sensor calibration

GENERAL DESCRIPTION

The AD5292-EP is a single-channel, 1024-position digital

potentiometer¹that combines industry leading variable resistor

performance with nonvolatile memory (NVM) in a compact

package. This device is capable of operating across a wide voltage

range, supporting both dual supply operation at 10.5 V to 1ꢀ.5

V and single-supply operation at +21 V to +33 V, while ensuring

less than 1% end-to-end resistor tolerance error and offering 20-

time programmable (20-TP) memory.

The AD5292-EP device wiper settings are controllable through

the SPI digital interface. Unlimited adjustments are allowed

before programming the resistance value into the 20-TP memory.

The AD5292-EP does not require any external voltage supply

to facilitate fuse blow, and there are 20 opportunities for perma-

nent programming. During 20-TP activation, a permanent blow

fuse command freezes the wiper position (analogous to placing

epoxy on a mechanical trimmer).

The guaranteed industry leading low resistor tolerance error

feature simplifies open-loop applications as well as precision

calibration and tolerance matching applications.

The AD5292-EP is available in a compact 14-lead TSSOP

package. The part is guaranteed to operate over the extended

industrial temperature range of −55°C to +125°C.

Additional application and technical information can be found

in the AD5292 data sheet.

¹The terms digital potentiometer and RDAC are used interchangeably.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5292-ꢄP

Data Sheet

ꢂABLꢄ OF CONꢂꢄNꢂS

Features .............................................................................................. 1

Interface Timing Specifications...................................................5

Absolute Maximum Ratings ............................................................7

Thermal Resistance.......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics ..............................................9

Test Circuits..................................................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5292-EP.................................... 3

Resistor Performance Mode Code Range ................................. 4

REVISION HISTORY

9/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

Data Sheet

AD5292-ꢄP

SPꢄCIFICAꢂIONS

ELECTRICAL CHARACTERISTICS—AD5292-EP

V_DD= 21 V to 33 V, V_SS= 0 V; V_DD= 10.5 V to 1ꢀ.5 V, V_SS= −10.5 V to −1ꢀ.5 V; V_LOGIC= 2.7 V to 5.5 V, V_A= V_DD, V_B= V_SS,

−55°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

N

10

−1

−2

−3

−1

Bits

LSB

%

R-DNL

R-INL

∆R_AB/R_AB

R_WB, V_A= NC

+1

+2

+3

+1

R_AB=20 kΩ, |V_DD− V_SS| = 26 V to 33 V

R_AB=20 kΩ, |V_DD− V_SS| = 21 V to 26 V

See Table 2

Nominal Resistor Tolerance (R-Perf Mode)³

±0.5

±±

Nominal Resistor Tolerance (Normal

Mode)⁴

%

Resistance Temperature Coefficient

Wiper Resistance

(∆R_AB/R_AB)/∆T × 10⁶

R_W

Code = full scale; see Figure 14

Code= zero scale

35

60

ppm/°C

Ω

100

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Resolution

N

10

Bits

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient⁴

Full-Scale Error

DNL

−1

+1

LSB

INL

−2.5

+2.5

LSB

(∆V_W/V_W)/∆T × 10⁶

Code = half scale; see Figure 1±

Code = full scale

5

ppm/°C

LSB

V_WFSE

V_WZSE

−8

0

+1

10

Zero-Scale Error

Code = zero scale

LSB

RESISTOR TERMINALS

Terminal Voltage Range⁶

Capacitance A, Capacitance B⁴

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

f = 1 MHz, measured to GND,

code = half scale

85

65

±1

pF

Capacitance W⁴

C_W

I_CM

f = 1 MHz, measured to GND,

code = half scale

pF

Common-Mode Leakage Current⁴

DIGITAL INPUTS

Input Logic High⁴

Input Logic Low⁴

V_A= V_B= V_W

−120

2.0

120

nA

JEDEC compliant

V_LOGIC= 2.± V to 5.5 V

V_IN= 0 V or V_LOGIC

V_IH

V_IL

I_IL

V

0.8

±1

V

Input Current

Input Capacitance⁴

μA

pF

C_IL

5

DIGITAL OUTPUTS (SDO and RDY)

Output High Voltage⁴

Output Low Voltage⁴

Three-State Leakage Current

Output Capacitance⁴

POWER SUPPLIES

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_LOGIC

V_LOGIC− 0.4

−1

V

GND + 0.4

+1

V

μA

pF

C_OL

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

Logic Supply Range

V_DD

V_SS= 0 V

9

33

V

V_DD/V_SS

I_DD

±9

±16.5

2

V

V_DD/V_SS= ±16.5 V

0.1

μA

V

I_SS

−2

−0.1

V_LOGIC

I_LOGIC

2.±

5.5

10

Logic Supply Current

OTP Store Current^{4, ±}

OTP Read Current^{4, 8}

V_LOGIC= 5 V, V_IH= 5 V or V_IL= GND

V_IH= 5 V or V_IL= GND

1

μA

mA

μW

%/%

I_{LOGIC_PROG}

I_{LOGIC_FUSE_READ}

P_DISS

25

8

V_IH= 5 V or V_IL= GND

Power Dissipation⁹

V_IH= 5 V or V_IL= GND

110

Power Supply Rejection Ratio

PSRR

∆V_DD/∆V_SS= ±15 V ± 10%

0.103

Rev. 0 | Page 3 of 16

AD5292-ꢄP

Data Sheet

Parameter

DYNAMIC CHARACTERISTICS^{5, 10}

Symbol

Conditions

Min

Typ¹

Max

Unit

Bandwidth

BW

THD_W

t_S

−3 dB

520

−93

kHz

dB

Total Harmonic Distortion

V_WSettling Time

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 30 V, V_B= 0 V, ±0.5 LSB error

band, initial code = zero scale, board

capacitance = 1±0 pF

Code = full-scale, normal mode

Code = full-scale, R-Perf mode

Code = half-scale, normal mode

Code = half-scale, R-Perf mode

±50

2.5

5

ns

μs

Resistor Noise Density

e_{N_WB}

Code = half-scale, T_A= 25°C, 0 kHz to

200 kHz

10

nV/√Hz

¹Typical values represent average readings at 25°C, V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

²Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between R_WBat Code 0x00B and Code 0x3FF or between R_WAat Code 0x3F3

and Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode,

with a wiper current of 1 mA for V_A< 12 V and 1.2 mA for V_A≥ 12 V.

³Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably.

⁴Guaranteed by design and characterization, not subject to production test.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

^±Different from operating current; supply current for fuse program lasts approximately 550 μs.

⁸Different from operating current; supply current for fuse read lasts approximately 550 μs.

⁹P_DISSis calculated from (I_DD× V_DD) + (I_SS× V_SS) + (I_LOGIC× V_LOGIC).

¹⁰All dynamic characteristics use V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

RESISTOR PERFORMANCE MODE CODE RANGE

Table 2.

−55°C < T_A< +125°C

Resistor

Tolerance per

Code

|V_DD− V_SS| = 30 V to 33 V

R_WBR_WA

From 0x1EF From 0x000 From 0x1F4 From 0x000 From 0x1F4 From 0x000 N/A

to 0x3FF to 0x210 to 0x3FF to 0x20B to 0x3FF to 0x20B

From 0x0C3 From 0x000 From 0x0E6 From 0x000 From 0x131 From 0x000 From 0x131 From 0x000

to 0x3FF to 0x33C to 0x3FF to 0x319 to 0x3FF to 0x2CE to 0x3FF to 0x2CE

From 0x0±3 From 0x000 From 0x08± From 0x000 From 0x0AF From 0x000 From 0x0AF From 0x000

|V_DD− V_SS| = 26 V to 30 V

|V_DD− V_SS| = 22 V to 26 V

|V_DD− V_SS| = 21 V to 22 V

R_WBR_WA

R_WB

R_WA

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

N/A

to 0x3FF

to 0x38C

to 0x3FF

to 0x3±8

to 0x3FF

to 0x350

to 0x3FF

to 0x350

Rev. 0 | Page 4 of 16

Data Sheet

AD5292-ꢄP

INTERFACE TIMING SPECIFICATIONS

V_DD/V_SS

= 15 V, V_LOGIC= 2.7 V to 5.5 V, −55°C < T_A< +125°C. All specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

Limit¹

20

10

5

1

400³

14

1

Unit

Description

2

t₁

ns min

ns max

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

t₂

t₃

t₄

t₅

t₆

t_±

t₈

t₉

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignore

RDY rising edge to SYNC falling edge

SYNC rising edge to RDY fall time

4

t₁₀

4

t₁₁

40

4

t₁₂

2.4

410

8

μs max

ns max

ms max

ms min

ns max

ms max

ns max

ns min

ms max

RDY low time, RDAC register write command execute time (R-Perf mode)

RDY low time, RDAC register write command execute time (normal mode)

RDY low time, memory program execute time

Software/hardware reset

4

t₁₂

4

t₁₂

4

t₁₂

1.5

450

1.3

450

20

4

t₁₃

RDY low time, RDAC register readback execute time

RDY low time, memory readback execute time

SCLK rising edge to SDO valid

4

t₁₃

4

t₁₄

t_RESET

Minimum RESET pulse width (asynchronous)

Power-on OTP restore time

5

t_POWER-UP

2

¹All input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 50 MHz.

³Refer to t₁₂and t₁₃for RDAC register and memory commands operations.

⁴R_{PULL_UP}= 2.2 kΩ to V_LOGIC, with a capacitance load of 168 pF.

⁵Maximum time after V_LOGICis equal to 2.5 V.

DB9 (MSB)

DB0 (LSB)

C3

C1

C0

D9

D7

D6

D5

D4

D3

D0

0

C2

D8

D2

D1

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

Rev. 0 | Page 5 of 16

AD5292-ꢄP

Timing Diagrams

t₄

Data Sheet

t₇

t₂

t₁

SCLK

t₉

t₃

t₈

SYNC

t₅

t₆

D7

DIN

D6

D2

X

C3

C2

D1

D0

SDO

t₁₁

t₁₀

t₁₂

RDY

t_RESET

RESET

Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1

SCLK

SYNC

t₉

DIN

X

C3

D0

X

D0

C3

D1

D0

t₁₄

C3

SDO

RDY

X

D1

D0

t₁₁

t₁₃

Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1

Rev. 0 | Page 6 of 16

Data Sheet

AD5292-ꢄP

ABSOLUꢂꢄ MAXIMUM ꢁAꢂINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

V_DDto GND

V_SSto GND

V_LOGICto GND

V_DDto V_SS

−0.3 V to +35 V

+0.3 V to −25 V

−0.3 V to +± V

35 V

V_SS− 0.3 V, V_DD+ 0.3 V

−0.3 V to V_LOGIC+ 0.3 V

−0.3 V to +± V

V_A, V_B, V_Wto GND

THERMAL RESISTANCE

Digital Input and Output Voltage to GND

EXT_CAP Voltage to GND

I_A, I_B, I_W

Continuous

Pulsed¹

Frequency > 10 kHz

Frequency ≤ 10 kHz

Operating Temperature Range³

Maximum Junction Temperature (T_Jmax)

Storage Temperature Range

Reflow Soldering

Peak Temperature

Time at Peak Temperature

Package Power Dissipation

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

±3 mA

Table 5. Thermal Resistance

±3/d²

±3/√d²

−55°C to +125°C

150°C

−65°C to +150°C

Package Type

θ_JA

93¹

θ_JC

Unit

14-Lead TSSOP

20

°C/W

¹JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow).

ESD CAUTION

260°C

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Pulse duty factor.

³Includes programming of OTP memory.

Rev. 0 | Page ± of 16

AD5292-ꢄP

Data Sheet

PIN CONFIGUꢁAꢂION AND FUNCꢂION DꢄSCꢁIPꢂIONS

RESET

1

2

3

4

5

6

7

14 RDY

V

13

SDO

SS

A

W

B

12

SYNC

AD5292-EP

11 SCLK

10 DIN

TOP VIEW

(Not to Scale)

V

9

8

GND

DD

EXT_CAP

V

LOGIC

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

RESET

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory

default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the

logic high transition. Tie RESET to V_LOGICif not used.

2

V_SS

Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF

ceramic capacitors and 10 μF capacitors.

3

4

5

6

±

8

A

W

B

V_DD

EXT_CAP

V_LOGIC

Terminal A of RDAC. V_SS≤ V_A≤ V_DD.

Wiper Terminal of RDAC. V_SS≤ V_W≤ V_DD.

Terminal B of RDAC. V_SS≤ V_B≤ V_DD.

Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.

External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥± V.

Logic Power Supply; 2.± V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.

9

10

GND

DIN

Ground Pin, Logic Ground Reference.

Serial Data Input. The AD5292-EP has a 16-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

11

12

SCLK

SYNC

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates up to 50 MHz.

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The

selected register is updated on the rising edge of SYNC following the 16^thclock cycle. If SYNC is taken high

before the 16^thclock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by

the DAC.

13

14

SDO

RDY

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the shift register in daisy-chain mode or in readback mode.

Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from

the RDAC register or memory.

Rev. 0 | Page 8 of 16

Data Sheet

AD5292-ꢄP

ꢂYPICAL PꢄꢁFOꢁMANCꢄ CHAꢁACꢂꢄꢁISꢂICS

1.0

0.6

0.5

0.4

0.3

0.2

0.1

0

–40°C

+25°C

0.8

0.6

+105°C

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

0

128

256

384

512

640

768

896

1023

0

128

256 384

640

896

1023

CODE (Decimal)

Figure 6. R-INL in R-Perf Mode vs. Code

Figure 9. R-DNL in R-Perf Mode vs. Code

1.5

1.0

0.6

0.5

0.4

0.3

0.2

0.1

0

0.5

0

–0.5

–1.0

–1.5

–0.1

–0.2

+105°C

768

+25°C

512

CODE (Decimal)

+105°C

768

–40°C

+25°C

512

CODE (Decimal)

–40°C

0

128

256 384

640

896

1023

0

128

256 384

640

896

1023

Figure 7. INL in R-Perf Mode vs. Code

Figure 10. DNL in R-Perf Mode vs. Code

1.0

0.8

0.15

0.10

0.05

0

0.6

0.4

0.2

–0.05

–0.10

–0.15

–0.20

0

–0.2

–0.4

–0.6

+105°C

768

+105°C

768

+25°C

512

CODE (Decimal)

+25°C

512

CODE (Decimal)

–40°C

0

128

256 384

640

896

1023

0

128

256 384

640

896

1023

Figure 8. R-INL in Normal Mode vs. Code

Figure 11. R-DNL in Normal Mode vs. Code

Rev. 0 | Page 9 of 16

AD5292-ꢄP

Data Sheet

0.8

0.10

0.05

–40°C

+25°C

+105°C

–40°C

+25°C

+105°C

0.6

0.4

0

0.2

0

–0.05

–0.10

–0.15

–0.20

–0.2

–0.4

–0.6

–0.8

0

128

256

384

512

640

768

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 15. DNL in Normal Mode vs. Code

Figure 12. INL in Normal Mode vs. Code

450

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

V

/V = ±15V

DD SS

V

= ±15V

DD

= +5V

LOGIC

400

350

300

250

200

150

100

50

I

LOGIC

I

DD

0

I

SS

–50

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 16. Supply Current I_LOGICvs. Digital Input Voltage

Figure 13. Supply Current (I_DD, I_SS, I_LOGIC) vs. Temperature

700

600

500

400

300

200

100

0

700

600

500

400

300

200

100

0

V

= 30V

= 0V

V

= 30V

= 0V

DD

SS

DD

SS

0

256

512

768

1023

0

256

512

768

1023

CODE (Decimal)

Figure 14. Rheostat Mode Tempco ΔR_WB/ΔT vs. Code

Figure 17. Potentiometer Mode Tempco ΔR_WB/ΔT vs. Code

Rev. 0 | Page 10 of 16

Data Sheet

AD5292-ꢄP

0

–10

–20

–30

–40

–50

–60

–70

0

0x200

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

0x100

0x080

0x040

0x020

0x010

0x008

0x004

0x002

0x001

100

10

1k

10k

100k

1M

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 21. Power Supply Rejection Ratio vs. Frequency

Figure 18. 20 kΩ Gain vs. Frequency vs. Code

0

–15

V

/V = ±15V

V

/V = ±15V,

DD SS

CODE = HALF SCALE

= 1V rms

CODE = HALF SCALE

f_IN= 1kHz

NOISE BW = 22kHz

V

–20

–40

IN

NOISE BW = 22kHz

–30

–45

–60

–80

–75

–100

–120

–140

–90

–105

–120

0.001

0.01

0.1

AMPLITUDE (V rms)

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 22. THD + Noise vs. Amplitude

Figure 19. THD + Noise vs. Frequency

1,000,000

900,000

800,000

700,000

600,000

500,000

400,000

300,000

200,000

100,000

0

35

30

25

20

15

10

5

0pF

75pF

150pF

250pF

0

–5

–0.4

0

8

16

32

64

128

256

512

–0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

CODE (Decimal)

TIME (ms)

Figure 20. Bandwidth vs. Code vs. Net Capacitance

Figure 23. I_DDWaveform While Blowing/Reading Fuse

Rev. 0 | Page 11 of 16

AD5292-ꢄP

Data Sheet

35

40

32

24

16

8

V

/V = ±15V

V

, CODE: FULL SCALE,

NORMAL MODE

V

/V = 30V/0V

DD SS

WB

DD SS

= V

= 5V

A

B

DD

SS

LOGIC

= V

30

25

20

15

= V

A

B

DD

CODE = HALF CODE

= V

SS

V

, CODE: FULL SCALE,

WB

R-PERF MODE

0

–8

–16

10

SYNC

5

0

V

, CODE: HALF-SCALE,

NORMAL MODE

–24

–32

WB

V

, CODE: HALF-SCALE,

R-PERF MODE

WB

–40

–5

–0.5

0

5

10

15

20

25

30

35

40

45

TIME (µs)

Figure 24. Large-Signal Settling Time from Code Zero Scale

Figure 27. Digital Feedthrough

8

7

6

5

4

3

2

1

0

6

5

V

/V = ±15V

DD SS

V

/V = 30V/0V

DD SS

= +5V

= V

LOGIC

A

B

DD

SS

4

3

2

1

0

–1

0

256

512

768

1023

CODE (Decimal)

TIME (ms)

Figure 25. Theoretical Maximum Current vs. Code

Figure 28. V_{EXT_CAP}Waveform While Reading Fuse Or Calibration

1.2

1.0

8

V

/V = ±15V

V

/V = ±15V

DD SS

= +5V

LOGIC

= V

A

B

DD

SS

0.8

6

3

0.6

0.4

0.2

0

2

–0.2

–0.4

–0.6

–0.8

0

–2

0

2

4

6

8

10

12

14

16

TIME (µs)

TIME (ms)

Figure 29. V_{EXT_CAP}Waveform While Writing Fuse

Figure 26. Maximum Transition Glitch

Rev. 0 | Page 12 of 16

Data Sheet

AD5292-ꢄP

300

80

70

60

50

40

30

20

10

0

V

= V

V

/V = ±15V

A

DD

DD SS

B

SS

TEMPERATURE = 25°C

250

200

150

100

50

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

21

26

30

33

VOLTAGE V /V

DD SS

Figure 30. Code Range > 1% R-Tolerance Error vs. Temperature

Figure 31. Code Range > 1% R-Tolerance Error vs. Voltage

Rev. 0 | Page 13 of 16

AD5292-ꢄP

Data Sheet

ꢂꢄSꢂ CIꢁCUIꢂS

Figure 32 to Figure 37 define the test conditions used in the Specifications section.

NC

DUT

A

I

V

W

A

V+ = V ± 10%

DD

W

∆V

MS

DD

V

A

B

DD

PSRR (dB) = 20 log

B

W

V+

~

V

MS

∆V

%

MS

DD

PSS (%/%) =

V

MS

NC = NO CONNECT

Figure 32. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

Figure 35. Power Supply Sensitivity (PSS, PSRR)

+15V

A

DUT

A

V+ = V

DD

1LSB = V+/2

W

V

N

IN

DUT

OP42

–15V

V

W

OUT

B

V+

OFFSET

GND

B

V

MS

2.5V

Figure 33. Potentiometer Divider Nonlinearity Error

(INL, DNL)

Figure 36. Gain vs. Frequency

+15V

NC

–15V

GND

0.1V

R

=

WB

A

V

DUT

I

DD

I

DUT

A

CM

WB

+15V

–15V

W

R

CODE = 0x00

WB

2

R

W

+

–

V

GND

SS

B

0.1V

I

GND

WB

V

TO V

DD

NC

+15V

GND

SS

A = NC

NC = NO CONNECT

–15V

Figure 37. Common-Mode Leakage Current

Figure 34. Wiper Resistance

Rev. 0 | Page 14 of 16

AD5292-ꢄP

Data Sheet

OUꢂLINꢄ DIMꢄNSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model

R_AB(kΩ)

Resolution

Memory

Temperature Range

Package Description

Package Option

AD5292SRU-20-EP

20

1024

20-TP

−55°C to +125°C

14-Lead TSSOP

RU-14

Rev. 0 | Page 15 of 16

AD5292-ꢄP

NOꢂꢄS

Data Sheet

registered trademarks are the property of their respective owners.

D10095-0-9/11(0)

Rev. 0 | Page 16 of 16


型号：	AD5292SRUZ-20-EP
厂家：	ADI
描述：	Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer with 20-Times Programmable Memory 光电二极管转换器电阻器
文件：	总16页 (文件大小：491K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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