AD53020JP [ADI]
IC ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44, PLASTIC, LCC-44, Delay Line;
| 型号： | AD53020JP |
| 厂家： | 
ADI |
| 描述： | IC ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44, PLASTIC, LCC-44, Delay Line 输出元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Four Channel ECL Delay Line
AD53020
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Four Delay Lines with the Ability to Independently
Adjust All Edges
GND
S0
S1
Pin Compatible and Functionally Equivalent with the
BT624
Reduced Power Dissipation
VWIDTH1
OUT1
AD53020
IN1, IN1
44-Lead PLCC Package with Internal Heat Spreader
OUT1
APPLICATIONS
VDELAY1
VWIDTH2
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
OUT2
IN2, IN2
Clocked ECL Circuits
OUT2
DRVMODE
VDELAY2
VWIDTH3
OUT3
IN3
OUT3
PRODUCT DESCRIPTION
VDELAY3
VWIDTH4
The AD53020 is a four-channel delay line designed for use in
automatic test equipment and digital logic systems. High speed
bipolar transistors and a 44-lead plastic PLCC package with
internal heat spreader provide high frequency performance a
minimum of space, cost and power dissipation.
OUT4
IN4, IN4
OUT4
VDELAY4
V
EE
Featuring full pin compatibility and functional equiv
the BT624, the AD53020 offers independent analog
positive and negative edges with five delay rangeThe A
offers attractive performance with optimizpower dissipat
and linear delay vs. program voltage conl. Thie is also
very stable over operating conditions and halow jit
V
COMP1
COMP2
REXT1
REXT2
BB
Digital inputs are ECL compatibey can either pro-
vided independently for each cN1, IN1 through IN4,
IN4), or fanned out to all annel 2 (IN2,
IN2). The choice of these twde by setting the
DRVMODE input, with ECL Loding four indepen-
dent channels, and 1 eng a logical OR function
between each chhannel Number 2.
The delay is programmed through the VDELAY and VWIDTH
pins for each channel. The acceptable range is –1.3 V to –0.1 V,
representing the longest and the shortest delays provided by the
device. An 0.01 µF ceramic capacitor to ground is recom-
mended for each input. The bias current for each input is fixed
by an internal current mirror. The value of the bias current is
set by the external resistor at REXT1. A 1.3 kΩ resistor to
ground at this pin establishes 1 mA bias in each input. The
nominal voltage at the REXT1 pin is –1.3 V.
For maximum tiifferential signals are recom-
mended for use wiinputs. However, single-ended
operation is also suppoand it is facilitated through the use
of the VBB midpoint level generated on-chip. To make use of
this feature, connect the VBB output to the inverting input of
each channel. It is also advisable, when using the VBB output,
to decouple this signal with a 0.1 µF ceramic capacitor to ground.
The VDELAY affects both the positive and negative edges in all
modes. The VWIDTH is an additional delay adjustment that is
active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0
and 1. For Modes 2 and 3, the effect of the VWIDTH adjust-
ment is to increase or decrease the delay of the negative edge
relative to the positive edge. In Mode 5, the total delay for both
positive and negative edges is set by the combination of VDELAY
and VWIDTH.
The outputs of the AD53020 are ECL compatible and should
be terminated by 50 Ω to –2.0 V at the inputs of the gates
they drive.
(continued on page 4)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD53020-Test Conditions (Unless otherwise noted): Recommended Operating
Conditions with all OUT and OUT outputs terminated through 50 ⍀ to –2.0 V, REXT1 = 1.3 k⍀, REXT2 = 2.94 k⍀. Typical values are based on
nominal temperature, TA = +25؇C, and nominal supply voltage, VEE = –5.2 V.
AD53020–SPECIFICATIONS
DC CHARACTERISTICS1
Parameter
Symbol
T(؇C)
Min
Typ
Max
Units
DIGITAL INPUT HIGH VOLTAGE
IN, IN, DRVMODE, S0, S1
VIH
70
–1.070
0.000
V
DIGITAL INPUT LOW VOLTAGE
IN, IN, DRVMODE, S0
VIL
VIL
70
–1.950
VEE
–1.450
–1.450
–3.2
V
V
V
V
V
DIGITAL INPUT LOW VOLTAGE, S1
S1 THIRD STATE (EXTENDED DELAY)
DIGITAL OUTPUT HIGH VOLTAGE
DIGITAL OUTPUT LOW VOLTAGE
70
Full
70
VEE
VOH
VOL
–1.000
–1.950
–0.735
–1.600
70
DIGITAL INPUT BIAS CURRENT
IN, IN, DRVMODE, S0, S1
–100 to
+100
IIN
µA
POWER SUPPLY REJECTION RATIO2
PSRR
Full
% Tpd/V
V
EE SUPPLY CURRENT
Mode 0
IEE
IEE
IEE
Full
Full
Full
174
225
267
200
250
290
mA
mA
mA
Modes 1, 2
Modes 3, 5
NOTES
1The specified limits shown can be met only after thermal equilibrium has been establid. Thermal equilibrius established by applying power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the deither mounted in the test socket or on the printed circuit board.
2This parameter is fully characterized, but not production tested.
Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter
l
Min
Typ
Max
Units
MINIMUM PROPAGATION DELAYS2
Mode S1
S0
0
1
0
1
VDELAY
–0.1 V
–0.1 V
–0.1 V
–0.1 V
–0.1 V
0
1
2
3
5
0
0
1
1
Tpd Min
Tpd Min
Tpd Min
Tpd Min
Tpd Min
3.6
4.9
3.9
5.2
6.8
4.5
6.3
5.3
7.1
8.8
5.4
7.3
6.8
8.8
10.3
ns
ns
ns
ns
ns
VEE
1
DELAY ADJUSTME
Mode S1
S0
0
1
2
3
5
0
0
1
1
0
1
0
1
Tpd Span
Tpd Span
Tpd Span
Tpd Span
Tpd Span
14.0
22.9
13.2
22.0
29.3
19.0
31.4
18.9
31.5
44.5
24.7
37.8
24.6
40.6
52.0
ns
ns
ns
ns
ns
VEE
1
MINIMUM PULSEWIDTH3
1.9
ns
RISING EDGE DELAY VS. VWIDTH DELAY
Change (Modes 2 and 3)3
DELAY VS. DUTY CYCLE3, 4
30
50
ps
ps
VWIDTH RANGE OF ADJUSTMENT
(VDELAY = –0.6 V, MODES 2 AND 3, DELAY
RELATIVE TO VWIDTH = –0.7 V)
VWIDTH = –0.1 V
–5.5
+5.5
+6.5
–4.0
ns
ns
ns
VWIDTH = –1.1 V
VWIDTH = –1.3 V
+4.0
–2–
REV. A
AD53020
Parameter
Symbol
Min
Typ
Max
Units
RISING TO FALLING EDGE DELAY MATCHING
(VDELAY = VFALL = –0.5 V)3
Modes 0, 1, 5
0.1
1.0
ns
ns
Modes 2, 3
PROPAGATION DELAY TEMPERATURE
COEFFICIENT3, 5
0.05
% Tpd/°C
OUTPUT RISE/FALL TIMES
(20% to 80%)3
550
ps
DELAY LINEARITY3
MONOTONIC
NOTES
1The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is estabed by aping power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test et or the printed circuit board.
2All minimum propagation delay time measurements refer to both rising and falling edges for Modes 0, 1, 5; these asureefer to risedges for Modes 2 and
3 only. DRVMODE is logically low.
3This parameter is fully characterized, but not production tested.
4Delay on leading and trailing edges are measured by setting VDELAY = VWIDTH = –0.7 V. The variatifor h delay are mered by changing the input duty
cycle from 5% to 95% at a constant frequency of 10 MHz.
5Propagation delay temperature coefficient measured at VDELAY = VWIDTH = –0.7 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
RDERING GUIDE
ckage
Description
Package
Option
Parameter
EE (Relative to GND)
Voltage on Any Digital Pin
Output Current
Symbol Min
Max Units
Model
V
–6.0
VEE
0
V
5302
44-Lead Plastic Leaded Chip Carrier P-44A
(PLCC)
50
+
Ambient Operating Temperature TA
–55
–65
Storage Temperature
Junction Temperature
Soldering Temperature2
(Soldering, 5 sec)
TS
TJ
+
+1
PIN CONFIGURATION
TSOL
0 °C
6
5
4
3
2
1
44 43 42 41 40
NOTES
1Stresses above those listed under Absolute imum Ratings may use perma-
nent damage to the device. This is a stronly; funceration of the
device at these or any other conditionlin the operational sections
of this specification is not implied. mits apply individually,
not in combination. Exposure to ating conditions for ex-
tended periods of time may affect devic
PIN 1
39
38
37
36
35
34
33
32
7
8
IN4
IN1
IDENTIFIER
V
IN1
EE4
9
GND1
VDELAY4
VWIDTH4
10
COMP1
REXT1
COMP2
2To ensure lead solderabg with s should be avoided and the
device should be storeat 24°5°C (75°F ± 10°F) with relative
humidity not to exc
VDELAY3 11
AD53020
12
13
14
VWIDTH3
VDELAY2
VWIDTH2
TOP VIEW
(Not to Scale)
REXT2
DRVMODE
VDELAY1 15
VWIDTH1 16
31 S0
S1
30
29 GND1
V
17
BB
19
26
27 28
18
20 21 22 23 24 25
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53020 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD53020
A second bias current reference is employed to set the bias
current of the delay cells. This current is set by the external
resistor at REXT2. A 2.94 kΩ resistor sets the nominal bias
current of 500 µA. The nominal voltage at the REXT2 pin
is –1.47 V.
Table I. Truth Table for Mode Determination
Typical Independent Adjustment of
S1 S0 Mode
Span
Positive and Negative Edges?
0
0
1
1
VEE
VEE
0
1
0
1
0
1
0
1
2
3
19 ns
31 ns
19 ns
31 ns
No
No
Yes
Yes
The current references require compensation capacitors of
0.1 µF to VEE at each of the COMP1 and COMP2 pins. In
addition, each VEE supply pin should also have its own decou-
pling capacitor of 0.1 µF to ground.
Not Valid
5
45 ns
No
All decoupling capacitors should be located as close as possible
to the AD53020 chip.
S0 and S1 accept logical ECL levels. In the case of S1 only, a third state is also
accepted, at the negative supply, VEE
.
The mode is set by the inputs S0 and S1. These pins use stan-
dard ECL levels, with the addition of a third level for the S1
Pin, which can also be connected to VEE. Refer to Table I for
the description of the modes and their respective settings.
Table II. Package Themal Chacteristics
Air Flow, FM
JA, ؇C/W
For Modes 2 and 3, it is important to note that an internal flip-
flop is used to provide the independent control of rising and
falling edges. The state of this flip-flop is indeterminate upon
power-up. The state becomes fixed once the first full pulse is
provided to each channel, consisting of a positive edge followed
by a negative edge.
0
400
.2
20
OUTLINE DIMENSIONS
Dimensions shown in es and (mm).
44-Lead PLC
80 (4.57)
165 (4.19)
)
(1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
PIN
0.050
(1.27)
BSC
IDENTI
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
7
29
28
18
0.040 (1.01)
0.025 (0.64)
0.
(0.50)
R
0.656 (16.66)
SQ
SQ
0.650 (16.51)
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
–4–
REV. A
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