AD53042 [ADI]

High Speed Window Comparator; 高速窗口比较器


型号：	AD53042
厂家：	ADI
描述：	High Speed Window Comparator 高速窗口比较器比较器
文件：	总4页 (文件大小：73K)
中文：	中文翻译
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High Speed Window Comparator

AD53042

FUNCTIONAL BLOCK DIAGRAM

FEATURES

–2 V to +7 V Input Voltage Range

Low V_INBias Current (<100 nA)

Up to 5 V/ns Input Signal Tracking

Low Dispersion of ؎100 ps

28-Lead PLCC Package

GND

LEA NC

GND

LEA

GND

LATCH/OUTPUT

APPLICATIONS

DGND

AD53042

Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems

LATCH/OUTPUT

GND

LEB LEB

NC NC –V GND

NOTE:

NOT THE ACTUAL PHYSICAL LAYOUT OF DEVICE.

NC = NO CONNECTION INSIDE PACKAGE.

PRODUCT DESCRIPTION

The AD53042 is an ultrahigh speed window comparator

with latch. It uses a high speed monolithic process to provide

high dc accuracy without sacrificing input voltage range.

On-chip connection of the common input eliminates the

contributions of a second bonding pad and package pin to

the input capacitance, resulting in a maximum input

capacitance of 2 pF.

3.0V

2.8V

MIN. POSITIVE

INPUT PULSE

3.0V

MIN. NEGATIVE

INPUT PULSE

The AD53042 employs a high precision differential input

stage with a common mode range of 9 V. Its complementary

digital outputs are fully ECL-compatible. The output stage is

capable of driving a 50 Ω line terminated to –2 V. The device

also provides a latch function, allowing operation in track-hold

mode and can also be used to generate hysteresis.

0.2V

Figure 1. Typical Application Circuit

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(All specifications apply with T_C= 40؇C to 100؇C and +V_S= +7.75 V to +11.5 V;

–V_S= –3.95 V to –7.7 V unless otherwise noted.)

AD53042–SPECIFICATIONS

Parameter

Min

Typ

Max

Units

Test Conditions

POWER SUPPLIES

Positive Supply Currents

Negative Supply Current

Power Dissipation

No Load

–85

1.19

No Load, +V_S= +10 V, –V_S= –5.2 V

DC INPUT CHARACTERISTICS

Offset Voltage (V_OS

V_INBias Current

)

–10

–0.5

–20

0.5

µA

CMV = 0 V

V_IN= 0 V

<0.1

V_A, V_BBias Current

Capacitance V_IN, V_A, V_B

mV/V

Voltage Range (V_CM

)

–V_S+ 2.7

–5

+V_S– 2.5

0.1

Differential Voltage (V_DIFF

Nonlinearity

V_A/V_BInteraction

)

See Note 1

BIAS CURRENT

Change vs. Comparator State

Nonlinearity

–1

–2

µA

Tempco

±0.1

µA/°C

LATCH ENABLE INPUTS

Common-Mode Range

Differential Voltage

Logic “1” Current (L_IH)

Logic “0” Current (L_IL)

–2

0.4

200

µA

–10

DIGITAL OUTPUTS

Logic “1” Voltage (V_OH

Logic “0” Voltage (V_OL

)

–0.98

Q or Q, 50 Ω to –2 V

–1.5

SWITCHING PERFORMANCE

Propagation Delay

Input to Output

Latch Enable to Output

Part-to-Part Skew

V_IN= 2 V p-p, t_PDR, t_PDF, Figure 1, Note 2

1.2

Change vs. Temperature

±1

ps/°C

DISPERSION

5 V p-p Input (All Edges)

V Slew = 1 V/ns (All Edges)

Minimum Pulsewidth

Edge Interaction

±100

±175

±50

<200

<100

10%, 90% 0.5 V/ns, 3 V/ns

10%, 90% 5 V/ns

10%, 90% 3 V, 5 V

20%, 80% 1 V

See Note 3

See Note 4

See Note 5

Duty Ratio

Comparator Interaction

NOTES

¹Defined as change in V_OSfrom –V_S+ 2.95 V to +V_S– 2.75 V (throughout the range) after V_Aand V_Bare corrected for gain and offset using 0 V and 5 V.

²Propagation delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing.

³The minimum input pulsewidth that will maintain a 600 mV ECL swing on the output. The input is a 0 V to 3 V signal with a 3 V/ns rise and fall times. The input

pulsewidth is measured between the 2.8 V point of a positive input pulse and the 0.2 V of a negative input pulse. See Figure 2.

⁴Maximum Change in propagation delay as the input pulse is reduced from 50 ns to a 2 ns pulsewidth. 0 V to 3 V swing with 3 V/ns rise/fall time and 25% duty cycle.

⁵Maximum Change in propagation delay as the input pulse is reduced from 99% to a 1% duty cycle. 0 V to 3 V swing with 3 V/ns rise/fall time and 50 ns to 4.95 µs

pulsewidth, period = 5 µs.

Specifications subject to change without notice.

REV. A

–2–

AD53042

ORDERING GUIDE

ABSOLUTE MAXIMUM RATINGS*

Power Supply Voltage

Shipment Method,

Quantity

Per Shipping

Container

+V_Sto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V

–V_Sto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V

+V_Sto –V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

Inputs

Package

Description

Package

Option

Model

V_IN, V_A, V_B. . . . . . . . . . . . . . . +V_S– 13.5 V, –V_S+ 13.7 V

LEA, LEA, LEB, LEB . . . . . . . . . +V_S– 14 V, –V_S+10 V

Currents

+V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mA

–V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–75 mA

QA, QA, QB, QB . . . . . . . . . . . . . . . . . .–40 mA to +2 mA

Environmental

AD53042KRP

28-Lead PLCC

Tube, 36 Pieces

P-28A

PIN CONFIGURATION

28 27 26

Operating Temperature (Ambient) . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature (Soldering, 20 sec) . . . . . . . . . . .+300°C

PIN 1

IDENTIFIER

GND

VINA

25 GND

AD53042

TOP VIEW

(Not to Scale)

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Absolute maximum limits apply

individually, not in combination. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

DGND

VINAB

VINB

GND

19 GND

The device must suffer no reliability degradation if any supply pin is either shorted

to ground or left floating for an indefinite periods of time during normal operation.

14 15 16 17 18

NC = NO CONNECT

LEA, LEB

t_PDR

t_PDF

~1.2ns

t_PDR

t_PDF

Figure 2. Timing Diagram I

Figure 3. Timing Diagram II

If either of the latch enables, LEA or LEB are low, the output

follows the input. If LEA or LEB are high, the comparator out-

puts will be latched and they won’t change.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD53042 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

AD53042

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Plastic Leaded Chip Carrier

(P-28A)

0.180 (4.57)

0.165 (4.19)

0.048 (1.21)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

0.048 (1.21)

0.042 (1.07)

PIN 1

IDENTIFIER

0.021 (0.53)

0.013 (0.33)

0.430 (10.92)

0.390 (9.91)

0.050

(1.27)

BSC

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

0.040 (1.01)

0.025 (0.64)

0.020

(0.50)

MAX

0.456 (11.58)

0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

(3) PLACES

0.110 (2.79)

0.085 (2.16)

–4–

REV. A

AD53042 [ADI]

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