AD5310RBRMZ-RL7 [ADI]
10-Bit nanoDAC, SPI Interface and 2 ppm/°C On-Chip Reference;
| 型号： | AD5310RBRMZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 10-Bit nanoDAC, SPI Interface and 2 ppm/°C On-Chip Reference 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit nanoDAC with SPI/I2C Interface
and 2 ppm/°C On-Chip Reference
Data Sheet
AD5310R/AD5311R
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
V
V
DD
LOGIC
REF
High relative accuracy (INL): 0.5 LSB maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: 1.5 mV maximum
POWER-ON
RESET
AD5310R
2.5V
REF
LDAC
REF
10-BIT
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
DAC
RESET
Gain error: 0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
Independent logic supply: 1.8 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
SYNC
SCLK SDI
LOGIC
GND
Figure 1. AD5310R
APPLICATIONS
V
V
V
DD
REF
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
Optical modules
POWER-ON
RESET
AD5311R
2.5V
REF
LDAC
REF
10-BIT
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
DAC
RESET
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
GENERAL DESCRIPTION
RESISTOR
NETWORK
The AD5310R/AD5311R, members of the nanoDAC® family, are
low power, single-channel, 10-bit buffered voltage output DACs.
The devices include an enabled by default internal 2.5 V
reference, and provides 2 ppm/°C. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in 10-lead
MSOP packages.
SDA
SCL
A0
GND
Figure 2. AD5311R
Table 1. Related Devices
Interface
Reference
12-Bit
10-Bit
AD53101
AD53111
SPI
I2C
External
External
AD5681R
The internal power-on reset circuit of the AD5310R/AD5311R
ensures that the DAC register is written to zero scale at powerup
when the internal output buffer is configured in normal mode.
The devices contain a power-down mode that reduces the
current consumption of the device to 2 µA at 5 V.
1 The AD5310R and AD5311R are not pin-to-pin or software compatible with
the AD5310 and AD5311, respectively.
PRODUCT HIGHLIGHTS
The AD5310R/AD5311R use a versatile SPI or I2C interface,
1. High Relative Accuracy (INL): 0.5 LSB maximum.
2. Low Drift 2.5 V On-Chip Reference: 5 ppm/°C maximum
temperature coefficient.
RESET
including an asynchronous
pin and a VLOGIC pin that
provides 1.8 V compatibility.
Rev. B
Document Feedback
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Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5310R/AD5311R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Transfer Function....................................................................... 17
DAC Architecture....................................................................... 17
Serial Interface ................................................................................ 18
AD5310R SPI Serial Data Interface ......................................... 18
Daisy-Chain Mode Compatibility............................................ 18
AD5311R I2C Serial Data Interface.......................................... 19
Commands.................................................................................. 21
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter .................................................... 17
LDAC
Load DAC (Hardware
Pin)........................................... 22
RESET
Hardware
........................................................................ 22
AD5311R, I2C Read Operation ................................................ 22
Thermal Hysteresis .................................................................... 23
Power-Up Sequence ................................................................... 23
Layout Guidelines....................................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
2/2017—Rev. A to Rev. B
1/2014—Rev. 0 to Rev. A
Changes to Features Section and Table 1 ...................................... 1
Changed 1.8 V ≤ VLOGIC ≤ 5.5 V (VLOGIC = 1.8 V to 5.5 V) to
1.62 V ≤ VLOGIC ≤ 5.5 V ...................................................................... 3
Changed 1.8 V ≤ VLOGIC ≤ VDD to 1.62 V ≤ VLOGIC ≤ 5.5 V ............ 4
Changes to VLOGIC Parameter, Table 2 ............................................ 4
Changed VLOGIC = 1.8 V to 5.5 V to 1.62 V ≤ VLOGIC ≤ 5.5 V ........ 5
Changes to Table 4 and Figure 3............................................................... 5
Changed VLOGIC = 1.8 V to 5.5 V to 1.62 V ≤ VLOGIC ≤ 5.5 V ........ 6
Changes to Table 8............................................................................ 9
Changes to Table 9.......................................................................... 10
Changes to Terminology Section.................................................. 16
Changes to Transfer Function Section......................................... 17
Change to Features Section..............................................................1
Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6,
Table 2; Renumbered Sequentially..................................................3
Removed Endnote 3, Table 3............................................................4
Removed Endnote 1, Table 4; Renumbered Sequentially ............5
Changes to Table 6.............................................................................8
Removed Solder Heat Reflow Section and Figure 44;
Renumbered Sequentially ............................................................. 23
1/2014—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD5310R/AD5311R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREF ≤ VDD, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < TA < +105°C, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution
10
Bits
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
0.5
0.5
1.25
1.5
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
All 0s loaded to DAC register
All 1s loaded to DAC register
0.075
0.05
0.16
0.14
0.075
0.06
Total Unadjusted Error, TUE
Internal reference, gain = 1
Internal reference, gain = 2
External reference, gain = 1
External reference, gain = 2
Zero-Code Error Drift
Offset Error Drift
1
1
µV/°C
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio, PSRR
1
0.2
ppm/°C
mV/V
DAC code = midscale, VDD = 5 V 10%
OUTPUT CHARACTERISTICS
Output Voltage Range
0
0
VREF
2 × VREF
V
V
nF
Gain = 1
Gain = 2
RL = ∞
Capacitive Load Stability
2
10
nF
kΩ
RL = 2 kΩ
CL = 0 µF
Resistive Load
1
Load Regulation
10
10
µV/mA
VDD = 5 V, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
VDD = 3 V, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
µV/mA
Short-Circuit Current
Load Impedance at Rails2
20
50
mA
20
Ω
REFERENCE OUTPUT
Output Voltage
Voltage Reference TC3
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
2.4975
2.5025
5
V
At ambient temperature
See the Terminology section
2
ppm/°C
Ω
0.05
16.5
240
0.1 Hz to 10 Hz
µV p-p
nV/√Hz
At ambient temperature; f = 10 kHz,
CL = 10 nF
Capacitive Load Stability
Load Regulation, Sourcing
Load Regulation, Sinking
Output Current Load Capability
Line Regulation
5
µF
RL = 2 kΩ
At ambient temperature; VDD ≥ 3 V
At ambient temperature
VDD ≥ 3 V
50
30
µV/mA
µV/mA
mA
±5
80
125
25
µV/V
ppm
ppm
At ambient temperature
First cycle
Additional cycles
Thermal Hysteresis
Rev. B | Page 3 of 24
AD5310R/AD5311R
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
Input Current, IIN
1
4
µA
µA
V
V
pF
Per pin
SDA and SCL pins (AD5311R)
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance, CIN
LOGIC OUTPUT (SDA)
Output Low Voltage, VOL
Output High Voltage, VOH
Pin Capacitance
POWER REQUIREMENTS
VLOGIC
0.3 × VLOGIC
0.7 × VLOGIC
2
AD5311R
0.4
V
ISINK = 200 μA
ISOURCE = 200 μA
VLOGIC − 0.4
V
4
pF
1.62
5.5
3
5.5
5.5
V
µA
V
ILOGIC
VDD
0.25
VIH = VLOGIC or VIL = GND
Gain = 1
Gain = 2
2.7
VREF + 1.5
V
IDD
VIH = VDD, VIL = GND
Internal reference enabled
Internal reference disabled
Normal Mode4
350
110
500
180
2
µA
µA
µA
Power-Down Modes5
1 Linearity is calculated using a reduced code range: Code 8 to Code 1024, output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage with 20 Ω, 1 mA generates 20 mV. See Figure 29.
3 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.
4 Interface inactive. DAC active. Code = zero-scale, DAC output unloaded.
5 DAC powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREF ≤ VDD, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < TA < +105°C, unless
otherwise noted.1
Table 3.
Parameter2
Typ
5
Max
Unit
µs
V/µs
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
Conditions/Comments
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Total Harmonic Distortion (THD)
Output Noise Spectral Density
Output Noise
7
Gain = 1, ¼ to ¾ scale settling to 0.25 LSB
0.7
0.1
0.1
−83
200
6
1 LSB change around major carry, gain = 1
VREF = 2 V 0.1 V p-p, f = 10 kHz
DAC code = midscale, f = 10 kHz
0.1 Hz to 10 Hz; internal reference
At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT
1 kHz
Signal-to-Noise Ratio (SNR)
90
=
=
=
Spurious-Free Dynamic Range (SFDR)
88
82
dB
dB
At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT
1 kHz
At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT
1 kHz
Signal-to-Noise-and Distortion (SINAD) Ratio
1 Temperature range = −40°C to +105°C, typical at 25°C.
2 See the Terminology section.
Rev. B | Page 4 of 24
Data Sheet
AD5310R/AD5311R
TIMING CHARACTERISTICS
AD5310R
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
1.8 V ≤ VLOGIC ≤ 2.7 V
2.7 V ≤ VLOGIC2 ≤ 5.5 V
Parameter 1
Symbol
Min
33
16
16
15
5
Typ
Max
Min
20
10
10
10
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
Data Hold Time
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Falling Edge to SCLK Fall Ignore
SYNC Rising Edge to SCLK Falling Edge
SYNC Rising Edge to LDAC Falling Edge
LDAC Pulse Width Low
15
20
16
10
20
10
t8
t9
t10
t11
t12
t13
t14
t15
25
25
20
15
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
75
75
150
1.9
150
1.7
SYNC Rising Edge to SYNC Rising Edge (DAC
Updates)
LDAC Falling Edge to SYNC Rising Edge
Reference Power-Up3
Exit Shutdown3
t16
1.8
1.65
µs
µs
µs
4
tREF_POWER_UP
tSHUTDOWN
600
600
5
6
6
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin.
3 Not shown in Figure 3.
4 Same timing must be expected when powering up the device after VDD = 2.7 V.
5
SYNC
Time required to exit power-down to normal mode of AD5310R/AD5311R operation;
rising edge to 90% of DAC midscale value, with output unloaded.
Timing and Circuit Diagrams
t4
t7
t1
t9
t2
SCLK
SYNC
t10
t3
t8
t15
t5
t6
SDI
DB23
DB22
DB21
DB20
DB2
DB1
DB0
t11
t12
t16
LDAC
t13
RESET
t14
V
OUT
Figure 3. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note)
Rev. B | Page 5 of 24
AD5310R/AD5311R
Data Sheet
AD5311R
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < T < +105°C, unless otherwise noted.
A
Table 5.
Parameter1
Symbol
Min
Typ
Max
Unit
kHz
µs
2
Serial Clock Frequency (Not Shown in Figure 4 or Figure 5) fSCL
SCL High Time, tHIGH
400
t1
0.6
SCL Low Time, tLOW
t2
1.3
µs
Data Setup Time, tSU; DAT
t3
100
ns
Data Hold Time, tHD; DAT
t4
0
0.9
µs
Setup Time for a Repeated Start Condition, tSU; STA
Hold Time (Repeated) Start Condition, tHD; STA
Bus Free Time Between a Stop and a Start Condition, tBUF
Setup Time for a Stop Condition, tSU; STO
Rise Time of SDA Signal, tR
Fall Time of SDA Signal, tF
Rise Time of SCL Signal, tR
Fall Time of SCL Signal, tF
Pulse Width of Suppressed Spike (Not Shown in Figure 4
Figure 5)
t5
t6
t7
t8
0.6
0.6
1.3
0.6
µs
µs
µs
µs
ns
ns
ns
ns
t9
20
300
300
300
300
50
t10
t11
t12
tSP
20 × (VDD/5.5 V)
20
20 × (VDD/5.5 V)
0
ns
LDAC Falling Edge to SCL Falling Edge
LDAC Pulse Width (Synchronous Mode)
LDAC Pulse Width (Asynchronous Mode)
RESET Pulse Width
t13
400
400
20
ns
ns
ns
ns
µs
µs
t14
t15
t16
75
3
Reference Power-Up (Not Shown in Figure 4 or Figure 5)
Exit Shutdown (Not Shown in Figure 4 or Figure 5)
tREF_POWER_UP
tSHUTDOWN
600
4
6
1 Maximum bus capacitance is limited to 400 pF. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the device.
3 Same timing should be expected when powering the device after VDD = 2.7 V.
4 Time to exit power-down to normal mode of operation.
t12
t11
t6
t8
t2
SCL
SDA
t5
t1
t10
t9
t3
t4
t7
START
OR
REPEATED START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
Figure 4. I2C Serial Interface Timing Diagram
Rev. B | Page 6 of 24
Data Sheet
AD5310R/AD5311R
SCL
SDA
ACK
STOP
CONDITION
t14
t15
t13
LDAC
ASYNCHRONOUS
DAC UPDATE
SYNCHRONOUS
DAC UPDATE
t16
RESET
Figure 5. I2C, LDAC, and RESET Timing
Rev. B | Page 7 of 24
AD5310R/AD5311R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Table 7. Thermal Resistance
Package Type
θJA
1351
θJC
N/A2
Unit
10-Lead MSOP
°C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
2 N/A means not applicable.
VREF to GND
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Digital Input Voltage to GND
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
ESD CAUTION
Operating Temperature Range
Industrial
−40°C to +105°C
−65°C to +150°C
135°C
(TJ max − TA)/θJA
4 kV
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
ESD1
FICDM2
1.25 kV
1 Human body model (HBM) classification.
2 Field-induced charged-device model classification.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 24
Data Sheet
AD5310R/AD5311R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
10
V
DD
OUT
V
9
V
LOGIC
REF
AD5310R
RESET
LDAC
GND
8
SDI
TOP VIEW
(Not to Scale)
7
SYNC
SCLK
6
Figure 6. Pin Configuration, AD5310R
Table 8. AD5310R Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
VDD
VLOGIC
RESET
Power Supply Input. This device can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND.
Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and
external pins are ignored. The input and DAC registers are loaded with zero-scale values, and the control
register is loaded with default values. This pin can be tied to VLOGIC if not used.
4
LDAC
Load DAC. LDAC can be operated in asynchronous mode (see Figure 3). Pulsing this pin low allows the
DAC register to be updated if the input register has new data. This pin can be tied permanently low; in this
case, the DAC register is automatically updated when new data is written to the input register.
5
6
GND
SCLK
Ground Reference.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data is transferred at rates up to 50 MHz.
7
SYNC
Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input shift
register.
8
9
SDI
VREF
Serial Data Input. Data is sampled on the falling edge of the SCLK.
Reference Input/Output. By default, this pin is a reference output. It is recommended that this pin be
decoupled with a 10 nF capacitor to GND.
10
VOUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. B | Page 9 of 24
AD5310R/AD5311R
Data Sheet
V
1
2
3
4
5
10
9
V
V
DD
OUT
V
LOGIC
REF
AD5311R
RESET
LDAC
GND
8
SDA
SCL
A0
TOP VIEW
(Not to Scale)
7
6
Figure 7. Pin Configuration, AD5311R
Table 9. AD5311R Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
VDD
VLOGIC
RESET
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND.
Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external
pins are ignored. The input and DAC registers are loaded with zero-scale value, and the control register is loaded
with default values. This pin can be tied to VLOGIC if not used.
4
LDAC
Load DAC. Transfers the contents of the input register to the DAC register. It can be operated in two modes,
asynchronously and synchronously, as shown in Figure 5. This pin can be tied permanently low; the DAC updates
when new data is written to the input register.
5
6
7
8
9
GND
A0
SCL
SDA
VREF
Ground Reference.
Programmable Address (ADDR1) for Multiple Package Decoding. The address pin can be updated on-the-fly.
Serial Clock Line.
Serial Data Input/Output.
Reference Input/Output. The default for this pin is as a reference output. It is recommended to decouple this pin
with a 10 nF capacitor to GND.
10
VOUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. B | Page 10 of 24
Data Sheet
AD5310R/AD5311R
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
Figure 8. INL
Figure 11. DNL
0.5
0.4
0.06
0.04
0.02
0
U1_EXT
U2_EXT
U3_EXT
U1_INT
U2_INT
U3_INT
V
= 5V
DD
GAIN = 1
= 2.5V
V
REF
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.02
–0.04
0
200
400
600
800
1000
–40
0
40
TEMPERATURE (°C)
80
CODE
Figure 9. TUE vs. Code
Figure 12. TUE vs. Temperature
0.04
0.03
0.02
0.01
0
500
450
400
350
300
250
200
150
100
50
T
= 25°C
V
= 5V
A
DD
GAIN = 1
V
= 2.5V
REF
ZS INTERNAL REFERENCE, GAIN = 1
FS EXTERNAL REFERENCE, GAIN = 2
FS INTERNAL REFERENCE, GAIN = 2
ZS INTERNAL REFERENCE, GAIN = 2
FS INTERNAL REFERENCE, GAIN = 1
FS EXTERNAL REFERENCE, GAIN = 1
U1 INTERNAL REFERENCE
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
–0.01
–0.02
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
0
2.70
3.30
3.75
4.25
(V)
4.75
5.25
–40
–20
0
20
40
60
80
105
V
DD
TEMPERATURE (°C)
Figure 10. TUE vs. Supply, Gain = 1
Figure 13. Supply Current vs. Temperature
Rev. B | Page 11 of 24
AD5310R/AD5311R
Data Sheet
500
400
300
200
100
0
350
V
= 5V
U1 INTERNAL REFERENCE
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
T
= 25°C
DD
A
GAIN = 1
= 2.5V
GAIN = 1
V
V
= 2.5V
300
250
200
150
100
50
REF
REF
U1 INTERNAL REFERENCE
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
0
2.70
3.30
3.75
4.25
(V)
4.75
5.25
5.50
–40
–20
0
20
40
60
80
105
V
TEMPERATURE (°C)
DD
Figure 14. Zero-Code Error and Offset Error vs. Temperature
Figure 17. Zero-Code Error and Offset Error vs. Supply
0.030
0.025
0.020
0.015
0.010
0.005
0
0.03
T
= 25°C
A
GAIN = 1
V
= 2.5V
REF
0.02
0.01
0
U1 INTERNAL REFERENCE
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
–0.01
–0.02
–0.03
–0.04
–0.005
–0.010
–0.015
–0.020
–0.025
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
U1 INTERNAL REFERENCE
U2 INTERNAL REFERENCE
U3 INTERNAL REFERENCE
U1 EXTERNAL REFERENCE
U2 EXTERNAL REFERENCE
U3 EXTERNAL REFERENCE
V
= 5V
DD
GAIN = 1
V
= 2.5V
REF
2.70
3.30
3.75
4.25
(V)
4.75
5.25
5.50
–40
0
40
TEMPERATURE (°C)
80
V
DD
Figure 15. Gain Error and Full-Scale Error vs. Temperature
Figure 18. Gain Error and Full-Scale Error vs. Supply
2.505
2.503
2.501
2.499
2.497
2.495
2.50015
2.50010
2.50005
2.50000
2.49995
2.49990
2.49985
2.49980
V
= 5V
U1
U2
U3
DD
T
= 25°C
A
D11
D12
D13
–40
10
TEMPERATURE (°C)
60
2.5
3.5
4.5
5.5
V
(V)
DD
Figure 16. Internal Reference Voltage vs. Temperature
Figure 19. Internal Reference Voltage vs. Supply Voltage
Rev. B | Page 12 of 24
Data Sheet
AD5310R/AD5311R
2.5009
2.5008
2.5007
2.5006
2.5005
2.5004
2.5003
4.5
5.5V
5.0V
3.0V
2.7V
V
= 5V
T
= 25°C
DD
= 25°C
A
T
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GAIN = 1
–0.005
–0.003
–0.001
0.001
0.003
0.005
LOAD CURRENT (A)
V
(V)
REF
Figure 20. Reference Output Spread
Figure 23. Internal Reference Voltage vs. Load Current
1800
1600
1400
1200
1000
800
600
400
200
0
T
T
V
= 25°C
V
= 5V
A
DD
T = 25°C
A
= 5V
DD
1
10
100
1k
10k
100k
1M
CH1 10µV
M1.00s
A
CH1
2.00µV
FREQUENCY (Hz)
Figure 21. Internal Reference Noise, 0.1 Hz to 10 Hz
Figure 24. Internal Reference Noise Spectral Density vs. Frequency
T
T
T
V
= 25°C
= 5V
T
V
= 25°C
A
A
= 5V
DD
DD
1
1
CH1 10µV
M1.00s
A
CH1
2.00µV
CH1 10µV
M1.00s
A
CH1
2.00µV
Figure 22. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 25. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Rev. B | Page 13 of 24
AD5310R/AD5311R
Data Sheet
1200
1.4
1.0
V
= 5V
FULL-SCALE
DD
= 25°C
SINKING, V = 3V
T = 25°C
A
DD
MIDSCALE
T
A
SOURCING, V = 5V
DD
ZEROSCALE
GAIN = 1
1000
800
600
400
200
0
SINKING, V = 5V
DD
SOURCING, V = 3V
DD
0.6
0.2
–0.2
–0.6
–1.0
–1.4
10
100
1k
10k
100k
1M
0
0.01
0.02
0.03
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 26. Noise Spectral Density, Gain = 1
Figure 29. Headroom/Footroom vs. Load Current
7
6
5
V
T
= 5V
= 25°C
0x3FF
0x300
0x200
0x100
0x000
V
T
= 5V
= 25°C
0x3FF
0x300
0x200
0x100
0x000
DD
DD
A
A
6
5
GAIN = 2
GAIN = 1
4
4
3
3
2
2
1
1
0
0
–1
–2
–1
–50
0
50
–50
0
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 30. Source and Sink Capability, Gain = 2
Figure 27. Source and Sink Capability, Gain = 1
2.5
2.0
1.5
1.0
0.5
0
4.5
C
C
C
C
C
= 0nF
= 0.2nF
= 1nF
= 4.7nF
= 10nF
C
C
C
C
C
= 0nF
= 0.2nF
= 1nF
= 4.7nF
= 10nF
L
L
L
L
L
L
L
L
L
L
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
T
= 5V
V
T
= 5V
DD
= 25°C
DD
= 25°C
A
A
GAIN = 1
R
INTERNAL REFERENCE = 2.5V
GAIN = 2
= 2kΩ
= 2kΩ
R
L
L
INTERNAL REFERENCE = 2.5V
0
0.01
TIME (ms)
0.02
0
0.01
0.02
TIME (ms)
Figure 31. Settling Time vs. Capacitive Load, Gain = 1
Figure 28. Settling Time vs. Capacitive Load, Gain = 2
Rev. B | Page 14 of 24
Data Sheet
AD5310R/AD5311R
0.0015
0
–10
–20
–30
–40
–50
–60
–70
–80
GAIN = 1
GAIN = 2
GAIN = 2
GAIN = 1
V
= 5V
= 25°C
DD
T
A
0.0010
0.0005
0
REFERENCE = 2.5V
CODE = 0x7FFF TO 0x8000
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
V
= 5V
= 25°C
DD
T
A
V
= MIDSCALE
OUT
EXTERNAL REFERENCE = 2.5V, ±0.1V p-p
0
1
2
3
4
5
6
7
1k
10k
100k
1M
10M
TIME (µs)
FREQUENCY (Hz)
Figure 32. Digital-to-Analog Glitch Impulse
Figure 35. Multiplying Bandwidth, External Reference 2.5 V 0.1 V p-p,
10 kHz to 10 MHz
20
–30
3
V
= 5V
= 25°C
DD
V
= 5V
= 25°C
DD
T
A
T
A
INTERNAL REFERENCE = 2.5V
MIDSCALE, GAIN = 2
2
1
0
–80
SYNC
MIDSCALE, GAIN = 1
–130
–180
0
5
10
15
20
–5
0
5
10
15
FREQUENCY (kHz)
TIME (µs)
Figure 33. Total Harmonic Distortion at 1 kHz
Figure 36. Exiting Power-Down to Midscale
6
5
4
3
2
1
0
0.06
0.05
0.04
0.03
0.02
0.01
0
V
DD
V
OUT
–1
–0.01
0
1
2
3
4
5
6
7
8
TIME (ms)
Figure 34. Power-On, Reset to 0 V
Rev. B | Page 15 of 24
AD5310R/AD5311R
Data Sheet
TERMINOLOGY
Digital-to-Analog Glitch Impulse
Relative Accuracy or Integral Nonlinearity (INL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by 1 LSB at
a major carry transition (0x1FF to 0x200).
For the DAC, relative accuracy (or integral nonlinearity) is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. See Figure 8 for a typical INL vs. code plot.
Differential Nonlinearity (DNL)
Digital Feedthrough
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 11 for a typical DNL vs. code plot.
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but it
is measured when the DAC output is not updated. Digital
feedthrough is specified in nV-sec and is measured with a full-
scale code change on the data bus, that is, from all 0s to all 1s
and vice versa.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero code error of the input is always positive;
the output of the DAC cannot fall below 0 V due to a combination
of the offset errors in the DAC and in the output amplifier. Zero
code error is expressed in mV. See Figure 14 and Figure 17 for plots
of zero code error.
Output Noise Spectral Density
Noise spectral density is a measurement of the internally generated
random noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. See
Figure 22, Figure 25, and Figure 26 for plots of noise spectral
density. See Figure 21 and Figure 24 for plots of the noise
spectral density for the internal reference.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0x3FF) is loaded to the DAC register. The recom-
mended output is VREF – 1 LSB or |2 × VREF| − 1 LSB. Full-scale
error is expressed in percent of full-scale range (% of FSR). See
Figure 15 and Figure 18 for plots of full-scale error.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Gain Error
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal, expressed as % of FSR.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in zero-
code error with a change in temperature. It is expressed in µV/°C.
Voltage Reference Temperature Coefficient (TC)
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in gain
error with changes in temperature. It is expressed in ppm of FSR/°C.
Voltage reference TC is a measurement of the change in the
reference output voltage with a change in temperature. The
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range expressed in ppm/°C, as follows:
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the transfer
function. Offset error is measured with Code 4 loaded in the
DAC register. It can be negative or positive.
VREFmax −VREFmin
TC =
×106
V
×TempRange
REFnom
where:
REFmax is the maximum reference output measured over the
total temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range, −40°C to +105°C.
DC Power Supply Rejection Ratio (PSRR)
V
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD varies by 10%.
V
V
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change.
Rev. B | Page 16 of 24
Data Sheet
AD5310R/AD5311R
THEORY OF OPERATION
V
REF
DIGITAL-TO-ANALOG CONVERTER
R
The AD5310R/AD5311R are single-channel, 10-bit, serial input,
voltage output DACs with a 2.5 V internal reference. The devices
operate from supply voltages of 2.7 V to 5.5 V. Data is written to
the AD5310R/AD5311R in a 24-bit word format via an I2C serial
interface or SPI interface.
R
R
TO OUTPUT
BUFFER
The AD5310R/AD5311R incorporate a power-on reset circuit that
ensures that the DAC output powers up to a zero scale. The
devices also have a software power-down mode that reduces the
typical current consumption to 2 μA maximum in specs.
R
R
TRANSFER FUNCTION
The internal reference is on by default. The input coding to the
DAC is straight binary, and the ideal output voltage is given by
the following equations:
For the AD5310R,
Figure 38. Simplified Resistor String Structure
D
1024
Internal Reference
VOUT (D) = Gain×VREF
×
The AD5310R/AD5311R has a 2.5 V, 2 ppm/°C reference that
provides a full-scale output of 2.5 V or 5 V, depending on the
state of the gain bit, see Table 15.
For the AD5311R,
VOUT (D) = Gain×VREF
where:
D
1024
×
The AD5310R/AD5311R on-chip reference is on at power-up
but can be disabled via a write to the control register.
The internal reference is available at the VREF pin. It is internally
buffered and capable of driving external loads of up to 50 mA.
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
Gain is the gain of the output amplifier and is set to ×1 by
default. The gain can also be set to 1 or 2 using the gain select
bit in the control register.
External Reference
The VREF pin can be configured as an input pin, allowing the use
of an external reference if the application requires it. The default
condition of the on-chip reference is on at power-up.
DAC ARCHITECTURE
Before connecting an external buffer to the pin, a write to the
control register is required to disable the internal reference, see
the REF Bit section.
The DAC architecture implements a segmented string DAC
with an internal output buffer. Figure 37 shows the internal
block diagram.
V
REF
Output Buffer
2.5V
REF
The output buffer is designed as an input/output rail-to-rail
buffer, which gives a maximum output voltage range of up to 0
V to VDD. The gain bit sets the segmented string DAC gain to ×1
or ×2 as shown in Table 15. The output buffer voltage is
determined by VREF, the gain bit, and the offset and gain errors.
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
GND
The output buffer can drive 10nF capacitance with a 2 kΩ
resistor in parallel, as shown in Figure 34. If a higher capacitance
load is required, a shunt resistor must be connected between the
output amplifier and the load. The slew rate is 0.7 V/µs with a ¼
to ¾ scale settling time of 5 µs.
Figure 37. DAC Channel Architecture Block Diagram
The simplified segmented resistor string DAC structure is
shown in Figure 38. The code loaded to the DAC register
determines the switch on the string that is connected to the
output buffer.
Because each resistance in the string has the same value, R, the
string DAC is guaranteed monotonic.
Rev. B | Page 17 of 24
AD5310R/AD5311R
Data Sheet
SERIAL INTERFACE
AD5310R SPI SERIAL DATA INTERFACE
DAISY-CHAIN MODE COMPATIBILITY
SYNC
The AD5310R can be operated in a daisy-chain configuration,
but cannot forward data because there is no SDO pin. To connect
the AD5310R in daisy-chain mode, it is possible to connect only
one device per chain, and the AD5310R should be connected
the last device.
The AD5310R has a 3-wire serial interface (
, SCLK, and
SDI) that is compatible with serial peripheral interface (SPI),
Mode 1 and Mode 2, and with completely synchronous interfaces
such as SPORT. See Figure 3 for a timing diagram of a typical
write sequence. See the AN-1248 Application Note for more
information about the SPI interface.
Daisy-chaining minimizes the number of pins required from
the controlling IC. As shown in Figure 39, the SDO pin of one
package must be tied to the SDI pin of the next package. The
clock period may need to be increased because of the
propagation delay of the line between subsequent devices. By
default, the daisy-chain configuration mode is disabled. To
enable it, the DCEN bit must be set in the control register, as
shown in Table 11.
SYNC
The write sequence begins by bringing the
from the SDI line is sampled into the input shift register on the
SYNC
line low. Data
falling edge of SCLK. The
complete data-word (16 bits) is loaded from the SDI pin, as
SYNC
pin must be held low until the
shown in Figure 3. When
returns high, the serial data-
word is decoded according to the instructions in Table 10.
SYNC
must be brought high for a minimum of 20 ns before the
When the DCEN bit is enabled in the control register, the
AD5310R accepts as a valid frame any data-word longer than 24
bits, and decodes the last 24 bits received, with the last 10 LSB
as do not care bits.
SYNC
next write sequence such that a falling edge of
initiate the next write sequence.
can
SYNC
If
is brought high after 16 falling clock edges occur, it is
interpreted as a valid write and the first 16 bits are loaded to the
input shift register.
AD5686
CONTROLLER
U1
SDIN
SCLK
SYNC
MOSI
SCLK
SS
SYNC
If
is brought high before 16 falling clock edges, the serial
write is ignored and the write sequence is considered invalid.
SDO
To minimize power consumption, it is recommended that all
serial interface pins be operated close to the supply rails.
MISO
SDI
AD5310R
U2
SCLK
SYNC
Figure 39. Daisy-Chain Connection
SCLK
SYNC
24
48
DB23
DB0
DB23
DB0
MOSI
INPUT WORD FOR AD5310R
INPUT WORD FOR AD5686
INPUT WORD FOR AD5310R
DB23
DB0
SDO_U1
UNDEFINED
Figure 40. Daisy-Chain Timing Diagram
Rev. B | Page 18 of 24
Data Sheet
AD5310R/AD5311R
Table 10. SPI Command Operation
Command
Bits[DB15:DB12]
Data Bits [DB11:DB0]1
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 [DB1:DB0] Operation
C3 C2 C1 C0 DB11 DB10
0
0
0
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
XX
XX
XX
NOP. Do nothing.
DB9
X
DB8
X
DB7
X
DB6
X
DB5
X
DB4
X
DB3
X
DB2
X
DB1
X
DB0
X
Write input register.
Update DAC register
(LDAC software).
0
0
0
1
1
0
1
0
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB6
DB5
DB5
DB4
DB4
DB3
0
DB2
0
DB1
0
DB0
0
XX
00
Write DAC and input
register.
Write control register.
1 X = don’t care.
I2C Address
Table 11. Control Register Bits
The AD5311R has a 7-bit slave address. The five MSBs are
10011. The second to the last bit, set by the state of the A0
address pin and the LSB, is 0. The ability to make hardwired
changes to A0 lets the user have two of these devices on one bus,
as outlined in Table 12. Additionally, the pin can be updated
before starting the transmission, allowing multiples devices in the
same bus by connecting the pin to a GPIO or a multiplexer.
DB11
DB10
DB9
DB8
REF
DB7
GAIN
DB6
RESET
PD1
PDO
DCEN
AD5311R I2C SERIAL DATA INTERFACE
The AD5311R has a 2-wire, I2C-compatible serial interface.
These devices can be connected to an I2C bus as a slave device,
under the control of a master device. See Figure 4 for a timing
diagram of a typical write sequence.
Table 12. Device Address Selection
A0 Pin Connection
A0 Bit
I2C Address
1001100
The AD5311R supports standard (100 kHz) and fast (400 kHz)
data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
GND
0
1
VLOGIC
1001110
The 2-wire serial bus protocol operates as follows:
I2C Write Operation
1. The master initiates a data transfer by establishing a start
condition when a high to low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
called the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to, or read from, its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
When writing to the AD5311R, the user must begin with a start
W
condition followed by an address byte (R/ = 0), after which
the DAC acknowledges that it is prepared to receive data by
pulling SDA low, as shown in Figure 41. The AD5311R requires
a command byte that controls various DAC functions (see
Table 13) and two bytes of data for the DAC. All these data
bytes are acknowledged by the AD5311R. A stop condition
follows. The write sequence is shown in Figure 41.
3. When all the data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the tenth clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the tenth clock pulse, and then high during the
tenth clock pulse to establish a stop condition.
Rev. B | Page 19 of 24
AD5310R/AD5311R
Data Sheet
SCL
1
0
0
1
1
A0
0
R/W
SDA
START
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
ADDRESS BYTE
ACK MSB
BY
COMMAND BYTE
ACK
BY
AD5311R
CONDITION
BY
AD5311R
MASTER
SCL
SDA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DATA HIGH BYTE
ACK
BY
AD5311R
DATA LOW BYTE
ACK
BY
AD5311R
STOP
CONDITION
BY
MASTER
Figure 41. I2C Write Operation
Table 13. I2C Command Table1
Command Byte
Data High Byte
Data Low Byte
DB7 DB6 DB5 DB4 [DB3:DB0]
[DB7:DB3]
XXXXX
[DB2:DB0]
XXX
[DB7:DB6]
XX
[DB5:DB0]
XXXXX
XXXXX
XXXXX
XXXXX
00000
Operation
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
XXXX
XXXX
XXXX
XXXX
XXXX
NOP: do nothing.
Write input register.
DB9:DB5
XXXXX
DB:DB2
XXX
DB1:DB0
XX
Update DAC register (LDAC software).
Write DAC and input registers.
Write control register.
DB9:DB5
DB9:DB5
DB4:DB2
000
DB1:DB0
00
1 X = don’t care.
Table 14. Control Register Bits
DB9
DB8
DB7
PDO
DB6
REF
DB5
RESET
PD1
GAIN
Rev. B | Page 20 of 24
Data Sheet
AD5310R/AD5311R
PD0 and PD1 Bits
COMMANDS
Write Input Register
The AD5310R/AD5311R provide two separate modes of
operation that are accessed by writing to the write control register.
The input register allows the preloading of a new value for the
DAC register. The transfer from the input register to the DAC
In normal mode, the output buffer is directly connected to the
register can be triggered by hardware, by the
pin, or by
LDAC
V
OUT pin.
software using Command 2.
In power-down mode, the output buffer is internally disabled
and the VOUT pin output impedance can be selected to a well-
known value, as shown in Table 17.
If new data is loaded into the DAC register, the DAC register
automatically overwrites the input register.
Update DAC Register
Table 17. Operation Modes
This command transfers the contents of the input register to the
DAC register and, consequently, the VOUT pin is updated. The
data contained in the serial write is ignored.
Operating Mode
PD1
PD0
Normal Mode
0
0
Power-Down Modes
1 kΩ Output Impedance
100 kΩ Output Impedance
Three-State Output Impedance
This operation is equivalent to a software
.
LDAC
0
1
1
1
0
1
Write DAC Register
This command updates the DAC register on completion of the
write operation. The input register is refreshed automatically
with the DAC register value.
In power-down mode, the part disables the output buffer, but
does not disable the internal reference. To achieve maximum
power saving, it is recommend that the REF bit be disabled.
Write Control Register
The write control register command is used to set the power-
down and gain functions. It is also used to enable/disable the
internal reference and perform a software reset. See Table 14 for
the control register bits.
Disabling both the internal reference and the output buffer
results in the supply current falling to 2 μA at 5 V.
The output stage is illustrated in Figure 42.
Gain Bit
DAC
AMPLIFIER
V
OUT
The gain bit selects the gain of the output amplifier. Table 15
shows how the output voltage range corresponds to the state of
the gain bit.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Table 15. Gain Bit
Gain
Output Voltage Range
0 V to VREF (default)
0 V to 2 × VREF
0
1
Figure 42. Output Stage During Power-Down
The output amplifier is shut down when the power-down mode
is activated. However, unless the internal reference is powered
down, the bias generator, reference, and resistor string remain
on. The supply current falls to 2 μA at 5 V. The contents of the
DAC register are unaffected in power-down mode, and the DAC
register can be updated while the device is in power-down mode.
The time that is required to exit power-down is typically 4 µs for
REF Bit
The on-chip reference is on at power-up by default. This reference
can be turned on or off by setting a software programmable bit,
DB6, in the control register. Table 16 shows how the state of the
bit corresponds to the mode of operation.
V
DD = 5 V, or 600 µs if the reference is disabled.
To reduce power consumption, it is recommended that the
internal reference be disabled if the device is placed in power-
down mode.
Reset Bit
The write control register of the AD5310R/AD5311R contains a
software reset bits that resets the DAC registers to zero scale
and resets the input, the DAC, and the control registers to their
default values. A software reset is initiated by setting the reset
bit in the control register to 1. When the software reset is
completed, the reset bit is cleared to 0 automatically.
Table 16. REF Bit
REF
Reference Function
Reference enabled (default)
Reference disabled
0
1
Rev. B | Page 21 of 24
AD5310R/AD5311R
Data Sheet
LDAC
RESET
HARDWARE
LOAD DAC (HARDWARE
PIN)
The AD5310R/AD5311R have a double buffered interface
RESET
is an active low signal that resets the DAC output to zero
scale and sets the input, DAC, and control registers to their default
RESET
LDAC
consisting of an input register and a DAC register. The
pin transfers data from the input register to the DAC register,
and the output is updated.
values. It is necessary to keep
low for 75 ns to complete
signal returns high, the output
remains at zero scale until a new value is programmed. While the
RESET
RESET
the operation. When the
Synchronous DAC Update (AD5311R Only)
pin is low, the AD5310R/AD5311R ignore any new
command.
RESET
LDAC
If the
pin is held low while the input register is written,
the DAC register, input register, and output are updated on the
last SCL falling edge before the ACK bit, as shown in Figure 5.
If
is held low at power-up, the internal reference is not
RESET
initialized correctly until the
AD5311R, I2C READ OPERATION
pin is released.
Asynchronous DAC Update
LDAC
is held high while data is transmitted to the device. The
LDAC
DAC output is updated by taking
low after the stop
When reading the input register back from the AD5311R DAC,
condition is generated. The output DAC is updated on the
LDAC
W
the user begins with an address byte (R/ = 1), after which the
falling edge of the
pin.
DAC acknowledges that it is prepared to receive data by pulling
SDA low. Two bytes of data containing the contents of the input
register are then read from the DAC, as shown in Figure 43. A
NACK condition from the master followed by a stop condition
completes the read sequence.
LDAC
If
is pulsed while the device is accessed, the pulse is ignored.
1
9
1
9
SCL
DB7 DB6
DB5 DB4
DB3 DB2
DB1
DB0
1
0
0
1
1
A0
0
R/W
SDA
START BY
MASTER
ACK. BY
AD5311R
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
DATA HIGH BYTE
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
NACK. BY STOP BY
MASTER MASTER
FRAME 3
DATA LOW BYTE
Figure 43. I2C Read Operation
Rev. B | Page 22 of 24
Data Sheet
AD5310R/AD5311R
THERMAL HYSTERESIS
POWER-UP SEQUENCE
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
Because diodes limit the voltage compliance at the digital and
analog pins, it is important to power GND first before applying
any voltage to VDD, VOUT, and VLOGIC. Otherwise, the diode is
forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is GND, VDD, VLOGIC, VREF, followed by
the digital inputs.
The thermal hysteresis data is shown in Figure 44. It is measured by
sweeping the temperature from ambient +25°C to −40°C, then to
+105°C, and finally returning to ambient +25°C. The VREF delta
is next measured between the two ambient measurements and
shown in the solid lines in Figure 44. The same temperature
sweep and measurements are immediately repeated and the
results are shown in the dashed lines in Figure 44.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The PCB on which the
AD5310R/AD5311R are mounted should be designed such that
the AD5310R/AD5311Rare placed on the analog plane.
6
FIRST TEMPERATURE SWEEP
SUBSEQUENT…
5
Ensure that the AD5310R/AD5311R have ample supply
bypassing of 10 µF in parallel with 0.1 µF on each supply,
located as close to the package as possible, ideally right up
against the device. The 10 µF capacitors are the tantalum bead
type. Use a 0.1 µF capacitor with low effective series resistance
(ESR) and low effective series inductance (ESI), such as the
common ceramic types, which provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
4
3
2
1
0
–100
–80
–60
–40
–20
0
20
40
60
DISTORTION (ppm)
Figure 44. Thermal Hysteresis
Rev. B | Page 23 of 24
AD5310R/AD5311R
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 45. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Resolution (Bits)
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Package Option
RM-10
RM-10
Branding
DJZ
DJZ
AD5310RBRMZ
AD5310RBRMZ-RL7
AD5311RBRMZ
AD5311RBRMZ-RL7
10
10
10
10
RM-10
RM-10
DJX
DJX
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11956-0-2/17(B)
Rev. B | Page 24 of 24
相关型号：
AD5311BRMZ-REEL7
SERIAL INPUT LOADING, 7us SETTLING TIME, 10-BIT DAC, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
ADI
AD5311BRMZ-REEL7
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8
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