AD5312BRMZ-REEL [ADI]
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs; 2.5 V至5.5 V , 230 μA ,双通道,轨到轨,电压输出8位/ 10位/ 12位DAC型号: | AD5312BRMZ-REEL |
厂家: | ADI |
描述: | 2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs |
文件: | 总24页 (文件大小:1044K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
AD5302/AD5312/AD5322
GENERAꢀ DESCRIPTION
FEATURES
AD5302: Two 8-bit buffered DACs in 1 package
A version: 1 ꢀSB INꢀ, B version: 0.5 ꢀSB INꢀ
AD5312: Two 10-bit buffered DACs in 1 package
A version: 4 ꢀSB INꢀ, B version: 2 ꢀSB INꢀ
AD5322: Two 12-bit buffered DACs in 1 package
A version: 16 ꢀSB INꢀ, B version: 8 ꢀSB INꢀ
10-lead MSOP
The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail-
to-rail with a slew rate of 0.7 V/μs. The AD5302/AD5312/AD5322
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI®,
QSPI™, MICROWIRE™, and DSP interface standards.
Micropower operation: 300 μA @ 5 V (including
reference current)
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs can be configured as
buffered or unbuffered inputs. The outputs of both DACs can be
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V power supply
Double-buffered input logic
LDAC
updated simultaneously using the asynchronous
input.
Guaranteed monotonic by design over all codes
Buffered/Unbuffered reference input options
0 V to VREF output voltage
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power-
down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software-
selectable output loads while in power-down mode.
Power-on-reset to 0 V
Simultaneous update of DAC outputs via ꢀDAC
ꢀow power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
Qualified for automotive applications
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated
equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW
at 3 V, reducing to 1 μW in power-down mode.
APPꢀICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
A
DD
REF
POWER-ON
RESET
AD5302/AD5312/AD5322
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
V
OUT
A
BUFFER
SYNC
SCLK
DIN
INTERFACE
LOGIC
POWER-DOWN
LOGIC
RESISTOR
NETWORK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
V
OUT
B
BUFFER
RESISTOR
NETWORK
V
B
GND
LDAC
REF
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2006-2011 Analog Devices, Inc. All rights reserved.
AD5302/AD5312/AD5322
TABLE OF CONTENTS
Features .............................................................................................. 1
Low Power Serial Interface ....................................................... 15
Double-Buffered Interface ........................................................ 15
Power-Down Modes ...................................................................... 16
Microprocessor Interfacing........................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description.................................................................. 14
Digital-to-Analog Section ......................................................... 14
Resistor String............................................................................. 14
DAC Reference Inputs ............................................................... 14
Output Amplifier........................................................................ 14
Power-On Reset.......................................................................... 14
Serial Interface ................................................................................ 15
Input Shift Register..................................................................... 15
AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103
Interface....................................................................................... 17
AD5302/AD5312/AD5322 to 68HC11/68L11 Interface ...... 17
AD5302/AD5312/AD5322 to 80C51/80L51 Interface.......... 17
AD5302/AD5312/AD5322 to MICROWIRE Interface ........ 17
Applications Information.............................................................. 18
Typical Application Circuit....................................................... 18
Bipolar Operation Using the AD5302/AD5312/AD5322..... 18
Opto-Isolated Interface for Process Control Applications ... 19
Decoding Multiple AD5302/AD5312/AD5322s.................... 19
AD5302/AD5312/AD5322 as a Digitally Programmable
Window Detector....................................................................... 19
Coarse and Fine Adjustment Using the
AD5302/AD5312/AD5322 ....................................................... 20
Power Supply Bypassing and Grounding................................ 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
5/11—Rev. C to Rev. D
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide.......................................................... 21
Added Automotive Products Information................. Throughout
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
8/03—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................4
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 16
4/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
12/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Rev. D | Page 2 of 24
AD5302/AD5312/AD5322
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Version1
Typ
B Version1
Typ
Parameter2
DC PERFORMANCE3, 4
Min
Max
Min
Max
Unit
Test Conditions/Comments
AD5302
Resolution
8
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5312
0.15
0.02
1
0.25
0.15
0.02
0.5
0.25
Guaranteed monotonic by design over all codes
Guaranteed monotonic by design over all codes
Resolution
10
0.5
0.05
10
0.5
0.05
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5322
4
0.5
2
0.5
Resolution
12
12
Bits
Relative Accuracy
Differential Nonlinearity
Offset Error
2
1ꢀ
1
3
2
8
1
3
1
LSB
LSB
% of FSR
% of FSR
mV
0.2
0.4
0.15
10
0.2
0.4
0.15
10
Guaranteed monotonic by design over all codes
See Figure 3 and Figure 4
See Figure 3 and Figure 4
Gain Error
1
Lower Deadband
Offset Error Drift5
ꢀ0
ꢀ0
See Figure 3 and Figure 4
−12
−12
ppm of
FSR/°C
ppm of
FSR/°C
Gain Error Drift5
−5
−5
Power Supply Rejection
Ratio5
DC Crosstalk5
−ꢀ0
30
−ꢀ0
30
dB
∆VDD = 10%
μV
DAC REFERENCE INPUTS5
VREF Input Range
1
0
VDD
VDD
1
0
VDD
VDD
V
V
MΩ
kΩ
dB
dB
Buffered reference mode
Unbuffered reference mode
Buffered reference mode
Unbuffered reference mode, input impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz
VREF Input Impedance
>10
180
−90
−80
>10
180
−90
−80
Reference Feedthrough
Channel-to-Channel
Isolation
OUTPUT CHARACTERISTICS5
Minimum Output Voltageꢀ
0.001
0.001
V min
V max
A measure of the minimum drive capability of
the output amplifier
A measure of the maximum drive capability of
the output amplifier
Maximum Output Voltageꢀ
VDD
−
VDD
−
0.001
0.5
50
20
2.5
5
0.001
0.5
50
20
2.5
5
DC Output Impedance
Short-Circuit Current
Ω
mA
mA
μs
VDD = 5 V
VDD = 3 V
Power-Up Time
Coming out of power-down mode, VDD = 5 V
Coming out of power-down mode, VDD = 3 V
μs
LOGIC INPUTS5
Input Current
VIL, Input Low Voltage
1
0.8
0.ꢀ
0.5
1
0.8
0.ꢀ
0.5
μA
V
V
VDD = 5 V 10%
VDD = 3 V 10%
VDD = 2.5 V
V
VIH, Input High Voltage
Pin Capacitance
2.4
2.1
2.0
2.4
2.1
2.0
V
V
V
pF
VDD = 5 V 10%
VDD = 3 V 10%
VDD = 2.5 V
2
3.5
2
3.5
Rev. D | Page 3 of 24
AD5302/AD5312/AD5322
A Version1
B Version1
Typ
Parameter2
Min
Typ
Max
Min
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.ꢀ V
2.5
5.5
2.5
5.5
V
IDD specification is valid for all DAC codes
Both DACs active and excluding load currents
Both DACs in unbuffered mode, VIH = VDD and
300
230
450
350
300
230
450
350
μA
μA
VIL = GND; in buffered mode, extra current is
typically × ꢁA per DAC where x = 5 ꢁA + VREF/RDAC
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.ꢀ V
0.2
0.05
1
1
0.2
0.05
1
1
μA
μA
1 Temperature range: A, B version: –40°C to +105°C.
2 See Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).
5 Guaranteed by design and characterization, not production tested.
ꢀ In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and offset plus gain error must be positive.
AC SPECIFICATIONS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
A, B Version2
Parameter3
Min
Typ
Max
Unit
Test Conditions/Comments
Output Voltage Settling Time
AD5302
AD5312
VREF = VDD = 5 V
ꢀ
7
8
8
9
10
μs
μs
μs
¼ Scale to ¾ Scale Change (0 × 40 to 0 × C0)
¼ Scale to ¾ Scale Change (0 × 100 to 0 × C300)
¼ Scale to ¾ Scale Change (0 × 400 to 0 × C00)
AD5322
Slew Rate
0.7
12
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1 LSB Change Around Major Carry (011…11 to 100…00)
0.10
0.01
0.01
200
−70
VREF = 2 V 0.1 V p-p, Unbuffered Mode
VREF = 2.5 V 0.1 V p-p, Frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 Temperature range: A, B version: −40°C to +105°C.
3 See Terminology section.
Rev. D | Page 4 of 24
AD5302/AD5312/AD5322
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.1, 2, 3
Table 3.
Parameter
ꢀimit at TMIN, TMAX (A, B Version)
Unit
Conditions/Comments
t1
t2
t3
t4
t5
tꢀ
t7
t8
t9
33
13
13
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Active Edge Setup Time
Data Setup Time
5
4.5
0
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulse Width
100
20
20
SCLK Falling Edge to LDAC Rising Edge
ns min
t10
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
t6
t5
1
DIN
DB15
DB0
t9
LDAC
t10
LDAC
1
SEE INPUT SHIFT REGISTER SECTION.
Figure 2. Serial Interface Timing Diagram
Rev. D | Page 5 of 24
AD5302/AD5312/AD5322
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
IDEAL
ACTUAL
POSITIVE
OFFSET
ERROR
DAC CODE
DEADBAND
AMPLIFIER
FOOTROOM
(1mV)
NEGATIVE
OFFSET
ERROR
Figure 3. Transfer Function with Negative Offset
GAIN ERROR
PLUS
OFFSET ERROR
ACTUAL
OUTPUT
VOLTAGE
IDEAL
POSITIVE
OFFSET
ERROR
DAC CODE
Figure 4. Transfer Function with Positive Offset
Rev. D | Page ꢀ of 24
AD5302/AD5312/AD5322
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
–0.3 V to +7 V
Digital Input Voltage to GND
Reference Input Voltage to
GND
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND
–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version)
Storage Temperature Range
–40°C to +105°C
–ꢀ5°C to +150°C
Junction Temperature (TJ max) +150°C
10-Lead MSOP
Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (ꢀ0 sec)
Infrared (15 sec)
(TJ max – TA)/θJA
20ꢀ°C/W
44°C/W
215°C
220°C
1
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 7 of 24
AD5302/AD5312/AD5322
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
1
2
3
4
5
10 GND
AD5302/
AD5312/
V
9
8
7
6
DIN
DD
V
B
A
SCLK
SYNC
REF
AD5322
V
TOP VIEW
REF
OUT
(Not to Scale)
V
A
V
B
OUT
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
LDAC
Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers.
Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data. This
allows simultaneous updating of both DAC outputs.
2
3
VDD
VREF
Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
B
Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an
unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to VDD in
unbuffered mode and 1 V to VDD in buffered mode.
4
VREF
A
Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an
unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to VDD in
unbuffered mode and 1 V to VDD in buffered mode.
5
ꢀ
7
VOUT
VOUT
SYNC
A
B
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the following 1ꢀ clocks. If SYNC is taken high before the 1ꢀth falling edge, the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the device.
8
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Serial Data Input. This device has a 1ꢀ-bit input shift register. Data is clocked into the register on the falling
edge of the serial clock input. The DIN input buffer is powered down after each write cycle.
9
10
GND
Ground Reference Point for All Circuitry on the Part.
Rev. D | Page 8 of 24
AD5302/AD5312/AD5322
TERMINOLOGY
LDAC
change (all 0s to all 1s and vice versa) while keeping
Relative Accuracy
LDAC
high, then pulsing
low, and monitoring the output of the
DAC whose digital code is not changed. The area of the glitch is
expressed in nV-sec.
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 6.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 9.
LDAC
change (all 0s to all 1s and vice versa) while keeping
low
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-sec.
DC Crosstalk
Offset Error
This is the dc change in the output level of one DAC in response
to a change in the output of the other DAC. It is measured with
a full-scale output change on one DAC while monitoring the
other DAC. It is expressed in μV.
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied 10ꢀ.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
LDAC
updated (that is,
is high). It is expressed in dB.
Major-Code Transition Glitch Energy
Total Harmonic Distortion (THD)
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-sec and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC and the THD is a measure of the
harmonics present on the DAC output. It is measured in dB.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
SYNC
(
held high). It is specified in nV-sec and is measured
Channel-to-Channel Isolation Definition
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dB.
with a full-scale change on the digital input pins, that is, from
all 0s to all 1s and vice versa.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code
Rev. D | Page 9 of 24
AD5302/AD5312/AD5322
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.3
0.2
T
V
= 25°C
= 5V
T
= 25°C
= 5V
A
A
V
DD
DD
0.5
0
0.1
0
–0.1
–0.2
–0.3
–0.5
–1.0
0
50
100
150
200
250
0
0
0
50
100
150
200
250
1000
4000
CODE
CODE
Figure 6. AD5302 Typical INL Plot
Figure 9. AD5302 Typical DNL Plot
3
0.6
0.4
T
V
= 25°C
T
V
= 25°C
A
A
= 5V
= 5V
DD
DD
2
1
0.2
0
0
–1
–2
–3
–0.2
–0.4
–0.6
0
200
400
600
800
1000
200
400
600
800
CODE
CODE
Figure 7. AD5312 Typical INL Plot
Figure 10. AD5312 Typical DNL Plot
3
2
1.0
0.5
T
V
= 25°C
= 5V
T
V
= 25°C
A
A
= 5V
DD
DD
1
0
0
–4
–8
–12
–0.5
–1.0
0
1000
2000
3000
4000
1000
2000
3000
CODE
CODE
Figure 8. AD5322 Typical INL Plot
Figure 11. AD5322 Typical DNL Plot
Rev. D | Page 10 of 24
AD5302/AD5312/AD5322
1.00
0.75
0.50
0.25
0
T
V
= 25°C
A
= 5V
DD
V
= 5V
DD
V
= 3V
DD
MAX INL
MAX DNL
MIN DNL
MIN INL
–0.25
–0.50
–0.75
–1.00
0
100
150
200
250
(µA)
300
350
400
2
3
4
5
I
DD
V
(V)
REF
Figure 15. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 12. AD5302 INL and DNL Error vs. VREF
5
4
1.00
0.75
0.50
0.25
0
V
V
= 5V
DD
= 3V
REF
5V SOURCE
3V SOURCE
MAX DNL
MAX INL
3
2
–0.25
–0.50
–0.75
–1.00
MIN INL
MIN DNL
3V SINK
5V SINK
1
–0
–40
0
40
80
120
0
1
2
3
4
5
6
SINK/SOURCE CURRENT(mA)
TEMPERATURE(°C)
Figure 16. Source and Sink Current Capability
Figure 13. AD5302 INL Error and DNL Error vs. Temperature
600
500
400
300
200
100
0
1.0
T
V
= 25°C
A
V
V
= 5V
DD
= 5V
DD
=2V
REF
0.5
0
GAIN ERROR
–0.5
–1.0
OFFSET ERROR
ZERO SCALE
FULL SCALE
–40
0
40
TEMPERATURE(°C)
80
120
Figure 14. Offset Error and Gain Error vs. Temperature
Figure 17. Supply Current vs. Code
Rev. D | Page 11 of 24
AD5302/AD5312/AD5322
600
V
T
= 5V
DD
= 25°C
BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED
A
500
CH2
CLK
400
+25°C
–40°C
300
+105°C
200
100
0
V
OUT
CH1
CH1 1V, CH2 5V, TIME BASE = 5µs/DIV
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
Figure 18. Supply Current vs. Supply Voltage
Figure 21. Half-Scale Setting (¼ to ¾ Scale Code Change)
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
A
BOTH DACS IN
THREE-STATE CONDITION
V
DD
–40°C
+25°C
CH1
CH2
V
A
OUT
+105°C
5.2
CH1 1V, CH2 1V, TIME BASE = 20µs/DIV
2.7
3.2
3.7
4.2
(V)
4.7
V
DD
Figure 19. Power-Down Current vs. Supply Voltage
Figure 22. Power-On Reset to 0 V
700
600
500
400
300
200
100
T
= 25°C
A
T
= 25°C
A
V
OUT
CH1
CH3
V
= 5V
DD
CLK
V
= 3V
DD
CH1 1V, CH3 5V, TIME BASE = 1µs/DIV
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
LOGIC
Figure 20. Supply vs. Logic Input Voltage
Figure 23. Existing Power-Down to Midscale
Rev. D | Page 12 of 24
AD5302/AD5312/AD5322
2.50
2.49
2.48
2.47
500ns/DIV
1µs/DIV
Figure 26. DAC-to-DAC Crosstalk
Figure 24. AD5322 Major-Code Transition
1.0
0.5
10
0
T
V
= 25°C
A
= 5V
DD
–10
–20
–30
–40
–50
–60
0
–0.5
–1.0
0
1
2
3
4
5
10
100
1k
10k
100k
1M
10M
V
(V)
FREQUENCY(Hz)
REF
Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response)
Figure 27. Full-Scale Error vs. VREF (Buffered)
Rev. D | Page 13 of 24
AD5302/AD5312/AD5322
FUNCTIONAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They contain reference buffers and output
buffer amplifiers, and are written to via a 3-wire serial interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/μs. Each DAC is provided with a separate
reference input, which can be buffered to draw virtually no
current from the reference source, or unbuffered to give a
reference input range from GND to VDD. The devices have three
programmable power-down modes, in which one or both DACs
can be turned off completely with a high impedance output, or
the output can be pulled low by an on-chip resistor.
R
R
R
TO OUTPUT
AMPLIFIER
R
R
Figure 29. Resistor String
DAC REFERENCE INPUTS
There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as
unbuffered. The advantage of the buffered input is the high
impedance it presents to the voltage source driving it.
DIGITAꢀ-TO-ANAꢀOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
However, if the unbuffered mode is used, the user can have a
reference voltage as low as GND and as high as VDD because
there is no restriction due to headroom and footroom of the
reference amplifier. If there is a buffered reference in the circuit
(for example, REF192), there is no need to use the on-chip
buffers of the AD5302/AD5312/AD5322. In unbuffered mode,
the impedance is still large (180 kꢁ per reference input).
V
REF × D
VOUT
=
2N
where:
The buffered/unbuffered option is controlled by the BUF bit in
the control word (see the Serial Interface section for a
description of the register contents).
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for AD5302 (8 bits)
0 to 1023 for AD5312 (10 bits)
0 to 4095 for AD5322 (12 bits)
N = DAC resolution.
OUTPUT AMPꢀIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to VDD – 0.001 V when the reference is VDD
V
A
REF
.
It is capable of driving a load of 2 kꢁ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 16.
SWITCH
CONTROLLED
BY CONTROL
LOGIC
REFERENCE
BUFFER
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at eight bits) of 6 μs. See Figure 21.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
A
OUT
OUTPUT BUFFER
AMPLIFIER
POWER-ON RESET
Figure 28. Single DAC Channel Architecture
The AD5302/AD5312/AD5322 are provided with a power-on
reset function to power them up in a defined state. The power-
on state is
RESISTOR STRING
The resistor-string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
•
•
•
Normal operation
Reference inputs unbuffered
Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
Rev. D | Page 14 of 24
AD5302/AD5312/AD5322
SERIAL INTERFACE
falling edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16th are ignored, and no further serial data
The AD5302/AD5312/AD5322 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
SYNC
transfers occur until
is taken high and low again.
th
SYNC
can be taken high after the falling edge of the 16 SCLK
SYNC
pulse, observing the minimum SCLK falling edge to
rising edge time, t7.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 30 to Figure 32).
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this
operation is shown in Figure 2. The 16-bit word consists of four
control bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. The first bit loaded is the MSB (Bit 15),
which determines whether the data is for DAC A or DAC B.
Bit 14 determines if the reference input is buffered or unbuffered.
Bit 13 and Bit 12 control the operating mode of the DAC.
After the end of serial data transfer, data is automatically
transferred from the input shift register to the input register of
th
SYNC
the selected DAC. If
is taken high before the 16 falling
edge of SCLK, the data transfer is aborted and the input
registers are not updated.
When data has been transferred into both input registers, the
DAC registers of both DACs can be simultaneously updated by
LDAC
taking
low.
Table 6. Control Bits
Bit Name Function
Power-On Default
ꢀOW POWER SERIAꢀ INTERFACE
15 A/B
14 BUF
0: Data Written to DAC A
N/A
To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being
written to. As soon as the 16-bit control word has been written
to the part, the SCLK and DIN input buffers are powered down.
1: Data Written to DAC B
0: Reference Is Unbuffered
1: Reference Is Buffered
Mode Bit
0
13 PD1
12 PD0
0
0
SYNC
They only power up again following a falling edge of
.
Mode Bit
DOUBꢀE-BUFFERED INTERFACE
BIT 15
(MSB)
BIT 0
(LSB)
The AD5302/AD5312/AD5322 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers and
DAC registers. The input register is connected directly to the input
shift register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.
A/B BUF PD1 PD0 D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
Figure 30. AD5302 Input Shift Register Contents
BIT 15
(MSB)
BIT 0
(LSB)
A/B BUF PD1 PD0 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
LDAC
Access to the DAC register is controlled by the
function.
is high, the DAC register is latched and the input
register can change state without affecting the contents of the
LDAC
DATA BITS
LDAC
When
Figure 31. AD5312 Input Shift Register Contents
BIT 15
(MSB)
BIT 0
(LSB)
DAC register. However, when
is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it.
A/B BUF PD1 PD0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 32. AD5322 Input Shift Register Contents
This is useful if the user requires simultaneous updating of both
DAC outputs. The user can write to both input registers
The remaining bits are DAC data bits, starting with the MSB and
ending with the LSB. The AD5322 uses all 12 bits of DAC data,
the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses
eight bits and ignores the last four bits. The data format is straight
binary, with all 0s corresponding to 0 V output, and all 1s
corresponding to full-scale output (VREF – 1 LSB).
LDAC
individually and then, by pulsing the
outputs update simultaneously.
input low, both
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
LDAC
the last time that
was brought low. Normally, when
SYNC
The
synchronization signal and chip enable. Data can only be
SYNC
input is a level-triggered input that acts as a frame
LDAC
is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5302/
AD5312/AD5322, the part only updates the DAC register if
the input register has been changed since the last time the
DAC register was updated, thereby removing unnecessary
digital crosstalk.
transferred into the device while
is low. To start the serial
SYNC
data transfer,
should be taken low observing the minimum
SYNC
SYNC
goes low,
to SCLK active edge setup time, t4. After
serial data is shifted into the device’s input shift register on the
Rev. D | Page 15 of 24
AD5302/AD5312/AD5322
POWER-DOWN MODES
The AD5302/AD5312/AD5322 have very low power consump-
tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Table 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.
•
•
•
The output is connected internally to GND through a
1 kꢁ resistor,
The output is connected internally to GND through a
100 kꢁ resistor, or
The output is left open-circuited (three-state).
The output stage is illustrated in Figure 33.
Table 7. PD1/PD0 Operating Modes
The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents of
the registers are unaffected when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
PD1
PDO
Operating Mode
0
0
1
1
0
1
0
1
Normal Operation
Power-Down (1 kΩ Load to GND)
Power-Down (100 kΩ Load to GND)
Power-Down (High Impedance Output)
VDD = 3 V. See Figure 23 for a plot.
When both bits are set to 0, the DACs work normally with
their normal power consumption of 300 μA at 5 V. However,
for the three power-down modes, the supply current falls to
200 nA at 5 V (50 nA at 3 V). Not only does the supply current
drop, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. There are three different options.
AMPLIFIER
RESISTOR-
STRING DAC
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 33. Output Stage During Power-Down
Rev. D | Page 1ꢀ of 24
AD5302/AD5312/AD5322
MICROPROCESSOR INTERFACING
AD5302/AD5312/AD5322 TO ADSP-2101/ADSP-
2103 INTERFACE
AD5302/AD5312/AD5322 TO 80C51/80ꢀ51
INTERFACE
Figure 34 shows a serial interface between the AD5302/AD5312/
AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-
2103 should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 sport is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. The data is clocked
out on each falling edge of the DSP’s serial clock and clocked into
the AD5302/AD5312/AD5322 on the rising edge of the DSP’s serial
clock. This corresponds to the falling edge of the DAC’s SCLK.
Figure 36 shows a serial interface between the AD5302/AD5312/
AD5322 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives
SCLK of the AD5302/AD5312/AD5322, while RXD drives the
SYNC
serial data line of the part. The
signal is again derived
from a bit programmable pin on the port. In this case, port line
P3.3 is used. When data is to be transmitted to the AD5302/
AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmit
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data in a format that has the LSB first. The
AD5302/AD5312/AD5322 require their data with the MSB as
the first bit received. The 80C51/80L51 transmit routine should
take this into account.
ADSP-2101/
ADSP-21031
AD5302/
AD5312/
AD53221
SYNC
TFS
DT
DIN
SCLK
SCLK
80C51/80L511
AD5302/
1
ADDITIONAL PINS OMITTED FOR CLARITY
AD5312/
AD53221
Figure 34. AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface
SYNC
SCLK
DIN
P3.3
TXD
RXD
AD5302/AD5312/AD5322 TO 68HC11/68ꢀ11
INTERFACE
Figure 35 shows a serial interface between the AD5302/AD5312/
AD5322 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5302/AD5312/AD5322,
while the MOSI output drives the serial data line of the DAC.
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. AD5302/AD5312/AD5322 to 80C51/80L51 Interface
AD5302/AD5312/AD5322 TO MICROWIRE
INTERFACE
SYNC
The
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit = 0
and its CPHA bit = 1. When data is being transmitted to the
Figure 37 shows an interface between the AD5302/AD5312/
AD5322 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked
into the AD5302/AD5312/AD5322 on the rising edge of the SK.
SYNC
DAC, the
line is taken low (PC7). When the 68HC11/
68L11 are configured as above, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/ 68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the
AD5302/AD5312/AD5322, PC7 is left low after the first eight
bits are transferred and a second serial write operation is
performed to the DAC; PC7 is taken high at the end of this
procedure.
MICROWIRE1
AD5302/
AD5312/
AD53221
CS
SYNC
SK
SO
SCLK
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. AD5302/AD5312/AD5322 to MICROWIRE Interface
68HC11/68L111
AD5302/
AD5312/
AD53221
SYNC
PC7
SCK
SCLK
DIN
MOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. AD5302/AD5312/AD5322 to 68HC11/68L11 Interface
Rev. D | Page 17 of 24
AD5302/AD5312/AD5322
APPLICATIONS INFORMATION
TYPICAꢀ APPꢀICATION CIRCUIT
6V to 16V
The AD5302/AD5312/AD5322 can be used with a wide range
of reference voltages, especially if the reference inputs are
configured to be unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0 V to VDD. More typically, the AD5302/AD5312/AD5322 can
be used with a fixed, precision reference voltage. Figure 38
shows a typical setup for the AD5302/AD5312/AD5322
when using an external reference. If the reference inputs are
unbuffered, the reference input range is from 0 V to VDD, but if
the on-chip reference buffers are used, the reference range is
reduced. Suitable references for 5 V operation are the AD780
and REF192 (2.5 V references). For 2.5 V operation, a suitable
external reference would be the REF191, a 2.048 V reference.
V
0.1µF
1µF
10µF
IN
REF195
V
OUT
V
DD
V
A
OUT
GND
V
V
A
B
REF
REF
AD5302/AD5312/
AD5322
SCLK
DIN
V
B
OUT
SYNC
GND
SERIAL
INTERFACE
Figure 39. Using a REF195 as Power and Reference to the
AD5302/AD5312/AD5322
V
= 2.5V to 5.5V
DD
BIPOꢀAR OPERATION USING THE
AD5302/AD5312/AD5322
V
DD
EXT
REF
V
The AD5302/AD5312/AD5322 are designed for single-supply
operation, but bipolar operation is also achievable using the
circuit shown in Figure 40. This circuit is configured to achieve
an output voltage range of –5 V < VOUT < +5 V. Rail-to-rail
operation at the amplifier output is achievable using an AD820
or OP295 as the output amplifier.
OUT
V
V
A
B
V
A
REF
OUT
1µF
REF
AD780/REF192
WITH V = 5V
OR REF191 WITH
AD5302/AD5312/
DD
AD5322
V
= 2.5V
DD
SCLK
DIN
V
B
OUT
SYNC
GND
V
= 5V
6V to 16V
DD
R2
10kΩ
SERIAL
INTERFACE
0.1µF
10µF
Figure 38. AD5302/AD5312/AD5322 Using External Reference
+5V
–5V
R1
10kΩ
V
IN
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered (for example, 0 V to 5 V),
the simplest solution is to connect the reference inputs to VDD
As this supply cannot be very accurate and can be noisy, the
AD5302/AD5312/AD5322 can be powered from the reference
voltage, for example, a 5 V reference such as the REF195, as
shown in Figure 39. The REF195 outputs a steady supply
voltage for the AD5302/AD5312/AD5322. The current required
from the REF195 is 300 μA supply current and approximately
30 μA into each reference input. This is with no load on the
DAC outputs. When the DAC outputs are loaded, the REF195
also needs to supply the current to the loads. The total current
required (with a 10 kꢁ load on each output) is
±5V
REF195
V
V
DD
AD820/
OP295
OUT
V
A/B
REF
.
1µF
GND
AD5302/AD5312/
AD5322
SCLK
DIN
V
A/B
OUT
SYNC
GND
SERIAL
INTERFACE
Figure 40. Bipolar Operation Using the AD5302/AD5312/AD5322
The output voltage for any input code can be calculated as
follows:
REF ×D /2N
R1
)
×(R1+ R2)
⎡
⎢
⎣
⎤
⎥
⎦
V
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
5 V
VOUT
=
−V
× R2/ R1
( )
REF
360 μA+2
=1.36 mA
10 kΩ
where:
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA
current drawn from it. This corresponds to a 0.0007 LSB error
at eight bits and a 0.011 LSB error at 12 bits.
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
V
REF is the reference voltage input.
If VREF = 5 V, R1 = R2 = 1 kꢁ, and VDD = 5 V:
VOUT − 5V
10 × D /2N
=
)
Rev. D | Page 18 of 24
AD5302/AD5312/AD5322
The 74HC139 is used as a 2-to-4 line decoder to address any of
the DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 42 shows a
diagram of a typical setup for decoding multiple AD5302/
AD5312/AD5322 devices in a system.
OPTO-ISOꢀATED INTERFACE FOR PROCESS
CONTROꢀ APPꢀICATIONS
Each AD5302/AD5312/AD5322 has a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it can be necessary to isolate the
AD5302/AD5312/AD5322 from the controller. This can easily
be achieved by using opto-isolators, which provide isolation in
excess of 3 kV. The serial loading structure of the AD5302/
AD5312/AD5322 makes them ideally suited for use in opto-
isolated applications. Figure 41 shows an opto-isolated interface
SCLK
AD5302/AD5312/AD5322
SYNC
DIN
DIN
SCLK
V
V
DD
CC
1G 74HC139
ENABLE
1Y0
1Y1
1Y2
1Y3
AD5302/AD5312/AD5322
SYNC
DIN
1A
1B
CODED
ADDRESS
SYNC
to the AD5302/AD5312/AD5322 where DIN, SCLK, and
SCLK
are driven from opto-couplers. The power supply to the part
also needs to be isolated by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5302/AD5312/AD5322.
DGND
AD5302/AD5312/AD5322
SYNC
DIN
SCLK
5V
REGULATOR
AD5302/AD5312/AD5322
SYNC
10µF
0.1µF
POWER
DIN
SCLK
V
DD
DD
DD
Figure 42. Decoding Multiple AD5302/AD5312/AD5322 Devices in a System
10kΩ
V
DD
AD5302/AD5312/AD5322 AS A DIGITAꢀꢀY
PROGRAMMABꢀE WINDOW DETECTOR
SCLK
SCLK
V
A
REF
V
B
REF
Figure 43 shows a digitally programmable upper-/lower-limit
detector using the two DACs in the AD5302/AD5312/AD5322.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition.
AD5302/AD5312/
AD5322
V
10kΩ
V
A
OUT
SYNC
SYNC
V
B
OUT
V
5V
10kΩ
0.1µF
10µF
V
1kΩ
FAIL
1kΩ
PASS
IN
DIN
DIN
GND
V
DD
V
V
V
A
REF
REF
V
A
OUT
B
REF
AD5302/AD5312/
Figure 41. AD5302/AD5312/AD5322 in an Opto-Isolated Interface
PASS/FAIL
1/6 74HC05
1/2
CMP04
AD5322
SYNC
SYNC
DIN
DECODING MUꢀTIPꢀE AD5302/AD5312/AD5322s
DIN
V
B
SCLK
SCLK
OUT
SYNC
The
pin on the AD5302/AD5312/AD5322 can be used in
GND
applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and serial
Figure 43. Window Detector Using AD5302/AD5312/AD5322
SYNC
data, but only the
to one of the devices is active at any one
time, allowing access to two channels in this eight-channel system.
Rev. D | Page 19 of 24
AD5302/AD5312/AD5322
POWER SUPPꢀY BYPASSING AND GROUNDING
COARSE AND FINE ADJUSTMENT USING THE
AD5302/AD5312/AD5322
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5302/AD5312/AD5322 is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5302/
AD5312/AD5322 are in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at one point only. The star ground point should be
established as close as possible to the AD5302/AD5312/
AD5322. The part should have ample supply bypassing of 10 μF
in parallel with 0.1 μF on the supply located as close as possible
to the package, ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. The 0.1 μF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESI), similar to the common ceramic types
that provide a low impedance path to ground at high frequencies
that handle transient currents due to internal logic switching.
The DACs in the AD5302/AD5312/AD5322 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 44. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, so the output range is 0 V to 2.5 V − 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B a
range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD can be used. The op amps indicated allow a
rail-to-rail output swing.
V
= 5V
DD
R3
R4
51.2kΩ
900Ω
+5V
0.1µF
1µF
10µF
V
IN
The power supply lines of the AD5302/AD5312/AD5322
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique
is by far the best, but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi-
cated to ground while signal traces are placed on the solder side.
EXT
REF
V
DD
V
OUT
R1
V
OUT
V
A
V
A
REF
OUT
AD820/
OP295
390Ω
GND
AD5302/AD5312/
AD5322
R2
V
B
V
B
OUT
REF
51.2kΩ
GND
Figure 44. Coarse/Fine Adjustment
Rev. D | Page 20 of 24
AD5302/AD5312/AD5322
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 45. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. D | Page 21 of 24
AD5302/AD5312/AD5322
ORDERING GUIDE
2
Model1,
Temperature Range
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
D5A
D5A
D5A#
D5A#
D5A#
D5B
AD5302ARM
AD5302ARM-REEL7
AD5302ARMZ
AD5302ARMZ-REEL
AD5302ARMZ-REEL7
AD5302BRM
AD5302BRM-REEL
AD5302BRM-REEL7
AD5302BRMZ
AD5302BRMZ-REEL
AD5302BRMZ-REEL7
AD5312ARM
AD5312ARMZ
AD5312ARMZ-REEL7
AD5312BRM
AD5312BRM-REEL
AD5312BRM-REEL7
AD5312BRMZ
AD5312BRMZ-REEL
AD5312BRMZ-REEL7
AD5322ARM
AD5322ARM-REEL7
AD5322ARMZ
AD5322ARMZ-REEL7
AD5322BRM
AD5322BRM-REEL
AD5322BRM-REEL7
AD5322BRMZ
AD5322BRMZ-REEL
AD5322BRMZ-REEL7
AD5312WARMZ-REEL7
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
D5B
D5B
D5B#
D5B#
D5B#
DꢀA
DꢀA#
DꢀA#
DꢀB
DꢀB
DꢀB
DꢀB#
DꢀB#
DꢀB#
D7A
D7A
DꢀT
DꢀT
D7B
D7B
D7B
D7B#
D7B#
D7B#
DꢀA#
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5312WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information
and to obtain the specific Automotive Reliability report for this model.
Rev. D | Page 22 of 24
AD5302/AD5312/AD5322
NOTES
Rev. D | Page 23 of 24
AD5302/AD5312/AD5322
NOTES
©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00928-0-5/11(D)
Rev. D | Page 24 of 24
相关型号:
AD5312BRMZ-REEL7
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO10, ROHS COMPLIANT, MO-187BA, MSOP-10
ROCHESTER
AD5313ARU
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153AB, TSSOP-16
ROCHESTER
AD5313ARU-REEL7
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, MO-153AB, TSSOP-16
ROCHESTER
AD5313ARUZ
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
ROCHESTER
©2020 ICPDF网 联系我们和版权申明