AD5318ARUZ-REEL7_技术文档

2.5 V to 5.5 V Octal Voltage Output

8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5308/AD5318/AD5328

APPꢀICATIONS

FEATURES

AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP

A version: 1 ꢀSB INꢀ, B version: 0.75 ꢀSB INꢀ

AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP

A version: 4 ꢀSB INꢀ, B version: 3 ꢀSB INꢀ

AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP

A version: 16 ꢀSB INꢀ, B version: 12 ꢀSB INꢀ

ꢀow power operation: 0.7 mA @ 3 V

Guaranteed monotonic by design over all codes

Power-down to 120 nA @ 3 V, 400 nA @ 5 V

Double-buffered input logic

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Optical networking

Automatic test equipment

Mobile communications

Programmable attenuators

Industrial process control

Buffered/unbuffered/V_DDreference input options

Output range: 0 V to V_REFor 0 V to 2 V_REF

Power-on reset to 0 V

Programmability

Individual channel power-down

Simultaneous update of outputs (ꢀDAC)

ꢀow power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-

compatible 3-wire serial interface

On-chip rail-to-rail output buffer amplifiers

Temperature range: −40°C to +125°C

Qualified for automotive applications

GENERAꢀ DESCRIPTION

incorporate a power-on reset circuit, which ensures that the

DAC outputs power up to 0 V and remain there until a valid

write to the device takes place. The outputs of all DACs may be

The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit

buffered voltage output DACs in a 16-lead TSSOP. They operate

from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical

at 3 V. Their on-chip output amplifiers allow the outputs to

swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308/

AD5318/AD5328 use a versatile 3-wire serial interface that

operates at clock rates up to 30 MHz and is compatible with

standard SPI, QSPI, MICROWIRE, and DSP interface

standards.

LDAC

updated simultaneously using the asynchronous

input.

The parts contain a power-down feature that reduces the current

consumption of the devices to 400 nA at 5 V (120 nA at 3 V).

The eight channels of the DAC may be powered down individually.

All three parts are offered in the same pinout, which allows

users to select the resolution appropriate for their application

without redesigning their circuit board.

The references for the eight DACs are derived from two

reference pins (one per DAC quad). These reference inputs can

be configured as buffered, unbuffered, or V_DDinputs. The parts

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5308/AD5318/AD5328

TABLE OF CONTENTS

Features .............................................................................................. 1

Low Power Serial Interface ....................................................... 18

LDAC

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 15

Digital-to-Analog Converter .................................................... 15

Resistor String............................................................................. 15

Output Amplifier........................................................................ 15

Power-On Reset.......................................................................... 16

Power-Down Mode .................................................................... 16

Serial Interface ............................................................................ 16

Load DAC Input (

) Function......................................... 18

Double-Buffered Interface ........................................................ 18

Microprocessor Interface............................................................... 19

ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328

Interface....................................................................................... 19

68HC11/68L11-to-AD5308/AD5318/AD5328 Interface ..... 19

80C51/80L51-to-AD5308/AD5318/AD5328 Interface......... 19

Microwire-to-AD5308/AD5318/AD5328 Interface.............. 20

Applications Information.............................................................. 21

Typical Application Circuit....................................................... 21

Driving V_DDfrom the Reference Voltage ................................ 21

Bipolar Operation Using the AD5308/AD5318/AD5328..... 21

Opto-Isolated Interface for Process Control Applications ... 21

Decoding Multiple AD5308/AD5318/AD5328s.................... 22

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

4/11—Rev. E to Rev. F

Added Automotive Products Information................. Throughout

2/11—Rev. D to Rev. E

Change to Temperature Range .................................... Throughout

Changes to Table 3, t₄Timing Characteristics.............................. 6

3/07—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings Section......................... 7

9/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Change to Equation........................................................................ 21

11/03—Rev. A to Rev. B

Changes to Ordering Guide ............................................................ 4

Changes to Y axis on TPCs 12, 13, and 15.................................... 9

8/03—Rev. 0 to Rev. A

Added A Version.................................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications................................................................ 2

Edits to Absolute Maximum Ratings ............................................. 4

Edits to Ordering Guide .................................................................. 4

Updated Outline Dimensions....................................................... 18

Rev. F | Page 2 of 28

AD5308/AD5318/AD5328

FUNCTIONAL BLOCK DIAGRAM

V

ABCD

V

REF

DD

V

DD

GAIN-SELECT

LOGIC

STRING

INPUT

REGISTER

DAC

REGISTER

V

A

B

C

D

E

F

BUFFER

DAC A

BUFFER

OUT

LDAC

STRING

DAC

REGISTER

STRING

DAC B

INPUT

REGISTER

DAC

REGISTER

INPUT

REGISTER

STRING

DAC C

SCLK

DAC

REGISTER

INPUT

REGISTER

STRING

DAC D

INTERFACE

LOGIC

SYNC

DIN

INPUT

REGISTER

DAC

REGISTER

STRING

DAC E

INPUT

REGISTER

DAC

REGISTER

STRING

DAC F

INPUT

REGISTER

DAC

REGISTER

STRING

DAC G

G

H

RESET

INPUT

REGISTER

DAC

REGISTER

STRING

DD

DAC H

GND

POWER-ON

RESET

GAIN-SELECT

LOGIC

POWER-DOWN

LOGIC

V

DD

V

EFGH

REF

GND

LDAC

Figure 1.

Rev. F | Page 3 of 28

AD5308/AD5318/AD5328

SPECIFICATIONS

V_DD= 2.5 V to 5.5 V; V_REF= 2 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise specified.

Table 1.

A Version¹

Typ

B Version¹

Typ

Parameter²

Min

Max

Min

Max

Unit

Conditions/Comments

DC PERFORMANCE^{3, 4}

AD5308

Resolution

Relative Accuracy

Differential Nonlinearity

8

Bits

LSB

0.15

0.02

1

0.25

0.15

0.02

0.ꢀ5

0.25

Guaranteed monotonic by

design over all codes

AD5318

Resolution

Relative Accuracy

Differential Nonlinearity

10

12

10

12

Bits

LSB

0.5

0.05

4

0.50

0.5

0.05

3

0.50

Guaranteed monotonic by

design over all codes

AD5328

Resolution

Relative Accuracy

Differential Nonlinearity

Bits

LSB

2

0.2

1ꢁ

1.0

2

0.2

12

1.0

Guaranteed monotonic by

design over all codes

Offset Error

5

ꢁ0

5

ꢁ0

mV

V_DD= 4.5 V, gain = 2, see

Figure 2ꢀ and Figure 28

Gain Error

0.30

10

1.25

0.30

1.25

% of FSR

mV

V_DD= 4.5 V, gain = 2, see

Figure 2ꢀ and Figure 28

Lower deadband exists only

if offset error is negative, see

Figure 2ꢀ

Upper deadband exists only

if V_REF= V_DDand offset plus

gain error is positive, see

Figure 28

Lower Deadband⁵

ꢁ0

10

ꢁ0

Upper Deadband⁵

10

ꢁ0

10

ꢁ0

mV

Offset Error Drift^ꢁ

Gain Error Drift^ꢁ

−12

−5

−12

−5

ppm of

FSR/°C

ppm of

FSR/°C

DC Power Supply Rejection Ratio^ꢁ

DC Crosstalk^ꢁ

−ꢁ0

200

−ꢁ0

200

dB

μV

V_DD= 10%

R_L= 2 kΩ to GND or V_DD

DAC REFERENCE INPUTS^ꢁ

V_REFInput Range

1.0

0.25

V_DD

1.0

0.25

V_DD

V

Buffered reference mode

Unbuffered reference mode

V_REFInput Impedance (R_DAC

)

>10.0

45.0

>10.0

45.0

MΩ

Buffered reference mode

and power-down mode

Unbuffered reference mode,

0 V to V_REFoutput range

Unbuffered reference mode,

0 V to 2 V_REFoutput range

3ꢀ.0

18.0

3ꢀ.0

18.0

kΩ

22.0

Reference Feedthrough

−ꢀ0.0

−ꢀ5.0

−ꢀ0.0

−ꢀ5.0

dB

Frequency = 10 kHz

Channel-to-Channel Isolation

OUTPUT CHARACTERISTICS^ꢁ

Minimum Output Voltage^ꢀ

0.001

V

Ω

This is a measure of the

minimum and maximum

Drive capability of the

output amplifier

Maximum Output Voltage^ꢀ

DC Output Impedance

V_DD

−

V_DD− 0.001

0.5

0.001

0.5

Rev. F | Page 4 of 28

AD5308/AD5318/AD5328

A Version¹

Typ

B Version¹

Typ

Parameter²

Min

Max

Min

Max

Unit

mA

μs

Conditions/Comments

V_DD= 5 V

V_DD= 3 V

Coming out of power-down

mode, V_DD= 5 V

Short Circuit Current

25.0

1ꢁ.0

2.5

25.0

1ꢁ.0

2.5

Power-Up Time

5.0

μs

Coming out of power-down

mode, V_DD= 3 V

LOGIC INPUTS^ꢁ

Input Current

V_IL, Input Low Voltage

1

0.8

0.ꢀ

1

0.8

0.ꢀ

μA

V

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

V

V_IH, Input High Voltage

1.ꢀ

2.5

1.ꢀ

2.5

V

V_DD= 2.5 V to 5.5 V, TTL and

CMOS compatible

Pin Capacitance

POWER REQUIREMENTS

V_DD

3.0

pF

V

5.5

I_DD(Normal Mode)⁸

V_DD= 4.5 V to 5.5 V

V_IH= V_DDand V_IL= GND

All DACs in unbuffered

mode, in buffered mode

Extra current is typically x μA

per DAC; x = (5 μA +

V_REF/R_DAC)/4

1.0

0.ꢀ

1.8

1.5

1.0

0.ꢀ

1.8

1.5

mA

V_DD= 2.5 V to 3.ꢁ V

I_DD(Power-Down Mode)⁹

V_DD= 4.5 V to 5.5 V

V_IH= V_DDand V_IL= GND

0.4

0.12

1

0.4

0.12

1

μA

V_DD= 2.5 V to 3.ꢁ V

¹Temperature range (A, B version): −40°C to +125°C; typical at 25°C.

²See the Terminology section.

³DC specifications tested with the outputs unloaded unless stated otherwise.

⁴Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).

⁵This corresponds to x codes. x = deadband voltage/LSB size.

^ꢁGuaranteed by design and characterization; not production tested.

^ꢀFor the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V_REF= V_DDand offset plus

gain error must be positive.

⁸Interface inactive. All DACs active. DAC outputs unloaded.

⁹All eight DACs powered down.

V_DD= 2.5 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2. AC Characteristics¹

A, B Version²

Parameter³

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5308

AD5318

V_REF= V_DD= 5 V

ꢁ

ꢀ

8

9

10

μs

1/4 scale to 3/4 scale change (0x40 to 0xC0)

1/4 scale to 3/4 scale change (0x100 To 0x300)

1/4 scale to 3/4 scale change (0x400 to 0xC00)

AD5328

Slew Rate

0.ꢀ

12

0.5

1

3

200

−ꢀ0

V/μs

nV-sec

kHz

Major-Code Change Glitch Energy

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB change around major carry

V_REF= 2 V 0.1 V p-p, unbuffered mode

V_REF= 2.5 V 0.1 V p-p, frequency = 10 kHz

dB

¹Guaranteed by design and characterization; not production tested.

²Temperature range (A, B version): –40°C to +125°C; typical at 25°C.

³See the Terminology section.

Rev. F | Page 5 of 28

AD5308/AD5318/AD5328

Table 3. Timing Characteristics^{1, 2, 3}

A, B Version

Parameter

ꢀimit at T_MIN, T_MAX

Unit

Conditions/Comments

t₁

t₂

t₃

t₄

33

13

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time; temperature range (A, B

verstion): −40°C to +105°C

15

ns min

SYNC to SCLK falling edge setup time; temperature range (A, B

verstion): −40°C to +125°C

t₅

t₆

t₇

5

4.5

0

ns min

Data set up time

Data hold time

SCLK falling edge to SYNC rising edge

t₈

50

20

0

Minimum SYNC high time

t₉

LDAC pulse width

t₁₀

t₁₁

SCLK falling edge to LDAC rising edge

SCLK falling edge to LDAC falling edge

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 2.

t₁

SCLK

t₂

t₃

t₇

t₈

t₄

t₆

SYNC

DIN

t₅

DB15

DB0

t₉

t₁₁

1

LDAC

t₁₀

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

2

Figure 2. Serial Interface Timing Diagram

Rev. F | Page 6 of 28

AD5308/AD5318/AD5328

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

T_A= 25°C, unless otherwise specified.

Table 4.

Parameter

Rating¹

V_DDto GND

−0.3 V to +7 V

Digital Input Voltage to GND

Reference Input Voltage to GND

V_OUTA–V_OUTDto GND

−0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Industrial (A, B Version)

Storage Temperature Range

ESD CAUTION

−40°C to +125°C

−65°C to +150°C

150°C

Junction Temperature (T_{J MAX}

16-Lead TSSOP

)

Power Dissipation

θ_JAThermal Impedance

Lead Temperature

Soldering

(T_{J MAX}− T_A)/θ_JA

150.4°C/W

JEDEC industry-standard

J-STD-020

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. F | Page 7 of 28

AD5308/AD5318/AD5328

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LDAC

SYNC

SCLK

DIN

AD5308/

AD5318/

AD5328

V

GND

DD

V

A

B

C

D

V

H

G

F

OUT

TOP VIEW

(Not to Scale)

E

V

ABCD

EFGH

REF

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

LDAC

This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simul-

taneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges

of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

3

V_DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND.

4

5

6

7

8

V_OUT

A

B

C

D

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or V_DDinput to the four

DACs, depending on the state of the BUF and V_DDcontrol bits. It has an input range from 0.25 V to V_DDin unbuffered

mode and from 1 V to V_DDin buffered mode.

V_REFABCD

9

V_REFEFGH

Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or V_DDinput to the four

DACs, depending on the state of the BUF and V_DDcontrol bits. It has an input range from 0.25 V to V_DDin unbuffered

mode and from 1 V to V_DDin buffered mode.

10

11

12

13

14

15

V_OUT

GND

DIN

E

F

G

H

Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input. The DIN input buffer is powered down after each write cycle.

16

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

Rev. F | Page 8 of 28

AD5308/AD5318/AD5328

TYPICAL PERFORMANCE CHARACTERISTICS

0.3

0.2

1.0

T

V

= 25°C

A

T

= 25°C

A

= 5V

DD

V

= 5V

DD

0.5

0

0.1

0

–0.1

–0.2

–0.3

–0.5

–1.0

0

50

100

150

200

250

0

50

100

150

200

250

CODE

Figure 7. AD5308 Typical DNL Plot

Figure 4. AD5308 Typical INL Plot

3

0.6

0.4

T

V

= 25°C

T = 25°C

A

= 5V

V

= 5V

DD

2

1

0.2

0

–1

–2

–3

–0.2

–0.4

–0.6

0

200

400

600

800

1000

0

200

400

600

800

1000

CODE

Figure 5. AD5318 Typical INL Plot

Figure 8. AD5318 Typical DNL Plot

12

8

1.0

0.5

T

V

= 25°C

T

V

= 25°C

A

= 5V

DD

4

0

–4

–8

–12

–0.5

–1.0

0

500

1000

1500

2000

2500

3000

3500

4000

0

500

1000

1500

2000

2500

3000

3500

4000

CODE

Figure 6. AD5328 Typical INL Plot

Figure 9. AD5328 Typical DNL Plot

Rev. F | Page 9 of 28

AD5308/AD5318/AD5328

0.50

0.2

0.1

T

V

= 25°C

T

V

= 25°C

= 2V

A

= 5V

DD

REF

MAX INL

0.25

0

GAIN ERROR

MAX DNL

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

MIN DNL

OFFSET ERROR

–0.25

–0.50

MIN INL

0

1

2

3

4

5

6

0

1

2

3

4

5

V

(V)

V

(V)

REF

DD

Figure 10. AD5308 INL and DNL Error vs. V_REF

Figure 13. Offset Error and Gain Error vs. V_DD

0.5

0.4

5

4

3

2

1

0

V

= 3V

REF

= 5V

V

DD

MAX INL

5V SOURCE

3V SOURCE

0.3

0.2

MAX DNL

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

MIN DNL

3V SINK

5V SINK

MIN INL

80

0

1

2

3

4

5

6

– 40

0

40

120

SINK/SOURCE CURRENT (mA)

TEMPERATURE (°C)

Figure 14. V_OUTSource and Sink Current Capability

Figure 11. AD5308 INL Error and DNL Error vs. Temperature

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

V

= 5V

DD

= 2V

REF

T

V

= 25°C

= 5V

A

DD

0.5

0

GAIN ERROR

OFFSET ERROR

–0.5

–1.0

ZERO SCALE

HALF SCALE

DAC CODE

FULL SCALE

–40

0

40

TEMPERATURE (°C)

80

120

Figure 15. Supply Current vs. DAC Code

Figure 12. AD5308 Offset Error and Gain Error vs. Temperature

Rev. F | Page 10 of 28

AD5308/AD5318/AD5328

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

T

= 25°C

T = 25°C

A

V

= 2V, GAIN = +1,

V

= 5V

REF

BUFFERED

DD

V

= 5V

REF

V

= V

DD

REF

V

A

OUT

CH1

CH2

SCLK

V

= 2V, GAIN = +1, UNBUFFERED

= V , GAIN = +1, UNBUFFERED

REF

DD

CH1 1V, CH2 5V, TIME BASE = 1μs/DIV

2.0

2.5

3.0

3.5

4.0

4.5

5.0

SUPPLY VOLTAGE (V)

Figure 16. Supply Current vs. Supply Voltage

Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T

V

= 25°C

A

T

= 25°C

= 5V

A

DD

= 2V

REF

V

DD

CH1

CH2

V

A

OUT

CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV

2.0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

DD

Figure 17. Power-Down Current vs. Supply Voltage

Figure 20. Power-On Reset to 0 V

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

T

V

= 25°C

DECREASING

A

T

V

= 25°C

A

= 5V

DD

= 5V

DD

= 2V

REF

INCREASING

V

A

OUT

CH1

CH2

PD

V

= 3V

DD

CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV

0

0.5

1.0

1.5

2.0

2.5

3.0

(V)

3.5

4.0

4.5

5.0

V

LOGIC

Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing

and Decreasing

Figure 21. Exiting Power-Down to Midscale

Rev. F | Page 11 of 28

AD5308/AD5318/AD5328

35

0.02

0.01

0

SS = 300

T

V

= 25°C

= 5V

A

V

= 3V

= 5V

DD

30

25

20

15

10

5

MEAN: 0.693798

MEAN: 1.02055

–0.01

–0.02

0

0.6

0.7

0.8

0.9

(mA)

1.0

1.1

0

1

2

3

4

5

6

I

DD

V

(V)

REF

Figure 22. I_DDHistogram with V_DD= 3 V and V_DD= 5 V

Figure 25. Full-Scale Error vs. V_REF

2.50

2.49

2.48

2.47

100ns/DIV

1μs/DIV

Figure 26. DAC-to-DAC Crosstalk

Figure 23. AD5328 Major-Code Transition Glitch Energy

10

0

–10

–20

–30

–40

–50

–60

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)

Rev. F | Page 12 of 28

AD5308/AD5318/AD5328

TERMINOLOGY

Relative Accuracy

Major-Code Transition Glitch Energy

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSB, from a straight

line passing through the endpoints of the DAC transfer func-

tion. Typical INL vs. code plots can be seen in Figure 4, Figure 5,

and Figure 6.

Major-code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC

register changes state. It is normally specified as the area of the

glitch in nV-sec and is measured when the digital code is

changed by 1 LSB at the major carry transition (011 ... 11 to

100 ... 00 or 100 ... 00 to 011 ... 11).

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. Typical DNL vs. code plots can be seen

in Figure 7, Figure 8, and Figure 9.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

SYNC

(

held high). It is specified in nV-sec and is measured

with a full-scale change on the digital input pins, that is, from

all 0s to all 1s and vice versa.

Offset Error

This is a measure of the offset error of the DAC and the output

amplifier (see Figure 27 and Figure 28). It can be negative or

positive, and is expressed in millivolts.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC

at midscale in response to a full-scale code change (all 0s to all

1s and vice versa) in the input register of another DAC. It is

measured in standalone mode and is expressed in nV-sec.

Gain Error

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the actual DAC transfer characteristic from the

ideal expressed as a percentage of the full-scale range.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a change in the output of another DAC. It is measured by

loading one of the input registers with a full-scale code change

Offset Error Drift

This is a measure of the change in offset error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

LDAC

(all 0s to all 1s and vice versa) while keeping

high. Then

LDAC

pulse

low and monitor the output of the DAC whose digital

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

code is not changed. The area of the glitch is expressed in nV-sec.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent output change of

another DAC. This includes both digital and analog crosstalk.

It is measured by loading one of the DACs with a full-scale code

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in decibels. V_REFis held at 2 V and V_DDis varied 10ꢀ.

LDAC

change (all 0s to all 1s and vice versa) with

low and

monitoring the output of another DAC. The energy of the glitch

is expressed in nV-sec.

DC Crosstalk

This is the dc change in the output level of one DAC in response

to a change in the output of another DAC. It is measured with a

full-scale output change on one DAC while monitoring another

DAC. It is expressed in microvolts.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC out-

put to the reference input when the DAC output is not being

Total Harmonic Distortion (THD)

LDAC

updated (that is,

is high). It is expressed in decibels.

This is the difference between an ideal sine wave and its atten-

uated version using the DAC. The sine wave is used as the refer-

ence for the DAC and the THD is a measure of the harmonics

present on the DAC output. It is measured in decibels.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of

one DAC to a sine wave on the reference input of another DAC.

It is measured in decibels.

Rev. F | Page 13 of 28

AD5308/AD5318/AD5328

GAIN ERROR

PLUS

OFFSET ERROR

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

UPPER

DEADBAND

CODES

OUTPUT

VOLTAGE

ACTUAL

IDEAL

NEGATIVE

OFFSET

ERROR

DAC CODE

POSITIVE

OFFSET

ERROR

ACTUAL

IDEAL

FULL SCALE

DAC CODE

Figure 28. Transfer Function with Positive Offset

LOWER

DEADBAND

CODES

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

Figure 27. Transfer Function with Negative Offset (V_REF= V_DD

)

Rev. F | Page 14 of 28

AD5308/AD5318/AD5328

THEORY OF OPERATION

If there is a buffered reference in the circuit (for example, the

REF192), there is no need to use the on-chip buffers of the

AD5308/AD5318/AD5328. In unbuffered mode, the input

impedance is still large at typically 45 kΩ per reference input

for 0 V to V_REFmode and 22 kΩ for 0 V to 2 V_REFmode.

The AD5308/AD5318/AD5328 are octal resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and

12 bits, respectively. Each contains eight output buffer ampli-

fiers and is written to via a 3-wire serial interface. They operate

from single supplies of 2.5 V to 5.5 V and the output buffer

amplifiers provide rail-to-rail output swing with a slew rate of

0.7 V/ꢁs. DAC A, DAC B, DAC C, and DAC D share a common

reference input, V_REFABCD. DAC E, DAC F, DAC G, and DAC H

share a common reference input, V_REFEFGH. Each reference

input can be buffered to draw virtually no current from the

reference source, can be unbuffered to give a reference input

range from 0.25 V to V_DD, or can come from V_DD. The devices

have a power-down mode in which all DACs can be turned off

individually with a high impedance output.

RESISTOR STRING

The resistor-string section is shown in Figure 30. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

R

DIGITAꢀ-TO-ANAꢀOG CONVERTER

The architecture of one DAC channel consists of a resistor

string DAC followed by an output buffer amplifier. The voltage

at the V_REFpin provides the reference voltage for the corre-

sponding DAC. Figure 29 shows a block diagram of the DAC

architecture. Since the input coding to the DAC is straight

binary, the ideal output voltage is given by

TO OUTPUT

AMPLIFIER

R

V_REF× D

V_OUT

where:

=

2^N

Figure 30. Resistor String

D is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 255 for AD5308 (8 bits)

0 to 1023 for AD5318 (10 bits)

0 to 4095 for AD5328 (12 bits)

N is the DAC resolution.

OUTPUT AMPꢀIFIER

The output buffer amplifier is capable of generating output

voltages to within 1 mV of either rail. Its actual range depends

on the value of V_REF, the gain of the output amplifier, the offset

error, and the gain error.

V

ABCD

REF

V

DD

If a gain of 1 is selected (gain bit = 0), the output range is

REFERENCE

BUFFER

0.001 V to V_REF

.

GAIN MODE

V

BUF

DD

(GAIN = +1 OR +2)

If a gain of 2 is selected (gain bit = 1), the output range is

0.001 V to 2 V_REF. Because of clamping, however, the maximum

output is limited to V_DD− 0.001 V.

DAC

REGISTER

INPUT

REGISTER

RESISTOR

STRING

V

A

OUT

The output amplifier is capable of driving a load of 2 kΩ to

GND or V_DD, in parallel with 500 pF to GND or V_DD. The

source and sink capabilities of the output amplifier can be seen

in the plot in Figure 14.

OUTPUT

BUFFER AMPLIFIER

Figure 29. Single DAC Channel Architecture

DAC Reference Inputs

The slew rate is 0.7 V/μs with a half-scale settling time to

0.5 LSB (at 8 bits) of 6 μs.

There is a reference pin for each quad of DACs. The reference

inputs can be buffered from V_DD, or unbuffered. The advantage

with the buffered input is the high impedance it presents to the

voltage source driving it. However, if the unbuffered mode is

used, the user can have a reference voltage as low as 0.25 V and

as high as V_DDsince there is no restriction due to the headroom

and footroom of the reference amplifier.

Rev. F | Page 15 of 28

AD5308/AD5318/AD5328

POWER-ON RESET

SERIAꢀ INTERFACE

The AD5308/AD5318/AD5328 are provided with a power-on

reset function so that they power up in a defined state. The

power-on state is

The AD5308/AD5318/AD5328 are controlled over a versatile

3-wire serial interface that operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

•

Normal operation

Input Shift Register

Reference inputs unbuffered

0 V to V_REFoutput range

Output voltage set to 0 V

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. The timing diagram for this operation is shown in Figure 2.

LDAC

SYNC

input is a level-triggered input that acts as a frame

bits set to

high

The

synchronization signal and chip enable. Data can be transferred

SYNC

Both input and DAC registers are filled with 0s and remain so

until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

into the device only while

is low. To start the serial data

SYNC

transfer,

SYNC

should be taken low, observing the minimum

SYNC

to SCLK falling edge set-up time, t₄. After

goes

low, serial data is shifted into the device’s input shift register on

the falling edges of SCLK for 16 clock pulses.

POWER-DOWN MODE

The AD5308/AD5318/AD5328 have low power consumption,

typically dissipating 2.4 mW with a 3 V supply and 5 mW with

a 5 V supply. Power consumption can be further reduced when

the DACs are not in use by putting them into power-down

mode, which is described in the Serial Interface section.

SYNC

To end the transfer,

edge of the 16th SCLK pulse, observing the minimum SCLK

SYNC

must be taken high after the falling

falling edge to

rising edge time, t₇.

After the end of the serial data transfer, data is automatically

transferred from the input shift register to the input register of

When in default mode, all DACs work normally with a typical

power consumption of 1 mA at 5 V (800 μA at 3 V). However,

when all DACs are powered down, that is, in power-down

mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V).

Not only does the supply current drop, but the output stage is

also internally switched from the output of the amplifier,

making it open-circuit. This has the advantage that the output is

three-state while the part is in power-down mode, and provides

a defined input condition for whatever is connected to the

output of the DAC amplifier. The output stage is illustrated in

Figure 31.

SYNC

the selected DAC. If

is taken high before the 16th falling

edge of SCLK, the data transfer is aborted and the DAC input

registers are not updated.

Data is loaded MSB first (Bit 15). The first bit determines

whether it is a DAC write or a control function.

DAC Write

The 16-bit word consists of 1 control bit and 3 address bits fol-

lowed by 8, 10, or 12 bits of DAC data, depending on the device

type. In the case of a DAC write, the MSB is a 0. The next 3

address bits determine whether the data is for DAC A, DAC B,

DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The

AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits

and ignores the 2 LSBs. The AD5308 uses 8 bits and ignores the

last 4 bits. These ignored LSBs should be set to 0. The data

format is straight binary, with all 0s corresponding to 0 V

output and all 1s corresponding to full-scale output.

The bias generator, the output amplifiers, the resistor string, and

all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. In fact, it is

possible to load new data to the input registers and DAC regis-

ters during power-down. The DAC outputs update as soon as

the device comes out of power-down mode. The time to exit

power-down is typically 2.5 μs when V_DD= 5 V and 5 μs when

Table 6. Address Bits for the AD5308/AD5318/AD5328

V_DD= 3 V.

A2 (Bit 14)

A1 (Bit 13)

A0 (Bit 12)

DAC Addressed

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

AMPLIFIER

RESISTOR-

STRING DAC

V

OUT

POWER-DOWN

CIRCUITRY

Figure 31. Output Stage During Power-Down

Rev. F | Page 16 of 28

AD5308/AD5318/AD5328

Control Functions

BUF

In the case of a control function, the MSB (Bit 15) is a 1. This is

followed by two control bits, which determine the mode. There

This controls whether the reference of a group of DACs is

buffered or unbuffered. The reference of the first group of DACs

(A, B, C, and D) is controlled by setting Bit 2, and the second

group of DACs (E, F, G, and H) is controlled by setting Bit 3.

LDAC

are four different control modes: reference and gain mode,

mode, power-down mode, and reset mode. The write sequences

for these modes are shown in Table 7.

0: unbuffered reference.

1: buffered reference.

Reference and Gain Mode

This mode determines whether the reference for each group of

DACs is buffered, unbuffered, or from V_DD. It also determines

the gain of the output amplifier. To set up the reference of both

groups, set the control bits to (00), set the GAIN bits, the BUF

bits, and the V_DDbits.

GAIN

The gain of the DACs is controlled by setting Bit 4 for the first

group of DACs (A, B, C, and D) and Bit 5 for the second group

of DACs (E, F, G, and H).

0: output range of 0 V to V_REF

.

1: output range of 0 V to 2 V_REF

.

Table 7. Control Words for the AD53x8

D/C

Control Bits

14

15

13 12 11 10

9

x

8

x

7

x

6

x

5

4

3

2

1

0

Mode

Gain of output amplifier and

GAIN Bits

BUF Bits

V_DDBits

1

0

1

0

x

E...H A...D E...H A...D E...H A...D reference selection

LDAC Bits

1

x

F

x

E

x

C

x

1/0

LDAC

Channels

D

0

Reset

1

x

H

x

G

x

B

A

Power-down

Reset

1/0

x

BIT 15

(MSB)

BIT 0

(LSB)

LDAC

Mode

D/C A2 A1

A0 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

0

LDAC

, which determines when data is

mode controls

transferred from the input registers to the DAC registers. There

are three options when updating the DAC registers, as shown in

Table 8.

Figure 32. AD5308 Input Shift Register Contents

BIT 15

(MSB)

BIT 0

(LSB)

D/C A2 A1

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

LDAC

Table 8.

Mode

DATA BITS

Bits 12:2

x ... x

Bit 15

Bit 14

Bit 13

Bit 1

0

Bit 0

0

Description

LDAC low

LDAC high

Figure 33. AD5318 Input Shift Register Contents

1

0

1

x ... x

0

1

BIT 15

(MSB)

BIT 0

(LSB)

x ... x

1

0

LDAC single

update

Reserved

D/C A2 A1

A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

1

0

1

x ... x

1

Figure 34. AD5328 Input Shift Register Contents

LDAC

Low (00): This option sets

permanently low,

V_DD

allowing the DAC registers to be updated continuously.

These bits are set when V_DDis to be used as a reference. The

first group of DACs (A, B, C, and D) can be set up to use V_DDby

setting Bit 0, and the second group of DACs (E, F, G, and H) by

setting Bit 1. The V_DDbits have priority over the BUF bits.

LDAC LDAC

High (01): This option sets

permanently high.

The DAC registers are latched and the input registers can

change without affecting the contents of the DAC registers.

This is the default option for this mode.

When V_DDis used as the reference, it is always unbuffered and

has an output range of 0 V to V_REFregardless of the state of the

GAIN and BUF bits.

LDAC

Single Update (10): This option causes a single pulse on

, updating the DAC registers once.

Reserved (11): reserved.

Rev. F | Page 17 of 28

AD5308/AD5318/AD5328

LDAC

function enables double-buffering of the DAC

Power-Down Mode

Use of the

data, and the GAIN, BUF and V_DDbits. There are two ways in

LDAC

The individual channels of the AD5308/AD5318/AD5328 can

be powered down separately. The control mode for this is (10).

On completion of this write sequence, the channels that have

been set to 1 are powered down.

which the

Synchronous

data is read in on the falling edge of the 16th SCLK pulse.

function can operate:

LDAC

: The DAC registers are updated after new

LDAC

can be permanently low or pulsed as in Figure 2.

Reset Mode

LDAC

Asynchronous

: The outputs are not updated at the same

LDAC

This mode consists of two possible reset functions, as outlined

in Table 9.

time that the input registers are written to. When

goes

low, the DAC registers are updated with the contents of the

input register.

Table 9. Reset Mode

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ... 0

Description

DOUBꢀE-BUFFERED INTERFACE

1

0

1

x ... x

DAC data reset

Data and control reset

The AD5308/AD5318/AD5328 DACs all have double-buffered

interfaces consisting of two banks of registers: input and DAC.

The input registers are connected directly to the input shift

register and the digital code is transferred to the relevant input

register on completion of a valid write sequence. The DAC

registers contain the digital code used by the resistor strings.

DAC Data Reset: On completion of this write sequence, all

DAC registers and input registers are filled with 0s.

Data and Control Reset: This function carries out a DAC data

reset and resets all the control bits (GAIN, BUF, V_DD,

power-down channels) to their power-on conditions.

LDAC

, and

LDAC

bits are set to (01),

When the

pin is high and the

ꢀOW POWER SERIAꢀ INTERFACE

the DAC registers are latched and the input registers can change

state without affecting the contents of the DAC registers. How-

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, that is,

on the falling edge of

LDAC

ever, when the

bits are set to (00) or when the

SYNC

. The SCLK and DIN input buffers

SYNC

is brought low, the DAC registers become transparent and the

contents of the input registers are transferred to them.

are powered down on the rising edge of

.

The double-buffered interface is useful if the user requires

simultaneous updating of all DAC outputs. The user can write

up to seven of the input registers individually and then, by

ꢀOAD DAC INPUT (ꢀDAC) FUNCTION

LDAC

Access to the DAC registers is controlled by both the

LDAC

function

LDAC

and the

mode bits. The operation of the

LDAC

bringing

low when writing to the remaining DAC input

can be likened to the configuration shown in Figure 35.

register, all outputs will update simultaneously.

EXTERNAL LDAC PIN

LDAC FUNCTION

These parts contain an extra feature whereby a DAC register is

not updated unless its input register has been updated since the

INTERNAL LDAC MODE

LDAC

last time

was low. Normally, when

is brought low,

LDAC

Figure 35.

Function

the DAC registers are filled with the contents of the input regis-

ters. In the case of the AD5308/AD5318/AD5328, the part

updates the DAC register only if the input register has been

changed since the last time the DAC register was updated,

thereby removing unnecessary digital crosstalk.

If the user wishes to update the DAC through software, the

LDAC LDAC

pin should be tied high and the

required. Alternatively, if the user wishes to control the DAC

LDAC LDAC

mode bits

mode bits set as

through hardware, that is, the

pin, the

high (default mode).

LDAC

should be set to

Rev. F | Page 18 of 28

AD5308/AD5318/AD5328

MICROPROCESSOR INTERFACE

ADSP-2101/ADSP-2103-to-

68HC11/68L11

AD5308/

AD5318/

AD5328*

AD5308/AD5318/AD5328 INTERFACE

Figure 36 shows a serial interface between the AD5308/AD5318/

AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT transmit

alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is

programmed through the SPORT control register and should be

configured as follows: internal clock operation, active low framing,

and 16-bit word length. Transmission is initiated by writing a word

to the Tx register after the SPORT has been enabled. The data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5308/AD5318/ AD5328 on the falling edge

of the DAC’s SCLK.

PC7

SYNC

SCLK

DIN

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface

80C51/80ꢀ51-to-AD5308/AD5318/AD5328

INTERFACE

Figure 38 shows a serial interface between the AD5308/AD5318/

AD5328 and the 80C51/80L51 microcontroller. The setup for

the interface is as follows: TxD of the 80C51/80L51 drives SCLK

of the AD5308/AD5318/AD5328, while RxD drives the serial data

ADSP-2101/

ADSP-2103*

AD5308/

AD5318/

AD5328*

SYNC

line of the part. The

signal is again derived from a bit

programmable pin on the port. In this case, port line P3.3 is used.

When data is transmitted to the AD5308/AD5318/AD5328, P3.3

is taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus, only eight falling clock edges occur in the transmit cycle. To

load data to the DAC, P3.3 is left low after the first eight bits are

transmitted, and a second write cycle is initiated to transmit the

second byte of data. P3.3 is taken high following the completion

of this cycle. The 80C51/80L51 outputs the serial data in a format

that has the LSB first. The AD5308/AD5318/AD5328 requires

its data with the MSB as the first bit received. The 80C51/80L51

transmit routine should take this into account.

TFS

DT

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface

68HC11/68ꢀ11-to-AD5308/AD5318/AD5328

INTERFACE

Figure 37 shows a serial interface between the AD5308/AD5318/

AD5328 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328,

and the MOSI output drives the serial data line (DIN) of the DAC.

The sync signal is derived from a port line (PC7). The set up

conditions for the correct operation of this interface are as follows:

the 68HC11/68L11 should be configured so that its CPOL bit is a

0 and its CPHA bit is a 1. When data is being transmitted to the

DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11

is configured as just described, data appearing on the MOSI output

is valid on the falling edge of SCK. Serial data from the 68HC11/

68L11 is transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. Data is transmitted MSB

first. To load data to the AD5308/AD5318/AD5328, PC7 is left

low after the first eight bits are transferred, and a second serial

write operation is performed to the DAC. PC7 is taken high at

the end of this procedure.

80C51/80L51*

AD5308/

AD5318/

AD5328*

P3.3

SYNC

SCLK

DIN

TxD

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface

Rev. F | Page 19 of 28

AD5308/AD5318/AD5328

MICROWIRE-to-AD5308/AD5318/AD5328

INTERFACE

MICROWIRE*

AD5308/

AD5318/

AD5328*

Figure 39 shows an interface between the AD5308/AD5318/

AD5328 and any MICROWIRE-compatible device. Serial data

is shifted out on the falling edge of the serial clock, SK, and is

clocked into the AD5308/AD5318/AD5328 on the rising edge

of SK, which corresponds to the falling edge of the DAC’s SCLK.

CS

SK

SO

SYNC

SCLK

DIN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. MICROWIRE-to-AD5308/AD5318/AD5328 Interface

Rev. F | Page 20 of 28

AD5308/AD5318/AD5328

APPLICATIONS INFORMATION

TYPICAꢀ APPꢀICATION CIRCUIT

output is achievable using an AD820, the AD8519, or an OP196

as the output amplifier.

The AD5308/AD5318/AD5328 can be used with a wide range

of reference voltages where the devices offer full, one-quadrant

multiplying capability over a reference range of 0.25 V to V_DD.

More typically, these devices are used with a fixed, precision

reference voltage. Suitable references for 5 V operation are the

AD780, ADR381, and REF192 (2.5 V references). For 2.5 V

operation, a suitable external reference is the AD589 or the

AD1580 (1.2 V band gap references). Figure 40 shows a typical

setup for the AD5308/AD5318/AD5328 when using an external

reference.

R2

10kΩ

+5V

R1

10kΩ

+6V TO +16V

10μF

0.1μF

±5V

V

DD

AD820/

AD8519/

OP196

V

A

OUT

AD5308/

AD5318/

AD5328

V

IN

–5V

REF192

V

OUT

V

ABCD

REF

V

B

C

OUT

1μF

GND

B

REF

V

= 2.5V TO 5.5V

DD

V

H

GND

OUT

10μF

0.1μF

1μF

DIN SCLK SYNC

V

A

B

OUT

V

IN

V

SERIAL

INTERFACE

V

ABCD

REF

OUT

EFGH

REF

Figure 41. Bipolar Operation with the AD5308/AD5318/AD5328

EXT

REF

AD5308/AD5318/

AD5328

The output voltage for any input code can be calculated as

follows:

AD780/ADR3811/REF192

SCL

WITH V = 5V OR

DD

AD589/AD1580 WITH

DIN

V

G

H

OUT

N

V

= 2.5V

DD

⎡

⎢

(

)

(

)

⎤

⎥

SYNC

REFIN × D /2 × R1+ R2

V_OUT

=

− REFIN ×

(

R2/ R1

)

GND

R1

⎢

⎥

⎣

⎦

SERIAL

INTERFACE

where:

Figure 40. AD5308/AD5318/AD5328 Using a 2.5 V or 5 V External Reference

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

DRIVING V_DDFROM THE REFERENCE VOꢀTAGE

If an output range of 0 V to V_DDis required when the reference

inputs are configured as unbuffered, the simplest solution is to

connect the reference input to V_DD. As this supply can be noisy

and not very accurate, the AD5308/AD5318/AD5328 can be

powered from a voltage reference. For example, using a 5 V

reference, such as the REF195, works because the REF195

outputs a steady supply voltage for the AD5308/AD5318/

AD5328. The typical current required from the REF195 is a

1 μA supply current and ≈ 112 μA into the reference inputs (if

unbuffered); this is with no load on the DAC outputs. When the

DAC outputs are loaded, the REF195 also needs to supply the

current to the loads. The total current required (with a10 kΩ

load on each output) is

with

REFIN = 5 V , R1 = R2 = 10 kΩ

N

(

)

V_OUT= 10 × D/2 − 5 V

OPTO-ISOꢀATED INTERFACE FOR PROCESS

CONTROꢀ APPꢀICATIONS

The AD5308/AD5318/AD5328 have a versatile 3-wire serial

interface, making them ideal for generating accurate voltages in

process control and industrial applications. Due to noise and

safety requirements, or distance, it may be necessary to isolate

the AD5308/AD5318/AD5328 from the controller. This can

easily be achieved by using opto-isolators that provide isolation

in excess of 3 kV. The actual data rate achieved may be limited

by the type of optocouplers chosen. The serial loading structure

of the AD5308/AD5318/AD5328 makes them ideally suited for

use in opto-isolated applications. Figure 42 shows an opto-

isolated interface to the AD5308/AD5318/AD5328 where DIN,

1.22 mA + 8(5 V/10 kΩ) = 5.22 mA

The load regulation of the REF195 is typically 2.0 ppm/mA,

which results in an error of 10.4 ppm (52 μV) for the 5.22 mA

current drawn from it. This corresponds to a 0.003 LSB error at

8 bits and 0.043 LSB error at 12 bits.

SYNC

SCLK, and

are driven from optocouplers. The power

BIPOꢀAR OPERATION USING THE

AD5308/AD5318/AD5328

supply to the part also needs to be isolated. This is done by

using a transformer. On the DAC side of the transformer, a 5 V

regulator provides the 5 V supply required for the AD5308/

AD5318/AD5328.

The AD5308/AD5318/AD5328 have been designed for single-

supply operation, but a bipolar output range is also possible

using the circuit in Figure 41. This circuit gives an output

voltage range of 5 V. Rail-to-rail operation at the amplifier

Rev. F | Page 21 of 28

AD5308/AD5318/AD5328

5V

V

A

B

OUT

REGULATOR

POWER

10μF

0.1μF

SCLK

DIN

SYNC

DIN

AD5308

V

DD

SCLK

10kΩ

V

DD

V

G

H

OUT

SCLK

V

ABCD

EFGH

SCLK

V

REF

DD

V

REF

V

CC

V

A

B

OUT

AD5308/AD5318/

AD5328

ENABLE

1G

1A

1B

1Y0

1Y1

1Y2

1Y3

V

DD

74HC139

DGND

SYNC

DIN

CODED

ADDRESS

AD5308

V

A

10kΩ

OUT

B

C

D

E

F

SYNC

SCLK

V

G

H

OUT

V

A

B

V

OUT

DD

G

H

10kΩ

SYNC

DIN

AD5308

GND

SCLK

V

G

H

OUT

Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface

V

A

B

OUT

DECODING MUꢀTIPꢀE AD5308/AD5318/AD5328s

SYNC

DIN

SYNC

The

pin on the AD5308/AD5318/AD5328 can be used in

AD5308

applications to decode a number of DACs. In this application,

the DACs in the system receive the same serial clock and serial

SCLK

V

G

H

OUT

SYNC

data but only the

to one of the devices is active at any one

Figure 43. Decoding Multiple AD5308 Devices in a System

time, allowing access to four channels in this 16-channel sys-

tem. The 74HC139 is used as a 2-to-4 line decoder to address

any of the DACs in the system. To prevent timing errors from

occurring, the enable input should be brought to its inactive

state while the coded-address inputs are changing state.

Figure 43 shows a diagram of a typical setup for decoding

multiple AD5308 devices in a system.

Rev. F | Page 22 of 28

AD5308/AD5318/AD5328

Table 10. Overview of AD53xx Serial Devices

Part No.

SINGꢀES

AD5300

AD5310

AD5320

AD5301

AD5311

AD5321

DUAꢀS

AD5302

AD5312

AD5322

AD5303

AD5313

AD5323

QUADS

AD5304

AD5314

AD5324

AD5305

AD5315

AD5325

AD5306

AD5316

AD5326

AD5307

AD5317

AD5327

OCTAꢀS

AD5308

AD5318

AD5328

Resolution

DNꢀ

V_REFPins

Settling Time (μs)

Interface

Package

Pins

8

0.25

0 (V_REF= V_DD)

4

6

8

6

7

8

SPI

2-Wire

SOT-23, MSOP

6, 8

10

12

8

10

12

0.50

1.00

0.25

0.50

1.00

8

0.25

0.50

1.00

0.25

0.50

1.00

2

6

7

8

6

7

8

SPI

MSOP

TSSOP

10

16

10

12

8

10

12

8

0.25

0.50

1.00

0.25

0.50

1.00

0.25

0.50

1.00

0.25

0.50

1.00

1

4

2

6

7

8

6

7

8

6

7

8

6

7

8

SPI

2-Wire

SPI

MSOP

TSSOP

10

16

10

12

8

10

12

8

10

12

8

10

12

SPI

8

10

12

0.25

0.50

1.00

2

6

7

8

SPI

TSSOP

16

Table 11. Overview of AD53xx Parallel Devices

Part No. Resolution DNꢀ

V_REFPins Settling Time (μs) Additional Pin Functions

Package Pins

SINGꢀES

BUF

GAIN HBEN CꢀR

AD5330

AD5331

AD5340

AD5341

8

0.25

0.50

1.00

1

6

7

8

TSSOP

20

24

20

✓

10

12

✓

DUAꢀS

AD5332

AD5333

AD5342

AD5343

8

0.25

0.50

1.00

2

1

6

7

8

TSSOP

20

24

28

20

✓

10

12

✓

QUADS

AD5334

AD5335

AD5336

AD5344

8

0.25

0.50

1.00

2

4

6

7

8

TSSOP

24

28

✓

10

12

Rev. F | Page 23 of 28

AD5308/AD5318/AD5328

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

2

Model^1,

Temperature Range

−40°C to +125°C

Package Description

Package Option

RU-16

AD5308ARU

16-Lead Thin Shrink Small Outline Package (TSSOP)

AD5308ARU-REEL7

AD5308ARUZ

AD5308ARUZ-REEL7

AD5308BRU

AD5308BRU-REEL

AD5308BRU-REEL7

AD5308BRUZ

AD5308BRUZ-REEL

AD5308BRUZ-REEL7

AD5318ARU

AD5318ARU-REEL7

AD5318ARUZ

AD5318ARUZ-REEL7

AD5318BRU

AD5318BRU-REEL

AD5318BRU-REEL7

AD5318BRUZ

AD5318BRUZ-REEL

AD5318BRUZ-REEL7

AD5328ARU

AD5328ARU-REEL7

AD5328ARUZ

AD5328ARUZ-REEL7

AD5328BRU

AD5328BRU-REEL

AD5328BRU-REEL7

AD5328BRUZ

AD5328BRUZ-REEL

AD5328BRUZ-REEL7

AD5308WARUZ-REEL7

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

Rev. F | Page 24 of 28

AD5308/AD5318/AD5328

AUTOMOTIVE PRODUCTS

The AD5308WARUZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirement s of

automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for

use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information

and to obtain the specific Automotive Reliability report for this model.

Rev. F | Page 25 of 28

AD5308/AD5318/AD5328

NOTES

Rev. F | Page 26 of 28

AD5308/AD5318/AD5328

NOTES

Rev. F | Page 27 of 28

AD5308/AD5318/AD5328

NOTES

registered trademarks are the property of their respective owners.

D02812-0-4/11(F)

Rev. F | Page 28 of 28


型号：	AD5318ARUZ-REEL7
厂家：	ADI
描述：	2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP 2.5 V至5.5 V八通道电压输出8位/ 10位/ 12位DAC，采用16引脚TSSOP 转换器数模转换器光电二极管
文件：	总28页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5318ARUZ-REEL7 [ADI]

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AD5318BRU-REEL

AD5318BRU-REEL7

AD5318BRUZ

AD5318BRUZ

AD5318BRUZ-REEL

AD5318BRUZ-REEL7

AD532

AD5320

AD5320*

AD5320BRM

AD5320BRM-REEL