AD5337BRMZ-REEL7 [ADI]
2.5 V to 5.5 V, 250 muA, 2-Wire Interface; 2.5 V至5.5 V ， 250 MUA ， 2线接口
| 型号： | AD5337BRMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.5 V to 5.5 V, 250 muA, 2-Wire Interface |
| 文件： | 总28页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
AD5337/AD5338/AD5339
GENERAL DESCRIPTION
FEATURES
AD5337
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at VDD < 3.6 V. Multiple devices
can be placed on the same bus.
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2-wire (I2C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
LDAC
using the software
function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
V
DD
REFIN
LDAC
INPUT
DAC
STRING
DAC A
SCL
SDA
V
V
A
B
BUFFER
BUFFER
OUT
OUT
REGISTER
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
A0
POWER-DOWN
LOGIC
POWER-ON
RESET
AD5337/AD5338/AD5339
GND
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD5337/AD5338/AD5339
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 15
Power-on Reset........................................................................... 15
Serial Interface............................................................................ 16
Write Operation.......................................................................... 17
Read Operation........................................................................... 18
Double-Buffered Interface ........................................................ 19
Power-Down Modes .................................................................. 19
Applications..................................................................................... 20
Typical Application Circuit....................................................... 20
Bipolar Operation....................................................................... 20
Multiple Devices on One Bus ................................................... 20
Product as a Digitally Programmable Window Detector ..... 21
Coarse and Fine Adjustment Capabilities............................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
Digital-to-Analog Converter Section ...................................... 15
Resistor String............................................................................. 15
DAC Reference Inputs ............................................................... 15
REVISION HISTORY
9/07—Rev. B to Rev. C
10/04—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Table 4............................................................................ 7
Changes to Ordering Guide .......................................................... 25
Updated Format..................................................................Universal
Added AD5338-1................................................................Universal
Changes to Specifications.................................................................4
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 31...................................................................... 16
Changes to Table 6.......................................................................... 16
Changes to Table 10........................................................................ 23
Changes to Ordering Guide .......................................................... 25
11/03—Rev. 0: Initial Version
Rev. C | Page 2 of 28
AD5337/AD5338/AD5339
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade1
Typ
B Grade1
Typ
Parameter2
DC PERFORMANCE3, 4
Min
Max
Min
Max
Unit
Conditions/Comments
AD5337
Resolution
Relative Accuracy
Differential Nonlinearity
8
8
Bits
LSB
LSB
±±.ꢀ5
±±.±2
±ꢀ
±±.25
±±.ꢀ5
±±.±2
±±.5
±±.25
Guaranteed monotonic by
design over all codes
AD5338
Resolution
Relative Accuracy
Differential Nonlinearity
ꢀ±
±±.5
±±.±5
ꢀ±
±±.5
±±.±5
Bits
LSB
LSB
±4
±±.5
±2
±±.5±
Guaranteed monotonic by
design over all codes
AD5339
Resolution
Relative Accuracy
Differential Nonlinearity
ꢀ2
±2
±±.2
ꢀ2
±2
±±.2
Bits
LSB
LSB
±ꢀ1
±ꢀ
±8
±ꢀ
Guaranteed monotonic by
design over all codes
Offset Error
Gain Error
Lower Deadband
±±.4
±±.ꢀ5
2±
±3
±ꢀ
1±
±±.4
±±.ꢀ5
2±
±3
±ꢀ
1±
% of FSR
% of FSR
mV
Lower deadband exists
only if offset error is
negative
Offset Error Drift5
Gain Error Drift5
−ꢀ2
−5
−ꢀ2
−5
ppm of
FSR/°C
ppm of
FSR/°C
Power Supply Rejection Ratio5
DC Crosstalk5
−1±
2±±
−1±
2±±
dB
μV
∆VDD = ±ꢀ±%
RL = 2 kΩ to GND or VDD
DAC REFERENCE INPUTS5
VREF Input Range
VREF Input Impedance
±.25
37
VDD
±.25
37
VDD
V
45
>ꢀ±
−9±
45
>ꢀ±
−9±
kΩ
MΩ
dB
Normal operation
Power-down mode
Frequency = ꢀ± kHz
Reference Feedthrough
OUTPUT CHARACTERISTICS5
Minimum Output Voltage1
±.±±ꢀ
±.±±ꢀ
V
V
Measure of the minimum
drive capabilities of the
output amplifier
Maximum Output Voltage1
VDD
−
VDD
−
Measure of the maximum
drive capabilities of the
output amplifier
±.±±ꢀ
±.±±ꢀ
DC Output Impedance
Short-Circuit Current
±.5
25
ꢀ1
±.5
25
ꢀ1
Ω
mA
mA
μs
VDD = 5 V
VDD = 3 V
Coming out of power-
down mode, VDD = 5 V
Power-Up Time
2.5
2.5
5
5
μs
Coming out of power-
down mode, VDD = 3 V
Rev. C | Page 3 of 28
AD5337/AD5338/AD5339
A Grade1
Typ
B Grade1
Typ
Parameter2
LOGIC INPUTS (A±)5
Min
Max
Min
Max
Unit
Conditions/Comments
Input Current
Input Low Voltage (VIL)
±ꢀ
±.8
±.1
±.5
±ꢀ
±.8
±.1
±.5
μA
V
V
VDD = 5 V ± ꢀ±%
VDD = 3 V ± ꢀ±%
VDD = 2.5 V
V
Input High Voltage (VIH)
2.4
2.ꢀ
2.±
2.4
2.ꢀ
2.±
V
V
V
VDD = 5 V ± ꢀ±%
VDD = 3 V ± ꢀ±%
VDD = 2.5 V
Pin Capacitance
3
3
pF
LOGIC INPUTS (SCL, SDA)5
Input High Voltage (VIH)
±.7 ×
VDD
−±.3
VDD
±.3
+±.3
VDD
+
±.7 ×
VDD
–±.3
VDD
±.3
+±.3
VDD
+
V
V
SMBus compatible at
VDD < 3.1 V
SMBus compatible at
Input Low Voltage (VIL)
V
DD < 3.1 V
Input Leakage Current (IIN)
±ꢀ
±ꢀ
μA
V
Input Hysteresis (VHYST
)
±.±5 ×
VDD
±.±5 ×
VDD
Input Capacitance (CIN)
Glitch Rejection
8
8
pF
ns
5±
5±
Input filtering suppresses
noise spikes of less than
5± ns
LOGIC OUTPUT (SDA)5
Output Low Voltage (VOL)
±.4
±.1
±ꢀ
±.4
±.1
±ꢀ
V
V
μA
pF
ISINK = 3 mA
ISINK = 1 mA
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)7
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.1 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
8
8
2.5
5.5
2.5
5.5
V
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
IDD = 4 μA (max) during ±
readback on SDA
3±±
25±
375
35±
3±±
25±
375
35±
μA
μA
±.2
ꢀ.±
±.2
ꢀ.±
μA
μA
VDD = 2.5 V to 3.1 V
±.±8
ꢀ.±±
±.±8
ꢀ.±±
IDD = ꢀ.5 μA (max) during ±
readback on SDA
ꢀ Temperature range for A Version and B Version: −4±°C to +ꢀ±5°C; typical at 25°C.
2 See the Terminology section for explanations of the specific parameters.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-ꢀ (Code 28 to Code 995), AD5339 (Code ꢀꢀ5 to Code 398ꢀ).
5 Guaranteed by design and characterization; not production tested.
1 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. C | Page 4 of 28
AD5337/AD5338/AD5339
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Version and B Version1
Parameter2, 3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5337
AD5338
VREF = VDD = 5 V
1
7
8
8
9
ꢀ±
μs
μs
μs
ꢀ/4 scale to 3/4 scale change (±x4± to ±xC±)
ꢀ/4 scale to 3/4 scale change (±xꢀ±± to ±x3±±)
ꢀ/4 scale to 3/4 scale change (±x4±± to ±xC±±)
AD5339
Slew Rate
±.7
ꢀ2
ꢀ
ꢀ
3
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
ꢀ LSB change around major carry
2±±
−7±
VREF = 2 V ± ±.ꢀ V p-p
VREF = 2.5 V ± ±.ꢀ V p-p, frequency = ꢀ± kHz
ꢀ Temperature range for A version and B version: −4±°C to +ꢀ±5°C; typical at 25°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section for explanations of the specific parameters.
Rev. C | Page 5 of 28
AD5337/AD5338/AD5339
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter
A Version and B Version
4±±
2.5
±.1
ꢀ.3
±.1
ꢀ±±
±.9
±
±.1
±.1
ꢀ.3
3±±
±
25±
±
Unit
Conditions/Comments
fSCL
tꢀ
t2
t3
t4
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
t5
t1
ꢀ
tHD, DAT, data hold time
t7
t8
t9
tꢀ±
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
tꢀꢀ
3±±
2± + ±.ꢀ CB
4±±
2
CB
ꢀ A master device must provide a hold time of at least 3±± ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
2 CB is the total capacitance of one bus line in pF; tR and tF measured between ±.3 VDD and ±.7 VDD
.
SDA
t9
t3
t10
t11
t4
SCL
t4
t2
t6
t1
t8
t5
t7
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. C | Page 1 of 28
AD5337/AD5338/AD5339
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
SCL, SDA to GND
A± to GND
−±.3 V to +7 V
−±.3 V to VDD + ±.3 V
−±.3 V to VDD + ±.3 V
Reference Input Voltage to GND −±.3 V to VDD + ±.3 V
Transient currents of up to 100 mA do not cause SCR latch-up.
VOUTA to VOUTB to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
MSOP Package
−±.3 V to VDD + ±.3 V
−4±°C to +ꢀ±5°C
−15°C to +ꢀ5±°C
ꢀ5±°C
ESD CAUTION
Power Dissipation
(TJ max − TA) θJA
2±1°C/W
44°C/W
JEDEC Industry Standard
J-STD-±2±
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
Soldering
Rev. C | Page 7 of 28
AD5337/AD5338/AD5339
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
A0
DD
A
AD5337/
AD5338/
V
V
SCL
SDA
GND
OUT
OUT
AD5339
B
TOP VIEW
(Not to Scale)
REFIN
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
ꢀ
2
3
4
5
1
VDD
VOUT
VOUT
REFIN
GND
SDA
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Reference Input Pin for the Two DACs. It has an input range from ±.25 V to VDD.
Ground Reference Point for All Circuitry on the Parts.
A
B
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the ꢀ1-bit input shift
register. SDA is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
7
8
SCL
A±
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the ꢀ1-bit input shift
register. Clock rates of up to 4±± kbps can be accommodated in the 2-wire interface.
Address Input. Sets the least significant bit of the 7-bit slave address.
Rev. C | Page 8 of 28
AD5337/AD5338/AD5339
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.3
0.2
T
= 25°C
T = 25°C
A
A
V
= 5V
V
= 5V
DD
DD
0.5
0
0.1
0
–0.1
–0.2
–0.3
–0.5
–1.0
0
0
0
50
100
150
200
250
0
0
0
50
100
150
200
250
CODE
CODE
Figure 4. AD5337 Typical INL Plot
Figure 7. AD5337 Typical DNL Plot
3
2
0.6
0.4
T
V
= 25°C
A
T
V
= 25°C
A
= 5V
DD
= 5V
DD
1
0.2
0
0
–1
–2
–3
–0.2
–0.4
–0.6
200
400
600
800
1000
200
400
600
800
1000
CODE
CODE
Figure 5. AD5338 Typical INL Plot
Figure 8. AD5338 Typical DNL Plot
12
8
1.0
0.5
T
= 25°C
T = 25°C
A
A
V
= 5V
V
= 5V
DD
DD
4
0
0
–4
–8
–12
–0.5
–1.0
500
1000
1500
2000
2500
3000
3500
4000
500
1000
1500
2000
2500
3000
3500
4000
CODE
CODE
Figure 6. AD5339 Typical INL Plot
Figure 9. AD5339 Typical DNL Plot
Rev. C | Page 9 of 28
AD5337/AD5338/AD5339
0.2
0.1
0.50
T
V
= 25°C
= 2V
T
V
= 25°C
= 5V
A
A
REF
DD
GAIN ERROR
0
0.25
0
MAX DNL
MIN DNL
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
MAX INL
–0.25
–0.50
MIN INL
OFFSET ERROR
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
120
120
V
(V)
V
DD
REF
Figure 13. Offset Error and Gain Error vs. VDD
Figure 10. AD5337 INL and DNL Error vs. VREF
5
4
3
2
1
0
0.5
0.4
V
V
= 5V
5V SOURCE
DD
= 3V
REF
0.3
0.2
MAX INL
MIN DNL
0.1
3V SOURCE
MAX DNL
0
–0.1
–0.2
–0.3
–0.4
–0.5
MIN INL
5V SINK
3V SINK
4
0
1
2
3
5
6
–40
0
40
TEMPERATURE (°C)
80
SINK/SOURCE CURRENT (mA)
Figure 14. VOUT Source and Sink Current Capability
Figure 11. AD5337 INL and DNL Error vs. Temperature
300
250
200
150
100
50
1.0
0.5
V
V
= 5V
DD
= 2V
REF
OFFSET ERROR
0
GAIN ERROR
–0.5
–1.0
T
V
V
= 25°C
= 5V
= 2V
A
DD
REF
0
ZERO SCALE
FULL SCALE
–40
0
40
TEMPERATURE (°C)
80
CODE
Figure 12. AD5337 Offset Error and Gain Error vs. Temperature
Figure 15. Supply Current vs. Code
Rev. C | Page ꢀ± of 28
AD5337/AD5338/AD5339
300
250
200
150
100
50
T
V
V
= 25°C
A
= 5V
DD
–40°C
= 5V
REF
CH1
+25°C
+105°C
V
A
OUT
SCL
CH2
0
2.5
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
Figure 19. Midscale Settling (¼ to ¾ Scale Code Change)
Figure 16. Supply Current vs. Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
T
V
V
= 25°C
A
= 5V
DD
= 2V
REF
CH1
V
DD
–40°C
+25°C
V
A
OUT
CH2
+105°C
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
Figure 20. Power-On Reset to 0 V
Figure 17. Power-Down Current vs. Supply Voltage
400
350
300
250
200
150
100
50
T
V
V
= 25°C
A
T
= 25°C
A
= 5V
DD
V
= 5V
DD
= 2V
REF
CH1
DECREASING
INCREASING
V
A
OUT
V
= 3V
DD
SCL
CH2
0
CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
LOGIC
Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage
Increasing and Decreasing
Figure 21. Existing Power-Down to Midscale
Rev. C | Page ꢀꢀ of 28
AD5337/AD5338/AD5339
0.02
0.01
0
T
V
= 25°C
A
= 5V
DD
V
= 3V
V
= 5V
DD
DD
–0.01
–0.02
150
200
250
(µA)
300
0
1
2
3
4
5
6
I
DD
V
(V)
REF
Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 25. Full-Scale Error vs. VREF
2.50
2.49
2.48
2.47
50ns/DIV
1µs/DIV
Figure 23. AD5339 Major Code Transition Glitch Energy
Figure 26. DAC-to-DAC Crosstalk
10
0
–10
–20
–30
–40
–50
–60
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)
Rev. C | Page ꢀ2 of 28
AD5337/AD5338/AD5339
TERMINOLOGY
Relative Accuracy (Integral Nonlinearity, INL)
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure, in LSBs, of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 4, Figure 5, and
Figure 6.
Major Code Transition Glitch Energy
The energy of the impulse injected into the analog output when
the code in the DAC register changes state. Normally specified
as the area of the glitch in nV-s, it is measured when the digital
code is changed by 1 LSB at the major carry transition (011...11
to 100...00 or 100...00 to 011...11).
Differential Nonlinearity (DNL)
Digital Feedthrough
The difference between the measured change and the ideal
1 LSB change between any two adjacent codes. A specified
differential nonlinearity of 1 LSB maximum ensures mono-
tonicity. This DAC is guaranteed monotonic by design. Typical
DNL vs. code plots can be seen in Figure 7, Figure 8, and
Figure 9.
A measure of the impulse injected into the analog output of the
DAC from the digital input pins of the device when the DAC
output is not being updated. Specified in nV-s and measured
with a worst-case change on the digital input pins, such as
changing from all 0s to all 1s or vice-versa.
Digital Crosstalk
Offset Error
The glitch impulse transferred to the output of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s,
or vice versa) in the input register of another DAC. It is
expressed in nV-s.
A measure of the offset error of the DAC and the output
amplifier, expressed as a percentage of the full-scale range.
Gain Error
A measure of the span error of the DAC. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range.
DAC-to-DAC Crosstalk
The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s, or vice versa) with the
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-s.
Offset Error Drift
A measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
LDAC
bit set low
Gain Error Drift
A measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied 10ꢀ.
Total Harmonic Distortion (THD)
DC Crosstalk
The difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonic
distortion present in the DAC output. It is measured in dB.
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in μV.
Reference Feedthrough
The ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated.
It is expressed in dB.
Rev. C | Page ꢀ3 of 28
AD5337/AD5338/AD5339
GAIN ERROR
PLUS
OFFSET ERROR
GAIN ERROR
PLUS
OFFSET ERROR
ACTUAL
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
IDEAL
ACTUAL
IDEAL
POSITIVE
OFFSET
NEGATIVE
OFFSET
ERROR
DAC CODE
DAC CODE
Figure 28. Transfer Function with Positive Offset
DEADBAND CODES
AMPLIFIER
FOOTROOM
(1mV)
NEGATIVE
OFFSET
ERROR
Figure 27. Transfer Function with Negative Offset
Rev. C | Page ꢀ4 of 28
AD5337/AD5338/AD5339
THEORY OF OPERATION
The AD5337/AD5338/AD5339 are dual resistor string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each part contains two output buffer
amplifiers and is written to via a 2-wire serial interface. The
DACs operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with
a slew rate of 0.7 V/μs. The two DACs share a single reference
input pin. Each DAC has three programmable power-down
modes that allow the output amplifier to be configured with
either a 1 kΩ load to ground, a 100 kΩ load to ground, or as
a high impedance three-state output.
R
R
R
TO OUTPUT
AMPLIFIER
R
R
DIGITAL-TO-ANALOG CONVERTER SECTION
Figure 30. Resistor String
The architecture of one DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the REFIN pin provides the reference voltage for the DAC.
Figure 29 shows a block diagram of the DAC architecture.
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
DAC REFERENCE INPUTS
There is a single reference input pin for the two DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as VDD, because there is no
restriction due to headroom and foot room of any reference
amplifier.
VREF × D
VOUT
where:
=
2N
It is recommended to use a buffered reference in the external
circuit, for example, REF192. The input impedance is typically
45 kΩ.
D is the decimal equivalent of the binary code, which is loaded
OUTPUT AMPLIFIER
to the DAC register
0 to 255 for AD5337 (8 bits)
0 to 1023 for AD5338 and AD5338-1 (10 bits)
0 to 4095 for AD5339 (12 bits)
N is the DAC resolution.
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to
VDD when the reference is VDD. The amplifier is capable of driving
a load of 2 kΩ to GND or VDD in parallel with 500 pF to GND
or VDD. The source and sink capabilities of the output amplifier
can be seen in the plot in Figure 14.
REFIN
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at 8 bits) of 6 μs.
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
V
A
OUT
POWER-ON RESET
OUTPUT BUFFER
AMPLIFIER
The AD5337/AD5338/AD5339 power on in a defined state via a
power-on reset function. The power-on state is normal operation,
with output voltage set to 0 V.
Figure 29. DAC Channel Architecture
RESISTOR STRING
Both input and DAC registers are filled with zeros until a valid
write sequence is made to the device. This is particularly useful
in applications where it is important to know the state of the
DAC outputs while the device is powering on.
The resistor string portion is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines the node at which the voltage is
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches that connects the
string to the amplifier. Because the DAC comprises a string
of resistors, it is guaranteed to be monotonic.
Rev. C | Page ꢀ5 of 28
AD5337/AD5338/AD5339
Read/Write Sequence
SERIAL INTERFACE
The AD5337/AD5338/AD5339 are controlled via an I2C®-
compatible serial bus. The DACs are connected to this bus as
slave devices, that is, no clock is generated by the AD5337/
AD5338/AD5339 DACs. This interface is SMBus compatible
at VDD < 3.6 V.
For the AD5337/AD5338/AD5339, all write access sequences
and most read sequences begin with the device address (with
W
R/ = 0), followed by the pointer byte. This pointer byte specifies
which DAC is being accessed in the subsequent read/write
operation (see Figure 31). In a write operation, the data follows
immediately. In a read operation, the address is resent with
The AD5337/AD5338/AD5339 have a 7-bit slave address. The
six MSBs are 000110, and the LSB is determined by the state of
the A0 pin. The facility of making hardwired changes to A0
allows the use of one or two of these devices on one bus. The
AD5338-1 has a unique 7-bit slave address. The six MSBs are
010001, and the LSB is determined by the state of the A0 pin.
Using a combination of AD5338 and AD5338-1 allows the user
to accommodate four of these dual 10-bit devices (eight
channels) on the same bus.
W
R/ = 1, and then the data is read back. However, it is also
possible to perform a read operation by sending only the
W
address with R/ = 1. The previously loaded pointer settings
are then used for the readback operation. See Figure 32 for a
graphical explanation of the interface.
MSB
LSB
0
0
DACB DACA
0
0
X
X
Figure 31. Pointer Byte
The 2-wire serial bus protocol operates as follows:
Table 6 explains the individual bits that make up the pointer byte.
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address, followed by
Table 6. Pointer Byte Bits
Pointer Byte Bit
Description
X
Don’t care bits.
±
This bit is reserved and must be set to ±
ꢀ: The following data bytes are for DAC B.
ꢀ: The following data bytes are for DAC A.
W
an R/ bit. (This bit determines whether data is read from
DACB
DACA
or written to the slave device.)
The slave with the address corresponding to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for this
operation is shown in Figure 2. The two data bytes consist of four
control bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. The first two bits loaded are Bit PD1 and
Bit PD0, which control the mode of operation of the device.
See the Power-Down Modes section for a complete description.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits, followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.
CLR
LDAC
Bit 13 is
, Bit 12 is
, and the remaining bits are left-
justified DAC data bits, starting with the MSB (see Figure 32).
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a No
Acknowledge for the ninth clock pulse, that is, the SDA
line remains high. The master then brings the SDA line low
before the 10th clock pulse and high during the 10th clock
pulse to establish a stop condition.
Table 7. Input Shift Register
Register Setting Result
CLR
±
All DAC registers and input registers are
filled with ±s on completion of the write
sequence.
ꢀ
±
Normal operation.
LDAC
The two DAC registers and, therefore, all
DAC outputs, simultaneously updated on
completion of the write sequence.
ꢀ
Addressed input register only is updated.
There is no change in the contents of the
DAC registers.
Rev. C | Page ꢀ1 of 28
AD5337/AD5338/AD5339
Default Readback Condition
Multiple DAC Read Back Sequence
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without writing to the pointer byte first, no
single DAC channel has been specified. In this case, the default
If the user attempts to read back data from more than one DAC
at a time, the part reads back the default, power-on reset
CLR
conditions, that is, all 0s except for
, which is 1.
CLR
readback bits are all 0s, except for the
bit, which is 1.
WRITE OPERATION
Multiple DAC Write Sequence
When writing to the AD5337/AD5338/AD5339 DACs, the user
Because there are individual bits in the pointer byte for each
DAC, it is possible to write the same data and control bits to two
DACs simultaneously by setting the relevant bits to 1.
W
must begin with an address byte (R/ = 0), after which the
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte,
which is also acknowledged by the DAC. Two bytes of data are
then written to the DAC, as shown in Figure 33. A stop
condition follows.
MOST SIGNIFICANT DATA BYTE
8-BIT AD5337
LEAST SIGNIFICANT DATA BYTE
8-BIT AD5337
MSB
PD1
LSB
D4
MSB
LSB
X
PD0
PD0
D7
D6
D5
D7
D9
D3
D2
D4
D6
D1
D3
D5
D0
X
X
X
X
CLR LDAC
10-BIT AD5338
D9
LSB
D6
10-BIT AD5338
D2 D1
LSB
X
MSB
PD1
MSB
D5
D8
D0
D2
LDAC
CLR
CLR
MSB
12-BIT AD5339
D11
LSB
D8
MSB
D7
12-BIT AD5339
LSB
D0
PD1 PD0
D10
D4
D3
D1
LDAC
Figure 32. Data Formats for Write and Read Back
SCL
SDA
R/W
0
0
0
1
1
0
A0
X
X
LSB
ACK
BY
AD533x
MSB
ACK
BY
AD533x
START
CONDITION
BY
ADDRESS BYTE
POINTER BYTE
MASTER
SCL
SDA
MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LEAST SIGNIFICANT DATA BYTE
LSB
ACK
BY
ACK
BY
AD533x
STOP
CONDITION
BY
AD533x
MASTER
Figure 33. Write Sequence
Rev. C | Page ꢀ7 of 28
AD5337/AD5338/AD5339
Note that in a read sequence, data bytes are the same as those in
the write sequence, except that don’t cares are read back as 0s.
However, if the master sends an ACK and continues clocking
SCL (no stop is sent), the DAC retransmits the same two bytes
of data on SDA. This allows continuous read back of data from
the selected DAC register. Alternatively, the user can send a
READ OPERATION
When reading data back from the AD5337/AD5338/AD5339
DACs, the user begins with an address byte (R/ = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Then, the
master initiates another start condition (repeated start) and the
W
W
start followed by the address with R/ = 1. In this case, the
previously loaded pointer settings are used and read back of
data can begin immediately.
W
address is resent with R/ = 1. This is acknowledged by the
DAC indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC as shown in Figure 34. A
stop condition follows.
SCL
LSB
0
0
0
1
1
0
A0
R/W
X
X
SDA
START
ACK
BY
MSB
ACK
BY
AD533x
CONDITION
BY
ADDRESS BYTE
POINTER BYTE
AD533x
MASTER
SCL
SDA
0
0
0
0
1
1
A0
R/W
MSB
LSB
ACK
BY
MASTER
REPEATED
START
ACK
BY
AD533x
DATA BYTE
ADDRESS BYTE
CONDITION
BY
MASTER
SCL
SDA
MSB
LSB
STOP
NO
CONDITION
BY
ACK
BY
LEAST SIGNIFICANT DATA BYTE
MASTER
MASTER
Figure 34. Read Sequence
Rev. C | Page ꢀ8 of 28
AD5337/AD5338/AD5339
When both bits are 0, the DAC works with its normal power
consumption of 300 μA at 5 V. However, for the three power-
down modes, the supply current falls to 200 nA at 5 V (80 nA
at 3 V). Not only does the supply current drop, but the output
stage is also internally switched from the output of the amplifier
to a resistor network of known values. This is advantageous in
that the output impedance of the part is known while the part is
in power-down mode, which provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
There are three options. The output can be connected internally
to GND through a 1 kΩ resistor, a 100 kΩ resistor, or can be left
open-circuited (three-state). Resistor tolerance = 20ꢀ. The
output stage is illustrated in Figure 35.
DOUBLE-BUFFERED INTERFACE
The AD5337/AD5338/AD5339 DACs have a double-buffered
interface consisting of two banks of registers—an input register
and a DAC register per channel. The input register is directly
connected to the input shift register, and the digital code is
transferred to the relevant input register upon completion of a
valid write sequence. The DAC register contains the digital code
used by the resistor string.
LDAC
Access to the DAC register is controlled by the
bit.
LDAC
When the
bit is set high, the DAC register is latched
and therefore, the input register can change state without
affecting the DAC register. This is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
LDAC
to three of the input registers individually; by setting the
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
bit low when writing to the remaining DAC input register, all
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is only updated if its input register has been updated since the
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
LDAC
last time that
was brought low, thereby removing
unnecessary digital crosstalk.
Figure 35. Output Stage During Power-Down
POWER-DOWN MODES
The bias generator, output amplifiers, resistor string, and all
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
registers remain unchanged when power-down mode is activated.
The time to exit power-down is typically 2.5 μs for VDD = 5 V
and 5 μs when VDD = 3 V. This is the time from the rising edge
of the eighth SCL pulse to the time when the output voltage
deviates from its power-down voltage (see Figure 21 for a plot).
The AD5337/AD5338/AD5339 have very low power consumption,
typically dissipating 0.75 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 15 and Bit 14
(PD1 and PD0) of the data byte. Table 8 shows how the state of
the bits corresponds to the mode of operation of the DAC.
Table 8. PD1/PD0 Operating Modes
PD1
PD0
Operating Mode
±
±
ꢀ
ꢀ
±
ꢀ
±
ꢀ
Normal operation
Power-down (ꢀ kΩ load to GND)
Power-down (ꢀ±± kΩ load to GND)
Power-down (three-state output)
Rev. C | Page ꢀ9 of 28
AD5337/AD5338/AD5339
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
BIPOLAR OPERATION
The AD5337/AD5338/AD5339 can be used with a wide
range of reference voltages for full, one-quadrant multiplying
capability over a reference range of 0 V to VDD. More typically,
these devices are used with a fixed precision reference voltage.
Suitable references for 5 V operation are the AD780, the REF192,
and the ADR391 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589 or AD1580, a
1.23 V band gap reference. Figure 36 shows a typical setup for
the AD5337/AD5338/AD5339 when using an external reference.
Note that A0 can be high or low.
The AD5337/AD5338/AD5339 are designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 37. This circuit gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
R2 = 10kΩ
+5V
6V TO 12V
10µF
R1 = 10kΩ
AD820/
OP295
0.1µF
±5V
+5V
V
V
A
B
DD
OUT
V
= 2.5V TO 5.5V
AD5339
DD
–5V
AD1585
V
IN
V
V
OUT
OUT
REFIN
10µF
0.1µF
1µF
GND
AD5337/
AD5338/
AD5339
A0
V
V
V
A
B
IN
OUT
GND SCL SDA
V
REFIN
OUT
EXT
REF
OUT
1µF
2-WIRE
SERIAL
AD780/REF192/ADR391
SCL
SDA
INTERFACE
WITH V = 5V OR
DD
AD589/AD1580 WITH
Figure 37. Bipolar Operation with the AD5339
V
= 2.5V
DD
A0
GND
The output voltage for any input code can be calculated as
follows:
SERIAL
INTERFACE
⎡
D
2N
R1 + R2
R2 ⎤
⎛
⎞
⎟
Figure 36. AD5337/AD5338/AD5339 Using External Reference
VOUT
=
REFIN ×
×
− REFIN ×
⎜
⎢
⎣
⎥
R1
R1
⎝
⎠
⎦
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference input to VDD. Because this
supply can be inaccurate and noisy, the AD5337/AD5338/
AD5339 can be powered from a reference voltage, for example,
using a 5 V reference such as the REF195, which provides a
steady output supply voltage. With no load on the DACs, the
REF195 is required to supply 600 μA supply current to the DAC
and 112 μA to the reference input. When the DAC outputs are
loaded, the REF195 also needs to supply the current to the loads;
therefore, the total current required with a 10 kΩ load on each
output is
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
With REFIN = 5 V, R1 = R2 = 10 kΩ:
V
OUT = (10 × D/2N) − 5
MULTIPLE DEVICES ON ONE BUS
Figure 38 shows two AD5339 devices on the same serial bus.
Each has a different slave address because the state of the A0 pin
is different. This allows each of four DACs to be written to or
read from independently.
712 μA + 2 × (5 V/10 kΩ) = 1.7 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3.4 ppm (17 μV) for the 1.7 mA
current drawn from it. This corresponds to a 0.0009 LSB error
at 8 bits and a 0.014 LSB error at 12 bits.
V
A0
DD
AD5339
PULL-UP
RESISTORS
SDA
SCL
MICROCONTROLLER
SCL
SDA
A0
AD5339
Figure 38. Multiple AD5339 Devices on One Bus
Rev. C | Page 2± of 28
AD5337/AD5338/AD5339
PRODUCT AS A DIGITALLY PROGRAMMABLE
WINDOW DETECTOR
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5337/AD5338/AD5339 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5337/AD5338/AD5339
are in a system where multiple devices require an AGND-to-
DGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device. The AD5337/AD5338/AD5339 should
have ample supply bypassing of 10 μF in parallel with 0.1 μF on
the supply located as close to the package as possible, ideally
right up against the device. The 10 μF capacitors are the tantalum
bead type. The 0.1 μF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) to
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching. The
power supply lines of the AD5337/AD5338/AD5339 should use
as large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. A ground
line routed between the SDA and SCL lines helps to reduce
crosstalk between them. This is not required on a multilayer
board because there is a separate ground plane, but separating
the lines does help.
Figure 39 shows a digitally programmable upper/lower limit
detector using the two DACs in the AD5337/AD5338/AD5339.
The upper and lower limits for the test are loaded into DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition.
5V
1kΩ
0.1µF
10µF
1kΩ
V
IN
PASS
FAIL
V
DD
V
REF
REFIN
V
A
OUT
AD5337/
AD5338/
AD53391
1/2
CMP04
PASS/FAIL
1/6 74HC05
DIN
SDA
SCL
V
B
SCL
OUT
GND
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Window Detection
COARSE AND FINE ADJUSTMENT CAPABILITIES
The two DACs in the AD5337/AD5338/AD5339 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 40. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, thus, the output range is 0 V to 2.5 V − 1 LSB.
For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B
a range equal to 19 mV.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. Using a microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, while signal
traces are placed on the solder side.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD can be used. The op amps indicated allow
a rail-to-rail output swing.
V
= 5V
DD
R3
51.2kΩ
R4
390Ω
10µF
0.1µF
5V
V
EXT
REF
IN
V
V
V
OUT
DD
REFIN
V
A
AD820/
OP295
OUT
OUT
R1
390Ω
1µF
GND
AD5337/
AD5338/
AD53391
AD780/REF192/ADR391
WITH V = 5V
DD
V
B
OUT
R2
51.2kΩ
GND
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Coarse/Fine Adjustment
Rev. C | Page 2ꢀ of 28
AD5337/AD5338/AD5339
Table 9. Overview of All AD53xx Serial Devices
Part No.
Resolution (Bits)
No. of DACs
DNL (LSBs)
Interface
Settling Time (μs)
Package
No. of Pins
Single
AD53±±
AD53ꢀ±
AD532±
AD53±ꢀ
AD53ꢀꢀ
AD532ꢀ
Dual
8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±ꢀ.±±
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
4
1
8
1
7
8
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
1, 8
1, 8
1, 8
1, 8
1, 8
1, 8
ꢀ±
ꢀ2
8
ꢀ±
ꢀ2
AD53±2
AD53ꢀ2
AD5322
AD53±3
AD53ꢀ3
AD5323
AD5337
AD5338
AD5338-ꢀ
AD5339
Quad
8
2
2
2
2
2
2
2
2
2
2
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±±.5±
±ꢀ.±±
SPI
SPI
SPI
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
1
7
8
1
7
8
1
7
7
8
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
MSOP
MSOP
MSOP
MSOP
8
8
8
ꢀ1
ꢀ1
ꢀ1
8
8
8
ꢀ±
ꢀ2
8
ꢀ±
ꢀ2
8
ꢀ±
ꢀ±
ꢀ2
8
AD53±4
AD53ꢀ4
AD5324
AD53±5
AD53ꢀ5
AD5325
AD53±1
AD53ꢀ1
AD5321
AD53±7
AD53ꢀ7
AD5327
Octal
8
4
4
4
4
4
4
4
4
4
4
4
4
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±ꢀ.±±
±±.25
±±.5±
±ꢀ.±±
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
SPI
1
7
8
1
7
8
1
7
8
1
7
8
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ±
ꢀ2
8
ꢀ±
ꢀ2
8
ꢀ±
ꢀ2
8
ꢀ±
ꢀ2
SPI
SPI
AD53±8
AD53ꢀ8
AD5328
8
ꢀ±
ꢀ2
8
8
8
±±.25
±±.5±
±ꢀ.±±
SPI
SPI
SPI
1
7
8
TSSOP
TSSOP
TSSOP
ꢀ1
ꢀ1
ꢀ1
Rev. C | Page 22 of 28
AD5337/AD5338/AD5339
Table 10. Overview of AD53xx Parallel Devices
Additional Pin Functions
BUF GAIN HBEN CLR
No. of
VREF Pins Time (μs)
Settling
Part No.
Single
Resolution (Bits)
DNL (LSBs)
Package
No. of Pins
AD53±±
AD533ꢀ
AD534±
AD534ꢀ
Dual
8
±±.25
±±.5±
±ꢀ.±±
±ꢀ.±±
ꢀ
ꢀ
ꢀ
ꢀ
1
7
8
8
*
*
*
*
*
*
*
*
*
TSSOP
TSSOP
TSSOP
TSSOP
2±
2±
24
2±
ꢀ±
ꢀ2
ꢀ2
*
*
*
AD5332
AD5333
AD5342
AD5343
Quad
AD5334
AD5335
AD5331
AD5344
Octal
8
±±.25
±±.5±
±ꢀ.±±
±ꢀ.±±
2
2
2
ꢀ
1
7
8
8
*
*
*
*
TSSOP
TSSOP
TSSOP
TSSOP
2±
24
28
2±
ꢀ±
ꢀ2
ꢀ2
*
*
*
*
*
*
8
±±.25
±±.5±
±±.5±
±ꢀ.±±
2
2
4
4
1
7
7
8
*
*
*
*
*
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
ꢀ±
ꢀ±
ꢀ2
AD5341
AD5347
AD5348
8
ꢀ±
ꢀ2
±±.25
±±.5±
±ꢀ.±±
4
4
4
1
7
8
*
*
*
*
*
*
*
*
*
TSSOP, LFCSP
TSSOP, LFCSP
TSSOP, LFCSP
38, 4±
38, 4±
38, 4±
Rev. C | Page 23 of 28
AD5337/AD5338/AD5339
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5337ARM
AD5337ARM-REEL7
AD5337ARMZꢀ
AD5337ARMZ-REEL7ꢀ
AD5337BRM-REEL
AD5337BRM-REEL7
AD5337BRMZꢀ
Temperature Range
−4±°C to +ꢀ±5°C
Package Description
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
D23
D23
D23#
D23#
D2±
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
−4±°C to +ꢀ±5°C
D2±
D2±#
D2±#
D2±#
D24
D5F
D5F
D57
D57
D2ꢀ
D2ꢀ
AD5337BRMZ-REELꢀ
AD5337BRMZ-REEL7ꢀ
AD5338ARM
AD5338ARMZꢀ
AD5338ARMZ-REEL7ꢀ
AD5338ARMZ-ꢀꢀ
AD5338ARMZ-ꢀREEL7ꢀ
AD5338BRM
AD5338BRM-REEL
AD5338BRM-REEL7
AD5338BRMZꢀ
AD5338BRMZ-ꢀꢀ
AD5338BRMZ-ꢀREEL7ꢀ
AD5339ARM
AD5339ARMZꢀ
AD5339ARMZ-REEL7ꢀ
AD5339BRM
AD5339BRM-REEL
AD5339BRM-REEL7
AD5339BRMZꢀ
AD5339BRMZ-REELꢀ
AD5339BRMZ-REEL7ꢀ
D2ꢀ
D5H
D58
D58
D25
D1P
D1P
D22
D22
D22
D1R
D1R
D1R
ꢀ Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked.
Rev. C | Page 24 of 28
AD5337/AD5338/AD5339
NOTES
Rev. C | Page 25 of 28
AD5337/AD5338/AD5339
NOTES
Rev. C | Page 21 of 28
AD5337/AD5338/AD5339
NOTES
Rev. C | Page 27 of 28
AD5337/AD5338/AD5339
NOTES
Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent
Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03756-0-9/07(C)
Rev. C | Page 28 of 28
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