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AD5347BRUZ [ADI]

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AD5347BRUZ
型号： AD5347BRUZ
厂家： ADI    ADI
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2.5 V to 5.5 V, Parallel Interface  
Octal Voltage Output 8-/10-/12-Bit DACs  
AD5346/AD5347/AD5348  
GENERAL DESCRIPTION  
FEATURES  
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit  
DACs, operating from a 2.5 V to 5.5 V supply. These devices  
incorporate an on-chip output buffer that can drive the output  
to both supply rails, and also allow a choice of buffered or  
unbuffered reference input.  
AD5346: octal 8-bit DAC  
AD5347: octal 10-bit DAC  
AD5348: octal 12-bit DAC  
Low power operation: 1.4 mA (max) @ 3.6 V  
Power-down to 120 nA @ 3 V, 400 nA @ 5 V  
Guaranteed monotonic by design over all codes  
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF  
Power-on reset to 0 V  
CS  
The AD5346/AD5347/AD5348 have a parallel interface.  
selects the device and data is loaded into the input registers on  
WR  
the rising edge of  
. A readback feature allows the internal  
LDAC  
Simultaneous update of DAC outputs via  
pin  
DAC registers to be read back through the digital port.  
CLR  
Asynchronous  
Readback  
facility  
The GAIN pin on these devices allows the output range to be  
Buffered/unbuffered reference inputs  
WR  
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging  
Temperature range: –40°C to +105°C  
set at 0 V to VREF or 0 V to 2 × VREF  
Input data to the DACs is double-buffered, allowing simultane-  
LDAC  
.
20 ns  
time  
ous update of multiple DACs in a system using the  
pin.  
input is also provided, which resets the  
CLR  
An asynchronous  
APPLICATIONS  
contents of the input register and the DAC register to all zeros.  
These devices also incorporate a power-on reset circuit that  
ensures that the DAC output powers on to 0 V and remains  
there until valid data is written to the device.  
Portable battery-powered instruments  
Digital gain and offset adjustment  
Programmable voltage and current sources  
Optical networking  
Automatic test equipment  
Mobile communications  
Programmable attenuators  
Industrial process control  
All three parts are pin compatible, which allows users to select  
the amount of resolution appropriate for their application  
without redesigning their circuit board.  
FUNCTIONAL BLOCK DIAGRAM  
V
V
AB  
V
CD  
REF  
AGND DGND  
DD  
REF  
POWER-ON  
RESET  
AD5348  
BUF  
INPUT  
REGISTER  
DAC  
REGISTER  
STRING  
DAC A  
GAIN  
BUFFER  
V
A
B
OUT  
DB11  
INPUT  
REGISTER  
DAC  
REGISTER  
.
.
.
STRING  
DAC B  
BUFFER  
BUFFER  
V
OUT  
DB0  
INPUT  
REGISTER  
DAC  
REGISTER  
STRING  
DAC C  
V
C
OUT  
INTER-  
FACE  
LOGIC  
CS  
DAC  
REGISTER  
INPUT  
REGISTER  
STRING  
DAC D  
V
D
BUFFER  
BUFFER  
OUT  
RD  
DAC  
REGISTER  
INPUT  
REGISTER  
STRING  
DAC E  
V
E
F
WR  
OUT  
DAC  
REGISTER  
INPUT  
REGISTER  
STRING  
DAC F  
V
OUT  
A2  
A1  
A0  
BUFFER  
BUFFER  
BUFFER  
INPUT  
REGISTER  
DAC  
REGISTER  
STRING  
DAC G  
V
V
G
OUT  
DAC  
REGISTER  
INPUT  
REGISTER  
STRING  
DAC H  
H
OUT  
CLR  
POWER-DOWN  
LOGIC  
LDAC  
V
GH  
V
EF  
REF  
PD  
REF  
Figure 1.  
1Protected by U.S. Patent No. 5,969,657; other patents pending.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
AD5346/AD5347/AD5348  
TABLE OF CONTENTS  
Specifications..................................................................................... 3  
Power-On Reset.......................................................................... 17  
Power-Down Mode.................................................................... 17  
Suggested Data Bus Formats..................................................... 18  
Applications Information.............................................................. 19  
Typical Application Circuits ..................................................... 19  
Driving VDD from the Reference Voltage................................. 19  
Bipolar Operation Using the AD5346/AD5347/AD5348..... 19  
Decoding Multiple AD5346/AD5347/AD5348s.................... 20  
AC Characteristics............................................................................ 4  
Timing Characteristics..................................................................... 5  
Absolute Maximum Ratings............................................................ 6  
ESD Caution.................................................................................. 6  
AD5346 Pin Configurations and Function Descriptions ........... 7  
AD5347 Pin Configurations and Function Descriptions ........... 8  
AD5348 Pin Configurations and Function Descriptions ........... 9  
Terminology .................................................................................... 10  
Typical Performance Characteristics ........................................... 12  
Functional Description .................................................................. 16  
Digital-to-Analog Section ......................................................... 16  
Resistor String............................................................................. 16  
DAC Reference Input................................................................. 16  
Output Amplifier........................................................................ 16  
Parallel Interface ......................................................................... 17  
AD5346/AD5347/AD5348 as Digitally Programmable  
Window Detectors ...................................................................... 20  
Programmable Current Source ................................................ 20  
Coarse and Fine Adjustment Using the  
AD5346/AD5347/AD5348 ....................................................... 21  
Power Supply Bypassing and Grounding................................ 21  
Outline Dimensions....................................................................... 23  
Ordering Guides......................................................................... 24  
REVISION HISTORY  
Revision 0: Initial Version  
Rev. 0 | Page 2 of 24  
AD5346/AD5347/AD5348  
SPECIFICATIONS  
Table 1. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX  
,
unless otherwise noted  
B Version1  
Parameter2  
DC PERFORMANCE3,4  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
AD5346  
Resolution  
8
Bits  
LSB  
0.25 LSB  
Relative Accuracy  
Differential Nonlinearity  
AD5347  
0.15  
0.02  
1
Guaranteed monotonic by design over all codes  
Guaranteed monotonic by design over all codes  
Guaranteed monotonic by design over all codes  
Resolution  
10  
0.5  
0.05  
Bits  
LSB  
LSB  
Relative Accuracy  
Differential Nonlinearity  
AD5348  
4
0.5  
Resolution  
12  
2
0.2  
0.4  
0.1  
10  
10  
–12  
–5  
–60  
Bits  
LSB  
LSB  
% of FSR  
% of FSR  
mV  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
16  
1
3
1
60  
Gain Error  
Lower Deadband5  
Upper Deadband5  
Offset Error Drift6  
Gain Error Drift6  
Lower deadband exists only if offset error is negative  
VDD = 5 V; upper deadband exists only if VREF = VDD  
60  
mV  
ppm of FSR/°C  
ppm of FSR/°C  
dB  
DC Power Supply Rejection  
∆VDD = 10%  
Ratio6  
DC Crosstalk6  
200  
µV  
RL = 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;  
Gain = +1  
DAC REFERENCE INPUT6  
VREF Input Range  
VREF Input Range  
1
0.25  
VDD  
VDD  
V
V
Buffered reference mode  
Unbuffered reference mode  
Buffered reference mode and power-down mode  
Gain = +1; input impedance = RDAC  
Gain = +2; input impedance = RDAC  
Frequency = 10 kHz  
VREF Input Impedance  
>10  
90  
45  
–90  
–75  
MΩ  
kΩ  
kΩ  
dB  
dB  
Reference Feedthrough  
Channel-to-Channel Isolation  
OUTPUT CHARACTERISTICS6  
Minimum Output Voltage4, 7  
Maximum Output Voltage4, 7  
Frequency = 10 kHz  
0.001  
V min  
V max  
Rail-to-rail operation  
VDD  
–
0.001  
0.5  
25  
16  
2.5  
5
DC Output Impedance  
Short Circuit Current  
Ω
mA  
mA  
µs  
VDD = 5 V  
VDD = 3 V  
Power-Up Time  
Coming out of power-down mode; VDD = 5 V  
Coming out of power-down mode; VDD = 3 V  
µs  
LOGIC INPUTS  
6
Input Current  
VIL, Input Low Voltage  
1
0.8  
0.7  
0.6  
µA  
V
V
VDD = 5 V 10%  
VDD = 3 V 10%  
VDD = 2.5 V  
V
VIH, Input High Voltage  
Pin Capacitance  
1.7  
V
pF  
VDD = 2.5 V to 5.5 V  
5
Rev. 0 | Page 3 of 24  
 
 
AD5346/AD5347/AD5348  
B Version1  
Typ  
Parameter2  
Min  
Max  
0.4  
Unit  
Conditions/Comments  
LOGIC OUTPUTS6  
VDD = 4.5 V to 5.5 V  
Output Low Voltage, VOL  
Output High Voltage, VOH  
VDD = 2.5 V to 3.6 V  
Output Low Voltage, VOL  
Output High Voltage, VOH  
POWER REQUIREMENTS  
VDD  
V
V
ISINK = 200 µA  
ISOURCE = 200 µA  
VDD – 1  
0.4  
V
V
ISINK = 200 µA  
ISOURCE = 200 µA  
VDD – 0.5  
2.5  
5.5  
V
IDD (Normal Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.6 V  
VIH = VDD, VIL = GND  
All DACs in unbuffered mode. In buffered mode,  
extra current is typically x µA per DAC, where x = 5 µA +  
VREF/RDAC  
1
0.8  
1.65  
1.4  
mA  
mA  
IDD (Power-Down Mode)  
VDD = 4.5 V to 5.5 V  
VDD = 2.5 V to 3.6 V  
VIH = VDD, VIL = GND  
0.4  
0.12  
1
1
µA  
µA  
See footnotes after the AC Characteristics table.  
AC CHARACTERISTICS6  
Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted  
B Version1  
Min Typ  
Parameter2  
Output Voltage Settling Time  
AD5346  
Max  
Unit  
Conditions/Comments  
VREF = 2 V  
6
8
9
10  
µs  
µs  
µs  
1/4 scale to 3/4 scale change (40 H to C0 H)  
1/4 scale to 3/4 scale change (100 H to 300 H)  
1/4 scale to 3/4 scale change (400 H to C00 H)  
AD5347  
7
AD5348  
8
Slew Rate  
0.7  
V/µs  
Major Code Transition Glitch  
Energy  
8
nV-s  
1 LSB change around major carry  
Digital Feedthrough  
Digital Crosstalk  
Analog Crosstalk  
DAC-to-DAC Crosstalk  
Multiplying Bandwidth  
Total Harmonic Distortion  
0.5  
1
1
3.5  
200  
–70  
nV-s  
nV-s  
nV-s  
nV-s  
kHz  
dB  
VREF = 2 V 0.1 V p-p; unbuffered mode  
VREF = 2. V 0.1 V p-p; frequency = 10 kHz; unbuffered mode  
1 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.  
2 See Terminology section.  
3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).  
4 DC specifications tested with outputs unloaded.  
5 This corresponds to x codes. x = deadband voltage/LSB size.  
6 Guaranteed by design and characterization, not production tested.  
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and  
the offset plus gain error must be positive.  
200µA  
I
OL  
TO OUTPUT  
PIN  
V
(min) + V (max)  
OL  
OH  
C
50pF  
L
2
200µA  
I
OH  
Figure 2. Load Circuit for Digital Output Timing Specifications  
Rev. 0 | Page 4 of 24  
 
 
AD5346/AD5347/AD5348  
TIMING CHARACTERISTICS1, 2, 3  
Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted  
Parameter  
Limit at TMIN, TMAX  
Unit  
Condition/Comments  
Data Write Mode (Figure 3)  
CS to WR setup time  
CS to WR hold time  
WR pulse width  
Data, GAIN, BUF setup time  
Data, GAIN, BUF hold time  
Synchronous mode. WR falling to LDAC falling.  
Synchronous mode. LDAC falling to WR rising.  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
0
0
20  
5
4.5  
5
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
5
WR  
rising to LDAC rising.  
t8  
4.5  
ns min  
Synchronous mode.  
Asynchronous mode. LDAC rising to WR rising.  
Asynchronous mode. WR rising to LDAC falling.  
LDAC pulse width  
t9  
t10  
t11  
5
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
4.5  
20  
10  
20  
20  
0
CLR  
t12  
t13  
t14  
t15  
pulse width  
Time between WR cycles  
A0, A1, A2 setup time  
A0, A1, A2 hold time  
Data Readback Mode (Figure 4)  
CS  
t16  
t17  
0
0
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns max  
ns min  
ns max  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min  
A0, A1, A2 to setup time  
CS  
A0, A1, A2 to hold time  
RD  
CS to falling edge of  
t18  
t19  
0
RD pulse width; VDD = 3.6 V to 5.5 V  
RD pulse width; VDD = 2.5 V to 3.6 V  
CS to RD hold time  
Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V  
Data access time after falling edge of RD VDD = 2.5 V to 3.6 V  
Bus relinquish time after rising edge of RD  
20  
30  
0
22  
30  
4
30  
22  
30  
30  
30  
30  
50  
t20  
t21  
t22  
t23  
CS falling edge to data; VDD = 3.6 V to 5.5 V  
CS falling edge to data; VDD = 2.5 V to 3.6 V  
RD  
t24  
t25  
t26  
Time between  
cycles  
Time from RD to WR  
Time from WR to RD, VDD = 3.6 V to 5.5 V  
Time from WR to RD, VDD = 2.5 V to 3.6 V  
1 Guaranteed by design and characterization, not production tested.  
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.  
3 See Figure 2.  
t1  
t2  
CS  
A0–A2  
t3  
t13  
t17  
t16  
WR  
t5  
CS  
t4  
DATA,  
GAIN, BUF  
t18  
t20  
t19  
t24  
t6  
t8  
t7  
t9  
RD  
DATA  
WR  
1
LDAC  
t21  
t22  
t10  
t11  
2
LDAC  
t23  
t12  
CLR  
t25  
t14  
t15  
A0–A2  
t26  
NOTES  
1. SYNCHRONOUS LDAC UPDATE MODE  
2. ASYNCHRONOUS LDAC UPDATE MODE  
Figure 3. Parallel Interface Write Timing Diagram  
Figure 4. Parallel Interface Read Timing Diagram  
Rev. 0 | Page 5 of 24  
 
 
 
AD5346/AD5347/AD5348  
ABSOLUTE MAXIMUM RATINGS  
Table 4. TA = 25°C, unless otherwise noted  
Parameter  
Rating  
VDD to GND  
–0.3 V to +7 V  
Digital Input Voltage to GND  
Digital Output Voltage to GND  
Reference Input Voltage to GND  
VOUT to GND  
–0.3 V to VDD + 0.3 V  
–0.3 V to VDD + 0.3 V  
–0.3 V to VDD + 0.3 V  
–0.3 V to VDD + 0.3 V  
Operating Temperature Range  
Industrial (B Version)  
Storage Temperature Range  
Junction Temperature  
38-Lead TSSOP Package  
Power Dissipation  
θJA Thermal Impedance  
θJC Thermal Impedance  
40-Lead LFCSP Package  
Power Dissipation  
–40°C to +105°C  
–65°C to +150°C  
150°C  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those listed in the operational sections  
of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
(TJ max − TA)/ θJA mW  
98.3°C/W  
8.9°C/W  
(TJ max − TA)/ θJA mW  
29.6°C/W  
θJA Thermal Impedance (3-layer  
board)  
Lead Temperature, Soldering (10 sec)  
IR Reflow, Peak Temperature  
300°C  
220°C  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on  
the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. 0 | Page 6 of 24  
 
AD5346/AD5347/AD5348  
AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
GH  
EF  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
PD  
REF  
V
2
CLR  
REF  
V
V
CD  
3
REF  
40 39 38 37 36 35 34 33 32 31  
GAIN  
WR  
4
V
V
V
V
V
A
B
C
D
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
DD  
AB  
A
OUT  
OUT  
OUT  
OUT  
RD  
CS  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
5
REF  
RD  
CS  
V
6
OUT  
8-BIT  
3
7
6
5
4
3
2
1
0
AD5346  
TOP VIEW  
(Not to Scale)  
V
V
V
B
C
D
7
DB  
7
OUT  
OUT  
OUT  
4
8-BIT  
8
DB  
6
5
4
5
AGND  
AGND  
AD5346  
TOP VIEW  
(Not to Scale)  
9
DB  
6
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
29 DB  
28  
AGND  
V
E
F
7
OUT  
DB  
V
E
F
3
2
1
0
OUT  
V
8
OUT  
27 DB  
V
OUT  
V
G
9
OUT  
DB  
DB  
26  
25  
V
G
OUT  
V
H
10  
OUT  
V
H
OUT  
11 12 13 14 15 16 17 18 19 20  
DGND  
BUF  
24 DGND  
23 DGND  
DGND  
DGND  
22  
21  
LDAC  
A0  
Figure 6. AD5346 Pin Configuration—LFCSP  
20 A2  
A1  
Figure 5. AD5346 Pin Configuration—TSSOP  
Table 5. AD5346 Pin Function Descriptions  
Pin Number  
TSSOP  
LFCSP  
35  
36  
37  
38, 39  
Mnemonic  
VREFGH  
VREFEF  
VREFCD  
VDD  
Function  
1
2
3
4
Reference Input for DACs G and H.  
Reference Input for DACs E and F.  
Reference Input for DACs C and D.  
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled  
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP  
package must be at the same potential.  
5
40  
VREFAB  
Reference Input for DACs A and B.  
6–9,  
1–4,  
VOUTX  
Output of DAC X. Buffered output with rail-to-rail operation.  
11–14  
7–10  
10  
15,  
5, 6  
11,  
AGND  
DGND  
Analog Ground. Ground reference for analog circuitry.  
Digital Ground. Ground reference for digital circuitry.  
21–24  
17–20  
16  
17  
12  
13  
BUF  
LDAC  
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.  
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which  
allows all DAC outputs to be simultaneously updated.  
18  
19  
14  
15  
A0  
A1  
LSB Address Pin. Selects which DAC is to be written to.  
Address Pin. Selects which DAC is to be written to.  
20  
25–32  
33  
16  
21–28  
29  
A2  
DB0–DB7  
CS  
MSB Address Pin. Selects which DAC is to be written to.  
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.  
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or  
with RD to read back data from a DAC.  
34  
35  
36  
37  
38  
30  
31  
32  
33  
34  
RD  
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.  
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.  
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.  
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.  
Power-Down Pin. This active low control pin puts all DACs into power-down mode.  
WR  
GAIN  
CLR  
PD  
Rev. 0 | Page 7 of 24  
 
AD5346/AD5347/AD5348  
AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
GH  
EF  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
PD  
REF  
V
2
CLR  
REF  
V
V
CD  
3
REF  
40 39 38 37 36 35 34 33 32 31  
GAIN  
WR  
4
V
V
V
V
V
A
B
C
D
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
DD  
AB  
A
OUT  
OUT  
OUT  
OUT  
RD  
CS  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
5
REF  
RD  
CS  
V
6
OUT  
10-BIT  
3
9
8
7
6
5
4
3
2
AD5347  
TOP VIEW  
(Not to Scale)  
V
V
V
B
C
D
7
DB  
9
OUT  
OUT  
OUT  
4
10-BIT  
8
DB  
8
7
6
5
4
3
5
AGND  
AGND  
AD5347  
TOP VIEW  
(Not to Scale)  
9
DB  
6
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
29 DB  
28  
AGND  
V
E
F
7
OUT  
DB  
27 DB  
V
E
F
OUT  
V
8
OUT  
V
OUT  
V
G
9
OUT  
DB  
DB  
26  
25  
V
G
OUT  
V
H
10  
OUT  
V
H
2
1
0
OUT  
11 12 13 14 15 16 17 18 19 20  
DGND  
BUF  
24 DB  
23 DB  
DGND  
DGND  
22  
21  
LDAC  
A0  
Figure 8. AD5347 Pin Configuration—LFCSP  
20 A2  
A1  
Figure 7. AD5347 Pin Configuration—TSSOP  
Table 6. AD5347 Pin Function Descriptions  
Pin Number  
TSSOP  
LFCSP  
35  
36  
37  
38, 39  
Mnemonic Function  
1
2
3
4
VREFGH  
VREFEF  
VREFCD  
VDD  
Reference Input for DACs G and H.  
Reference Input for DACs E and F.  
Reference Input for DACs C and D.  
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled  
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package  
must be at the same potential.  
5
40  
VREFAB  
Reference Input for DACs A and B.  
6–9,  
1–4,  
VOUTX  
Output of DAC X. Buffered output with rail-to-rail operation.  
11–14  
7–10  
10  
15, 21–22  
5, 6  
11,  
AGND  
DGND  
Analog Ground. Ground reference for analog circuitry.  
Digital Ground. Ground reference for digital circuitry.  
17–18  
16  
17  
12  
13  
BUF  
LDAC  
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.  
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which  
allows all DAC outputs to be simultaneously updated.  
18  
19  
14  
15  
A0  
A1  
LSB Address Pin. Selects which DAC is to be written to.  
Address Pin. Selects which DAC is to be written to.  
20  
23–32  
33  
16  
19–28  
29  
A2  
DB0–DB9  
CS  
MSB Address Pin. Selects which DAC is to be written to.  
Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits.  
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or  
with RD to read back data from a DAC.  
34  
35  
36  
37  
38  
30  
31  
32  
33  
34  
RD  
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.  
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.  
WR  
GAIN  
CLR  
PD  
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF  
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.  
Power-Down Pin. This active low control pin puts all DACs into power-down mode.  
.
Rev. 0 | Page 8 of 24  
 
AD5346/AD5347/AD5348  
AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
GH  
EF  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
PD  
REF  
V
2
CLR  
REF  
V
V
CD  
3
REF  
40 39 38 37 36 35 34 33 32 31  
GAIN  
WR  
4
V
V
V
V
V
A
B
C
D
1
2
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
DD  
AB  
A
OUT  
OUT  
OUT  
OUT  
RD  
CS  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
DB  
5
REF  
RD  
CS  
V
6
OUT  
12-BIT  
3
11  
10  
9
AD5348  
TOP VIEW  
(Not to Scale)  
V
V
V
B
C
D
7
DB  
11  
OUT  
OUT  
OUT  
4
12-BIT  
8
DB  
DB  
10  
9
5
AGND  
AGND  
AD5348  
TOP VIEW  
(Not to Scale)  
9
6
8
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
29 DB  
AGND  
8
V
E
F
7
OUT  
7
28  
DB  
V
E
7
OUT  
V
8
OUT  
6
27 DB  
V
F
6
OUT  
V
G
9
OUT  
5
DB  
26  
25  
5
V
G
OUT  
V
H
10  
OUT  
4
DB  
V
H
4
3
OUT  
11 12 13 14 15 16 17 18 19 20  
DGND  
BUF  
24 DB  
23 DB  
2
1
DB  
DB  
22  
21  
LDAC  
A0  
0
Figure 10. AD5348 Pin Configuration—LFCSP  
20 A2  
A1  
Figure 9. AD5348 Pin Configuration—TSSOP  
Table 7. AD5348 Pin Function Descriptions  
Pin Number  
TSSOP LFCSP Mnemonic Function  
1
2
3
4
35  
36  
37  
VREFGH  
VREFEF  
VREFCD  
Reference Input for DACs G and H.  
Reference Input for DACs E and F.  
Reference Input for DACs C and D.  
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a  
10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at  
the same potential.  
38, 39 VDD  
5
6–9,  
40  
1–4,  
VREFAB  
VOUT  
Reference Input for DACs A and B.  
Output of DAC X. Buffered output with rail-to-rail operation.  
X
11–14  
7–10  
10  
15  
16  
17  
5, 6  
11  
12  
AGND  
DGND  
BUF  
Analog Ground. Ground reference for analog circuitry.  
Digital Ground. Ground reference for digital circuitry.  
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.  
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows  
all DAC outputs to be simultaneously updated.  
13  
LDAC  
18  
19  
20  
21–32  
33  
14  
15  
16  
A0  
A1  
A2  
LSB Address Pin. Selects which DAC is to be written to.  
Address Pin. Selects which DAC is to be written to.  
MSB Address Pin. Selects which DAC is to be written to.  
Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits.  
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with  
RD to read back data from a DAC.  
17–28 DB0–DB11  
29  
CS  
34  
35  
36  
37  
38  
30  
31  
32  
33  
34  
RD  
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.  
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.  
WR  
GAIN  
CLR  
PD  
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF  
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.  
Power-Down Pin. This active low control pin puts all DACs into power-down mode.  
.
Rev. 0 | Page 9 of 24  
 
AD5346/AD5347/AD5348  
TERMINOLOGY  
Relative Accuracy  
GAIN ERROR  
AND  
OFFSET  
ERROR  
For the DAC, relative accuracy or integral nonlinearity (INL) is  
a measure of the maximum deviation, in LSBs, from a straight  
line passing through the actual endpoints of the DAC transfer  
function. Typical INL versus code plots can be seen in Figure 14,  
Figure 15, and Figure 16.  
ACTUAL  
OUTPUT  
VOLTAGE  
Differential Nonlinearity  
Differential nonlinearity (DNL) is the difference between the  
measured change and the ideal 1 LSB change between any two  
adjacent codes. A specified differential nonlinearity of 1 LSB  
maximum ensures monotonicity. This DAC is guaranteed  
monotonic by design. Typical DNL versus code plots can be  
seen in Figure 17, Figure 18, and Figure 19.  
IDEAL  
POSITIVE  
OFFSET  
Gain Error  
DAC CODE  
This is a measure of the span error of the DAC, including any  
error in the gain of the buffer amplifier. It is the deviation in  
slope of the actual DAC transfer characteristic from the ideal  
and is expressed as a percentage of the full-scale range. This is  
illustrated in Figure 11.  
Figure 12. Positive Offset Error and Gain Error  
GAIN ERROR  
AND  
OFFSET  
ERROR  
Offset Error  
IDEAL  
This is a measure of the offset error of the DAC and the output  
amplifier. It is expressed as a percentage of the full-scale range.  
OUTPUT  
VOLTAGE  
If the offset voltage is positive, the output voltage still positive at  
zero input code. This is shown in Figure 12. Because the DACs  
operate from a single supply, a negative offset cannot appear at  
the output of the buffer amplifier. Instead, there is a code close  
to zero at which the amplifier output saturates (amplifier  
footroom). Below this code there is a dead band over which the  
output voltage does not change. This is illustrated in Figure 13.  
ACTUAL  
NEGATIVE  
OFFSET  
DAC CODE  
POSITIVE  
GAIN ERROR  
DEADBAND CODES  
AMPLIFIER  
FOOTROOM  
(~1mV)  
NEGATIVE  
ACTUAL  
GAIN ERROR  
OUTPUT  
VOLTAGE  
NEGATIVE  
OFFSET  
IDEAL  
Figure 13. Negative Offset Error and Gain Error  
DAC CODE  
Figure 11. Gain Error  
Rev. 0 | Page 10 of 24  
 
 
 
 
AD5346/AD5347/AD5348  
Offset Error Drift  
Digital Crosstalk  
This is a measure of the change in offset error with changes in  
temperature. It is expressed in (ppm of full-scale range)/°C.  
This is the glitch impulse transferred to the output of one DAC  
at midscale in response to a full-scale code change (all 0s to all  
1s and vice versa) in the input register of another DAC. It is  
expressed in nV-s.  
Gain Error Drift  
This is a measure of the change in gain error with changes in  
temperature. It is expressed in (ppm of full-scale range)/°C.  
Analog Crosstalk  
This is the glitch impulse transferred to the output of one DAC  
due to a change in the output of another DAC. It is measured by  
loading one of the input registers with a full-scale code change  
DC Power-Supply Rejection Ratio (PSRR)  
This indicates how the output of the DAC is affected by changes  
in the supply voltage. PSRR is the ratio of the change in VOUT to  
a change in VDD for full-scale output of the DAC. It is measured  
in dB. VREF is held at 2 V and VDD is varied 10%.  
LDAC  
(all 0s to all 1s and vice versa) while keeping  
high. Then  
low and monitor the output of the DAC whose  
LDAC  
pulse  
digital code was not changed. The area of the glitch is expressed  
in nV-s.  
DC Crosstalk  
This is the dc change in the output level of one DAC at midscale  
in response to a full-scale code change (all 0s to all 1s and vice  
versa) and output change of another DAC. It is expressed in µV.  
DAC-to-DAC Crosstalk  
This is the glitch impulse transferred to the output of one DAC  
due to a digital code change and subsequent output change of  
another DAC. This includes both digital and analog crosstalk. It  
is measured by loading one of the DACs with a full-scale code  
Reference Feedthrough  
This is the ratio of the amplitude of the signal at the DAC  
output to the reference input when the DAC output is not being  
LDAC  
change (all 0s to all 1s and vice versa) with the  
pin set  
low and monitoring the output of another DAC. The energy of  
the glitch is expressed in nV-s.  
LDAC  
updated, i.e.,  
is high. It is expressed in dB.  
Channel-to-Channel Isolation  
Multiplying Bandwidth  
This is a ratio of the amplitude of the signal at the output of one  
DAC to a sine wave on the reference inputs of the other DACs.  
It is measured by grounding one VREF pin and applying a 10 kHz,  
4 V p-p sine wave to the other VREF pins. It is expressed in dB.  
The amplifiers within the DAC have a finite bandwidth. The  
multiplying bandwidth is a measure of this. A sine wave on the  
reference (with full-scale code loaded to the DAC) appears on  
the output. The multiplying bandwidth is the frequency at  
which the output amplitude falls to 3 dB below the input.  
Major-Code Transition Glitch Energy  
This is the energy of the impulse injected into the analog output  
when the DAC changes state. It is normally specified as the area  
of the glitch in nV-s and is measured when the digital code is  
changed by 1 LSB at the major carry transition (011 . . . 11 to  
100 . . . 00 or 100 . . . 00 to 011 . . . 11).  
Total Harmonic Distortion (THD)  
This is the difference between an ideal sine wave and its  
attenuated version using the DAC. The sine wave is used as the  
reference for the DAC, and the THD is a measure of the  
harmonics present on the DAC output. It is measured in dB.  
Digital Feedthrough  
This is a measure of the impulse injected into the analog output  
of the DAC from the digital input pins of the device, but it is  
CS  
measured when the DAC is not being written to,  
held high.  
It is specified in nV-s and is measured with a full-scale change  
on the digital input pins, i.e., from all 0s to all 1s and vice versa.  
Rev. 0 | Page 11 of 24  
AD5346/AD5347/AD5348  
TYPICAL PERFORMANCE CHARACTERISTICS  
1.0  
0.3  
0.2  
0.1  
T
V
= 25°C  
DD  
T
= 25°C  
A
A
= 5V  
V
= 5V  
DD  
0.5  
0
0
–0.1  
–0.2  
–0.3  
–0.5  
–1.0  
0
50  
100  
150  
200  
250  
1000  
4000  
0
0
0
50  
100  
150  
200  
250  
CODE  
CODE  
Figure 14. AD5346 Typical INL Plot  
Figure 17. AD5346 Typical DNL Plot  
0.6  
0.4  
0.2  
3
2
T
V
= 25°C  
T
V
= 25°C  
A
A
= 5V  
= 5V  
DD  
DD  
1
0
0
–0.2  
–1  
–2  
–3  
–0.4  
–0.6  
0
200  
400  
600  
800  
200  
400  
600  
800  
1000  
CODE  
CODE  
Figure 15. AD5347 Typical INL Plot  
Figure 18. AD5347 Typical DNL Plot  
1.0  
0.5  
12  
8
T
V
= 25°C  
A
T
V
= 25°C  
DD  
A
= 5V  
DD  
= 5V  
4
0
0
–4  
–8  
–12  
–0.5  
–1.0  
1000  
2000  
3000  
4000  
0
1000  
2000  
3000  
CODE  
CODE  
Figure 19. AD5348 Typical DNL Plot  
Figure 16. AD5348 Typical INL Plot  
Rev. 0 | Page 12 of 24  
 
AD5346/AD5347/AD5348  
0.2  
0.1  
0.5  
0.4  
0.3  
0.2  
0.1  
0
V
T
= 5V  
= 25°C  
T
V
= 25°C  
REF  
DD  
A
= 2V  
A
MAX INL  
0
GAIN ERROR  
MAX DNL  
–0.1  
–0.2  
–0.3  
–0.4  
–0.1  
MIN DNL  
MIN INL  
–0.2  
–0.3  
–0.4  
–0.5  
OFFSET ERROR  
–0.5  
–0.6  
0
1
2
3
4
5
0
1
2
3
4
5
6
V
(V)  
V
(V)  
REF  
DD  
Figure 20. AD5346 INL and DNL Error vs. VREF  
Figure 23. Offset Error and Gain Error vs. VDD  
0.5  
0.4  
0.3  
5
V
V
= 5V  
= 2V  
DD  
REF  
MAX INL  
5V SOURCE  
3V SOURCE  
4
3
0.2  
0.1  
0
MAX DNL  
2
–0.1  
–0.2  
MIN DNL  
MIN INL  
–0.3  
–0.4  
–0.5  
1
0
3V SINK  
5V SINK  
–40  
–20  
0
20  
40  
60  
80  
100  
0
1
2
3
4
5
6
TEMPERATURE (°C)  
SINK/SOURCE CURRENT (mA)  
Figure 21. AD5346 INL and DNL Error vs. Temperature  
Figure 24. VOUT Source and Sink Current Capability  
1.0  
0.5  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
V
V
= 5V  
DD  
= 2V  
REF  
V
= 5V  
= 25°C  
DD  
T
A
0
–0.5  
–1.0  
OFFSET ERROR  
0.4  
0.3  
0.2  
GAIN ERROR  
0.1  
0
–40  
–20  
0
20  
40  
60  
80  
100  
ZERO SCALE  
HALF SCALE  
DAC CODE  
FULL SCALE  
TEMPERATURE (°C)  
Figure 22. AD5346 Offset Error and Gain Error vs. Temperature  
Figure 25. Supply Current vs. DAC Code  
Rev. 0 | Page 13 of 24  
 
AD5346/AD5347/AD5348  
1.4  
T
V
V
= 25°C  
= 5V  
V
= 2V  
A
REF  
GAIN = 1 UNBUFFERED  
DD  
= 5V  
1.2  
REF  
T
= –40°C  
A
T
= +25°C  
A
1.0  
0.8  
0.6  
0.4  
0.2  
0
V
A
OUT  
T
= +105°C  
A
CH1  
CH2  
LDAC  
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
SUPPLY VOLTAGE (V)  
Figure 29. Half-Scale Settling (¼ to ¾ Scale Code)  
Figure 26. Supply Current vs. Supply Voltage  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
T
V
V
= 25°C  
= 5V  
A
T
= 25°C  
DD  
A
= 2V  
REF  
CH1  
V
DD  
V
A
OUT  
CH2  
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV  
2.0  
2.5  
3.0  
3.5  
4.0  
(V)  
4.5  
5.0  
5.5  
V
DD  
Figure 30. Power-On Reset to 0 V  
Figure 27. Power-Down Current vs. Supply Voltage  
2.5  
T
= 25  
°C  
A
V
= 5V  
DD  
2.0  
1.5  
1.0  
V
1
OUT  
CH2  
PD  
V
= 3V  
DD  
0.5  
0
CH1  
CH1 2.00V, CH2 1.00V, TIME BASE = 20µs/DIV  
0
1
2
3
4
5
VLOGIC (V)  
Figure 31. Exiting Power-Down to Midscale  
Figure 28. Supply Current vs. Logic Input Voltage  
Rev. 0 | Page 14 of 24  
 
 
AD5346/AD5347/AD5348  
21  
18  
15  
12  
9
0.02  
0.01  
0
V
= 5V  
= 25°C  
DD  
T
A
V
=
3V  
V
= 5V  
DD  
DD  
6
–0.01  
–0.02  
3
0
0
1
2
3
4
5
6
0.6  
0.8  
1.0  
(mA)  
1.2  
1.4  
V
(V)  
REF  
I
DD  
Figure 35. Full-Scale Error vs. VREF  
Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V  
2.50  
2.49  
2.48  
2.47  
1.999  
1.998  
1.997  
1.996  
1µs/DIV  
Figure 36. DAC-to-DAC Crosstalk  
Figure 33. AD5348 Major Code Transition Glitch Energy  
10  
0
–10  
–20  
–30  
–40  
–50  
–60  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 34. Multiplying Bandwidth (Small Signal Frequency Response)  
Rev. 0 | Page 15 of 24  
AD5346/AD5347/AD5348  
FUNCTIONAL DESCRIPTION  
V
REF  
The AD5346/AD5347/AD5348 are octal resistor-string DACs  
fabricated by a CMOS process with resolutions of 8, 10, and 12  
bits, respectively. They are written to using a parallel interface.  
They operate from single supplies of 2.5 V to 5.5 V, and the  
output buffer amplifiers offer rail-to-rail output swing. The gain  
of the buffer amplifiers can be set to 1 or 2 to give an output  
voltage range of 0 V to VREF or 0 V to 2 × VREF. The AD5346/  
AD5347/AD5348 have reference inputs that may be buffered to  
draw virtually no current from the reference source. The devices  
have a power-down feature that reduces current consumption  
to only 100 nA @ 3 V.  
R
R
R
TO OUTPUT  
AMPLIFIER  
R
R
DIGITAL-TO-ANALOG SECTION  
Figure 38. Resistor String  
The architecture of one DAC channel consists of a reference  
buffer and a resistor-string DAC followed by an output buffer  
amplifier. The voltage at the VREF pin provides the reference  
voltage for the DAC. Figure 37 shows a block diagram of the  
DAC architecture. Because the input coding to the DAC is  
straight binary, the ideal output voltage is given by  
DAC REFERENCE INPUT  
The DACs operate with an external reference. The AD5346/  
AD5347/AD5348 have a reference input for each pair of DACs.  
The reference inputs may be configured as buffered or  
unbuffered. This option is controlled by the BUF pin.  
D
VOUT =VREF  
×
×Gain  
In buffered mode (BUF = 1), the current drawn from an  
external reference voltage is virtually zero because the imped-  
2N  
ance is at least 10 MΩ. The reference input range is 1 V to VDD  
.
where:  
In unbuffered mode (BUF = 0), the user can have a reference  
D is the decimal equivalent of the binary code, which is loaded  
to the DAC register:  
voltage as low as 0.25 V and as high as VDD because there is no  
restriction due to headroom and footroom of the reference  
amplifier. The impedance is still large at typically 90 kΩ for 0 V  
to VREF mode and 45 kΩ for 0 V to 2 × VREF mode.  
0–255 for AD5346 (8 bits)  
0–1023 for AD5347 (10 bits)  
0–4095 for AD5348 (12 bits)  
N is the DAC resolution.  
Gain is the output amplifier gain (1 or 2).  
If using an external buffered reference (such as REF192), there  
is no need to use the on-chip buffer.  
V
AB  
REF  
OUTPUT AMPLIFIER  
The output buffer amplifier is capable of generating output  
voltages to within 1 mV of either rail. Its actual range depends  
on VREF, GAIN, the load on VOUT, and offset error.  
REFERENCE  
BUFFER  
BUF  
(GAIN = +1 OR +2)  
If a gain of +1 is selected (GAIN = 0), the output range is  
DAC  
REGISTER  
RESISTOR  
STRING  
INPUT  
REGISTER  
V
A
OUT  
0.001 V to VREF  
.
OUTPUT  
BUFFER AMPLIFIER  
If a gain of +2 is selected (GAIN = +1), the output range is  
0.001 V to 2 × VREF. However, because of clamping, the  
maximum output is limited to VDD – 0.001 V.  
Figure 37. Single DAC Channel Architecture  
RESISTOR STRING  
The output amplifier is capable of driving a load of 2 kΩ to  
GND or VDD, in parallel with 500 pF to GND or VDD. The source  
and sink capabilities of the output amplifier can be seen in  
Figure 24.  
The resistor string section is shown in Figure 38. It is simply a  
string of resistors, each of value R. The digital code loaded to  
the DAC register determines at what node on the string the  
voltage is tapped off to be fed into the output amplifier. The  
voltage is tapped off by closing one of the switches connecting  
The slew rate is 0.7 V/µs with a half-scale settling time to 0.5 LSB  
(at 8 bits) of 6 s with the output unloaded. See Figure 29.  
the string to the amplifier. Because it is a string of resistors, it is  
guaranteed monotonic.  
Rev. 0 | Page 16 of 24  
 
 
 
AD5346/AD5347/AD5348  
where IDYNAMIC  
=
cvf and  
PARALLEL INTERFACE  
c = capacitance or the data bus  
v = VDD  
f = readback frequency  
The AD5346/AD5347/AD5348 load their data as a single 8-,  
10-, or 12-bit word.  
Double-Buffered Interface  
LDAC  
Load DAC Input (  
)
The AD5346/AD5347/AD5348 DACs all have double-buffered  
interfaces consisting of an input register and a DAC register.  
DAC data, BUF, and GAIN inputs are written to the input regis-  
LDAC  
transfers data from the input register to the DAC register,  
LDAC  
and therefore updates the outputs. The  
function enables  
double-buffering of the DAC data, GAIN data, and BUF. There  
LDAC  
CS  
WR  
ter under control of the Chip Select ( ) and Write (  
) pins.  
are two  
modes:  
LDAC  
Access to the DAC register is controlled by the  
LDAC  
function.  
•
Synchronous Mode. In this mode, the DAC register is  
When  
register may change state without affecting the contents of the  
LDAC  
is high, the DAC register is latched and the input  
updated after new data is read in on the rising edge of the  
WR  
LDAC  
input.  
shown in Figure 3.  
can be tied permanently low or pulsed as  
DAC register. However, when  
is brought low, the DAC  
register becomes transparent and the contents of the input  
register are transferred to it. The gain and buffer control signals  
are also double-buffered and are updated only when  
taken low.  
•
Asynchronous Mode. In this mode, the outputs are not  
updated at the same time that the input register is written  
to. When  
the contents of the input register.  
LDAC  
is  
LDAC  
goes low, the DAC register is updated with  
This is useful if the user requires simultaneous updating of all  
DACs and peripherals. The user can write to all input registers  
POWER-ON RESET  
The AD5346/AD5347/AD5348 have a power-on reset function,  
so that they power up in a defined state. The power-on state is  
LDAC  
individually and then, by pulsing the  
outputs update simultaneously.  
input low, all  
•
•
•
•
Normal operation  
These parts contain an extra feature whereby the DAC register  
is not updated unless its input register has been updated since  
Reference input buffered  
0 V to VREF output range  
Output voltage set to 0 V  
LDAC  
the last time that  
was brought low. Normally, when  
LDAC  
is brought low, the DAC registers are filled with the  
Both input and DAC registers are filled with zeros and remain  
so until a valid write sequence is made to the device. This is  
particularly useful in applications where it is important to know  
the state of the DAC outputs while the device is powering up.  
contents of the input registers. In the case of the AD5346/  
AD5347/AD5348, the part updates the DAC register only if the  
input register has been changed since the last time the DAC  
register was updated. This removes unnecessary crosstalk.  
CLR  
Clear Input (  
)
POWER-DOWN MODE  
CLR  
is an active low, asynchronous clear that resets the input  
The AD5346/AD5347/AD5348 have low power consumption,  
dissipating typically 2.4 mW with a 3 V supply and 5 mW with  
a 5 V supply. Power consumption can be further reduced when  
the DACs are not in use by putting them into power-down  
and DAC registers.  
CS  
Chip Select Input (  
)
CS  
is an active low input that selects the device.  
PD  
mode, which is selected by taking the  
pin low.  
WR  
Write Input (  
)
PD  
When the  
pin is high, the DACs work normally with a typi-  
WR  
is an active low input that controls writing of data to the  
device. Data is latched into the input register on the rising edge  
WR  
cal power consumption of 1 mA at 5 V (0.8 mA at 3 V). In  
power-down mode, however, the supply current falls to 400 nA  
at 5 V (120 nA at 3 V) when the DACs are powered down. Not  
only does the supply current drop, but the output stage is also  
internally switched from the output of the amplifier, making it  
open-circuit. This has the advantage that the outputs are three-  
state while the part is in power-down mode, and provides a  
defined input condition for whatever is connected to the outputs  
of the DAC amplifiers. The output stage is illustrated in Figure 39.  
of  
.
RD  
Read Input (  
)
RD  
is an active low input that controls when data is read back  
RD  
from the internal DAC registers. On the falling edge of  
is shifted onto the data bus. Under the conditions of a high  
capacitive load and high supplies, the user must ensure that the  
dynamic current remains at an acceptable level, therefore  
ensuring that the die temperature is within specification. The  
die temperature can be calculated as  
, data  
RESISTOR  
STRING DAC  
AMPLIFIER  
V
OUT  
POWER-DOWN  
CIRCUITRY  
TDIE = TAMBIENT + VDD (IDD + IDYNAMIC)θJA  
Figure 39. Output Stage During Power-Down  
Rev. 0 | Page 17 of 24  
 
 
AD5346/AD5347/AD5348  
The bias generator, the output amplifier, the resistor string, and  
all other associated linear circuitry are all shut down when the  
power-down mode is activated. However, the contents of the  
registers are unaffected when in power-down. The time to exit  
power-down is typically 2.5 s for VDD = 5 V and 5 µs when VDD  
The AD5347 and AD5348 data bus must be at least 10 and 12  
bits wide, respectively, and are best suited to a 16-bit data bus  
system.  
Examples of data formats for putting GAIN and BUF on a  
16-bit data bus are shown in Figure 40. Note that any unused  
bits above the actual DAC data may be used for GAIN and BUF.  
=
PD  
3 V. This is the time from a rising edge on the  
pin to when  
the output voltage deviates from its power-down voltage. See  
Figure 31.  
AD5347  
X
X
X
X
BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
SUGGESTED DATA BUS FORMATS  
AD5348  
In many applications, the GAIN and BUF pins are hardwired.  
However, if more flexibility is required, they can be included in  
a data bus. This enables the user to software program GAIN,  
giving the option of doubling the resolution in the lower half of  
the DAC range. In a bused system, GAIN and BUF may be  
treated as data inputs because they are written to the device  
X
X
BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
X = UNUSED BIT  
Figure 40. AD5347/AD5348 Data Format for Word Load with  
GAIN and BUF Data on 16-Bit Bus  
LDAC  
during a write operation and take effect when  
is taken  
low. This means that the reference buffers and the output  
amplifier gain of multiple DAC devices can be controlled using  
common GAIN and BUF lines. Note that GAIN and BUF are  
RD  
not read back during an  
operation.  
Table 8. AD5346/AD5347/AD5348 Truth Table  
CLR  
LDAC  
CS  
WR  
RD  
A2  
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
A1  
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
A0  
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
Function  
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
0
X
1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
X
1
X
X
1
X
1
No Data Transfer  
No Data Transfer  
Clear All Registers  
Load DAC A Input Register  
Load DAC B Input Register  
Load DAC C Input Register  
Load DAC D Input Register  
Load DAC E Input Register  
Load DAC F Input Register  
Load DAC G Input Register  
Load DAC H Input Register  
Read Back DAC Register A  
Read Back DAC Register B  
Read Back DAC Register C  
Read Back DAC Register D  
Read Back DAC Register E  
Read Back DAC Register F  
Read Back DAC Register G  
Read Back DAC Register H  
Update DAC Registers  
Invalid Operation  
0→1  
0→1  
0→1  
0→1  
0→1  
0→1  
0→1  
0→1  
1
1
1
1
1
1
1
1
1→0  
1→0  
1→0  
1→0  
1→0  
1→0  
1→0  
1→0  
1
1
1
1
1
1
1
1
X
0
0
X = Don’t Care  
Rev. 0 | Page 18 of 24  
 
 
AD5346/AD5347/AD5348  
APPLICATIONS INFORMATION  
TYPICAL APPLICATION CIRCUITS  
BIPOLAR OPERATION USING THE  
AD5346/AD5347/AD5348  
The AD5346/AD5347/AD5348 can be used with a wide range  
of reference voltages, especially if the reference inputs are  
configured as unbuffered, in which case the devices offer full,  
one-quadrant multiplying capability over a reference range of  
0.25 V to VDD. More typically, these devices may be used with a  
fixed, precision reference voltage. Figure 41 shows a typical  
setup for the devices when using an external reference  
connected to the reference inputs. Suitable references for 5 V  
operation are the AD780, ADR381, and REF192 (2.5 V refer-  
ences). For 2.5 V operation, suitable external references are the  
AD589 and the AD1580 (1.2 V band gap references).  
The AD5346/AD5347/AD5348 have been designed for single-  
supply operation, but a bipolar output range is also possible by  
using the circuit shown in Figure 43. This circuit has an output  
voltage range of 5 V. Rail-to-rail operation at the amplifier  
output is achievable using an AD820, an AD8519, or an OP196  
as the output amplifier.  
5V  
R4  
20kΩ  
0.1µF  
10µF  
+5V  
R3  
10kΩ  
V
= 2.5V to 5.5V  
DD  
V
±5V  
IN  
V
DD  
EXT  
REF  
AD820/AD8519/  
OP196  
V
*
V
REF  
OUT  
0.1µF  
10µF  
–5V  
0.1µF  
AD5346/AD5347/  
AD5348  
GND  
R1  
10kΩ  
V
IN  
V
*
OUT  
V
DD  
EXT  
REF  
V
V
*
R2  
20kΩ  
OUT  
REF  
V
*
OUT  
GND  
AD5346/AD5347/  
AD5348  
*ONLY ONE CHANNEL OF V  
REF  
AND V  
SHOWN  
OUT  
AD780/ADR381/REF192  
WITH V = 5V  
DD  
OR AD589/AD1580 WITH  
GND  
Figure 43. Bipolar Operation with the AD5346/ AD5347/AD5348  
V
= 2.5V  
DD  
*ONLY ONE CHANNEL OF V  
AND V  
SHOWN  
REF  
OUT  
The output voltage for any input code can be calculated as  
follows:  
Figure 41. AD5346/AD5347/AD5348 Using an External Reference  
VOUT = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] –  
R4 × VREF/R3  
DRIVING VDD FROM THE REFERENCE VOLTAGE  
If an output range of 0 V to VDD is required, the simplest  
solution is to connect the reference inputs to VDD. Because this  
supply may not be very accurate and may be noisy, the devices  
can be powered from the reference voltage, for example, by  
using a 5 V reference such as the ADM663 or ADM666, as  
shown in Figure 42.  
where:  
D is the decimal equivalent of the code loaded to the DAC.  
N is the DAC resolution.  
VREF is the reference voltage input.  
with:  
6V TO 16V  
VREF = 5 V  
10µF  
0.1µF  
R1 = R3 = 10 kΩ  
R2 = R4 = 20 kΩ  
VDD = 5 V  
V
IN  
ADM663/ADM666  
GAIN = 2  
V
V
SENSE  
EXT  
DD  
V
*
REF  
V
OUT  
*
OUT(2)  
REF  
VOUT = (10 × D/2N) – 5  
0.1µF  
VSET GND SHDN  
AD5346/AD5347/  
AD5348  
GND  
*ONLY ONE CHANNEL OF V  
AND V  
SHOWN  
OUT  
REF  
Figure 42. Using an ADM663/ADM666 as Power and  
Reference to the AD5346/AD5347/AD5348  
Rev. 0 | Page 19 of 24  
 
 
 
 
AD5346/AD5347/AD5348  
5V  
DECODING MULTIPLE AD5346/AD5347/AD5348s  
0.1µF  
10µF  
1kΩ  
1kΩ  
V
IN  
FAIL  
PASS  
CS  
The  
decode a number of DACs. In this application, all DACs in the  
WR CS  
to  
pin on these devices can be used in applications to  
V
DD  
V
V
AB  
REF  
REF  
V
A
OUT  
system receive the same data and  
one of the DACs will be active at any one time, so data will only  
CS  
pulses, but only the  
PASS/  
FAIL  
1/2  
CMP04  
AD5346/AD5347/  
AD5348  
be written to the DAC whose  
is low.  
V
B
OUT  
1/6 74HC05  
GND  
The 74HC139 is used as a 2-line to 4-line decoder to address  
any of the DACs in the system. To prevent timing errors from  
occurring, the enable input should be brought to its inactive  
state while the coded address inputs are changing state.  
Figure 44 shows a diagram of a typical setup for decoding  
multiple devices in a system. Once data has been written  
sequentially to all DACs in a system, all the DACs can be  
Figure 45. Programmable Window Detector  
PROGRAMMABLE CURRENT SOURCE  
Figure 46 shows the AD5346/AD5347/AD5348 used as the  
control element of a programmable current source. In this  
example, the full-scale current is set to 1 mA. The output  
voltage from the DAC is applied across the current setting  
resistor of 4.7 kΩ in series with the 470 Ω adjustment  
potentiometer, which gives an adjustment of about 5%.  
Suitable transistors to place in the feedback loop of the ampli-  
fier include the BC107 and the 2N3904, which enable the  
current source to operate from a minimum VSOURCE of 6 V. The  
operating range is determined by the operating characteristics  
of the transistor. Suitable amplifiers include the AD820 and the  
OP295, both having rail-to-rail operation on their outputs. The  
current for any digital input code and resistor value can be  
calculated as follows:  
LDAC  
updated simultaneously using a common  
line. A com-  
CLR  
mon  
line can also be used to reset all DAC outputs to 0 V.  
AD5346/AD5347  
A0  
/AD5348  
A0  
A1  
A2  
A1  
A2  
WR  
LDAC  
CLR  
WR  
LDAC  
CLR  
CS  
DATA  
INPUTS  
AD5346/AD5347  
/AD5348  
A0  
A1  
A2  
WR  
DATA  
LDAC  
CLR  
CS  
INPUTS  
V
DD  
D
I = G ×VREF (2N × R)  
mA  
V
CC  
1G  
1A  
1B  
AD5346/AD5347  
1Y0  
1Y1  
1Y2  
ENABLE  
CODED  
/AD5348  
A0  
A1  
A2  
where:  
74HC139  
DGND  
ADDRESS  
WR  
LDAC  
CLR  
CS  
DATA  
INPUTS  
1Y3  
G is the gain of the buffer amplifier (1 or 2).  
D is the digital input code.  
N is the DAC resolution (8, 10, or 12 bits).  
R is the sum of the resistor plus adjustment potentiometer in kΩ.  
AD5346/AD5347  
/AD5348  
A0  
A1  
A2  
WR  
LDAC  
CLR  
CS  
DATA  
INPUTS  
V
= 5V  
DD  
0.1µF  
0.1µF  
10µF  
Figure 44. Decoding Multiple DAC Devices  
V
SOURCE  
AD5346/AD5347/AD5348 AS DIGITALLY  
PROGRAMMABLE WINDOW DETECTORS  
V
IN  
5V  
LOAD  
V
DD  
EXT  
REF  
V
V
*
V
*
OUT  
OUT  
REF  
A digitally programmable upper/lower limit detector using two  
of the DACs in the AD5346/AD5347/AD5348 is shown in  
Figure 45. Any pair of DACs in the device may be used, but for  
simplicity the description refers to DACs A and B.  
AD5346/AD5347/  
AD5348  
GND  
4.7kΩ  
470Ω  
The upper and lower limits for the test are loaded to DACs A  
and B which, in turn, set the limits on the CMP04. If a signal at  
the VIN input is not within the programmed window, an LED  
indicates the fail condition.  
GND  
*ONLY ONE CHANNEL OF V  
AND V  
SHOWN  
REF  
OUT  
Figure 46. Programmable Current Source  
Rev. 0 | Page 20 of 24  
 
 
 
 
AD5346/AD5347/AD5348  
COARSE AND FINE ADJUSTMENT USING  
THE AD5346/AD5347/AD5348  
POWER SUPPLY BYPASSING AND GROUNDING  
In any circuit where accuracy is important, careful consideration  
of the power supply and ground return layout helps to ensure  
the rated performance.  
Two of the DACs in the AD5346/AD5347/AD5348 can be  
paired together to form a coarse and fine adjustment function,  
as shown in Figure 47. As with the window comparator  
previously described, the description refers to DACs A and B.  
The printed circuit board on which the AD5346/AD5347/  
AD5348 is mounted should be designed so that the analog and  
digital sections are separated and are confined to certain areas  
of the board. This facilitates the use of ground planes that can  
be separated easily. A minimum etch technique is generally best  
for ground planes because it gives the best shielding. Digital and  
analog ground planes should be joined in one place only. If the  
AD5346/AD5347/AD5348 is the only device requiring an  
AGND-to-DGND connection, then the ground planes should  
be connected at the AGND and DGND pins of the AD5346/  
AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a  
system where multiple devices require AGND-to-DGND  
connections, the connection should be made at one point only, a  
star ground point that should be established as close as possible  
to the AD5346/AD5347/AD5348.  
DAC A provides the coarse adjustment, while DAC B provides  
the fine adjustment. Varying the ratio of R1 and R2 changes the  
relative effect of the coarse and fine adjustments. With the  
resistor values shown, the output amplifier has unity gain for  
the DAC A output, so the output range is 0 V to (VREF – 1 LSB).  
For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B  
a range equal to 2 LSBs of DAC A.  
The circuit is shown with a 2.5 V reference, but reference  
voltages up to VDD may be used. The op amps indicated allow a  
rail-to-rail output swing.  
V
= 5V  
DD  
R4  
R3  
390Ω  
51.2kΩ  
0.1µF  
10µF  
5V  
The AD5346/AD5347/AD5348 should have ample supply  
bypassing of 10 µF in parallel with 0.1 µF on the supply located  
as close to the package as possible, ideally right up against the  
device. The 10 µF capacitors are the tantalum bead type. The  
0.1 µF capacitor should have low effective series resistance  
(ESR) and effective series inductance (ESI), such as the  
common ceramic types that provide a low impedance path to  
ground at high frequencies to handle transient currents due to  
internal logic switching.  
V
DD  
V
V
OUT  
IN  
V
A
OUT  
EXT  
REF  
R1  
390Ω  
V
V
AB  
OUT  
REF  
0.1µF  
AD5346/AD5347/  
AD5348  
GND  
R2  
51.2kΩ  
V
B
OUT  
AD780/ADR381/REF192  
WITH V = 5V  
DD  
GND  
Figure 47. Coarse and Fine Adjustment  
The power supply lines of the device should use the largest trace  
possible to provide low impedance paths and to reduce the  
effects of glitches on the power supply line. Fast switching  
signals such as clocks should be shielded with digital ground to  
avoid radiating noise to other parts of the board, and should  
never be run near the reference inputs. Avoid crossover of  
digital and analog signals. Traces on opposite sides of the board  
should run at right angles to each other to reduce the effects of  
feedthrough through the board. A microstrip technique is by far  
the best, but not always possible with a double-sided board. In  
this technique, the component side of the board is dedicated to  
ground plane, while signal traces are placed on the solder side.  
Rev. 0 | Page 21 of 24  
 
 
AD5346/AD5347/AD5348  
Table 9. Overview of AD53xx Parallel Devices  
Additional Pin Functions  
BUF GAIN HBEN CLR  
Part No.  
SINGLES  
AD5330  
AD5331  
AD5340  
AD5341  
DUALS  
AD5332  
AD5333  
AD5342  
AD5343  
QUADS  
AD5334  
AD5335  
AD5336  
AD5344  
OCTALS  
AD5346  
AD5347  
AD4348  
Resolution  
DNL  
VREF Pins  
Settling Time  
Package  
Pins  
8
0.25  
1
1
1
1
6 µs  
7 µs  
8 µs  
8 µs  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
20  
20  
24  
20  
9
9
9
9
9
9
9
9
9
10  
12  
12  
0.5  
1.0  
1.0  
9
9
9
8
0.25  
0.5  
1.0  
2
2
2
1
6 µs  
7 µs  
8 µs  
8 µs  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
20  
24  
28  
20  
9
9
9
9
10  
12  
12  
9
9
9
9
1.0  
9
9
8
0.25  
0.5  
0.5  
2
2
4
4
6 µs  
7 µs  
7 µs  
8 µs  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
24  
24  
28  
28  
9
9
9
9
9
10  
10  
12  
1.0  
8
10  
12  
0.25  
0.5  
1.0  
4
4
4
6 µs  
7 µs  
8 µs  
TSSOP, LFCSP  
TSSOP, LFCSP  
TSSOP, LFCSP  
38, 40  
38, 40  
38, 40  
9
9
9
9
9
9
9
9
9
Table 10. Overview of AD53xx Serial Devices  
Part No.  
SINGLES  
AD5300  
AD5310  
AD5320  
AD5301  
AD5311  
AD5321  
DUALS  
AD5302  
AD5312  
AD5322  
AD5303  
AD5313  
AD5323  
QUADS  
AD5304  
AD5314  
AD5324  
AD5305  
AD5315  
AD5325  
AD5306  
AD5316  
AD5326  
AD5307  
AD5317  
AD5327  
OCTALS  
AD5308  
AD5318  
AD5328  
Resolution  
DNL  
VREF Pins  
Settling Time  
Interface  
Package  
Pins  
8
0.25  
0 (VREF = VDD)  
0 (VREF = VDD)  
0 (VREF = VDD)  
0 (VREF = VDD)  
0 (VREF = VDD)  
0 (VREF = VDD)  
4 µs  
6 µs  
8 µs  
6 µs  
7 µs  
8 µs  
SPI®  
SPI  
SPI  
2-Wire  
2-Wire  
2-Wire  
SOT-23, MSOP  
SOT-23, MSOP  
SOT-23, MSOP  
SOT-23, MSOP  
SOT-23, MSOP  
SOT-23, MSOP  
6, 8  
6, 8  
6, 8  
6, 8  
6, 8  
6, 8  
10  
12  
8
10  
12  
0.5  
1.0  
0.25  
0.5  
1.0  
8
0.25  
0.5  
1.0  
0.25  
0.5  
1.0  
2
2
2
2
2
2
6 µs  
7 µs  
8 µs  
6 µs  
7 µs  
8 µs  
SPI  
SPI  
SPI  
SPI  
SPI  
SPI  
MSOP  
MSOP  
MSOP  
TSSOP  
TSSOP  
TSSOP  
8
8
8
16  
16  
16  
10  
12  
8
10  
12  
8
0.25  
0.5  
1.0  
0.25  
0.5  
1.0  
0.25  
0.5  
1.0  
0.25  
0.5  
1.0  
1
1
1
1
1
1
4
4
4
2
2
2
6 µs  
7 µs  
8 µs  
6 µs  
7 µs  
8 µs  
6 µs  
7 µs  
8 µs  
6 µs  
7 µs  
8 µs  
SPI  
SPI  
SPI  
2-Wire  
2-Wire  
2-Wire  
2-Wire  
2-Wire  
2-Wire  
SPI  
MSOP  
MSOP  
MSOP  
MSOP  
MSOP  
MSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
10  
10  
10  
10  
10  
10  
16  
16  
16  
16  
16  
16  
10  
12  
8
10  
12  
8
10  
12  
8
10  
12  
SPI  
SPI  
8
10  
12  
0.25  
0.5  
1.0  
2
2
2
6 µs  
7 µs  
8 µs  
SPI  
SPI  
SPI  
TSSOP  
TSSOP  
TSSOP  
16  
16  
16  
Rev. 0 | Page 22 of 24  
AD5346/AD5347/AD5348  
OUTLINE DIMENSIONS  
9.80  
9.70  
9.60  
38  
20  
19  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
1.20  
MAX  
0.15  
0.05  
8°  
0°  
0.50  
BSC  
0.27  
0.17  
0.70  
0.60  
0.45  
SEATING  
PLANE  
0.20  
0.09  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153BD-1  
Figure 48. 38-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-38)  
Dimensions shown in millimeters  
6.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
31  
30  
40  
1
PIN 1  
INDICATOR  
0.50  
BSC  
4.25  
TOP  
VIEW  
5.75  
BSC SQ  
BOTTOM  
VIEW  
4.10 SQ  
3.95  
0.50  
0.40  
0.30  
21  
20  
10  
11  
0.25 MIN  
4.50  
REF  
12° MAX  
0.80 MAX  
0.65 TYP  
0.05 MAX  
0.02 NOM  
1.00  
0.85  
0.80  
0.30  
0.23  
0.18  
COPLANARITY  
0.08  
0.20 REF  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2  
Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP]  
(CP-40)  
Dimensions shown in millimeters  
Rev. 0 | Page 23 of 24  
 
AD5346/AD5347/AD5348  
ORDERING GUIDES  
Table 11. AD5346 Ordering Guide  
Model  
Temperature Range  
Package Description  
Package Option  
RU-38  
RU-38  
RU-38  
CP-40  
AD5346BRU  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
AD5346BRU-REEL  
AD5346BRU-REEL7  
AD5346BCP  
AD5346BCP-REEL  
AD5346BCP-REEL7  
CP-40  
CP-40  
Table 12. AD5347 Ordering Guide  
Model  
Temperature Range  
Package Description  
Package Option  
RU-38  
RU-38  
RU-38  
CP-40  
AD5347BRU  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
AD5347BRU-REEL  
AD5347BRU-REEL7  
AD5347BCP  
AD5347BCP-REEL  
AD5347BCP-REEL7  
CP-40  
CP-40  
Table 13. AD5348 Ordering Guide  
Model  
Temperature Range  
Package Description  
Package Option  
RU-38  
RU-38  
RU-38  
CP-40  
AD5348BRU  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +105°C  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
TSSOP (Thin Shrink Small Outline Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
LFCSP (Lead Frame Chip Scale Package)  
AD5348BRU-REEL  
AD5348BRU-REEL7  
AD5348BCP  
AD5348BCP-REEL  
AD5348BCP-REEL7  
CP-40  
CP-40  
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
C03331–0–11/03(0)  
Rev. 0 | Page 24 of 24  
 

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