AD53522JSQ_技术文档

High Speed

Dual Pin Electronic

a

AD53522

FEATURES

FUNCTIONAL BLOCK DIAGRAM (One-Half)

1000 MHz Toggle Rate

Driver/Comparator/Active Load and Dynamic Clamp

Included

Inhibit Mode Function

100-Lead LQFP Package with Built-In Heat Sink

Driver

48 ꢃ Output Resistance

800 ps Tr/Tf for a 3 V Step

Comparator

V

EE

CC

EE

VH

VTERM

DATA

DATAB

IOD

AD53522

VCH

VHDCPL

OUT

DRIVER

IODB

RLD

VLDCPL

VCL

1.1 ns Propagation Delay at 3 V

Load

RLDB

VL

ꢄ40 mA Voltage Programmable Current Range

50 ns Settling Time to 15 mV

PWRD

HCOMP

VCCO

QH

APPLICATIONS

Automatic Test Equipment

Semiconductor Test Systems

Board Test Systems

QHB

COMPARATOR

Instrumentation and Characterization Equipment

QL

QLB

LCOMP

PRODUCT DESCRIPTION

The AD53522 is a complete, high speed, single-chip solution

that performs the pin electronics functions of driver, comparator,

and active load (DCL) for ATE applications. In addition, the

driver contains a dynamic clamp function and the active load

contains an integrated Schottky diode bridge.

VCOM

IOLC

+1

VCOM_S

V/I

IOXRTN

ACTIVE LOAD

The driver is a proprietary design that features three active states:

Data High mode, Data Low mode, and Term mode, as well as

an Inhibit State. In conjunction with the integrated dynamic

clamp, this facilitates the implementation of a high speed active

termination. The output voltage range is –0.5 V to +6.5 V to

accommodate a wide variety of test devices.

PROT_LO

PROT_HI

INHL

INHLB

THERM*

IOHC

V/I

1.0ꢀA/ꢁK

DR_GND GND_ROT PWRGND HQGND THERMSTART

The dual comparator, with an input range equal to the driver

output range, features PECL compatible outputs. Signal tracking

capability is in the range of 3 V/ns.

ꢂ9

*ONLY 1 (ONE) THERM PER DEVICE

The active load can be set for up to 40 mA load current. I_OH, I_OL

and the buffered VCOM are independently adjustable. On-board

Schottky diodes provide high speed switching and low capacitance.

,

that is proportional to absolute temperature. The gain is trimmed

to a nominal value of 1.0 µA/K. As an example, the output current

can be sensed by using a 10 kΩ resistor connected from 10 V to

the THERM (I_OUT) pin. A voltage drop across the resistor will

be developed that equals 10 kΩ ϫ 1 µA/°K = 10 mV/°K = 2.98 V

at room temperature.

Also included is an on-board temperature sensor that gives an

indication of the silicon surface temperature of the DCL. This

information can be used to measure ␪_JCand ␪_JAor flag an alarm

if proper cooling is lost. Output from the sensor is a current sink

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD53522–SPECIFICATIONS

DRIVER¹(T_J= 85ꢁC ꢄ 5ꢁC, +V_S= +10.5 V ꢄ 1%, –V_S= –4.5 V ꢄ 1%, VCCO = 3.3 V, unless otherwise noted.)

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²

Max

Unit

DIFFERENTIAL INPUT CHARACTERISTICS

(DATA to DATAB, IOD to IODB, RLD to RLDB)

1

2

3

Voltage Range

Note: Inputs are from Same Logic

Type Family

Note: AC Tests Performed

0

+3.3

V

N

P

Differential Voltage with

LVPECL Levels

Bias Current

400

–250

600

1000

mV

µA

V

_IN= 1.5 V, 2.5 V

+250

+50

P

REFERENCE INPUTS

Bias Currents

4

Max Value Measured during

Linearity Tests

–50

µA

P

OUTPUT CHARACTERISTICS

Logic High Range

10

11

12

Data = H, VH = –0.4 V to +6.5 V,

Vl = –0.5 V (VT = 0 V, VH Meets

Test 20, 21, and 22 Specs)

Data = L, VL = –0.5 V to +6.4 V,

VH = 6.5 V (VT = 0 V, VL Meets

Test 30, 31, and 32 Specs)

VL = –0.05 V, VH = +0.05 V,

VT = 0 V and VL = –0.5 V,

VH = +6.5 V, VT = 0 V

–0.4

–0.5

+0.1

+6.5

+6.4

+7.0

V

P

Logic Low Range

Amplitude [VH–VL]

ABSOLUTE ACCURACY

VH Offset

20

21

22

30

31

32

33

Data = H, VH = 0 V, VL = –0.5 V,

VT = +3 V

Data = H, VH = –0.4 V to +6.5 V,

VL = –0.5 V, VT = +3 V

Data = H, VH = –0.4 V to +6.5 V,

VL = –0.5 V, VT = +3 V

–50

–0.3

–5

+50

+0.3

+5

mV

P

N

VH Gain Error

% of VH

mV

Linearity Error

VL Offset

Data = L, VL = 0 V, VH = +6.5 V,

VT = +3 V

–50

–0.3

–5

+50

+0.3

+5

mV

VL Gain Error

Data = L, VL = –0.5 V to +6.4 V,

VH = +6.5 V, VT = +3 V

Data = L, VL = –0.5 V to +6.4 V,

VH = +6.5 V, VT = +3 V

VL = 0 V, VH = +5 V, VT = 0 V

% of VL

mV

Linearity Error

Offset Temperature Coefficient

+0.5

mV/°C

OUTPUT RESISTANCE

VH = –0.3 V

40

41

42

43

44

50

51

52

VL = –0.5 V, VT = 0 V, I_OUT= +1,

+30 mA

VL = –0.5 V, VT = 0 V, I_OUT= –1,

–30 mA

VH = +6.5 V, VT = 0 V, I_OUT= +1,

+30 mA

VH = +6.5 V, VT = 0 V, I_OUT= –1,

–30 mA

VL = 0 V, VT = 0 V, I_OUT= –30 mA

(Trim Point)

Cbyp = 39 nF, VH = +6.5 V,

VL = –0.5 V, VT = 0 V

+46

+50

Ω

N

P

VH = +6.5 V

Ω

VL = –0.5 V

Ω

P

VL = +6.4 V

Ω

N

P

VH = +2.5 V

+47.5

Ω

Dynamic Current Limit

Static Current Limit

+100

–120

+60

mA

N

P

Output to –0.5 V, VH = +6.5 V,

VL = –0.5 V, VT = 0 V, DATA = H

Output to +6.5 V, VH = +6.5 V,

VL = –0.5 V, VT = 0 V, DATA = L

–60

+120

P

–2–

REV. A

AD53522

DRIVER¹(continued)

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²

Max

Unit

VTERM

60

Voltage Range

Term Mode, VTERM = –0.3 V

to +6.3 V, VL = 0 V, VH = +3 V

(VTERM Meets Test 61, 62, and 63 specs)

Term Mode, VTERM = 0 V,

–0.3

+6.3

V

P

61

62

63

VTERM Offset

–50

–0.3

–5

+50

+0.3

+5

mV

P

VL = 0 V, VH = +3 V

VTERM Gain Error

VTERM Linearity Error⁴

Term Mode, VTERM = –0.3 V

to +6.3 V, VL = 0 V, VH = +3 V

Term Mode, VTERM = –0.3 V

to +6.3 V, VL = 0 V, VH = +3 V

VTERM = 0 V, VL = 0 V, VH = +3 V

% of V_SET

mV

P

64

70

Offset Temperature Coefficient

Output Resistance DC

+0.5

mV/°C

Ω

N

I

_OUT= +30 mA, –1 mA,

VTERM = –0.3 V, VH = +3 V, VL = 0 V

_OUT= –30 mA, +1 mA,

VTERM =+6.3 V, VH = +3 V, VL = 0 V

I_OUT30 mA, 1 mA,

+46

+50

I

=

VTERM = +2.5 V, VH = +3 V, VL = 0 V

+V_S, –V_S1%

Output to –0.3 V, VTERM = +6.3 V

P

N

P

72

73

74

PSRR, Drive, or Term Mode

Static Current Limit

+17.8

mV/V

mA

–120

+60

–60

+120

Output to +6.3 V, VTERM = –0.3 V

DYNAMIC PERFORMANCE, DRIVE (VH and VL)

80

81

82

Propagation Delay Time

Measured at 50%, VL = 0 V,

1.25

1.4

2

1.55

200

ns

P

VH = 3 V, into 500 Ω

Propagation Delay T.C.

Measured at 50%, VL = 0 V,

VH = 3 V, into 500 Ω

ps/°C

ps

N

P

Delay Matching, Edge-to-Edge

Measured at 50%, VL = 0 V,

VH = 3 V, into 500 Ω

RISE AND FALL TIMES

200 mV Swing

90

Measured 20%–80%, VL = –0.1 V,

VH = +0.1 V, into 50 Ω

0.25

0.3

ns

N

P

91

1 V Swing

3 V Swing

5 V Swing

Measured 20%–80%, VL = 0 V,

VH = 1 V, into 50 Ω

92

Measured 10%–90%, VL = 0 V,

VH = 3 V, into 50 Ω

0.8

93

Measured 10%–90%, VL = 0 V,

VH = 3 V, into 500 Ω

0.8

93A

94

Measured 20%–80%, VL = 0 V,

VH = 3 V, into 500 Ω

0.450

0.560

1.2

0.670

1.5

Measured 10%–90%, VL = 0 V,

VH = 5 V, into 500 Ω

N

RISE AND FALL TIME TEMPERATURE COEFFICIENT

100

101

102

110

1 V Swing

3 V Swing

5 V Swing

Overshoot and Preshoot

(Per Test 91)

(Per Test 92)

(Per Test 94)

VL, VH = –0.1 V, +0.1 V,

Driver Terminated into 50 Ω

VL, VH = 0.0 V, 3 V,

Driver Terminated into 50 Ω

2

4

ps/°C

N

0 – 50

0 + 50

% of Step N

+ mV

–6.0 – 50

+6.0 + 50 % of Step N

+ mV

SETTLING TIME

to 15 mV

120

VL = 0 V, VH = 0.5 V,

50

ns

N

Driver Terminated into 50 Ω

121

130

to 4 mV

Delay Change vs. Pulse Width

VL = 0 V, VH = 0.5 V

10

25

µs

ps

N

VL/VH = 0/3, PW = 2.5 ns/7.5 ns,

30 ns/90 ns, DC = 25%

75

131

Delay Change vs. Duty Cycle

VL = 0 V, VH = 3 V, Duty Cycle

25

ps

N

(DC) 5% to 95%, T = 40 ns

–3–

REV. A

AD53522

SPECIFICATIONS (continued)

DRIVER¹(continued)

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²

Max

Unit

MINIMUM WIDTH PULSE

140

141

142

1 V Swing

3 V Swing

Toggle Rate

Measured at 50% point width

0.6

ns

N

V

_OUTAC Swing = 0.9 ꢂ V_OUTDC

Swing Terminated, 50 Ω Load on

Transmission Line

VH = 1 V, VL = 0 V, Terminated

to 50 Ω,V_OUT> 300 mV p-p

1.5

ns

1000

MHz

DYNAMIC PERFORMANCE, INHIBIT

150

151

152

153

Delay Time, Active to Inhibit

Measured at 50%, VH = 4 V,

VL = 0 V, VTT = 2

Measured at 50%, VH = 4 V,

VL = 0 V, VTT = 2

Measured at 50%, VH = 4 V,

VL = 0 V, VTT = 2

Measured at 50%, VH = 4 V,

VL = 0 V, VTT = 2

1.7

150

2.0

2.2

250

ns

ps

P

Delay Time, Inhibit to Active

Delay Time Matching,

Inhibit to Active

Delay Time Matching,

Active to Inhibit

160

170

I/O Spike

Rise, Fall Time, Active to Inhibit

VH = 0 V, VL = 0 V

VL = 0 V, VTT = 2

200

1.2

mV p-p

ns

N

(20%–80% of 1 V Output)

VH = 4 V, VL = 0 V, VTT = 2

(20%–80% of 1 V Output)

171

Rise, Fall Time, Inhibit to Active

0.6

ns

N

DYNAMIC PERFORMANCE, VTERM

Delay Time, VH to VTERM

180

Measured at 50%, VL = VH = 2 V,

VTERM = 0 V, VTT = 0 V

Measured at 50%, VL = VH = 0 V,

VTERM = 2 V, VTT = 0 V

Measured at 50%, VL = VH = 2 V,

VTERM = 0 V, VTT = 0 V

Measured at 50%, VL = VH = 0 V,

VTERM = 2 V, VTT = 0 V

VH/VL, VTERM = (0 V, 2 V),

(0 V, 6 V)

1.5

1.6

1.9

2.0

ns

P

181

Delay Time, VL to VTERM

Delay Time, VTERM to VH

Delay Time, VTERM to VL

Overshoot and Preshoot

182

183

190

–6.0 + 50

+6.0 + 50 % of Step N

+ mV

191A

191B

192A

192B

VTERM Rise Time, VL to VT,

Normal Mode

VTERM Rise Time, VT to VH,

Normal Mode

VTERM Fall Time, VT to VL,

Normal Mode

VTERM Fall Time, VH to VT,

VL, VH = 0 V, VTERM = 2 V,

20%–80%

VL, VH = 2 V, VTERM = 0 V,

20%–80%

VL, VH = 0 V, VTERM = 2 V,

20%–80%

1.0

0.6

1.0

ns

N

VL, VH = 2V, VTERM = 0 V,

Normal Mode

20%–80%

–4–

REV. A

AD53522

COMPARATOR¹

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²Max

Unit

DC INPUT CHARACTERISTICS

VCCO Range

Offset Voltage (V_OS

Offset Voltage Drift

HCOMP, LCOMP

200

201

202

203

+2.0

–25

+4.5

+25

V

N

P

N

)

Common-Mode Voltage = 0 V

Over Linearity Range

mV

µV/°C

µA

+50

–50

+50

P

BIAS CURRENTS

Voltage Range (V_CM

Differential Voltage (V_DIFF

Gain Error

Linearity Error

Extended Range Operation

206

207

208

209

210

)

–0.5

+6.5

+7

0.0

V

P

N

P

)

V

_IN= –0.5 V to +6.5 V

–0.25

–2

%FSR

mV

V

+2

HCOMP, LCOMP = –1, Output –1.0

Toggle V_OUTfrom –0.9 V to –1.1 V

DIGITAL OUTPUTS

Logic 1 Voltage Q

220

221

222

225

Q or QB, 150 Ω to GND,

150 Ω from Q to QB

VCCO – 1.05

VCCO – 0.85

V

ps

P

N

Logic 0 Voltage QB

Logic Differential, Q–QB

Slew Rate

Q or QB, 150 Ω to GND,

150 Ω from Q to QB

VCCO – 2.2

0.65

VCCO – 1.5

1.15

Q or Qb, 150 Ω to GND,

150 Ω from Q to QB

Q or QB (20% – 80% of output,

150 Ω from Q to QB)

0.9

380

CHANNEL COMPARATOR SWITCHING PERFORMANCE

PROPAGATION DELAY^{5, 6, 7}

240

241

Input to Output

V_IN= 3 V p-p, 2 V/ns

0.7

1.1

ns

ps/°C

P

N

Propagation Delay Tempco

Prop Delay Change with respect to:

Slew Rate: 1, 2, 3 V/ns

Amplitude: 500 mV, 1.0 V, 3.0 V

Equivalent Input Rise Time

V

_IN= 3 V p-p, 2 V/ns

1.0

250

260

270

V

_IN= 0 V to 3 V

_IN= 1.0 V/ns

_IN= 0 V to 2 V, < 80 ps,

120

100

275

ps

N

20%–80% Rise Time

Driver in VTERM = 0 V

280

281

Pulse Width Linearity

Settling Time

V

_IN= 0 V to 3 V, 2 V/ns, PW =

50

ps

ns

N

3, 4, 5, 10 ns, Driver Hi-Z mode

Settling to 8 mV, V_IN= 0 V to

3 V, Driver Hi-Z mode

25

6

282

290

Hysteresis

Comparator Propagation Delay

Matching, HCOMP to LCOMP

mV

ps

N

P

V

_IN= 0 V to 3 V, 2 V/ns

125

INPUT CHARACTERISTICS (INHL, INHLB)

See Driver Spec No. 1

300

301

302

Input Voltage

VIOH = 1 V, VIOL = 1 V,

VCOM = 2 V, VDUT = 0 V

INHL, INHLB = 0 V, 3.3 V,

AC Tests 0.2 V and 0.8 V

VDUT = 0.8 V, 6.5 V

0

+3.3

+250

+4.0

V

P

INHL, INHLB Bias Current

–250

0

µA

V

VIOH Current Program Range,

IOH = 0 mA to –40 mA

–5–

REV. A

AD53522

SPECIFICATIONS (continued)

ACTIVE LOAD¹

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²

Max

Unit

303

304

305

310

311

312

VIOL Current Program Range,

IOL = 0 mA to 40 mA

VIOH, VIOL Input Bias Current

VDUT = –0.5 V, +5.2 V

VIOL = 0 V, 4 V and

VIOH = 0 V, 4 V

0

–300

4.0

+300 µA

V

P

IOXRTN Range

VDUT = –0.5 V, +6.5 V

VDUT Range

IOL = +40 mA, IOH = –40 mA,

–0.5, +6.5

V

N

P

IOL = +40 mA, IOH = –40 mA,

|VDUT – VCOM|> 1.3 V

VDUT – VCOM > 1.3 V

–0.5

+0.8

–0.5

+6.5

+5.2

V

VDUT Range,

IOH = 0 mA to –40 mA

VDUT Range,

VCOM – VDUT > 1.3 V

IOL = 0 mA to +40 mA

OUTPUT CHARACTERISTICS

Accuracy

320

321

Gain Error, Load Current,

Normal Range Calculated at

1 mA and 40 mA points²

IOL, IOH = 25 µA – 40 mA,

–0.35

+0.35 %I_SET

P

VCOM = 0 V, VDUT = 2 V, and

IOL = 25 µA to 40 mA, VCOM = +6.5 V,

VDUT = +5.2 V and IOH = 25 µA to

40 mA, VCOM = –0.5 V, VDUT = +0.8 V

Calculated from Intercept of 1 mA

and 40 mA Points

Load Offset

–300

–80

+300 µA

322

323

Load Nonlinearity

Output Current Tempco

IOL, IOH from 25 µA to 40 mA

Measured at IOH, IOL = 200 µA

+80

µA

P

N

<

3

µA/°C

324 IOH Extended Range

Driver Inhibited, IOH = 1 mA,

Change in IOH from VTT = 0 V to

VTT = –1.0 V

2

%

P

VCOM BUFFER

330

331

332

VCOM Buffer Offset Error

VCOM Buffer Bias Current

VCOM Buffer Gain Error

IOL, IOH = 40 mA, VCOM = 0 V

VCOM = 0 V

IOL, IOH = 40 mA,

–50

–20

–4

+50

+20

+4

mV

µA

%

P

VCOM = –0.5 V to +6.5 V

IOL, IOH = 40 mA,

333

VCOM Buffer Linearity Error

–10

+10

mV

P

VCOMI = –0.5 V to +6.5 V

DYNAMIC PERFORMANCE

Propagation Delay

340

341

342

350

360

361

I

_MAXto INHIBIT

VTT = +2 V, VCOM = +4 V/0 V,

IOL = +20 mA, IOH = –20 mA

VTT= +2 V, VCOM = +4 V/0 V,

IOL = +20 mA, IOH = –20 mA

Matching = (Test 340 Value) –

(Test 341 Value)

VCOM = 0 V, IOL = +20 mA,

IOH = –20 mA

IOL = +20 mA, IOH = –20 mA,

1.0

1.3

1.8

2.0

ns

mV

ns

µs

P

INHIBIT to I_MAX

Propagation Delay Matching

I/O Spike

1.2

2.4

P

–1.0

+1.0

P

250

50

N

Settling Time to 15 mV

Settling Time to 4 mV

50 Ω Load, to 15 mV

IOL = +20 mA, IOH = –20 mA,

50 Ω Load, to 4 mV

10

–6–

REV. A

AD53522

DYNAMIC CLAMP¹

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²Max

Unit

400

401

402

410

411

420

430

440

Input Voltage VCH

Input Voltage VCL

2

7.5

+4

+250

1.01

75

V

P

N

P

–1.5

–250

0.96

50

Input Bias Current VCH/VCL

VCH, VCL Offset Error

VCH, VCL Gain Error

Static Current Capability

Incremental Resistance

VCHP, VCLP Protection

Diodes Vf @ 500 µA

Overrange Spec 401, 402

µA

mV

V/V

mA

Ω

I

_TEST= 1 mA

I

_TEST= 1 mA

11 mA to 21 mA

45

0.52

48

52

0.64

V

441

Protection Diodes Max Current

For Information Only

2

mA

N

TOTAL FUNCTION

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²Max

Unit

500

501

503

504

PWRD Input Voltage

PWRD Bias Current

Power-Down Supply Reduction

Power-Down Output

Leakage Current

0

–250

35

5

V

µA

%

P

PWRD Trip Point 1.4 V 0.15 V

VIOH = 0 V, VIOL = 0 V

VIOH = 0 V, VIOL = 0 V,

+250

60

+20

–20

nA

V

_OUT= –0.5 V to +5.5 V

505

Power-Down Output

VIOH = 0 V, VIOL = 0 V,

–500

+500

nA

P

Leakage Current

V

_OUT= 5.5 V to 6.5 V

_OUT= –0.5 V to +6.5 V

_OUT= 0 V to 5 V

_OUT= –1 V

600

601

602

605

606

Output Leakage Current

Output Capacitance

–1

–500

–5

+1

+500

+5

µA

nA

µA

pF

P

N

Driver and Load Inhibited

9.2

2.5

Output Capacitance Term

Driver VTERM = 0 V, Load Inhibited

N

POWER SUPPLIES

Spec

Spec³

Perf

No. Parameter

Conditions

Min

Typ²Max

Unit

610

620

630

640

Total Supply Range

15

+10.5

–4.5

465

475

V

mA

N

P

Positive Supply, VCC

Negative Supply, VEE

Positive Supply Current, VCC

Driver = Inhibit, I_LOADProgram = 40 mA,

Load = Active

Driver = Inhibit, I_LOADProgram = 40 mA,

Load = Active

Driver = Inhibit, I_LOADProgram = 40 mA,

Load = Active (I_VCCO– (comparator

logic output currents))

570

600

45

650

651

Negative Supply Current, VEE

mA

P

Comparator Supply Current

Overhead, VCCO

660

Total Power Dissipation

Driver = Inhibit, I_LOADProgram = 40 mA,

Load = Active

Driver = Inhibit, I_LOADProgram = 40 mA, 0 mA

R_LOAD= 10 kΩ, V_SOURCE= 10.5 V

7.2

7.9

5.9

W

P

661

700

Total Power Dissipation

Temperature Sensor Gain Factor

5.2

1

W

µA/°K

P

N

NOTES

¹All temperature coefficients are measured at T_J= 75°C to 95°C. In test figures, voltmeter loading is 1 MΩ or greater, scope probe loading is 100 kΩ in parallel with 0.6 pF.

²Typical values are not tested or guaranteed. Nominal values are generated from design or simulation analyses and/or limited bench evaluations and are not tested or guaranteed.

³Spec Perf: N = Nominal, O = Operating Condition, T = Typical, P = Production, Max/Min.

⁴VTERM linearity over the following condition: VL – 6 V < VTERM < VH + 6 V.

⁵All ac input values are referred to the source end of transmission line input.

⁶All ac tests are performed with driver in VTERM mode except where noted.

⁷Rise time is calculated SQRT((comp out Tr)²– (comp in Tr)²).

Specifications are subject to change without notice.

–7–

REV. A

AD53522

ABSOLUTE MAXIMUM RATINGS¹

POWER SUPPLY VOLTAGE

V_CCto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 V

DATA to DATAB, IOD to IODB, RLD to RLDB . . . 3 V

INHL to INHLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

VH, VL, VTERM to GND (R_SERIES< 500 Ω) . +7.5 V, –1.1 V

VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V, –3.5 V

(VH – VTERM) and (VTERM – VL) . . . . . . . . . . . . . 8 V

Reflection Clamp High/Low . . . . . . . . . . . . . . . +8.5 V, –2 V

Protection Clamp Breakdown Voltage . . . . . . . . . . . . . . 12 V

Protection Clamp Current . . . . . . . . . . . . . . . . . . . . . 5 mA

V_OUTto HCOMP or LCOMP . . . . . . . . . . . . . . . . . . 7.8 V

ENVIRONMENTAL

V

_EEto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V

V_CCto V_EE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

VCCO to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

PWRGND, DRGND, GND_ROT, or HQGND . . . .

OUTPUTS

0.4 V

V_OUTShort Circuit Duration . . . . . . . . . . . . . . . . Indefinite²

V_OUT, Inhibit Mode . . . . . . . . . . . . . . . . . . . . . +8.5 V, –2 V

V_OUT, Inhibit Mode . . . . . VL – 5.5 V < V_OUT< VH + 5.5 V

VHDCPL . . . . . . . . Do Not Connect Except for Cap to V_CC

VLDCPL . . . . . . . . Do Not Connect Except for Cap to V_EE

Operating Temperature (Junction) . . . . . . . . . . . . . . . 175°C

Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec)³. . . . . . . . . . . 260°C

QH, QHB, QL, QLB Maximum I_OUT

:

NOTES

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Surge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V, 0 V

Driver Output Capacitance, Maximum . . . . . . . . . . . . 10 pF

INPUTS

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Absolute maximum limits apply

individually, not in combination. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

²Output short circuit protection is guaranteed as long as proper heat sinking is

employed to ensure compliance with the operating temperature limits.

³To ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare

hands should be avoided and the device should be stored in environments at 24°C

5°C (75°F 10°F) with relative humidity not to exceed 65%.

DATA, DATAB, IOD, IODB, RLD, RLDB

. . . . . . . . . . . . . . . . . . . . . . . . (V_CCO+ 1.5 V, V_CCO– 4.5 V)

INHL, INHLB, CMPD . . . . . . . . . . . . . . . –0.4 V to +5.5 V

PWRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +4.5 V

ORDERING GUIDE

Model

Temperature Range

0°C to 70°C

Package Description

Package Option

AD53522JSQ

100-Lead LQFP-EDQUAD

with Integral Heat Slug

SQ-100

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD53522 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

Table I. Driver Truth Table

Table II. Comparator Truth Table

Output States

Output

DATA DATAB IOD IODB RLD RLDB State

V_OUT

QH

QHB

QL

QLB

0

1

X

1

0

X

1

0

1

X

0

X

1

VL

VH

INH and

CLAMP

VTERM

> HCOMP > LCOMP

> HCOMP < LCOMP

< HCOMP > LCOMP

< HCOMP < LCOMP

1

0

1

0

1

0

1

0

1

X

0

1

0

Table III. Active Load Truth Table

Output States (Including Diode Bridge)

IOL I(V_OUT

VDUT

INHL INHLB IOH

)

<VCOM 0

>VCOM 0

1

0

V(IOHC) ϫ +10 mA V(IOLC) ϫ –10 mA IOL

V(IOHC) ϫ +10 mA V(IOLC) ϫ –10 mA IOH

X

1

0

–8–

REV. A

AD53522

PIN CONFIGURATION

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

PIN 1

IDENTIFIER

1

2

75 LCOMP1

PROT_HI1

IOXRTN1

VCH1

74

73

72

71

70

V

CC

3

V

CC

4

V

EE

VCL1

5

VHDCPL1

OUT1

V

EE

HEAT SLUG

6

QH1

7

69 QHB1

68 VCCO1

67 QLB1

66 QL1

VLDCPL1

PWRGND

DR_GND

PWRGND

GND_ROT

PWRGND

8

9

10

11

12

13

14

15

65

64

RLDB1

PWRD1

AD53522

63 GND_ROT

62 PWRD2

61 RLDB2

60 QL2

TOP VIEW

(Not to Scale)

DR_GND2 16

PWRGND 17

PWRGND 18

VLDCPL2 19

OUT2 20

59 QLB2

58 VCCO2

57 QHB2

56 QH2

VHDCPL2 21

VCL2 22

55

54

53

52

51

V

EE

V

EE

VCH2 23

V

CC

IOXRTN2 24

PROT_HI2 25

V

CC

LCOMP2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NOTE

DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG.

THE PACKAGE IS MOUNTED TO THE BOARD, HEAT SLUG UP.

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic

Description

1

2

3

4

5

PROT_HI1

IOXRTN1

VCH1

Channel 1, Output Voltage Sensing Diode.

Current Return Path for the Active Load for Channel 1. Typically connected to a power ground.

Analog Input Voltage that Sets the Reflection Clamp High Level of Channel 1.

VCL1

Analog Input Voltage that Sets the Reflection Clamp Low Level of Channel 1.

VHDCPL1

Internal Supply Decoupling for the Driver Output Stage of Channel 1. This pin needs to be connected to

V

_CCthrough a 39 nF (minimum) capacitor.

6

7

OUT1

Input/Output For The Driver, Window Comparator, Reflection Clamp, and Active Load of Channel 1.

VLDCPL1

Internal Supply Decoupling for the Driver Output Stage of Channel 1. This pin needs to be connected to

V_EEthrough a 39 nF (minimum) capacitor.

8, 9, 11, 12, 14, PWRGND

15, 17, 18, 27,

Power Ground.

28, 38, 44, 45,

81, 82, 88, 98, 99

10

DR_GND

Analog Ground.

REV. A

–9–

AD53522

Pin Number Mnemonic

Description

13

16

19

GND_ROT

DR_GND2

VLDCPL2

Analog Ground.

Internal Supply Decoupling for the Driver Output Stage of Channel 2. This pin needs to be connected to

V_EEthrough a 39 nF (minimum) capacitor.

20

21

OUT2

Input/Output for the Driver, Window Comparator, Reflection Clamp, and Active Load of Channel 2

VHDCPL2

Internal Supply Decoupling for the Driver Output Stage of Channel 2. This pin needs to be connected to

V

_CCthrough a 39 nF (minimum) capacitor.

22

23

24

25

26

29

30

31

32

33

34

35

VCL2

Analog Input Voltage that Sets the Reflection Clamp Low Level of Channel 2

Analog Input Voltage that Sets the Reflection Clamp High Level of Channel 2

Current Return Path for the Active Load for Channel 2. Typically connected to a power ground.

Channel 2, Output Voltage Sensing Diode.

VCH2

IOXRTN2

PROT_HI2

PROT_LO2

VCOM_S2

Channel 2, Output Voltage Sensing Diode.

Analog Output Voltage that Represents a Buffered VCOM1 Input

THERMSTART Temperature Sensor Startup Pin. Normally not connected.

IOLC2

IOHC2

HQGND

INHL2

INHLB2

V_EE

Analog Input Voltage that Programs the Channel 2 Active Load Source Current.

Analog Input Voltage that Programs the Channel 2 Active Load Sink Current.

Clean Analog Ground for the Active Load for Channel 2.

One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 2.

Negative Supply Terminal.

36, 54, 55,

71, 72, 90

37, 52, 53,

73, 74, 89

V_CC

Positive Supply Terminal.

39

40

41

42

43

RLD2

IOD2

One of Two Complementary Inputs that Control, in Conjunction with IOD2 and IODB2, the Operating

Mode of the Channel 2 Driver. Refer to Table I for specific conditions.

One of Two Complementary Inputs that Control, in Conjunction with RLD2 and RLDB2, the Operating

Mode of the Channel 2 Driver. Refer to Table I for specific conditions.

IODB2

DATA2

DATAB2

One of Two Complementary Inputs that Control, in Conjunction with RLD2 and RLDB2, the Operating

Mode of the Channel 2 Driver. Refer to Table I for specific conditions.

One of Two Complementary Inputs that Determine the High and Low State of the Channel 2 Driver.

Driver output is high for DATA2 > DATAB2. Refer to Table I for specific conditions.

One of Two Complementary Inputs that Determine the High and Low State of the Channel 2 Driver.

Driver output is high for DATA2 > DATAB2. Refer to Table I for specific conditions.

46

47

VCOM2

VH2

Analog Input Voltage that Establishes the Commutation Voltage for the Active Load Diode Bridge for Channel 2.

Analog Input Voltage that Sets the Logic 1 Level of the Driver Output Limit for Channel 2. Determines

the driver output for DATA2 > DATAB2.

48

49

VTERM2

VL2

Analog Input Voltage that Set the Termination Voltage Level of the Channel 2 Driver when in VTERM Mode.

Analog Input Voltage that Set the Logic 0 Level of the Driver Output Limit for Channel 2. Determines

the driver output for DATAB2 > DATA2.

50

51

56

57

58

HCOMP2

LCOMP2

QH2

Analog Input Voltage that Sets the Logic 1 Compare Reference for the Window Comparator of Channel 2.

Analog Input Voltage that Sets the Logic 0 Compare Reference for the Window Comparator of Channel 2.

One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.

QHB2

VCCO2

Input Supply Voltage for QH2, QHB2, QL2, and QLB2 Signals and Reference Voltage for DATA2, DATAB2,

IOD2, IODB2, RLD2, and RLDB2.

59

QLB2

One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 2.

–10–

REV. A

AD53522

Pin Number Mnemonic

Description

60

61

QL2

One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 2.

RLDB2

One of Two Complementary Inputs that Control, in Conjunction with IOD2 and IODB2, the Operating

Mode of the Channel 2 Driver. Refer to Table I for specific conditions.

62

63

64

65

PWRD2

GND_ROT

PWRD1

RLDB1

Power-Down Control for Channel 2.

Analog Ground.

Power-Down Control for Channel 1.

One of Two Complementary Inputs that Control, in Conjunction with IOD1 and IODB1, the Operating

Mode of the Channel 1 Driver.

66

67

68

QL1

One of Two Complementary Outputs for the Logic 0 Window Comparator of Channel 1.

QLB1

VCCO1

Input Supply Voltage for QH1, QHB1, QL1, and QLB1 Signals and Reference Voltage for DATA1,

DATAB1, IOD1, IODB1, RLD1, and RLDB1.

69

70

75

76

77

QHB1

One of Two Complementary Outputs for the Logic 1 Window Comparator of Channel 1.

Analog Input Voltage that Sets the Logic 0 Compare Reference for the Window Comparator of Channel 1.

Analog Input Voltage that Sets the Logic 1 Compare Reference for the Window Comparator of Channel 1.

QH1

LCOMP1

HCOMP1

VL1

Analog Input Voltage that Sets the Logic 0 Level of the Driver Output Limit for Channel 1. Determines

the driver output for DATAB1 > DATA1.

78

79

VTERM1

VH1

Analog Input Voltage that Sets the Termination Voltage Level of the Channel 1 Driver when in VTERM Mode.

Analog Input Voltage that Sets the Logic 1 Level of the Driver Output Limit for Channel 1. Determines

the driver output for DATA1 > DATAB1.

80

83

VCOM1

Analog Input Voltage that Establishes the Commutation Voltage for the Active Load Diode Bridge for Channel 1.

DATAB1

One of Two Complementary Inputs that Determine the High and Low State of the Channel 1 Driver.

Driver output is high for DATA1 > DATAB1. Refer to the Driver Truth Table for specific conditions.

84

85

86

87

DATA1

IODB1

IOD1

One of Two Complementary Inputs that Determine the High and Low State of the Channel 1 Driver.

Driver output is high for DATA1 > DATAB1. Refer to the Driver Truth Table for specific conditions.

One of Two Complementary Inputs that Control, in Conjunction with RLD1 and RLDB1, the Operating

Mode of the Channel 1 Driver. Refer to Table I for specific conditions.

One of Two Complementary Inputs that Control, in Conjunction with RLD1 and RLDB1, the Operating

Mode of the Channel 1 Driver. Refer to Table I for specific conditions.

RLD1

One of Two Complementary Inputs that Control, in Conjunction with IOD1 and IODB1, the Operating

Mode of the Channel 1 Driver. Refer to Table I for specific conditions.

91

92

93

94

95

96

INHLB1

INHL1

One of Two Complementary Inputs that Control the Inhibit Mode for the Active Load Bridge of Channel 1.

Clean Analog Ground for the Active Load for Channel 1.

HQGND

IOHC1

IOLC1

Analog Input Voltage that Programs the Channel 1 Active Load Sink Current.

Analog Input Voltage that Programs the Channel 1 Active Load Source Current.

THERM

Temperature Sensor Output Pin. A resistor (10 kΩ) should be connected between THERM and V_CC.

The approximate die temperature can be determined by measuring the current through the resistor. The

typical scale factor is 1 µA/°K.

97

VCOM_S1

Analog Output Voltage that Represents a Buffered VCOM1 Input.

Channel 1 Output Voltage Sensing Diode.

100

PROT_LO1

REV. A

–11–

AD53522

OUTLINE DIMENSIONS

100-Lead Low Profile Quad Flat Package, Integrated Heat Sink [LQFP-ED]

(SQ-100)

Dimensions shown in millimeters

16.00 BSC SQ

1.60 MAX

14.00 BSC SQ

0.75

0.60

0.45

100

1

76

75

PIN 1

SEATING

PLANE

9.78

9.65

9.40

12.00

REF

BOTTOM VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

VIEW A

7؇

3.5؇

0؇

0.15

0.05

0.08

50

25

MAX LEAD

26

49

COPLANARITY

0.27

0.22

0.17

0.50 BSC

VIEW A

ROTATED 90؇ CCW

COMPLIANT TO JEDEC STANDARDS MS-026BED-HU

Revision History

Location

Page

10/03—Data Sheet changed from REV. 0 to REV. A.

Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

–12–

REV. A


型号：	AD53522JSQ
厂家：	ADI
描述：	High Speed Dual Pin Electronic 高速双引脚电子电子
文件：	总12页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD53522JSQ [ADI]

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