AD5361BSTZ-REEL1_技术文档

16-Channel, 16-/14-Bit,

Serial Input, Voltage-Output DAC

AD5360/AD5361

SPI-compatible serial interface

FEATURES

2.5 V to 5.5 V digital interface

16-channel DAC in 52-lead LQFP and 56-lead LFCSP

packages

RESET

Digital reset (

)

Clear function to user-defined SIGGNDx

Simultaneous update of DAC outputs

Guaranteed monotonic to 16/14 bits

Nominal output voltage range of −10 V to +10 V

Multiple output spans available

Temperature monitoring function

Channel monitoring multiplexer

GPIO function

System calibration function allowing user-programmable

offset and gain

Channel grouping and addressing features

Data error checking feature

APPLICATIONS

Instrumentation

Industrial control systems

Level setting in automatic test equipment (ATE)

Variable optical attenuators (VOA)

Optical line cards

FUNCTIONAL BLOCK DIAGRAM

DV_CC

V_DD

V_SS

AGND DGND

LDAC

TEMP

VREF0

TEMP_OUT

PEC

n = 16 FOR AD5360

n = 14 FOR AD5361

SENSOR

GROUP 0

BUFFER

8

CONTROL

REGISTER

14

n

14

n

OFFSET

DAC 0

OFS0

REGISTER

VOUT0 TO

VOUT15

8

n

8

A/B SELECT

REGISTER

TO

MON_IN0

MON_IN1

BUFFER

MUX 2s

6

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

n

X2A REGISTER

X2B REGISTER

DAC 0

REGISTER

MUX

n

A/B

MUX

2

DAC 0

X1 REGISTER

n

·

M REGISTER

C REGISTER

·

MON_OUT

n

·

2

GPIO

REGISTER

·

GPIO

BIN/2SCOMP

·

OUTPUT BUFFER

AND POWER-

n

X2A REGISTER

n

A/B

MUX

2

DAC 7

SYNC

SDI

X1 REGISTER

DOWN CONTROL

DAC 7

MUX

REGISTER

SIGGND0

VREF1

X2B REGISTER

n

SERIAL

INTERFACE

M REGISTER

C REGISTER

SCLK

SDO

GROUP 1

14

n

OFFSET

DAC 1

OFS1

REGISTER

BUSY

8

TO

MUX 2s

A/B SELECT

REGISTER

BUFFER

RESET

CLR

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

VOUT8

n

X2A REGISTER

DAC 0

REGISTER

n

A/B

MUX

2

DAC 0

X1 REGISTER

VOUT9

X2B REGISTER

n

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

·

M REGISTER

C REGISTER

·

STATE

MACHINE

·

n

·

OUTPUT BUFFER

AND POWER-

n

X2A REGISTER

n

DAC 7

A/B

MUX

2

X1 REGISTER

DAC 7

DOWN CONTROL

REGISTER

MUX

SIGGND1

X2B REGISTER

AD5360/

AD5361

n

M REGISTER

C REGISTER

n

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD5360/AD5361

TABLE OF CONTENTS

Features .............................................................................................. 1

Reset Function............................................................................ 19

Clear Function............................................................................ 19

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 14

Functional Description.................................................................. 15

DAC Architecture....................................................................... 15

Channel Groups.......................................................................... 15

BUSY

LDAC

and

Functions...................................................... 19

BIN

/2SCOMP PIN..................................................................... 19

Temperature Sensor ................................................................... 19

Monitor Function....................................................................... 20

GPIO Pin ..................................................................................... 20

Power-Down Mode.................................................................... 20

Thermal Monitoring Function................................................. 20

Toggle Mode................................................................................ 20

Serial Interface ................................................................................ 21

SPI Write Mode .......................................................................... 21

SPI Readback Mode ................................................................... 22

Register Update Rates................................................................ 22

Packet Error Checking............................................................... 22

Channel Addressing and Special Modes................................. 23

Special Function Mode.............................................................. 24

Power Supply Decoupling ......................................................... 25

Power Supply Sequencing ......................................................... 25

Interfacing Examples...................................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

A

/B Registers Gain/Offset Adjustment ................................... 16

Offset DACs ................................................................................ 16

Output Amplifier........................................................................ 17

Transfer Function....................................................................... 17

Reference Selection .................................................................... 17

Calibration................................................................................... 18

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Added LFCSP Package.......................................................Universal

Change to DC Crosstalk Parameter............................................... 4

Change to Power Dissipation Unloaded (P) Parameter.............. 5

Added t₂₃Parameter ......................................................................... 6

Change to Figure 4 ........................................................................... 7

Change to Table 5 Summary ........................................................... 9

Added Figure 8................................................................................ 10

Changes to Table 6.......................................................................... 10

Changes to Calibration Section .................................................... 18

Changes to Reset Function Section.............................................. 19

Added Packet Error Checking Section ........................................ 22

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide .......................................................... 27

10/07—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD5360/AD5361

GENERAL DESCRIPTION

The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a

single 52-lead LQFP or 56-lead LFCSP package. They provide

buffered voltage outputs with a span four times the reference

voltage. The gain and offset of each DAC can be independently

trimmed to remove errors. For even greater flexibility, the device is

divided into two groups of eight DACs, and the output range of

each group can be independently adjusted by an offset DAC.

The AD5360/AD5361 have a high speed 4-wire serial interface,

which is compatible with SPI, QSPI™, MICROWIRE™, and DSP

interface standards and can handle clock speeds of up to

50 MHz. All the outputs can be updated simultaneously by

LDAC

taking the

input low. Each channel has a programmable

gain register and an offset adjust register.

Each DAC output is amplified and buffered on-chip with

respect to an external SIGGNDx input. The DAC outputs can

The AD5360/AD5361 offer guaranteed operation over a wide

supply range with V_SSfrom −4.5 V to −16.5 V and V_DDfrom

+8 V to +16.5 V. The output amplifier headroom requirement

is 1.4 V.

CLR

also be switched to SIGGNDx via the

pin.

Rev. A | Page 3 of 28

AD5360/AD5361

SPECIFICATIONS

DV_CC= 2.5 V to 5.5 V; V_DD= 9 V to 16.5 V; V_SS= −16.5 V to −4.5 V; V_REF= 5 V; AGND = DGND = SIGGND = 0 V; R_L= open circuit;

gain (M), offset (C), and DAC offset registers at default value; all specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

B Version¹

Unit

Test Conditions/Comments

ACCURACY

Resolution

AD5360

AD5361

16

14

Bits

Relative Accuracy

AD5360

AD5361

4

1

15

20

0.1

1

LSB max

mV max

% FSR

LSB typ

mV max

ppm FSR/°C typ

μV max

Differential Nonlinearity

Zero-Scale Error

Full-Scale Error

Gain Error

Zero-Scale Error²

Full-Scale Error²

Span Error of Offset DAC

VOUTx³Temperature Coefficient

DC Crosstalk⁴

Guaranteed monotonic by design over temperature

Before calibration

After calibration

1

After calibration

75

5

180

See the Offset DACS section for details

Includes linearity, offset, and gain drift

Typically 20 μV; measured channel at midscale, full-scale

change on any other channel

REFERENCE INPUTS (VREF0, VREF1)²

VREF Input Current

VREF Range²

10

2/5

μA max

V min/max

Per input; typically 30 nA

2% for specified operation

SIGGND INPUT (SIGGND0 to SIGGND1)⁴

DC Input Impedance

Input Range

50

0.5

kΩ min

V max

Typically 55 kΩ

SIGGND Gain

0.995/1.005

Min/max

OUTPUT CHARACTERISTICS²

Output Voltage Range

V_SS+ 1.4

V_DD− 1.4

−10 to +10

15

1

2200

V min

V max

I_LOAD= 1 mA

Nominal Output Voltage Range

Short-Circuit Current

Load Current

V nominal

mA max

pF max

Ω max

VOUTx³to DV_CC, V_DD, or V_SS

Capacitive Load

DC Output Impedance

MONITOR PIN (MON_OUT)⁴

Output Impedance

0.5

DAC Output at Positive Full-Scale

DAC Output at Negative Full-Scale

Three-State Leakage Current

Continuous Current Limit

DIGITAL INPUTS

1000

500

100

2

Ω typ

nA typ

mA max

JEDEC compliant

Input High Voltage

1.7

2.0

0.8

1

V min

V max

μA max

pF max

DV_CC= 2.5 V to 3.6 V

DV_CC= 3.6 V to 5.5 V

DV_CC= 2.5 V to 5.5 V

Input Low Voltage

Input Current

RESET SYNC

,

, SDI, and SCLK pins

20

10

CLR BIN

, /2SCOMP, and GPIO pins

Input Capacitance⁴

Rev. A | Page 4 of 28

AD5360/AD5361

Parameter

B Version¹

Unit

Test Conditions/Comments

BUSY

, GPIO,

PEC

)

DIGITAL OUTPUTS (SDO,

Output Low Voltage

0.5

DV_CC− 0.5

5

10

V max

V min

μA max

pF typ

Sinking 200 μA

Sourcing 200 μA

SDO only

Output High Voltage (SDO)

High Impedance Leakage Current

High Impedance Output Capacitance⁴

TEMPERATURE SENSOR (TEMP_OUT)⁴

Accuracy

1

5

°C typ

@ 25°C

−40°C < T < +85°C

Output Voltage at 25°C

Output Voltage Scale Factor

Output Load Current

Power-On Time

1.46

4.4

200

10

V typ

mV/°C typ

μA max

ms typ

Current source only

To within 5°C

POWER REQUIREMENTS

DV_CC

V_DD

V_SS

2.5/5.5

8/16.5

−4.5/−16.5

V min/max

Power Supply Sensitivity⁴

∆ Full Scale/∆ V_DD

∆ Full Scale/∆ V_SS

∆ Full Scale/∆ DV_CC

DI_CC

−75

−90

2

10

dB typ

mA max

V_CC= 5.5 V, V_IH= DV_CC, V_IL= GND

Outputs unloaded

I_DD

I_SS

Power-Down Mode

Bit 0 in the Control Register is 1

DI_CC

I_DD

I_SS

5

35

−35

μA typ

Power Dissipation

Power Dissipation Unloaded (P)

Junction Temperature

245

130

mW max

°C max

V_SS= −12 V, V_DD= +12 V, DV_CC= 2.5 V

T_J= T_A+ P_TOTAL× θ_JA

¹Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

²Specifications are guaranteed for a 5 V reference only.

³VOUTx refers to any of VOUT0 to VOUT15.

⁴Guaranteed by design and characterization, not production tested.

AC CHARACTERISTICS

DV_CC= 2.5 V; V_DD= 15 V; V_SS= −15 V; V_REF= 5 V; AGND = DGND = SIGGND = 0 V; C_L= 200 pF; R_L= 10 kΩ; gain (M), offset (C), and

DAC offset registers at default value; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

DYNAMIC PERFORMANCE¹

B Version¹

Unit

Test Conditions/Comments

Output Voltage Settling Time

20

30

1

μs typ

μs max

Full-scale change

DAC latch contents alternately loaded with all 0s and all 1s

Slew Rate

V/μs typ

nV-s typ

mV max

dB typ

nV-s typ

nV/√Hz typ

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

Digital Feedthrough

5

10

100

10

0.2

0.02

250

VREF0, VREF1 = 2 V p-p, 1 kHz

Effect of input bus activity on DAC output under test

VREF0 = VREF1 = 0 V

Output Noise Spectral Density @ 10 kHz

¹Guaranteed by design and characterization, not production tested.

Rev. A | Page 5 of 28

AD5360/AD5361

TIMING CHARACTERISTICS

DV_CC= 2.5 V to 5.5 V; V_DD= 9 V to 16.5 V; V_SS= −8 V to −16.5 V; V_REF= 5 V; AGND = DGND = SIGGND = 0 V; C_L= 200 pF to GND;

R_L= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3. SPI Interface (See Figure 4 and Figure 5)

Parameter^{1, 2}

Limit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

20

8

11

20

10

5

ns min

ns max

μs typ/max

ns max

ns min

μs max

ns min

μs max

μs typ/max

ns max

ns min

μs max

ns min

ns max

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

Minimum SYNC high time

24th SCLK falling edge to SYNC rising edge

Data setup time

Data hold time

SYNC rising edge to BUSY falling edge

BUSY pulse width low (single-channel update); see Table 8

Single-channel update cycle time

SYNC rising edge to LDAC falling edge

LDAC pulse width low

5

3

t₉

42

1/1.5

600

20

10

3

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

BUSY rising edge to DAC output response time

BUSY rising edge to LDAC falling edge

LDAC falling edge to DAC output response time

DAC output settling time

CLR/RESET pulse activation time

RESET pulse width low

0

3

20/30

140

30

400

270

25

80

RESET time indicated by BUSY low

Minimum SYNC high time in readback mode

SCLK rising edge to SDO valid

RESET rising edge to BUSY falling edge

4

t₂₂

t₂₃

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with t_r= t_f= 2 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

³This is measured with the load circuit shown in Figure 2.

⁴This is measured with the load circuit shown in Figure 3.

200µA

I

OL

DV

CC

R

V

(MIN) – V (MAX)

OL

OH

TO OUTPUT

2

L

C

L

2.2k

Ω

TO

OUTPUT

50pF

V

OL

C

L

200µA

I

OH

50pF

BUSY

Figure 2. Load Circuit for

Timing Diagram

Figure 3. Load Circuit for SDO Timing Diagram

Rev. A | Page 6 of 28

AD5360/AD5361

t₁

SCLK

1

24

1

24

2

t₃

t₁₁

t₂

t₄

t₆

t₅

SYNC

SDI

t₇

t₈

DB0

DB23

t₉

t₁₀

BUSY

t₁₂

t₁₃

1

LDAC

t₁₇

t₁₄

t₁₅

1

VOUTx

t₁₃

2

LDAC

t₁₇

2

VOUTx

t

16

CLR

t₁₈

VOUTx

t₁₉

RESET

VOUTx

t₁₈

t₂₀

BUSY

1

t₂₃

LDAC ACTIVE DURING BUSY.

LDAC ACTIVE AFTER BUSY.

2

Figure 4. SPI Write Timing

Rev. A | Page 7 of 28

AD5360/AD5361

t₂₂

SCLK

48

t₂₁

SYNC

SDI

DB23

DB0

DB23

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB15

DB0

DB23

DB0

SDO

SELECTED REGISTER DATA CLOCKED OUT

LSB FROM PREVIOUS WRITE

Figure 5. SPI Read Timing

OUTPUT

VOLTAGE

FULL-SCALE

ERROR

VMAX

+

ZERO-SCALE

ERROR

ACTUAL

TRANSFER

FUNCTION

IDEAL

TRANSFER

FUNCTION

N

0

DAC CODE

2

– 1

n = 16 FOR AD5360

n = 14 FOR AD5361

ZERO-SCALE

ERROR

VMIN

Figure 6. DAC Transfer Function

Rev. A | Page 8 of 28

AD5360/AD5361

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

T_A= 25°C, unless otherwise noted. Transient currents of up to

60 mA do not cause SCR latch-up.

Table 4.

Parameter

Rating

V_DDto AGND

V_SSto AGND

DV_CCto DGND

−0.3 V to +17 V

−17 V to +0.3 V

−0.3 V to +7 V

Digital Inputs to DGND

Digital Outputs to DGND

VREF0, VREF1 to AGND

VOUT0 to VOUT15 to AGND

SIGGND0, SIGGND1 to AGND

AGND to DGND

−0.3 V to DV_CC+ 0.3 V

−0.3 V to +5.5 V

V_SS− 0.3 V to V_DD+ 0.3 V

−1 V to +1 V

ESD CAUTION

−0.3 V to +0.3 V

MON_IN0, MON_IN1, MON_OUT to AGND V_SS− 0.3 V to V_DD+ 0.3 V

Operating Temperature (T_A)

Industrial (B Version)

Storage

Junction (T_Jmax)

θ_JAThermal Impedance

52-Lead LQFP

−40°C to +85°C

−65°C to +150°C

130°C

38°C/W

25°C/W

56-Lead LFCSP

Reflow Soldering

Peak Temperature

Time at Peak Temperature

230°C

10 sec to 40 sec

Rev. A | Page 9 of 28

AD5360/AD5361

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

52 51 50 49 48 47 46 45 44 43 42 41 40

LDAC

CLR

1

2

39 VOUT4

38 SIGGND0

37 VOUT3

PIN 1

RESET

BIN/2SCOMP

BUSY

1

2

3

4

5

6

7

8

9

PIN 1

42 VOUT5

41 VOUT4

40 SIGGND0

39 VOUT3

38 VOUT2

37 VOUT1

36 VOUT0

35 TEMP_OUT

34 MON_IN1

33 VREF0

32 NC

INDICATOR

RESET

BIN/2SCOMP

BUSY

3

36

35

34

33

32

31

30

29

28

27

4

VOUT2

VOUT1

VOUT0

TEMP_OUT

MON_IN1

VREF0

NC

GPIO

5

MON_OUT

MON_IN0

NC

AD5360/

AD5361

TOP VIEW

(Not to Scale)

6

GPIO

AD5360/

AD5361

TOP VIEW

(Not to Scale)

7

MON_OUT

MON_IN0

NC

NC 10

NC 11

8

9

10

11

12

13

NC

V

12

31 NC

V

DD

SS

V

13

30

V

SS

DD

V

SS

VREF1

DD

NC

VREF1 14

29

NC = NO CONNECT

14 15 16 17 18 19 20 21 22 23 24 25 26

NC = NO CONNECT

Figure 7. 52-Lead LQFP Pin Configuration

Figure 8. 56-Lead LFCSP Pin Configuration

Table 5. LQFP Pin Function Descriptions

Pin No.

LQFP

LFCSP

Mnemonic

Description

1

55

LDAC

Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions

section for more information.

2

56

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear

Function section for more information.

3

4

1

2

RESET

Digital Reset Input.

BIN/2SCOMP

Data Format Digital Input. Connecting this pin to DGND selects offset binary.

Connecting this pin to logic 1 selects twos complement. This input has a weak

pull-down.

5

6

3

4

BUSY

GPIO

Digital Input/Open-Drain Output. BUSY is open drain when it is an output.

See the BUSY and LDAC Functions section for more information.

Digital I/O Pin. This pin can be configured as an input or output that can be

read or programmed high or low via the serial interface. When configured as

an input, it has a weak pull-down.

7

5

MON_OUT

Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the

MON_IN1 input can be switched to this output.

8, 32

6, 34

MON_IN0, MON_IN1

NC

Analog Multiplexer Inputs. Can be switched to MON_OUT.

No Connect.

9, 10, 14, 24, 25, 7 to 11, 15, 16,

26, 27, 30

26 to 28, 31, 32

11, 28

12, 29

V_DD

Positive Analog Power Supply; +9 V to +16.5 V for specified performance.

These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.

12, 29

13, 30

V_SS

Negative Analog Power Supply; −16.5 V to −8 V for specified performance.

These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.

13

19

14

21

VREF1

SIGGND1

Reference Input for DAC 8 to DAC 15. This voltage is referred to AGND.

Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to

this voltage.

31

33

35

VREF0

TEMP_OUT

Reference Input for DAC 0 to DAC 7. This voltage is referred to AGND.

Provides an output voltage proportional to chip temperature. This is typically

1.46 V at 25°C with an output variation of 4.4 mV/°C.

34 to 37, 39 to

42, 15 to 18, 20

to 23

36 to 39, 41 to

44, 17 to 20, 22

to 25

VOUT0 to VOUT15

DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each

analog output is capable of driving an output load of 10 kΩ to ground.

Typical output impedance of these amplifiers is 0.5 Ω.

Rev. A | Page 10 of 28

AD5360/AD5361

Pin No.

LFCSP

LQFP

Mnemonic

Description

38

40

SIGGND0

Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to

this voltage.

43, 51

44, 50

45

45, 53

46, 52

47

DGND

DV_CC

Ground for All Digital Circuitry. Both DGND pins should be connected to the

DGND plane.

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1

μF ceramic capacitors and 10 μF capacitors.

Active Low or SYNC Input for SPI Interface. This is the frame synchronization

signal for the SPI serial interface. See Figure 4, Figure 5, and the Serial

Interface section for more details.

SYNC

46

47

48

49

52

48

49

50

51

54

EP

SCLK

Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial

Interface section for more details.

Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial

Interface section for more details.

Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up

that goes low if the packet error check fails.

Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial

Interface section for more details.

SDI

PEC

SDO

AGND

Connect to V_SS

Ground for All Analog Circuitry. The AGND pin should be connected to the

AGND plane.

Exposed Paddle.

Rev. A | Page 11 of 28

AD5360/AD5361

TYPICAL PERFORMANCE CHARACTERISTICS

2

0.0050

0.0025

0

T

= 25°C

A

V

= –15V

= +15V

SS

DD

= +4.096V

REF

1

0

–0.0025

–0.0050

–1

–2

0

16384

32768

49152

65535

0

1

2

3

4

5

DAC CODE

TIME (µs)

Figure 9. Typical AD5360 INL Plot

Figure 12. Digital Crosstalk

1.0

0.5

0

1.0

0.5

V

DV

= +15V

= –15V

DD

SS

= +5V

= +3V

CC

V

REF

0

–0.5

–1.0

0

16384

32768

49152

65535

0

20

40

60

80

DAC CODE

TEMPERATURE (°C)

Figure 10. Typical INL Error vs. Temperature

Figure 13. Typical AD5360 DNL Plot

600

500

400

300

200

100

0

–0.01

–0.02

T

= 25°C

A

V

= –15V

= +15V

SS

DD

= +4.096V

REF

0

1

2

3

4

5

0

2

4

6

8

10

TIME (µs)

FREQUENCY (Hz)

LDAC

Figure 14. Noise Spectral Density

Figure 11. Analog Crosstalk Due to

Rev. A | Page 12 of 28

AD5360/AD5361

6

5

4

3

2

1

0.50

0.45

0.40

0.35

0.30

0.25

DV

= 5V

CC

= 25°C

V

= –12V

= +12V

= +3V

SS

DD

T

A

V

REF

DV = +5.5V

CC

DV = +3.6V

CC

DV = +2.5V

CC

0

0.48

0.50

0.52

0.54

(mA)

0.56

0.58

–40

–20

0

20

40

60

80

I

CC

TEMPERATURE (°C)

Figure 15. I_CCvs. Temperature

Figure 18. Typical I_CCDistribution

8.0

7.5

7.0

6.5

6.0

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

I

DD

I

SS

V

= –12V

= +12V

SS

DD

= +3V

REF

–40

–25

–10

5

20

35

50

65

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 16. I_DD/I_SSvs. Temperature

Figure 19. TEMP_OUT Voltage vs. Temperature

1.0

V

= 15V

= 25°C

14

12

10

8

DD

FULL-SCALE

SS

T

A

0.5

0

MIDSCALE

ZERO-SCALE

6

4

–0.5

–1.0

2

0

7.75

8.00

7.00

7.25

7.50

(mA)

–1.0

–0.5

0

0.5

1.0

I

DD

MON_OUT CURRENT (mA)

Figure 17. Typical I_DDDistribution

Figure 20. (VOUTx − MON_OUT Voltage) vs. MON_OUT Current

Rev. A | Page 13 of 28

AD5360/AD5361

TERMINOLOGY

Output Voltage Settling Time

The amount of time it takes for the output of a DAC to settle to

a specified level for a full-scale input change.

Integral Nonlinearity (INL)

Integral nonlinearity, or relative accuracy, is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero-scale error and full-scale error and is

expressed in least significant bits (LSB).

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at

the major code transition. It is specified as the area of the glitch

in nV-s. It is measured by toggling the DAC register data between

0x7FFF and 0x8000 (AD5360) or 0x1FFF and 0x2000 (AD5361).

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input

signal from the reference input of one DAC that appears at the

output of another DAC operating from another reference. It is

expressed in decibels and measured at midscale.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all

0s are loaded into the DAC register.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the

output of one converter due to both the digital change and

subsequent analog output change at another converter. It is

specified in nV-s.

Zero-scale error is a measure of the difference between VOUT

(actual) and VOUT (ideal), expressed in millivolts, when the

channel is at its minimum value. Zero-scale error is mainly due

to offsets in the output amplifier.

Digital Crosstalk

Full-Scale Error

Digital crosstalk is defined as the glitch impulse transferred to

the output of one converter due to a change in the DAC register

code of another converter and is specified in nV-s.

Full-scale error is the error in DAC output voltage when all 1s

are loaded into the DAC register.

Full-scale error is a measure of the difference between VOUT

(actual) and VOUT (ideal), expressed in millivolts, when

the channel is at its maximum value. It does not include zero-

scale error.

Digital Feedthrough

When the device is not selected, high frequency logic activity

on the device’s digital inputs can be capacitively coupled both

across and through the device to show up as noise on the

VOUTx pins. It can also be coupled along the supply and

ground lines. This noise is digital feedthrough.

Gain Error

Gain error is the difference between full-scale error and zero-

scale error. It is expressed in millivolts.

Output Noise Spectral Density

Gain Error = Full-Scale Error − Zero-Scale Error

Output noise spectral density is a measure of internally

generated random noise. Random noise is characterized as a

spectral density (voltage per √Hz). It is measured by loading all

DACs to midscale and measuring noise at the output. It is

measured in nV/√Hz.

VOUT Temperature Coefficient

This includes output error contributions from linearity, offset,

and gain drift.

DC Output Impedance

DC output impedance is the effective output source resistance.

It is dominated by package lead resistance.

DC Crosstalk

The DAC outputs are buffered by op amps that share common

V

_DDand V_SSpower supplies. If the dc load current changes in

one channel (due to an update), this can result in a further dc

change in one or more channel outputs. This effect is more

significant at high load currents and reduces as the load

currents are reduced. With high impedance loads, the effect is

virtually immeasurable. Multiple V_DDand V_SSterminals are

provided to minimize dc crosstalk.

Rev. A | Page 14 of 28

AD5360/AD5361

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE

CHANNEL GROUPS

The AD5360/AD5361 contain 16 DAC channels and 16 output

amplifiers in a single package. The architecture of a single DAC

channel consists of a 16-bit resistor-string DAC in the case of

the AD5360 and a 14-bit DAC in the case of the AD5361,

followed by an output buffer amplifier. The resistor-string

section is simply a string of resistors, of equal value, from

VREF0 or VREF1 to AGND. This type of architecture

guarantees DAC monotonicity. The 16-/14-bit binary digital

code loaded to the DAC register determines at which node

on the string the voltage is tapped off before being fed into

the output amplifier. The output amplifier multiplies the

DAC output voltage by 4. The nominal output span is 12 V

with a 3 V reference and 20 V with a 5 V reference.

The 16 DAC channels of the AD5360/AD5361 are arranged into

two groups of eight channels. The eight DACs of Group 0 derive

their reference voltage from VREF0. Group 1 derives its refer-

ence voltage from VREF1. Each group has its own signal

ground pin.

Table 6. AD5360/AD5361 Registers

Register Name

Word Length in Bits

Description

X1A (group) (channel)

X1B (group) (channel)

M (group) (channel)

C (group) (channel)

X2A (group) (channel)

16 (14)

Input Data Register A, one for each DAC channel.

Input Data Register B, one for each DAC channel.

Gain trim register, one for each DAC channel.

Offset trim register, one for each DAC channel.

Output Data Register A, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable or directly

writable.

16 (14)

X2B (group) (channel)

DAC (group) (channel)

16 (14)

Output Data Register B, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable or directly

writable.

Data registers from which the DACs take their final input data. The DAC registers are

updated from the X2A or X2B registers. They are not readable or directly writable.

OFS0

OFS1

Control

Monitor

GPIO

14

5

6

2

Offset DAC 0 data register, sets offset for Group 0.

Offset DAC 1 data register, sets offset for Group 1.

Control register.

Monitor enable and configuration register.

GPIO configuration register.

Table 7. AD5360/AD5361 Input Register Default Values

Register Name

AD5360 Default Value

AD5361 Default Value

X1A, X1B

M

C

OFS0, OFS1

Control

0x8000

0xFFFF

0x8000

0x2000

0x00

0x2000

0x3FFF

0x2000

0x00

A/B Select 0 and A/B Select 1

0x00

Rev. A | Page 15 of 28

AD5360/AD5361

A/B REGISTERS GAIN/OFFSET ADJUSTMENT

Each DAC channel has seven data registers. The actual DAC

data word can be written to either the X1A or X1B input

All DACs in the AD5360/AD5361 can be updated simultane-

LDAC

ously by taking

low, when each DAC register is updated

A

register, depending on the setting of the /B bit in the control

from either its X2A or X2B register, depending on the setting of

A

register. If the /B bit is 0, data is written to the X1A register. If

the /B select registers. The DAC register is not readable or

A

directly writable by the user.

the /B bit is 1, data is written to the X1B register. Note that

this single bit is a global control and affects every DAC channel

in the device. It is not possible to set up the device on a per-

channel basis so that some writes are to the X1A register and

some writes are to the X1B register.

OFFSET DACs

In addition to the gain and offset trim for each DAC, there are

two 14-bit offset DACs, one for Group 0, and one for Group 1.

These allow the output range of all DACs connected to them to

be offset within a defined range. Thus, subject to the limitations

of headroom, it is possible to set the output range of Group 0

and/or Group 1 to be unipolar positive, unipolar negative, or

bipolar (either symmetrical or asymmetrical) about 0 V. The

DACs in the AD5360/AD5361 are factory trimmed with the

offset DACs set at their default values. This gives the best offset

and gain performance for the default output range and span.

X1A

REGISTER

X2A

REGISTER

DAC

REGISTER

MUX

DAC

X1B

REGISTER

X2B

REGISTER

M

REGISTER

C

REGISTER

Figure 21. Data Registers Associated with Each DAC Channel

When the output range is adjusted by changing the value of

the offset DAC, an extra offset is introduced due to the gain

error of the offset DAC. The amount of offset is dependent on

the magnitude of the reference and how much the offset DAC

moves from its default value. This offset is shown in Table 1. The

worst-case offset occurs when the offset DAC is at positive full

scale or negative full scale. This value can be added to the offset

present in the main DAC of a channel to give an indication of

the overall offset for that channel. In most cases, the offset can be

removed by programming the C register of the channel with an

appropriate value. The extra offset caused by the offset DACs

needs to be taken into account only when the offset DAC is

changed from its default value. Figure 22 shows the allowable

code range that can be loaded to the offset DAC, and this is

dependent on the reference value used. Thus, for a 5 V

reference, the offset DAC should not be programmed with

a value greater than 8192 (0x2000).

Each DAC channel also has a gain register (M) and an offset (C)

register, which allow trimming out of the gain and offset errors

of the entire signal chain. Data from the X1A register is oper-

ated on by a digital multiplier and adder by the contents of the

M and C registers. The calibrated DAC data is then stored in the

X2A register. Similarly, data from the X1B register is operated

on by the multiplier and adder and stored in the X2B register.

Although a multiplier and adder symbol are shown for each

channel, there is only one multiplier and one adder in the

device, which are shared among all channels. This has

implications for the update speed when several channels are

updated at once, as described in the Register Update Rates

section.

Each time data is written to the X1A register, or to the M or

A

C register with the /B control bit set to 0, the X2A data is

recalculated and the X2A register is automatically updated.

Similarly, X2B is updated each time data is written to X1B, or

5

RESERVED

A

to M or C with /B set to 1. The X2A and X2B registers are

4

3

2

1

0

not readable or directly writable by the user.

Data output from the X2A and X2B registers is routed to the

final DAC register by a multiplexer. An 8-bit /B select register

A

associated with each group of eight DACs controls whether

each individual DAC takes its data from the X2A or X2B

register. If a bit in this register is 0, the DAC takes its data

from the X2A register; if 1, the DAC takes its data from the

X2B register (Bit 0 through Bit 7 control DAC 0 through

DAC 7, respectively).

0

4096

8192

12288

16383

Note that because there are 16 bits in two registers, it is possible

to set up, on a per-channel basis, whether each DAC takes its

data from the X2A register or X2B register. A global command

OFFSET DAC CODE

Figure 22. Offset DAC Code Range

A

is also provided that sets all bits in the /B select registers to 0

or to 1.

Rev. A | Page 16 of 28

AD5360/AD5361

OFFSET_CODE is the code loaded to the offset DAC. It is

multiplied by 4 in the transfer function because this DAC is a

14-bit device. On power-up, the default code loaded to the

offset DAC is 8192 (0x2000). With a 10 V reference, this gives

a span of −10 V to +10 V.

OUTPUT AMPLIFIER

Because the output amplifiers can swing to 1.4 V below the

positive supply and 1.4 V above the negative supply, this limits

how much the output can be offset for a given reference voltage.

For example, it is not possible to have a unipolar output range of

20 V because the maximum supply voltage is 16.5 V.

AD5361 Transfer Function

S1

The input code is the value in the X1A or X1B register that is

applied to DAC (X1A, X1B default code = 8192)

DAC

CHANNEL

OUTPUT

R6

10kΩ

DAC_CODE = INPUT_CODE × (M + 1)/2¹⁴+ C − 2¹³

S2

R5

60kΩ

CLR

DAC output voltage

R1

20kΩ

S3

_OUT= 4 × V_REF× (DAC_CODE − OFFSET_CODE)/2¹⁴+

CLR

V

R4

60kΩ

SIGGND

R3

20kΩ

R2

20kΩ

V_SIGGND

where:

SIGGND

DAC_CODE should be within the range of 0 to 16,383.

OFFSET

DAC

V

_REF= 3.0 V, for a 12 V span.

V

_REF= 5.0 V, for a 20 V span.

Figure 23. Output Amplifier and Offset DAC

M = code in gain register − default code = 2¹⁴− 1.

C = code in offset register − default code = 2¹³.

Figure 23 shows details of a DAC output amplifier and its

connections to the offset DAC. On power-up, S1 is open,

disconnecting the amplifier from the output. S3 is closed, so

the output is pulled to SIGGND. S2 is also closed to prevent

OFFSET_CODE is the code loaded to the offset DAC.

On power-up, the default code loaded to the offset DAC

is 8192 (0x2000). With a 5 V reference, this gives a span of

−10 V to +10 V.

CLR

the output amplifier from being open-loop. If

is low at

CLR

power-up, the output remains in this condition until

is

REFERENCE SELECTION

taken high. The DAC registers can be programmed, and the

CLR

The AD5360/AD5361 have two reference input pins. The

voltage applied to the reference pins determines the output

voltage span on VOUT0 to VOUT15. VREF0 determines the

voltage span for VOUT0 to VOUT7 (Group 0), and VREF1

determines the voltage span for VOUT8 to VOUT15 (Group 1).

The reference voltage applied to each VREF pin can be different,

if required, allowing each group of eight channels to have a

different voltage span. The output voltage range and span can

be adjusted by programming the offset register and gain register

for each channel as well as programming the offset DAC. If the

offset and gain features are not used (that is, the M and C

registers are left at their default values), the required reference

levels can be calculated as follows:

outputs assume the programmed values when

is taken

CLR

high. Even if

is high at power-up, the output remains

in this condition until V_DD> 6 V and V_SS< −4 V and the

initialization sequence has finished. The outputs then go to

their power-on default values.

TRANSFER FUNCTION

The output voltage of a DAC in the AD5360/AD5361 is dependent

on the value in the input register, the value of the M and C

registers, and the value in the offset DAC. The transfer functions

for the AD5360/AD5361 are shown in the following sections.

AD5360 Transfer Function

The input code is the value in the X1A or X1B register that is

applied to DAC (X1A, X1B default code = 32,768)

VREF = (VOUT_MAX− VOUT_MIN)/4

DAC_CODE = INPUT_CODE × (M + 1)/2¹⁶+ C − 2¹⁵

If the offset and gain features of the AD5360/AD5361 are used,

the required output range is slightly different. The chosen

output range should take into account the system offset and

gain errors that need to be trimmed out. Therefore, the chosen

output range should be larger than the actual, required range.

DAC output voltage

V

_OUT= 4 × V_REF× (DAC_CODE − (OFFSET_CODE × 4))/

2¹⁶+ V_SIGGND

where:

The required reference levels can be calculated as follows:

DAC_CODE should be within the range of 0 to 65,535.

1. Identify the nominal output range on VOUT.

2. Identify the maximum offset span and the maximum gain

required on the full output signal range.

3. Calculate the new maximum output range on VOUT,

including the expected maximum offset and gain errors.

V

_REF= 3.0 V, for a 12 V span.

_REF= 5.0 V, for a 20 V span.

M = code in gain register − default code = 2¹⁶– 1.

C = code in offset register − default code = 2¹⁵.

Rev. A | Page 17 of 28

AD5360/AD5361

4. Choose the new required VOUT_MAXand VOUT_MIN, keeping

the VOUT limits centered on the nominal values. Note that

Full-scale error can be reduced as follows:

1. Measure the zero-scale error.

V_DDand V_SSmust provide sufficient headroom.

2. Set the output to the highest possible value.

3. Measure the actual output voltage and compare it with the

required value. Add this error to the zero-scale error. This

is the span error, which includes full-scale error.

4. Calculate the number of LSBs equivalent to the span error

and subtract it from the default value of the M register.

Note that only positive full-scale error can be reduced.

5. Calculate the value of VREF as follows:

VREF = (VOUT_MAX− VOUT_MIN)/4

Reference Selection Example

Nominal output range = 20 V (−10 V to +10 V)

Offset error = 100 mV

Gain error = 3ꢀ

SIGGND = AGND = 0 V

The M and C registers should not be programmed until both

zero-scale errors and full-scale errors have been calculated.

Gain error = 3ꢀ

Maximum positive gain error = +3ꢀ

Output range including gain error = 20 + 0.03 (20) =

20.6 V

AD5360 Calibration Example

This example assumes that a −10 V to +10 V output is required.

The DAC output is set to −10 V but is measured at −10.03 V.

This gives a zero-scale error of −30 mV.

Offset error = 100 mV

Maximum offset error span = 2 (100 mV) = 0.2 V

Output range including gain error and offset error =

20.6 V + 0.2 V = 20.8 V

1 LSB = 20 V/65,536 = 305.176 μV

30 mV = 98 LSBs

The full-scale error can now be removed. The output is set

to +10 V, and a value of +10.02 V is measured. The full-scale

error is +20 mV. The span error is +20 mV − (−30 mV) =

+50 mV.

VREF calculation

Actual output range = 20.6 V, that is, −10.3 V to +10.3 V

(centered);

VREF = (10.3 V + 10.3 V)/4 = 5.15 V

+50 mV = 164 LSBs

If the solution yields an inconvenient reference level, the user

can adopt one of the following approaches:

The errors can now be removed.

1. 98 LSBs should be added to the default C register value;

(32,768 + 98) = 32,866.

2. 32,866 should be programmed to the C register.

3. 164 LSBs should be subtracted from the default M register

value; (65,535 − 164) = 65,371.

•

Use a resistor divider to divide down a convenient, higher

reference level to the required level.

•

Select a convenient reference level above VREF and modify

the gain and offset registers to digitally downsize the

reference. In this way, the user can use almost any conven-

ient reference level but may reduce the performance by

overcompaction of the transfer function.

4. 65,371 should be programmed to the M register.

Additional Calibration

•

Use a combination of these two approaches.

The techniques described in the previous section are usually

enough to reduce the zero-scale errors and full-scale errors in

most applications. However, there are limitations whereby the

errors may not be sufficiently removed. For example, the offset

(C) register can only be used to reduce the offset caused by the

negative zero-scale error. A positive offset cannot be reduced.

Likewise, if the maximum voltage is below the ideal value, that

is, a negative full-scale error, the gain (M) register cannot be

used to increase the gain to compensate for the error.

CALIBRATION

The user can perform a system calibration on the AD5360 and

AD5361 to reduce gain and offset errors to below 1 LSB. This is

achieved by calculating new values for the M and C registers and

reprogramming them.

Reducing Zero-Scale and Full-Scale Error

Zero-scale error can be reduced as follows:

These limitations can be overcome by increasing the refer-

ence value. With a 2.5 V reference, a 10 V span is achieved.

The ideal voltage range, for the AD5360 or AD5361, is

−5 V to +5 V. Using a 2.6 V reference increases the range

to −5.2 V to +5.2 V. Clearly, in this case, the offset and gain

errors are insignificant and the M and C registers can be

used to raise the negative voltage to −5 V and then reduce

the maximum voltage down to +5 V to give the most

accurate values possible.

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it with the

required value. This gives the zero-scale error.

3. Calculate the number of LSBs equivalent to the error and

add this from the default value of the C register. Note that

only negative zero-scale error can be reduced.

Rev. A | Page 18 of 28

AD5360/AD5361

A

BUSY

high. Whenever the /B select registers are written to,

RESET FUNCTION

also goes low, for approximately 600 ns.

RESET

The reset function is initiated by the

pin. On the rising

The AD5360/AD5361 have flexible addressing that allows

writing of data to a single channel, all channels in a group, the

same channel in Group 0 and Group 1, or all channels in the

device. This means that 1, 2, 8, or 16 DAC register values may

need to be calculated and updated. Because there is only one

multiplier shared among 16 channels, this task must be done

RESET

edge of

, the AD5360/AD5361 state machine initiates a

reset sequence to reset the X, M, and C registers to their default

values. This sequence typically takes 300 μs, and the user should

not write to the part during this time. On power-up, it is recom-

mended that the user bring

properly initialize the registers.

RESET

high as soon as possible to

BUSY

sequentially, so the length of the

the number of channels being updated.

pulse varies according to

CLR

When the reset sequence is complete (and provided that

is

high), the DAC output is at a potential specified by the default

register settings, which are equivalent to SIGGNDx. The DAC

outputs remain at SIGGNDx until the X, M, or C register is

BUSY

Table 8.

Action

Pulse Widths

BUSY Pulse Width¹

LDAC

updated and

returned to the default state by pulsing

30 ns. Note that, because the reset function is rising edge trig-

is taken low. The AD5360/AD5361 can be

Loading Input, C, or M to 1 Channel²

Loading Input, C, or M to 2 Channels

Loading Input, C, or M to 8 Channels

Loading Input, C, or M to 16 Channels

1.5 μs maximum

2.1 μs maximum

5.7 μs maximum

10.5 μs maximum

RESET

low for at least

RESET

gered, bringing

low has no effect on the operation of

the AD5360/AD5361.

¹BUSY

pulse width = ((number of channels + 1) × 600 ns) + 300 ns.

²A single channel update is typically 1 μs.

CLEAR FUNCTION

CLR

operation. The

resistor. When

is an active low input that should be high for normal

The AD5360/AD5361 contain an extra feature whereby a DAC

register is not updated unless its X2A or X2B register has been

CLR

pin has an internal 500 kΩ pull-down

is low, the input to each of the DAC output

LDAC

written to since the last time

was brought low. Normally,

is brought low, the DAC registers are filled with

the contents of the X2A or X2B registers, depending on the

buffer stages (VOUT0 to VOUT15) is switched to the externally

CLR

LDAC

when

set potential on the relevant SIGGNDx pin. While

is low,

is taken high again, the

LDAC CLR

all

pulses are ignored. When

A

setting of the /B select register. However, the AD5360/

DAC outputs return to their previous values. The contents of

input registers and DAC Register 0 to DAC Register 15 are not

affected by taking

AD5361 update the DAC register only if the X2A or X2B data has

changed, thereby removing unnecessary digital crosstalk.

CLR

low. To prevent glitches appearing on

BIN/2SCOMP PIN

CLR

the outputs,

should be brought low whenever the output

span is adjusted by writing to the offset DAC.

BIN

/2SCOMP pin determines if the output data is presented

The

as offset binary or twos complement. If this pin is low, the data

is straight binary. If it is high, the data is twos complement. This

affects only the X, C, and offset DAC registers; the M register

and the control and command data are interpreted as straight

binary.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M register.

BUSY

During the calculation of X2, the

output goes low. While

BUSY

is low, the user can continue writing new data to the X1,

TEMPERATURE SENSOR

M, or C register (see the Register Update Rates section for more

details), but no DAC output updates can take place.

The on-chip temperature sensor provides a voltage output

at the TEMP_OUT pin that is linearly proportional to the

Centigrade temperature scale. The typical accuracy of the

temperature sensor is 1ꢀC at +25ꢀC and 5ꢀC over the −40ꢀC

to +85ꢀC range. Its nominal output voltage is 1.46 V at +25ꢀC,

varying at 4.4 mV/ꢀC. Its low output impedance, low self-

heating, and linear output simplify interfacing to temperature

control circuitry and analog-to-digital converters.

BUSY

The

resistor. When multiple AD5360 or AD5361 devices may be

BUSY

pin is bidirectional and has a 50 kΩ internal pull-up

used in one system, the

pins can be tied together. This is

useful when it is required that no DAC in any device be updated

until all other DACs are ready. When each device has finished

updating the X2 (A or B) register, it releases the

BUSY

pin. If

another device has not finished updating its X2 registers, it

BUSY

LDAC

holds

The DAC outputs are updated by taking the

LDAC BUSY

low, thus delaying the effect of

going low.

input low. If

LDAC

goes low while

and the DAC outputs update immediately after

LDAC

is active, the

event is stored

BUSY

goes

input permanently low. In

BUSY

high. A user can also hold the

this case, the DAC outputs update immediately after

goes

Rev. A | Page 19 of 28

AD5360/AD5361

MONITOR FUNCTION

POWER-DOWN MODE

The AD5360/AD5361 contain a channel monitor function

that consists of an analog multiplexer addressed via the serial

interface, allowing any channel output to be routed to this pin

for monitoring using an external ADC. In addition, two monitor

inputs, MON_IN0 and MON_IN1, are provided, which can also

be routed to MON_OUT. The monitor function is controlled by

the monitor register, which allows the monitor output to be

enabled or disabled, and selection of a DAC channel or one of

the monitor pins. When disabled, the monitor output is high

impedance, so several monitor outputs can be connected in

parallel and only one enabled at a time. Table 9 shows the

control register settings relevant to the monitor function.

The AD5360/AD5361 can be powered down by setting Bit 0 in

the control register to 1. This turns off the DACs, thus reducing

the current consumption. The DAC outputs are connected to

their respective SIGGND potentials. The power-down mode

does not change the contents of the registers, and the DACs

return to their previous voltage when the power-down bit is

cleared to 0.

THERMAL MONITORING FUNCTION

The AD5360/AD5361 can be programmed to power down the

DACs if the temperature on the die exceeds 130°C. Setting Bit 1

in the control register to 1 (see Table 15) enables this function.

If the die temperature exceeds 130°C, the AD5360/AD5361

enter a temperature power-down mode, which is equivalent to

setting the power-down bit in the control register. To indicate

that the AD5360/AD5361 have entered temperature shutdown

mode, Bit 4 of the control register is set to 1. The AD5360/AD5361

remain in temperature shutdown mode, even if the die tempera-

ture falls, until Bit 1 in the control register is cleared to 0.

Table 9. Control Register Monitor Functions

F5

F4

X

0

F3

X

0

1

F2

X

0

1

F1

X

0

1

F0

X

0

1

Function

0

1

MON_OUT disabled

MON_OUT enabled

MON_OUT = VOUT0

MON_OUT = VOUT1

MON_OUT = VOUT15

MON_OUT = MON_IN0

MON_OUT = MON_IN1

TOGGLE MODE

1

0

1

The AD5360/AD5361 have two X2 registers per channel, X2A

and X2B, which can be used to switch the DAC output between

two levels with ease. This approach greatly reduces the overhead

required by a microprocessor, which would otherwise have to

write to each channel individually. When the user writes to

either the X1A, X2A, M, or C register, the calculation engine

takes a certain amount of time to calculate the appropriate X2A

or X2B values. If the application only requires that the DAC

output switch between two levels, such as a data generator, any

method that reduces the amount of calculation time encoun-

tered is advantageous. For the data generator example, the user

should set the high and low levels for each channel once, by

writing to the X1A and X1B registers. The values of X2A and

X2B are calculated and stored in their respective registers. The

calculation delay, therefore, only happens during the setup

phase, that is, when programming the initial values. To toggle a

DAC output between the two levels, it is only required to write

The multiplexer is implemented as a series of analog switches.

Because this could conceivably cause a large amount of current

to flow from the input of the multiplexer, that is, VOUTx or

MON_INx to the output of the multiplexer, MON_OUT, care

should taken to ensure that whatever is connected to the

MON_OUT pin is of high enough impedance to prevent the

continuous current limit specification from being exceeded.

Because the MON_OUT pin is not buffered, the amount of

current drawn from this pin creates a voltage drop across the

switches, which in turn leads to an error in the voltage being

monitored. Where accuracy is important, it is recommended

that the MON_OUT pin be buffered. Figure 20 shows the

typical error due to the MON_OUT current

GPIO PIN

The AD5360/AD5361 have a general-purpose I/O pin, GPIO.

This can be configured as an input or an output and read back

or programmed (when configured as an output) via the serial

interface. Typical applications for this pin include monitoring

the status of a logic signal, monitoring a limit switch, or

controlling an external multiplexer. The GPIO pin is configured

by writing to the GPIO register, which has the special function

code of 001101 (see Table 14 and Table 15 ). When Bit F1 is set,

the GPIO pin becomes an output and F0 determines whether

the pin is high or low. The GPIO pin can be set as an input by

writing 0 to both F1 and F0. The status of the GPIO pin can be

determined by initiating a read operation using the appropriate

bits in Table 16. The status of the pin is indicated by the LSB of

the register read.

A

to the relevant /B select register to set the MUX 2 register bit.

Furthermore, because there are eight MUX 2 control bits per

register, it is possible to update eight channels with a single

write. Table 17 shows the bits that correspond to each DAC

output.

Rev. A | Page 20 of 28

AD5360/AD5361

SERIAL INTERFACE

The AD5360/AD5361 contain a high speed SPI operating at

clock frequencies up to 50 MHz (20 MHz for read operations).

To minimize both the power consumption of the device and

on-chip digital noise, the interface powers up fully only when

the device is being written to, that is, on the falling edge of

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into

the AD5360/AD5361 by clock pulses applied to SCLK. The first

SYNC

falling edge of

clock edges must be applied to SCLK to clock in 24 bits of data,

SYNC SYNC

starts the write cycle. At least 24 falling

SYNC

. The serial interface is 2.5 V LVTTL-compatible when

operating from a 2.5 V to 3.6 V DV_CCsupply. It is controlled by

SYNC

before

the 24th falling clock edge, the write operation is aborted.

SYNC

is taken high again. If

is taken high before

four pins:

(frame synchronization input), SDI (serial data

If a continuous clock is used,

must be taken high before

input), SCLK (clocking of data in and out of the device), and

SDO (serial data output for data readback).

the 25th falling clock edge. This inhibits the clock within the

AD5360/AD5361. If more than 24 falling clock edges are

SYNC

SPI WRITE MODE

applied before

is taken high again, the input data is

corrupted. If an externally gated clock of exactly 24 pulses is

SYNC

The AD5360/AD5361 allow writing of data via the serial inter-

face to every register directly accessible to the serial interface,

which are all registers except the X2A, X2B, and DAC registers.

The X2A and X2B registers are updated when writing to the

X1A, X1B, M, and C registers, and the DAC registers are

used,

clock edge.

The input register addressed is updated on the rising edge of

may be taken high any time after the 24th falling

SYNC

. For another serial transfer to take place,

taken low again.

must be

LDAC

updated by

. The serial word (see Table 10 or Table 11)

is 24 bits long; 16 or 14 of these bits are data bits, six bits are

address bits, and two bits are mode bits that determine what

is done with the data. Two bits are reserved on the AD5361.

Table 10. AD5360 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

M1 M0 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 11. AD5361 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15

I14

I13

I12

I11 I10 I9

I8

I7

I6

I5

I4

I3

I2

I1¹I0¹

M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9

D8 D7 D6 D5 D4 D3 D2 D1 D0

0

¹I1 and I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.

Rev. A | Page 21 of 28

AD5360/AD5361

SPI READBACK MODE

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environ-

ments, the AD5360/AD5361 offer the option of error checking

based on an 8-bit (CRC-8) cyclic redundancy check. The device

controlling the AD5360/AD5361 should generate an 8-bit

checksum using the polynomial C(x) = x⁸+ x²+ x¹+1. The

checksum is added to the end of the data word, and 32 data bits

The AD5360/AD5361 allow data readback via the serial inter-

face from every register directly accessible to the serial interface,

which is all registers except the X2A, X2B, and DAC data

registers. To read back a register, it is first necessary to tell the

AD5360/AD5361 which register is to be read. This is achieved

by writing a word whose first two bits are the Special Function

Code 00 to the device. The remaining bits then determine if the

operation is a readback and which register is to be read back, or

if it is a write to of the special function registers, such as the

control register.

SYNC

are sent to the AD5360/AD5361 before taking

the AD5360/AD5361 see a 32-bit data frame, they perform the

SYNC

high. If

error check when

data is written to the selected register. If the checksum is invalid,

PEC

goes high. If the checksum is valid, the

the data is ignored, the packet error check output (

) goes

If a readback command is written to a special function register,

data from the selected register is clocked out of the SDO pin

during the next SPI operation. The SDO pin is normally three-

stated but becomes driven as soon as a read command is issued.

The pin remains driven until the register’s data is clocked out.

See Figure 5 for the read timing diagram. Note that, due to the

timing requirements of t₂₂(25 ns), the maximum speed of the

SPI interface during a read operation should not exceed 20 MHz.

low, and Bit 3 of the control register is set. After reading the

control register, the error flag is cleared automatically and

goes high again.

PEC

UPDATE ON SYNC HIGH

SYNC

SCLK

MSB

D23

LSB

D0

REGISTER UPDATE RATES

The value of the X2A or X2B register is calculated each time the

user writes new data to the corresponding X1, C, or M register.

The calculation is performed by a three-stage process. The first

two stages take approximately 600 ns each, and the third stage

takes approximately 300 ns. When the write to a X1, C, or M

register is complete, the calculation process begins. If the write

operation involves the update of a single DAC channel, the user

is free to write to another register provided that the write

operation does not finish until the first stage calculation is

complete, that is, 600 ns after the completion of the first write

operation. If a group of channels is being updated by a single

write operation, the first stage calculation is repeated for each

channel, taking 600 ns per channel. In this case, the user should

not complete the next write operation until this time has elapsed.

24-BIT DATA

SDI

24-BIT DATA TRANSFER—NO ERROR CHECKING

UPDATE AFTER SYNC HIGH

ONLY IF ERROR CHECK PASSED

SYNC

SCLK

SDI

MSB

D31

LSB

D8

D7

D0

24-BIT DATA

8-BIT CHECKSUM

PEC GOES LOW IF

ERROR CHECK FAILS

PEC

24-BIT DATA TRANSFER WITH ERROR CHECKING

Figure 24. SPI Write with and Without Error Checking

Rev. A | Page 22 of 28

AD5360/AD5361

device. Table 13 shows all these address modes. It shows which

group(s) and which channel(s) is/are addressed for every

combination of Address Bit A4 to Address Bit A0.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D15 to D0

(AD5360) or D13 to D0 (AD5361) is written to the device.

Address Bit A4 to Address Bit A0 determine which channel or

channels is/are written to, while the mode bits determine to

which register (X1A, X1B, C, or M) the data is written, as

shown in Table 10 and Table 11. Data is to be written to the

Table 12. Mode Bits

M1 M0 Action

1

0

1

0

1

0

Write DAC data (X) register

Write DAC offset (C) register

Write DAC gain (M) register

Special function, used in combination with other

bits of a word

A

X1A when the /B bit in the control register is 0 or to the X1B

register when the bit is 1.

The AD5360/AD5361 have very flexible addressing that allows

writing of data to a single channel, all channels in a group, the

same channel in Group 0 and Group 1 or all channels in the

Table 13. Group and Channel Addressing

Address Bit A4 to Address Bit A3

Address Bit A2 to Address Bit A0

00

01

10

11

000

001

010

011

100

101

110

111

All groups, all channels

Group 0, all channels

Group 1, all channels

Unused

Group 0, Channel 0

Group 0, Channel 1

Group 0, Channel 2

Group 0, Channel 3

Group 0, Channel 4

Group 0, Channel 5

Group 0, Channel 6

Group 0, Channel 7

Group 1, Channel 0

Group 1, Channel 1

Group 1, Channel 2

Group 1, Channel 3

Group 1, Channel 4

Group 1, Channel 5

Group 1, Channel 6

Group 1, Channel 7

Unused

Rev. A | Page 23 of 28

AD5360/AD5361

SPECIAL FUNCTION MODE

data required for execution of the special function, for example

the channel address for data readback.

If the mode bits are 00, then the special function mode is

selected, as shown in Table 14. Bits I21 to I16 of the serial data

word select the special function, while the remaining bits are

The codes for the special functions in Table 16 show the

addresses for data readback.

Table 14. Special Function Mode

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

0

S5

S4

S3

S2

S1

S0

F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Table 15. Special Function Codes

Special Function Code

S5 S4 S3 S2 S1 S0 Data (F15 to F0)

Action

0

1

0000 0000 0000 0000

NOP.

XXXX XXXX XXXX X [F2:F0]

Write control register.

F4 = 1: temperature over 130°C.

F4 = 0: temperature under 130°C.

Read-only bit. This bit should be 0 when writing to the control register.

F3 = 1: PEC error.

F3 = 0: No PEC error. Reserved.

Read-only bit. This bit should be 0 when writing to the control register.

F2 = 1: select Register X1B for input.

F2 = 0: select Register X1A for input.

F1 = 1: enable temperature shutdown.

F1 = 0: disable temperature shutdown.

F0 = 1: soft power-down.

F0 = 0: soft power-up.

0

1

0

1

0

1

0

1

0

1

XX [F13:F0]

Write data in F13 to F0 to OFS0 register.

Write data in F13 to F0 to OFS1 register.

XX [F13:F0]

Reserved

See Table 16

XXXX XXXX [F7:F0]

Select register for readback.

Write data in F7 to F0 to A/B Select Register 0.

Write data in F7 to F0 to A/B Select Register 1.

0

1

0

1

0

1

0

1

Reserved

XXXX XXXX [F7:F0]

Block write A/B select registers.

F7 to F0 = 0: write all 0s (all channels use X2A register).

F7 to F0 = 1: write all 1s (all channels use X2B register).

0

1

0

XXXX XXXX XX [F5:F0]

F5 = 1: monitor enable.

F5 = 0: monitor disable.

F4 = 1: monitor input pin selected by F0.

F4 = 0: monitor DAC channel selected by F3:F0

(0000 = DAC0; 1111 = DAC15).

F3 = not used if F4 = 1.

F2 = not used if F4 = 1.

F1 = not used.

F0 = 0: MON_IN0 selected for monitoring (if F4 and F5 = 1).

F0 = 1: MON_IN1 selected for monitoring (if F4 and F5 = 1).

GPIO configure and write.

0

1

0

1

XXXX XXXX XXXX XX [F1:F0]

F1 = 1: GPIO is an output. Data to output is written to F0.

F1 = 0: GPIO is an input. Data can be read from F0 on readback.

Rev. A | Page 24 of 28

AD5360/AD5361

Table 16. Address Codes for Data Readback¹

F15

F14

F13

F12

F11

F10

F9

F8

F7

Register Read

X1A Register

0

Bit F12 to Bit F7 select channel to be read back,

Channel 0 = 001000 to Channel 15 = 010111

0

1

X1B Register

0

1

0

C Register

0

1

M Register

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Control Register

OFS0 Data Register

OFS1 Data Register

Reserved

1

0

1

0

1

0

1

0

A/B Select Register 0

A/B Select Register 1

Reserved

1

0

1

0

1

0

Reserved

1

0

Reserved

GPIO Read (Data in F0)²

1

0

¹F6 to F0 are don’t cares for the data readback function.

²F6 to F0 should be 0 for GPIO read.

A

Table 17. DACs Selected by /B Select Registers

Bits¹

F3

A/B Select

Register

F7

F6

F5

F4

F2

F1

F0

0

1

DAC7

DAC15

DAC6

DAC14

DAC5

DAC13

DAC4

DAC12

DAC3

DAC2

DAC1

DAC9

DAC0

DAC8

DAC11

DAC10

¹If the bit is 0, Register X2A is selected. If the bit is 1, Register X2B is selected.

supply line. Fast switching digital signals should be shielded

with digital ground to avoid radiating noise to other parts of the

board and should never be run near the reference inputs. It is

essential to minimize noise on all VREFx lines.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit board on

which the AD5360/AD5361 are mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5360/AD5361 are in a

system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as close as possible

to the device. For supplies with multiple pins (V_SS, V_DD, DV_CC),

it is recommended to tie these pins together and to decouple

each supply once.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best, but this is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to the ground

plane, while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid

flexing the package and to avoid a point load on the surface of

this package during the assembly process.

The AD5360/AD5361 should have ample supply decoupling of

10 μF in parallel with 0.1 μF on each supply located as close to

the package as possible, ideally right up against the device. The

10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-

tor should have low effective series resistance (ESR) and effective

series inductance (ESI), such as the common ceramic types that

provide a low impedance path to ground at high frequencies, to

handle transient currents due to internal logic switching.

POWER SUPPLY SEQUENCING

When the supplies are connected to the AD5360/AD5361, it is

important that the AGND and DGND pins be connected to the

relevant ground plane before the positive or negative supplies

are applied. In most applications, this is not an issue because the

ground pins for the power supplies are connected to the ground

pins of the AD5360/AD5361 via ground planes. Where the

AD5360/AD5361 are used in a hot-swap card, care should be

taken to ensure that the ground pins are connected to the

supply grounds before the positive or negative supplies are

connected. This is required to prevent currents from flowing in

directions other than toward an analog or digital ground.

Digital lines running under the device should be avoided

because these couple noise onto the device. The analog ground

plane should be allowed to run under the AD5360/AD5361 to

avoid noise coupling. The power supply lines of the AD5360/

AD5361 should use as large a trace as possible to provide low

impedance paths and reduce the effects of glitches on the power

Rev. A | Page 25 of 28

AD5360/AD5361

INTERFACING EXAMPLES

The Analog Devices ADSP-21065L is a floating-point DSP with

two serial ports (SPORTs). Figure 26 shows how one SPORT

can be used to control the AD5360 or AD5361. In this example,

the transmit frame synchronization (TFS) pin is connected

to the receive frame synchronization (RFS) pin. Similarly,

the transmit and receive clocks (TCLK and RCLK) are also

connected together. The user can write to the AD5360 or

AD5361 by writing to the transmit register. A read operation

can be accomplished by first writing to the AD5360/AD5361

to tell the part that a read operation is required. A second write

operation with a NOP instruction causes the data to be read

from the AD5360/AD5361. The DSPs receive interrupt can be

used to indicate when the read operation is complete.

The SPI interface of the AD5360 and AD5361 is designed to

allow the parts to be easily connected to industry standard DSPs

and microcontrollers. Figure 25 shows how the AD5360/AD5361

can be connected to the Analog Devices, Inc., Blackfin® DSP. The

Blackfin has an integrated SPI port that can be connected directly

to the SPI pins of the AD5360 or AD5361, and programmable

I/O pins that can be used to set or read the state of the digital

input or output pins associated with the interface.

AD5360/

AD5361

SYNC

SPISELx

SCK

SCLK

MOSI

SDI

SDO

MISO

ADSP-21065L

TFSx

AD5360/

AD5361

RESET

PF10

PF9

PF8

PF7

RFSx

SYNC

ADSP-BF531

LDAC

CLR

TCLKx

RCLKx

SCLK

SDI

BUSY

DTxA

DRxA

SDO

Figure 25. Interfacing to a Blackfin DSP

FLAG

0

RESET

FLAG

1

LDAC

CLR

FLAG

2

3

BUSY

FLAG

Figure 26. Interfacing to an ADSP-21065L DSP

Rev. A | Page 26 of 28

AD5360/AD5361

OUTLINE DIMENSIONS

12.20

12.00 SQ

11.80

0.75

0.60

0.45

1.60

MAX

52

40

39

1

PIN 1

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

13

27

3.5°

0.15

0.05

0°

14

26

SEATING

PLANE

0.10

COPLANARITY

0.38

0.32

0.22

VIEW A

0.65

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BCC

Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP]

(ST-52)

Dimensions shown in millimeters

0.30

8.00

BSC SQ

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

43

42

56

1

PIN 1

INDICATOR

6.25

6.10 SQ

5.95

TOP

VIEW

EXPOSED

PAD

(BOTTOM VIEW)

7.75

BSC SQ

0.50

0.40

0.30

29

28

14

15

0.25 MIN

6.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SEATING

PLANE

0.50 BSC

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm, Very Thin Quad (CP-56-1)

Dimensions shown in millimeter

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ST-52

CP-56-1

ST-52

CP-56-1

AD5360BSTZ¹

−40°C to +85°C

52-Lead Low Profile Quad Flat Pack [LQFP]

AD5360BSTZ-REEL¹

AD5360BCPZ¹

AD5360BCPZ-REEL7¹

AD5361BSTZ¹

AD5361BSTZ-REEL¹

AD5361BCPZ¹

AD5361BCPZ-REEL7¹

EVAL-AD5360EBZ¹

EVAL-AD5361EBZ¹

56-Lead Lead Frame Chip Scale Package [LFCSP _VQ]

52-Lead Low Profile Quad Flat Pack [LQFP]

56-Lead Lead Frame Chip Scale Package [LFCSP _VQ]

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. A | Page 27 of 28

AD5360/AD5361

NOTES

registered trademarks are the property of their respective owners.

D05761-0-2/08(A)

Rev. A | Page 28 of 28


型号：	AD5361BSTZ-REEL1
厂家：	ADI
描述：	16-Channel, 16-/14-Bit, Serial Input, Voltage-Output DAC 16通道， 16位/ 14位，串行输入，电压输出DAC
文件：	总28页 (文件大小：825K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5361BSTZ-REEL1 [ADI]

相关型号：

AD5361BSTZ1

AD5361_15

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AD5362BCPZ

AD5362BCPZ

AD5362BCPZ-REEL7

AD5362BSTZ

AD5362_15

AD5363

AD5363BCPZ

AD5363BCPZ

AD5363BCPZ-REEL7