AD5363_15 [ADI]
8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC;
| 型号： | AD5363_15 |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC |
| 文件： | 总29页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5362/AD5363
FEATURES
8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output voltage spans available
Thermal shutdown function
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Channel monitoring multiplexer
GPIO function
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
FUNCTIONAL BLOCK DIAGRAM
DV
V
V
SS
CC
AGND DGND
LDAC
DD
TEMP
TEMP_OUT
PEC
VREF0
SENSOR
n = 16 FOR AD5362
n = 14 FOR AD5363
GROUP 0
BUFFER
8
CONTROL
REGISTER
14
n
14
n
OFFSET
DAC 0
OFS0
REGISTER
8
8
TO
VOUT0 TO
VOUT7
A/B SELECT
REGISTER
MON_IN0
MON_IN1
MUX 2s
BUFFER
6
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT0
VOUT1
n
X2A REGISTER
X2B REGISTER
DAC 0
REGISTER
A/B
MUX
n
MUX
n
MUX
2
DAC 0
X1 REGISTER
n
n
n
M REGISTER
MON_OUT
n
·
·
·
·
·
·
·
·
·
·
·
·
C REGISTER
2
GPIO
REGISTER
GPIO
·
·
·
·
·
·
·
·
·
·
·
·
VOUT2
BIN/2SCOMP
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
n
n
X2A REGISTER
X2B REGISTER
VOUT3
DAC 3
REGISTER
A/B
MUX
n
n
MUX
2
DAC 3
X1 REGISTER
SYNC
SDI
SIGGND0
n
n
n
n
M REGISTER
C REGISTER
SERIAL
INTERFACE
SCLK
SDO
VREF1
VOUT4
GROUP 1
BUFFER
14
n
n
n
OFFSET
DAC 1
OFS1
REGISTER
BUSY
8
n
8
n
TO
MUX 2s
A/B SELECT
REGISTER
BUFFER
RESET
CLR
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
X2A REGISTER
X2B REGISTER
DAC 4
REGISTER
A/B
MUX
MUX
2
DAC 4
X1 REGISTER
n
n
n
n
M REGISTER
C REGISTER
VOUT5
VOUT6
STATE
MACHINE
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
n
·
n
n
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
VOUT7
X2A REGISTER
X2B REGISTER
DAC 7
A/B
MUX
n
n
MUX
2
DAC 7
X1 REGISTER
REGISTER
SIGGND1
AD5362/
AD5363
n
n
n
n
M REGISTER
C REGISTER
Figure 1.
Rev. A
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Fax: 781.461.3113
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©2008 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD5362_5363*
Last content update 09/06/2013 12:23 pm
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DOCUMENTATION
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AN-1036: Clear to Any Voltage Using the AD5370
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EVALUATION KITS & SYMBOLS & FOOTPRINTS
SAMPLE & BUY
AD5362
View the Evaluation Boards and Kits page for the AD5362
View the Evaluation Boards and Kits page for the AD5363
Symbols and Footprints for the AD5362
AD5363
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AD5362/AD5363
TABLE OF CONTENTS
Features .............................................................................................. 1
Reset Function............................................................................ 20
Clear Function............................................................................ 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
DAC Architecture....................................................................... 16
Channel Groups.......................................................................... 16
A/B Registers and Gain/Offset Adjustment............................ 17
Offset DACs ................................................................................ 17
Output Amplifier........................................................................ 18
Transfer Function....................................................................... 18
Reference Selection .................................................................... 18
Calibration................................................................................... 19
Additional Calibration............................................................... 19
BUSY
LDAC
and
Functions...................................................... 20
BIN
/2SCOMP Pin...................................................................... 20
Temperature Sensor ................................................................... 20
Monitor Function....................................................................... 21
GPIO Pin ..................................................................................... 21
Power-Down Mode.................................................................... 21
Thermal Shutdown Function ................................................... 21
Toggle Mode................................................................................ 21
Serial Interface ................................................................................ 22
SPI Write Mode .......................................................................... 22
SPI Readback Mode ................................................................... 22
Register Update Rates................................................................ 22
Packet Error Checking............................................................... 23
Channel Addressing and Special Modes................................. 23
Special Function Mode.............................................................. 24
Applications Information.............................................................. 26
Power Supply Decoupling ......................................................... 26
Power Supply Sequencing ......................................................... 26
Interfacing Examples ................................................................. 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Added 56-Lead LFCSP_VQ ..............................................Universal
Changes to Table 2............................................................................ 4
Added t23 Parameter ......................................................................... 7
Changes to Figure 4.......................................................................... 8
Changes to Table 6.......................................................................... 11
Changes to A/B Registers and Gain/Offset Adjustment
Changes to Calibration Section.................................................... 19
BUSY
LDAC
Changes to Reset Function Section and
and
Functions Section........................................................................... 20
Changes to Channel Addressing and Special Modes Section .. 23
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
Section.............................................................................................. 17
1/08—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD5362/AD5363
GENERAL DESCRIPTION
The AD5362/AD5363 contain eight 16-/14-bit DACs in a single
52-lead LQFP package or 56-lead LFCSP package. The devices
provide buffered voltage outputs with a span of 4× the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device
is divided into two groups of four DACs, and the output range
of each group can be independently adjusted by an offset DAC.
The AD5362/AD5363 have a high speed 4-wire serial interface
that is compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
LDAC
taking the
input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
The AD5362/AD5363 offer guaranteed operation over a wide
supply range with VSS from −16.5 V to −4.5 V and VDD from 8 V
to 16.5 V. The output amplifier headroom requirement is 1.4 V,
operating with a load current of 1 mA.
CLR
switched to SIGGNDx via the
pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution (Bits)
Nominal Output Span
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
8.75 V
Output Channels
Linearity Error (LSB)
AD5360
AD5361
AD5362
AD5363
AD5370
AD5371
AD5372
AD5373
AD5378
AD5379
16
14
16
14
16
14
16
14
14
14
16
16
8
4
1
4
1
4
1
4
1
3
3
8
40
40
32
32
32
40
8.75 V
Rev. A | Page 3 of 28
AD5362/AD5363
SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
B Version1
Unit
Test Conditions/Comments
16
14
4
Bits
AD5362
Bits
AD5363
Integral Nonlinearity (INL)
LSB max
LSB max
LSB max
mV max
mV max
% FSR
LSB typ
LSB typ
mV max
ppm FSR/°C typ
μV max
AD5362
AD5363
1
1
15
20
0.1
1
Differential Nonlinearity (DNL)
Zero-Scale Error
Full-Scale Error
Guaranteed monotonic by design over temperature
Before calibration
Before calibration
Before calibration
After calibration
After calibration
See the Offset DACs section for details
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale, full-scale
change on any other channel
Gain Error
Zero-Scale Error2
Full-Scale Error2
1
Span Error of Offset DAC
VOUTx3 Temperature Coefficient
DC Crosstalk2
75
5
180
REFERENCE INPUTS (VREF0, VREF1)2
VREFx Input Current
VREFx Range2
10
2/5
μA max
V min/V max
Per input; typically 30 nA
2% for specified operation
SIGGND0 AND SIGGND1 INPUTS2
DC Input Impedance
Input Range
50
0.5
kΩ min
V min/V max
Typically 55 kΩ
SIGGNDx Gain
0.995/1.005 min/max
OUTPUT CHARACTERISTICS2
Output Voltage Range
VSS + 1.4
VDD − 1.4
−10 to +10
15
V min
V max
V
mA max
mA max
pF max
Ω max
ILOAD = 1 mA
ILOAD = 1 mA
Nominal Output Voltage Range
Short-Circuit Current
Load Current
VOUTx3 to DVCC, VDD, or VSS
1
Capacitive Load
2200
0.5
DC Output Impedance
MONITOR PIN (MON_OUT)2
Output Impedance
DAC Output at Positive Full Scale
DAC Output at Negative Full Scale
Three-State Leakage Current
Continuous Current Limit
DIGITAL INPUTS
1000
500
100
2
Ω typ
Ω typ
nA typ
mA max
Input High Voltage
1.7
2.0
0.8
1
V min
V min
V max
μA max
μA max
pF max
DVCC = 2.5 V to 3.6 V
DVCC = 3.6 V to 5.5 V
DVCC = 2.5 V to 5.5 V
RESET, SYNC, SDI, and SCLK pins
CLR, BIN/2SCOMP, and GPIO pins
Input Low Voltage
Input Current
20
10
Input Capacitance2
Rev. A | Page 4 of 28
AD5362/AD5363
Parameter
B Version1
Unit
Test Conditions/Comments
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)
Output Low Voltage
0.5
DVCC − 0.5
5
10
V max
V min
μA max
pF typ
Sinking 200 μA
Sourcing 200 μA
SDO only
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance2
TEMPERATURE SENSOR (TEMP_OUT)2
Accuracy
1
5
°C typ
°C typ
@ 25°C
−40°C < T < +85°C
Output Voltage at 25°C
Output Voltage Scale Factor
Output Load Current
Power-On Time
1.46
4.4
200
10
V typ
mV/°C typ
μA max
ms typ
Current source only
To within 5°C
POWER REQUIREMENTS
DVCC
VDD
VSS
2.5/5.5
8/16.5
−16.5/−4.5
V min/V max
V min/V max
V min/V max
Power Supply Sensitivity2
∆Full Scale/∆VDD
∆Full Scale/∆VSS
∆Full Scale/∆DVCC
−75
−75
−90
2
8.5
8.5
dB typ
dB typ
dB typ
mA max
mA max
mA max
DICC
DVCC = 5.5 V, VIH = DVCC, VIL = GND
Outputs = 0 V and unloaded
Outputs = 0 V and unloaded
Bit 0 in the control register is 1
IDD
ISS
Power-Down Mode
DICC
IDD
ISS
5
35
−35
μA typ
μA typ
μA typ
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature4
209
130
mW max
°C max
VSS = −12 V, VDD = 12 V, DVCC = 2.5 V
TJ = TA + PTOTAL × θJA
1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization; not production tested.
3 VOUTx refers to any of VOUT0 to VOUT7.
4 θJA represents the package thermal impedance.
Rev. A | Page 5 of 28
AD5362/AD5363
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE1
B Version1
Unit
Test Conditions/Comments
Output Voltage Settling Time
20
30
1
μs typ
μs max
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
5
10
100
10
0.2
0.02
250
VREF0, VREF1 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
Output Noise Spectral Density @ 10 kHz
1 Guaranteed by design and characterization; not production tested.
Rev. A | Page 6 of 28
AD5362/AD5363
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
11
20
10
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs typ/μs max
ns max
ns min
ns min
μs max
ns min
μs max
μs typ/μs max
ns max
ns min
μs max
ns min
ns max
ns max
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
5
Data hold time
4
t9
42
1/1.5
600
20
10
3
SYNC rising edge to BUSY falling edge
BUSY pulse width low (single-channel update); see Table 9
Single-channel update cycle time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR/RESET pulse activation time
RESET pulse width low
0
3
20/30
140
30
400
270
25
80
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
RESET rising edge to BUSY falling edge
5
t22
t23
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 t9 is measured with the load circuit shown in Figure 2.
5 t22 is measured with the load circuit shown in Figure 3.
200µA
I
OL
DV
CC
R
V
(MIN) – V (MAX)
OL
OH
TO OUTPUT
PIN
2
L
C
L
2.2k
Ω
TO
OUTPUT
PIN
50pF
V
OL
C
L
200µA
I
OH
50pF
BUSY
Figure 2. Load Circuit for
Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
Rev. A | Page 7 of 28
AD5362/AD5363
t1
SCLK
1
24
1
24
2
t3
t11
t2
t4
t6
t5
SYNC
SDI
t7
t8
DB0
DB23
t9
t10
BUSY
t12
t13
1
LDAC
t17
t14
t15
1
VOUTx
t13
2
LDAC
t17
2
VOUTx
t
16
CLR
t18
VOUTx
t19
RESET
VOUTx
t18
t20
BUSY
1
t23
LDAC ACTIVE DURING BUSY.
LDAC ACTIVE AFTER BUSY.
2
Figure 4. SPI Write Timing
Rev. A | Page 8 of 28
AD5362/AD5363
t22
SCLK
48
t21
SYNC
SDI
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB15
DB0
DB23
DB0
SDO
SELECTED REGISTER DATA CLOCKED OUT
LSB FROM PREVIOUS WRITE
Figure 5. SPI Read Timing
OUTPUT
VOLTAGE
FULL-SCALE
ERROR
V
MAX
+
ZERO-SCALE
ERROR
ACTUAL
TRANSFER
FUNCTION
IDEAL
TRANSFER
FUNCTION
N
0
DAC CODE
2
– 1
n = 16 FOR AD5362
n = 14 FOR AD5363
ZERO-SCALE
ERROR
V
MIN
Figure 6. DAC Transfer Function
Rev. A | Page 9 of 28
AD5362/AD5363
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.
Table 5.
Parameter
Rating
VDD to AGND
VSS to AGND
DVCC to DGND
−0.3 V to +17 V
−17 V to +0.3 V
−0.3 V to +7 V
Digital Inputs to DGND
Digital Outputs to DGND
VREF0, VREF1 to AGND
VOUT0 through VOUT7 to AGND
SIGGND0, SIGGND1 to AGND
AGND to DGND
−0.3 V to DVCC + 0.3 V
−0.3 V to DVCC + 0.3 V
−0.3 V to +5.5 V
VSS − 0.3 V to VDD + 0.3 V
−1 V to +1 V
ESD CAUTION
−0.3 V to +0.3 V
MON_IN0, MON_IN1, MON_OUT
to AGND
VSS − 0.3 V to VDD + 0.3 V
Operating Temperature Range (TA)
Industrial (J Version)
Storage Temperature Range
Operating Junction Temperature
(TJ max)
−40°C to +85°C
−65°C to +150°C
130°C
θJA Thermal Impedance
52-Lead LQFP
56-Lead LFCSP
38°C/W
25°C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
230°C
10 sec to 40 sec
Rev. A | Page 10 of 28
AD5362/AD5363
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
LDAC
CLR
1
2
39 NC
38 SIGGND0
37 VOUT3
RESET
BIN/2SCOMP
BUSY
1
2
42 NC
PIN 1
NC
41
RESET
BIN/2SCOMP
BUSY
3
INDICATOR
PIN 1
3
40 SIGGND0
39 VOUT3
38 VOUT2
37 VOUT1
36
35
34
33
32
31
30
29
28
27
4
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
INDICATOR
GPIO
4
5
MON_OUT
MON_IN0
NC
5
6
AD5362/
AD5363
TOP VIEW
(Not to Scale)
AD5362/
AD5363
TOP VIEW
(Not to Scale)
6
GPIO
VOUT0
36
7
7
MON_OUT
MON_IN0
NC
NC
35 TEMP_OUT
34 MON_IN1
33 VREF0
32 NC
8
NC
9
8
NC
10
11
12
13
14
9
NC
NC
31
V
10
11
12
13
NC
DD
SS
V
30 V
29 V
SS
DD
V
V
V
DD
SS
DD
VREF1
V
SS
VREF1
NC = NO CONNECT
NC
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
Figure 7. 52-Lead LQFP Pin Configuration
Figure 8. 56-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LQFP
LFCSP
Mnemonic
Description
1
55
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section
for more information.
2
56
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function
section for more information.
3
4
1
2
RESET
Digital Reset Input.
BIN/2SCOMP
Data Format Digital Input. Connecting this pin to DGND selects offset binary.
Setting this pin to 1 selects twos complement. This input has a weak pull-down.
5
6
3
4
BUSY
Digital Input/Open-Drain Output. BUSY is open drain when it is an output. See
the BUSY and LDAC Functions section for more information.
GPIO
Digital I/O Pin. This pin can be configured as an input or output that can be
read back or programmed high or low via the serial interface. When configured
as an input, this pin has a weak pull-down.
7
5
MON_OUT
Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the
MON_IN1 input can be routed to this output for monitoring.
8, 32
6, 34
MON_IN0,
MON_IN1
Analog Multiplexer Inputs. Can be routed to MON_OUT.
9, 10, 14, 20 to
27, 30, 39 to 42
7 to 11, 15, 16,
22 to 28, 31, 32,
41 to 44
NC
No Connect.
11, 28
12, 29
12, 29
VDD
VSS
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These
pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Negative Analog Power Supply; −16.5 V to −8 V for specified performance.
These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
13, 30
13
14
VREF1
Reference Input for DAC 4 to DAC 7. This reference voltage is referred to AGND.
34 to 37, 15 to 18 36 to 39, 17 to 20 VOUT0 to VOUT7 DAC Outputs. Buffered analog outputs for each of the eight DAC channels.
Each analog output is capable of driving an output load of 10 kΩ to ground.
Typical output impedance of these amplifiers is 0.5 Ω.
19
31
21
33
SIGGND1
VREF0
Reference Ground for DAC 4 to DAC 7. VOUT4 to VOUT7 are referenced to this
voltage.
Reference Input for DAC 0 to DAC 3. This reference voltage is referred to AGND.
Rev. A | Page 11 of 28
AD5362/AD5363
Pin No.
LQFP
LFCSP
Mnemonic
Description
33
35
TEMP_OUT
Provides an output voltage proportional to the chip temperature, typically
1.46 V at 25°C with an output variation of 4.4 mV/°C.
38
40
SIGGND0
DGND
DVCC
Reference Ground for DAC 0 to DAC 3. VOUT0 to VOUT3 are referenced to this
voltage.
Ground for All Digital Circuitry. Both DGND pins should be connected to the
DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
Active Low or SYNC Input for SPI Interface. This is the frame synchronization
signal for the SPI serial interface. See Figure 4, Figure 5, and the Serial Interface
section for more details.
43, 51
44, 50
45
45, 53
46, 52
47
SYNC
46
47
48
49
52
48
SCLK
SDI
Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface
section for more details.
Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface
section for more details.
Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up
that goes low if the packet error check fails.
Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.
49
50
PEC
SDO
AGND
EP
51
54
Ground for All Analog Circuitry. The AGND pin should be connected to the
AGND plane.
Exposed Paddle. Connect to VSS.
Exposed Paddle
Rev. A | Page 12 of 28
AD5362/AD5363
TYPICAL PERFORMANCE CHARACTERISTICS
2
0.0050
0.0025
0
T
= 25°C
A
V
V
V
= –15V
= +15V
SS
DD
= +4.096V
REF
1
0
–0.0025
–0.0050
–1
–2
0
16384
32768
49152
65535
0
1
2
3
4
5
DAC CODE
TIME (µs)
Figure 9. Typical AD5362 INL Plot
Figure 12. Digital Crosstalk
1.0
0.5
0
1.0
0.5
V
V
DV
V
= +15V
= –15V
DD
SS
= +5V
= +3V
CC
REF
0
–0.5
–0.5
–1.0
–1.0
0
16384
32768
49152
65535
0
20
40
60
80
DAC CODE
TEMPERATURE (°C)
Figure 10. Typical INL Error vs. Temperature
Figure 13. Typical AD5362 DNL Plot
0
–0.01
–0.02
600
500
400
300
200
100
T
= 25°C
A
V
V
V
= –15V
= +15V
SS
DD
= +4.096V
REF
0
0
0
2
4
6
8
10
1
2
3
4
5
TIME (µs)
FREQUENCY (Hz)
LDAC
Figure 14. Output Noise Spectral Density
Figure 11. Analog Crosstalk Due to
Rev. A | Page 13 of 28
AD5362/AD5363
0.50
14
12
10
8
DV
= 5V
CC
= 25°C
V
V
= –12V
= +12V
= +3V
SS
DD
T
A
V
REF
0.45
0.40
0.35
0.30
0.25
DV = +5.5V
CC
DV = +3.6V
CC
6
DV = +2.5V
CC
4
2
0
0.45
0.50
0.30
0.35
0.40
DI (mA)
–40
–20
0
20
40
60
80
CC
TEMPERATURE (°C)
Figure 15. DICC vs. Temperature
Figure 18. Typical DICC Distribution
2.0
6.5
6.0
5.5
5.0
4.5
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
I
DD
I
SS
V
= –12V
= +12V
= +3V
SS
DD
V
V
REF
–40
–25
–10
5
20
35
50
65
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. IDD/ISS vs. Temperature
Figure 19. TEMP_OUT Voltage vs. Temperature
1.0
14
V
V
= –15V
= +15V
SS
DD
FULL-SCALE
T
= 25°C
A
12
10
8
0.5
0
MIDSCALE
ZERO-SCALE
6
4
–0.5
–1.0
2
0
6.4
6.6
5.8
6.0
6.2
–1.0
–0.5
0
0.5
–1.0
I
(mA)
DD
MON_OUT CURRENT (mA)
Figure 17. Typical IDD Distribution
Figure 20. VOUTx MON_OUT Error vs. MON_OUT Current
Rev. A | Page 14 of 28
AD5362/AD5363
TERMINOLOGY
Output Voltage Settling Time
Integral Nonlinearity (INL)
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Integral nonlinearity, or endpoint linearity, is a measure of
the maximum deviation from a straight line passing through
the endpoints of the DAC transfer function. It is measured
after adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It is
specified as the area of the glitch in nV-s. It is measured by
toggling the DAC register data between 0x7FFF and 0x8000
(AD5362) or 0x1FFF and 0x2000 (AD5363).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC reference input that appears at the output
of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
all 0s are loaded into the DAC register. Zero-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its mini-
mum value. Zero-scale error is mainly due to offsets in the
output amplifier.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at
the output of one converter due to both the digital change
and subsequent analog output change at another converter.
It is specified in nV-s.
Full-Scale Error
Full-scale error is the error in the DAC output voltage when
all 1s are loaded into the DAC register. Full-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its maxi-
mum value. Full-scale error does not include zero-scale error.
Digital Crosstalk
Digital crosstalk is defined as the glitch impulse transferred to
the output of one converter due to a change in the DAC register
code of another converter. It is specified in nV-s.
Gain Error
Digital Feedthrough
Gain error is the difference between full-scale error and
zero-scale error. It is expressed as a percentage of the full-
scale range (FSR).
When the device is not selected, high frequency logic activity
on the digital inputs of the device can be capacitively coupled
both across and through the device to appear as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Gain Error = Full-Scale Error − Zero-Scale Error
VOUT Temperature Coefficient
The VOUT temperature coefficient includes output error
contributions from linearity, offset, and gain drift.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading
all DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
V
DD and VSS power supplies. If the dc load current changes in
one channel (due to an update), this change can result in a
further dc change in one or more channel outputs. This effect is
more significant at high load currents and is reduced as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple VDD and VSS terminals are
provided to minimize dc crosstalk.
Rev. A | Page 15 of 28
AD5362/AD5363
THEORY OF OPERATION
tapped off before being fed into the output amplifier. The output
amplifier multiplies the DAC output voltage by 4. The nominal
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.
DAC ARCHITECTURE
The AD5362/AD5363 contain eight DAC channels and eight
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5362) or 14-bit
(AD5363) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of resistors,
of equal value, from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit (AD5362)
or 14-bit (AD5363) binary digital code loaded to the DAC
register determines at which node on the string the voltage is
CHANNEL GROUPS
The eight DAC channels of the AD5362/AD5363 are arranged
into two groups of four channels. The four DACs of Group 0
derive their reference voltage from VREF0. The four DACs of
Group 1 derive their reference voltage from VREF1. Each group
has its own signal ground pin.
Table 7. AD5362/AD5363 Registers
Register Name
Word Length in Bits
Description
X1A (Group) (Channel)
X1B (Group) (Channel)
M (Group) (Channel)
C (Group) (Channel)
X2A (Group) (Channel)
16 (14)
16 (14)
16 (14)
16 (14)
Input Data Register A, one for each DAC channel.
Input Data Register B, one for each DAC channel.
Gain trim registers, one for each DAC channel.
Offset trim registers, one for each DAC channel.
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
16 (14)
X2B (Group) (Channel)
DAC (Group) (Channel)
16 (14)
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
OFS0
OFS1
Control
14
14
5
Offset DAC 0 data register: sets offset for Group 0.
Offset DAC 1 data register: sets offset for Group 1.
Bit 4 = overtemperature indicator.
Bit 3 = PEC error flag.
Bit 2 = A/B select.
Bit 1 = thermal shutdown.
Bit 0 = software power-down.
Monitor
6
Bit 5 = monitor enable.
Bit 4 = monitor DACs or monitor MON_INx pin.
Bit 3 to Bit 0 = monitor selection control.
GPIO
2
8
8
Bit 1 = GPIO configuration.
Bit 0 = GPIO data.
Bits [3:0] in this register determine whether a DAC in Group 0 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
Bits [3:0] in this register determine whether a DAC in Group 1 takes its data from
Register X2A or Register X2B (0 = X2A, 1 = X2B).
A/B Select 0
A/B Select 1
Table 8. AD5362/AD5363 Input Register Default Values
Register Name
AD5362 Default Value
AD5363 Default Value
X1A, X1B
M
C
OFS0, OFS1
Control
0x8000
0xFFFF
0x8000
0x2000
0x00
0x2000
0x3FFF
0x2000
0x2000
0x00
A/B Select 0 and A/B Select 1
0x00
0x00
Rev. A | Page 16 of 28
AD5362/AD5363
All DACs in the AD5362/AD5363 can be updated simultane-
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
LDAC
ously by taking
low when each DAC register is updated
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or X1B input
from either its X2A or X2B register, depending on the setting of
the A/B select registers. The DAC register is not readable or
A
register, depending on the setting of the /B bit in the control
LDAC
directly writable by the user.
can be permanently tied
A
register. If the /B bit is 0, data is written to the X1A register.
low, and the DAC output is updated whenever new data appears
in the appropriate DAC register.
A
If the /B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per-
channel basis so that some writes are to X1A registers and some
writes are to X1B registers.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
two 14-bit offset DACs, one for Group 0 and one for Group 1.
These allow the output range of all DACs connected to them to
be offset within a defined range. Thus, subject to the limitations
of headroom, it is possible to set the output range of Group 0 or
Group 1 to be unipolar positive, unipolar negative, or bipolar,
either symmetrical or asymmetrical about 0 V. The DACs in the
AD5362/AD5363 are factory trimmed with the offset DACs set
at their default values. This gives the best offset and gain perfor-
mance for the default output range and span.
X1A
REGISTER
X2A
REGISTER
DAC
REGISTER
MUX
MUX
DAC
X1B
REGISTER
X2B
REGISTER
M
REGISTER
C
REGISTER
Figure 21. Data Registers Associated with Each DAC Channel
When the output range is adjusted by changing the value of the
offset DAC, an extra offset is introduced due to the gain error of
the offset DAC. The amount of offset is dependent on the mag-
nitude of the reference and how much the offset DAC moves
from its default value. See the Specifications section for this
offset. The worst-case offset occurs when the offset DAC is at
positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can
be removed by programming the C register of the channel with
an appropriate value. The extra offset caused by the offset DAC
needs to be taken into account only when the offset DAC is
changed from its default value. Figure 22 shows the allowable
code range that can be loaded to the offset DAC, depending on
the reference value used. Thus, for a 5 V reference, the offset
DAC should not be programmed with a value greater than 8192
(0x2000).
Each DAC channel also has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is operated
on by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
Although a multiplier and an adder symbol are shown in Figure 21
for each channel, there is only one multiplier and one adder in
the device, which are shared among all channels. This has impli-
cations for the update speed when several channels are updated
at once, as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
A
register with the /B control bit set to 0, the X2A data is recal-
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B, or to M or C
5
A
with /B set to 1. The X2A and X2B registers are not readable
RESERVED
or directly writable by the user.
4
3
2
1
0
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. A 4-bit A/B select register
associated with each group of four DACs controls whether each
individual DAC takes its data from the X2A or X2B register. If a
bit in this register is 0, the DAC takes its data from the X2A
register; if 1, the DAC takes its data from the X2B register.
Note that because there are eight bits in two registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B select registers to 0 or to 1.
0
4096
8192
12288
16383
OFFSET DAC CODE
Figure 22. Offset DAC Code Range
Rev. A | Page 17 of 28
AD5362/AD5363
offset DAC is 8192 (0x2000). With a ꢁ V reference, this gives
a span of −10 V to +10 V.
OUTPUT AMPLIFIER
Because the output amplifiers can swing to 1.4 V below the
positive supply and 1.4 V above the negative supply, this limits
how much the output can be offset for a given reference voltage.
For example, it is not possible to have a unipolar output range
of 20 V, because the maximum supply voltage is 1ꢀ.ꢁ V.
AD5363 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 8192).
DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213
S1
DAC
CHANNEL
where:
OUTPUT
M = code in gain register − default code = 214 – 1.
C = code in offset register − default code = 213.
R6
10kΩ
S2
R5
60kΩ
CLR
CLR
The DAC output voltage is calculated as follows:
R1
20kΩ
S3
CLR
VOUT = 4 × VREF × (DAC_CODE − OFFSET_CODE)/
214 + VSIGGND
R4
60kΩ
SIGGNDx
R3
20kΩ
R2
20kΩ
SIGGNDx
where:
DAC_CODE should be within the range of 0 to 1ꢀ,383.
For 12 V span, VREF = 3.0 V.
OFFSET
DAC
For 20 V span, VREF = ꢁ.0 V.
Figure 23. Output Amplifier and Offset DAC
OFFSET_CODE is the code loaded to the offset DAC. On power-
up, the default code loaded to the offset DAC is 8192 (0x2000).
With a ꢁ V reference, this gives a span of −10 V to +10 V.
Figure 23 shows details of a DAC output amplifier and its connec-
tions to the offset DAC. On power-up, S1 is open, disconnecting
the amplifier from the output. S3 is closed, so the output is pulled
to SIGGNDx (R1 and R2 are greater than Rꢀ). S2 is also closed to
REFERENCE SELECTION
CLR
CLR
prevent the output amplifier from being open-loop. If
power-up, the output remains in this condition until
is low at
is taken
The ADꢁ3ꢀ2/ADꢁ3ꢀ3 have two reference input pins. The
voltage applied to the reference pins determines the output
voltage span on VOUT0 to VOUT7. VREF0 determines the
voltage span for VOUT0 to VOUT3 (Group 0), and VREF1
determines the voltage span for VOUT4 to VOUT7 (Group 1).
The reference voltage applied to each VREF pin can be differ-
ent, if required, allowing each group of four channels to have a
different voltage span. The output voltage range and span can
be adjusted further by programming the offset and gain
registers for each channel as well as programming the offset
DAC. If the offset and gain features are not used (that is, the M
and C registers are left at their default values), the required
reference levels can be calculated as follows:
high. The DAC registers can be programmed, and the outputs
CLR
assume the programmed values when
CLR
is taken high. Even if
is high at power-up, the output remains in this condition
until VDD > ꢀ V and VSS < −4 V and the initialization sequence has
finished. The outputs then go to their power-on default value.
TRANSFER FUNCTION
The output voltage of a DAC in the ADꢁ3ꢀ2/ADꢁ3ꢀ3 is depen-
dent on the value in the input register, the value of the M and C
registers, and the value in the offset DAC.
AD5362 Transfer Function
VREF = (VOUTMAX − VOUTMIN)/4
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 32,7ꢀ8).
If the offset and gain features of the ADꢁ3ꢀ2/ADꢁ3ꢀ3 are used,
the required output range is slightly different. The selected
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the selected
output range should be larger than the actual, required range.
DAC_CODE = INPUT_CODE × (M + 1)/21ꢀ + C − 21ꢁ
where:
M = code in gain register − default code = 21ꢀ – 1.
C = code in offset register − default code = 21ꢁ.
The required reference levels can be calculated as follows:
The DAC output voltage is calculated as follows:
1. Identify the nominal output range on VOUT.
2. Identify the maximum offset span and the maximum gain
required on the full output signal range.
3. Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4. Choose the new required VOUTMAX and VOUTMIN, keep-
ing the VOUT limits centered on the nominal values. Note
that VDD and VSS must provide sufficient headroom.
ꢁ. Calculate the value of VREF as follows:
VOUT = 4 × VREF × (DAC_CODE − (OFFSET_CODE ×
4))/21ꢀ + VSIGGND
where:
DAC_CODE should be within the range of 0 to ꢀꢁ,ꢁ3ꢁ.
For 12 V span, VREF = 3.0 V.
For 20 V span, VREF = ꢁ.0 V.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because this DAC is a
14-bit device. On power-up, the default code loaded to the
VREF = (VOUTMAX − VOUTMIN)/4
Rev. A | Page 18 of 28
AD5362/AD5363
Reference Selection Example
If
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
Nominal output range = 20 V (−10 V to +10 V)
Offset error = 100 mV
Gain error = 3%, and
SIGGND = AGND = 0 V
Then
1. Measure the zero-scale error.
2. Set the output to the highest possible value.
3. Measure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4. Calculate the number of LSBs equivalent to the span error
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
Gain error = 3%
=> Maximum positive gain error = 3%
=> Output range including gain error = 20 + 0.03(20) = 20.ꢀ V
AD5362 Calibration Example
Offset error = 100 mV
This example assumes that a −10 V to +10 V output is required.
The DAC output is set to −10 V but measured at −10.03 V. This
gives a zero-scale error of −30 mV.
=> Maximum offset error span = 2(100 mV) = 0.2 V
=> Output range including gain error and offset error =
20.ꢀ V + 0.2 V = 20.8 V
1 LSB = 20 V/ꢀꢁ,ꢁ3ꢀ = 30ꢁ.17ꢀ μV
30 mV = 98 LSBs
VREF calculation
Actual output range = 20.ꢀ V, that is, −10.3 V to +10.3 V
(centered);
The full-scale error can now be calculated. The output is set to
10 V and a value of 10.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV – (–30 mV) =
+ꢁ0 mV.
VREF = (10.3 V + 10.3 V)/4 = ꢁ.1ꢁ V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
•
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
ꢁ0 mV = 1ꢀ4 LSBs
The errors can now be removed as follows:
•
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
1. Add 98 LSBs to the default C register value:
(32,7ꢀ8 + 98) = 32,8ꢀꢀ
2. Subtract 1ꢀ4 LSBs from the default M register value:
(ꢀꢁ,ꢁ3ꢁ − 1ꢀ4) = ꢀꢁ,371
3. Program the M register to ꢀꢁ,371; program the C register
to 32,8ꢀꢀ.
•
Use a combination of these two approaches.
CALIBRATION
ADDITIONAL CALIBRATION
The user can perform a system calibration on the ADꢁ3ꢀ2/
ADꢁ3ꢀ3 to reduce gain and offset errors to below 1 LSB. This
reduction is achieved by calculating new values for the M and
C registers and reprogramming them.
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
The M and C registers should not be programmed until both
the zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1. Set the output to the lowest possible value.
These limitations can be overcome by increasing the reference
value. With a 2.ꢁ V reference, a 10 V span is achieved. The ideal
voltage range, for the ADꢁ3ꢀ2 or the ADꢁ3ꢀ3, is −ꢁ V to +ꢁ V.
Using a +2.ꢀ V reference increases the range to −ꢁ.2 V to +ꢁ.2 V.
Clearly, in this case, the offset and gain errors are insignificant,
and the M and C registers can be used to raise the negative
voltage to −ꢁ V and then reduce the maximum voltage to +5 V
to give the most accurate values possible.
2. Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
3. Calculate the number of LSBs equivalent to the error and
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Rev. A | Page 19 of 28
AD5362/AD5363
LDAC
The DAC outputs are updated by taking the
LDAC BUSY LDAC
input low. If
event is stored
BUSY
RESET FUNCTION
goes low while
and the DAC outputs are updated immediately after
LDAC
is active, the
RESET
The reset function is initiated by the
pin. On the rising
goes
input permanently low. In
BUSY
RESET
edge of
, the AD5362/AD5363 state machine initiates a
high. A user can also hold the
this case, the DAC outputs update immediately after
reset sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom-
goes
BUSY
high. Whenever the A/B select registers are written to,
also goes low, for approximately 600 ns.
RESET
mended that the user bring
high as soon as possible to
properly initialize the registers.
The AD5362/AD5363 have flexible addressing that allows
writing of data to a single channel, all channels in a group, or
all channels in the device. This means that one, two, four, or
eight DAC register values may need to be calculated and
updated. Because there is only one multiplier shared between
eight channels, this task must be done sequentially, so the
CLR
When the reset sequence is complete (and provided that
is
high), the DAC output is at a potential specified by the default
register settings, which is equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
LDAC
updated and
returned to the default state by pulsing
30 ns. Note that, because the reset function is triggered by the
is taken low. The AD5362/AD5363 can be
BUSY
length of the
pulse varies according to the number of
RESET
low for at least
channels being updated.
RESET
of the AD5362/AD5363.
rising edge, bringing
low has no effect on the operation
BUSY
Table 9.
Action
Pulse Widths
BUSY Pulse Width1
Loading input, C, or M to 1 channel2
Loading input, C, or M to 2 channels
Loading input, C, or M to 8 channels
1.5 μs maximum
2.1 μs maximum
5.7 μs maximum
CLEAR FUNCTION
CLR
is an active low input that should be high for normal
CLR
CLR
operation. The
resistor. When
pin has an internal 500 kΩ pull-down
is low, the input to each of the DAC output
1 BUSY
pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
buffer stages (VOUT0 to VOUT7) is switched to the externally
CLR
set potential on the relevant SIGGNDx pin. While
is low,
is taken high again,
The AD5362/AD5363 contain an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
LDAC CLR
all
pulses are ignored. When
the DAC outputs return to their previous values. The contents
of the input registers and DAC Register 0 to DAC Register 7 are
LDAC
written to since the last time
was brought low. Normally,
is brought low, the DAC registers are filled with
LDAC
when
CLR
not affected by taking
low. To prevent glitches appearing
the contents of the X2A or X2B registers, depending on the
setting of the A/B select registers. However, the AD5362/
AD5363 update the DAC register only if the X2A or X2B data
has changed, thereby removing unnecessary digital crosstalk.
CLR
on the outputs,
should be brought low whenever the
output span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M registers.
BIN/2SCOMP PIN
BIN
/2SCOMP pin determines if the output data is presented
The
BUSY
During the calculation of X2, the
output goes low. While
as offset binary or twos complement. If this pin is low, the data
is straight binary. If it is high, the data is twos complement. This
affects only the X, C, and offset DAC registers; the M register and
the control and command data are interpreted as straight binary.
BUSY
is low, the user can continue writing new data to the X1,
M, or C registers (see the Register Update Rates section for
more details), but no DAC output updates can take place.
BUSY
The
resistor. When multiple AD5362 or AD5363 devices are used in
BUSY
pin is bidirectional and has a 50 kΩ internal pull-up
TEMPERATURE SENSOR
The on-chip temperature sensor provides a voltage output
at the TEMP_OUT pin that is linearly proportional to the
Centigrade temperature scale. The typical accuracy of the
temperature sensor is +1°C at +25°C and 5°C over the −40°C
to +85°C range. Its nominal output voltage is 1.46 V at 25°C,
varying at 4.4 mV/°C. Its low output impedance, low self-
heating, and linear output simplify interfacing to temperature
control circuitry and analog-to-digital converters.
one system, the
pins can be tied together. This is useful
when it is required that no DAC in any device be updated until
all other DACs are ready. When each device has finished updat-
BUSY
ing the X2 (A or B) registers, it releases the
another device has not finished updating its X2 registers, it
BUSY LDAC
going low.
pin. If
holds
low, thus delaying the effect of
Rev. A | Page 20 of 28
AD5362/AD5363
When Bit F1 is set, the GPIO pin becomes an output and Bit F0
determines whether the pin is high or low. The GPIO pin can be
set as an input by writing 0 to both Bit F1 and Bit F0. The status
of the GPIO pin can be determined by initiating a read operation
using the appropriate bits in Table 17. The status of the pin is
indicated by the LSB of the register read.
MONITOR FUNCTION
The AD5362/AD5363 contain a channel monitor function
that consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to the
MON_OUT pin for monitoring using an external ADC. In
addition, two monitor inputs, MON_IN0 and MON_IN1,
are provided, which can also be routed to MON_OUT. The
monitor function is controlled by the monitor register, which
allows the monitor output to be enabled or disabled, and selects
a DAC channel or one of the monitor pins. When disabled, the
monitor output is high impedance so that several monitor
outputs can be connected in parallel with only one enabled at
a time. Table 10 shows the monitor register settings.
POWER-DOWN MODE
The AD5362/AD5363 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGNDx potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
Table 10. Monitor Register Functions
F5
0
1
1
1
1
1
1
1
1
1
1
1
F4
X
X
0
0
0
0
0
0
0
F3
X
X
0
0
0
0
1
1
1
F2
X
X
0
0
0
0
0
0
0
F1
X
X
0
0
1
1
0
0
1
F0
X
X
0
1
0
1
0
1
0
Function
THERMAL SHUTDOWN FUNCTION
MON_OUT disabled
MON_OUT enabled
MON_OUT = VOUT0
MON_OUT = VOUT1
MON_OUT = VOUT2
MON_OUT = VOUT3
MON_OUT = VOUT4
MON_OUT = VOUT5
MON_OUT = VOUT6
MON_OUT = VOUT7
MON_OUT = MON_IN0
MON_OUT = MON_IN1
The AD5362/AD5363 can be programmed to shut down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 enables this function (see Table 16).
If the die temperature exceeds 130°C, the AD5362/AD5363
enter a thermal shutdown mode, which is equivalent to setting
the power-down bit in the control register. To indicate that the
AD5362/AD5363 have entered thermal shutdown mode, Bit 4
of the control register is set to 1. The AD5362/AD5363 remain
in thermal shutdown mode, even if the die temperature falls,
until Bit 1 in the control register is cleared to 0.
0
1
1
1
0
0
0
0
0
1
0
0
1
0
1
TOGGLE MODE
The AD5362/AD5363 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise need to
write to each channel individually. When the user writes to the
X1A, X1B, M, or C register, the calculation engine takes a certain
amount of time to calculate the appropriate X2A or X2B value.
If an application, such as a data generator, requires that the DAC
output switch between two levels only, any method that reduces
the amount of calculation time necessary is advantageous. For
the data generator example, the user needs only to set the high
and low levels for each channel once by writing to the X1A and
X1B registers. The values of X2A and X2B are calculated and
stored in their respective registers. The calculation delay,
therefore, happens only during the setup phase, that is, when
programming the initial values. To toggle a DAC output between
the two levels, it is only required to write to the relevant A/B
select register to set the MUX2 register bit. Furthermore,
because there are four MUX2 control bits per register, it is
possible to update eight channels with just two writes. Table 18
shows the bits that correspond to each DAC output.
The multiplexer is implemented as a series of analog switches.
Because this could conceivably cause a large amount of current
to flow from the input of the multiplexer (VOUTx or MON_INx)
to the output of the multiplexer (MON_OUT), care should be
taken to ensure that whatever is connected to the MON_OUT
pin is of high enough impedance to prevent the continuous
current limit specification from being exceeded. Because the
MON_OUT pin is not buffered, the amount of current drawn
from this pin creates a voltage drop across the switches, which
in turn leads to an error in the voltage being monitored. Where
accuracy is important, it is recommended that the MON_OUT
pin be buffered. Figure 20 shows the typical error due to
MON_OUT current.
GPIO PIN
The AD5362/AD5363 have a general-purpose I/O pin, GPIO.
This pin can be configured as an input or an output and read
back or programmed (when configured as an output) via the
serial interface. Typical applications for this pin include moni-
toring the status of a logic signal, a limit switch, or controlling
an external multiplexer. The GPIO pin is configured by writing
to the GPIO register, which has the special function code of
001101 (see Table 15 and Table 16).
Rev. A | Page 21 of 28
AD5362/AD5363
SERIAL INTERFACE
The AD5362/AD5363 contain a high speed SPI operating at
clock frequencies up to 50 MHz (20 MHz for read operations).
To minimize both the power consumption of the device and
on-chip digital noise, the interface powers up fully only when
the device is being written to, that is, on the falling edge of
The input register addressed is updated on the rising edge of
SYNC SYNC
taken low again.
. For another serial transfer to take place,
must be
SPI READBACK MODE
The AD5362/AD5363 allow data readback via the serial
interface from every register directly accessible to the serial
interface, that is, all registers except the X2A, X2B, and DAC
data registers. To read back a register, it is first necessary to
tell the AD5362/AD5363 which register is to be read. This is
achieved by writing a word whose first two bits are the Special
Function Code 00 to the device. The remaining bits then
determine which register is to be read back.
SYNC
. The serial interface is 2.5 V LVTTL-compatible when
operating from a 2.5 V to 3.6 V DVCC supply. It is controlled by
SYNC
four pins:
(frame synchronization input), SDI (serial data
input pin), SCLK (clocks data in and out of the device), and
SDO (serial data output pin for data readback).
SPI WRITE MODE
The AD5362/AD5363 allow writing of data via the serial inter-
face to every register directly accessible to the serial interface,
that is, all registers except the X2A, X2B, and DAC registers.
The X2A and X2B registers are updated when writing to the
X1A, X1B, M, and C registers, and the DAC data registers are
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See Figure 5 for the read timing diagram. Note that due to the
timing requirements of t22 (25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
LDAC
updated by
. The serial word (see Table 11 or Table 12)
is 24 bits long: 16 (AD5362) or 14 (AD5363) of these bits are
data bits; six bits are address bits; and two bits are mode bits
that determine what is done with the data. Two bits are reserved
on the AD5363.
REGISTER UPDATE RATES
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5362/AD5363 by clock pulses applied to SCLK. The first
The value of the X2A register or the X2B register is calculated
each time the user writes new data to the corresponding X1, C,
or M register. The calculation is performed by a three-stage
process. The first two stages take approximately 600 ns each, and
the third stage takes approximately 300 ns. When the write to an
X1, C, or M register is complete, the calculation process begins.
If the write operation involves the update of a single DAC
channel, the user is free to write to another register, provided
that the write operation does not finish until the first-stage
calculation is complete, that is, 600 ns after the completion of
the first write operation. If a group of channels is being updated
by a single write operation, the first-stage calculation is repeated
for each channel, taking 600 ns per channel. In this case, the
user should not complete the next write operation until this time
has elapsed.
SYNC
falling edge of
clock edges must be applied to SCLK to clock in 24 bits of data
SYNC SYNC
starts the write cycle. At least 24 falling
before
the 24th falling clock edge, the write operation is aborted.
SYNC
is taken high again. If
is taken high before
If a continuous clock is used,
must be taken high before the
25th falling clock edge. This inhibits the clock within the AD5362/
AD5363. If more than 24 falling clock edges are applied before
SYNC
If an externally gated clock of exactly 24 pulses is used,
can be taken high any time after the 24th falling clock edge.
is taken high again, the input data becomes corrupted.
SYNC
Table 11. AD5362 Serial Word Bit Assignment
I23 I22 I21 I20 I19 I18 I17 I16 I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 12. AD5363 Serial Word Bit Assignment
I23 I22 I21 I20 I19 I18 I17 I16 I15
I14
I13
I12
I11 I10 I9
I8
I7
I6
I5
I4
I3
I2
I11 I01
M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1 Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.
Rev. A | Page 22 of 28
AD5362/AD5363
PACKET ERROR CHECKING
CHANNEL ADDRESSING AND SPECIAL MODES
To verify that data has been received correctly in noisy environ-
ments, the AD5362/AD5363 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5362/AD5363 should generate an 8-bit
checksum using the polynomial C(x) = x8 + x2 + x1 + 1. This is
added to the end of the data-word, and 32 data bits are sent to
If the mode bits are not 00, the data-word D15 to D0 (AD5362)
or D13 to D0 (AD5363) is written to the device. Address Bit A4
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in Table 13 and Table 14. Data is to
A
be written to the X1A register when the /B bit in the control
SYNC
the AD5362/AD5363 before taking
AD5363 see a 32-bit data frame, an error check is performed
SYNC
high. If the AD5362/
A
register is 0, or to the X1B register when the /B bit is 1.
The AD5362/AD5363 have very flexible addressing that allows
the writing of data to a single channel, all channels in a group,
or all channels in the device.
when
written to the selected register. If the checksum is invalid, the
PEC
goes high. If the checksum is valid, the data is
packet error check (
control register is set. After reading the control register, Bit 3
PEC
) output goes low and Bit 3 of the
Table 14 shows which groups and which channels are addressed
for every combination of Address Bit A4 to Address Bit A0.
is cleared automatically and
goes high again.
Table 13. Mode Bits
M1 M0 Action
UPDATE ON SYNC HIGH
SYNC
1
1
0
0
1
0
1
0
Write to DAC data (X) register
Write to DAC offset (C) register
Write to DAC gain (M) register
Special function, used in combination with other
bits of the data-word
SCLK
SDI
MSB
D23
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO ERROR CHECKING
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SCLK
SDI
MSB
D31
LSB
D8
D7
D0
8-BIT FCS
24-BIT DATA
PEC GOES LOW IF
ERROR CHECK FAILS
PEC
24-BIT DATA TRANSFER WITH ERROR CHECKING
Figure 24. SPI Write With and Without Error Checking
Table 14. Group and Channel Addressing
Address Bit A4 to Address Bit A3
10
Address Bit A2
to Address Bit A0
00
01
11
000
001
010
011
100
101
110
111
All groups, all channels
Group 0, all channels
Group 1, all channels
Unused
Unused
Unused
Group 0, Channel 0
Group 0, Channel 1
Group 0, Channel 2
Group 0, Channel 3
Unused
Unused
Unused
Unused
Group 1, Channel 0
Group 1, Channel 1
Group 1, Channel 2
Group 1, Channel 3
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Rev. A | Page 23 of 28
AD5362/AD5363
SPECIAL FUNCTION MODE
If the mode bits are 00, the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the
special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data
readback. The codes for the special functions are shown in Table 16. Table 17 shows the addresses for data readback.
Table 15. Special Function Mode
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
0
0
S5
S4
S3
S2
S1
S0
F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
Table 16. Special Function Codes
Special Function Code
S5 S4 S3 S2 S1 S0 Data (F15 to F0)
Action
0
0
0
0
0
0
0
0
0
0
0
1
0000 0000 0000 0000
XXXX XXXX XXXX X [F2:F0]
NOP.
Write control register.
F4 = 1: Temperature over 130°C.
F4 = 0: Temperature below 130°C.
Read-only bit. This bit should be 0 when writing to the control register.
F3 = 1: PEC error.
F3 = 0: No PEC error. Reserved.
Read-only bit. This bit should be 0 when writing to the control register.
F2 = 1: Select Register X1B for input.
F2 = 0: Select Register X1A for input.
F1 = 1: Enable thermal shutdown mode.
F1 = 0: Disable thermal shutdown mode.
F0 = 1: Software power-down.
F0 = 0: Software power-up.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
XX [F13:F0]
XX [F13:F0]
Reserved
See Table 17
XXXX XXXX XXXX [F3:F0]
XXXX XXXX XXXX [F3:F0]
Reserved
Reserved
Reserved
Write data in F13 to F0 to OFS0 register.
Write data in F13 to F0 to OFS1 register.
Select register for readback.
Write data in F3 to F0 to A/B Select Register 0.
Write data in F3 to F0 to A/B Select Register 1.
XXXX XXXX [F7:F0]
Block write to A/B select registers.
F7 to F0 = 0: Write all 0s (all channels use X2A register).
F7 to F0 = 1: Write all 1s (all channels use X2B register).
F5 = 1: Monitor enable.
0
0
1
1
0
0
XXXX XXXX XX [F5:F0]
F5 = 0: Monitor disable.
F4 = 1: Monitor input pin selected by F0.
F4 = 0: Monitor DAC channel selected by F3:F0 (see Table 10).
F3 = not used if F4 = 1.
F2 = not used if F4 = 1.
F1 = not used if F4 = 1.
F0 = 0: MON_IN0 selected for monitoring (if F4 and F5 = 1).
F0 = 1: MON_IN1 selected for monitoring (if F4 and F5 = 1).
GPIO configure and write.
0
0
1
1
0
1
XXXX XXXX XXXX XX [F1:F0]
F1 = 1: GPIO is an output. Data to output is written to F0.
F1 = 0: GPIO is an input. Data can be read from F0 on readback.
Rev. A | Page 24 of 28
AD5362/AD5363
Table 17. Address Codes for Data Readback1
F15
F14
F13
F12
F11
F10
F9
F8
F7
Register Read
X1A register
X1B register
C register
M register
0
0
0
0
0
0
1
1
0
1
0
1
Bit F12 to Bit F7 select the channel to be read back;
Channel 0 = 001000 to Channel 3 = 001011
Channel 4 = 010000 to Channel 7 = 010011
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
Control register
OFS0 data register
OFS1 data register
Reserved
1
0
0
A/B Select Register 0
A/B Select Register 1
Reserved
Reserved
Reserved
GPIO read (data in F0)2
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1 Bit F6 to Bit F0 are don’t cares for the data readback function.
2 Bit F6 to Bit F0 should be 0 for GPIO read.
Table 18. DACs Selected by A/B Select Registers
Bits1
F3
A/B Select
Register
F7
F6
F5
F4
F2
F1
F0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DAC 3
DAC 7
DAC 2
DAC 6
DAC 1
DAC 5
DAC 0
DAC 4
1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.
Rev. A | Page 25 of 28
AD5362/AD5363
APPLICATIONS INFORMATION
care should be taken to ensure that the ground pins are
connected to the supply grounds before the positive or negative
supplies are connected. This is required to prevent currents
from flowing in directions other than toward an analog or
digital ground.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit boards on
which the AD5362/AD5363 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5362/AD5363 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (VSS, VDD, DVCC),
it is recommended that these pins be tied together and that each
supply be decoupled only once.
INTERFACING EXAMPLES
The SPI interface of the AD5362/AD5363 is designed to allow
the parts to be easily connected to industry-standard DSPs and
microcontrollers. Figure 25 shows how the AD5362/AD5363 can
connect to the Analog Devices, Inc., Blackfin® DSP. The Blackfin
has an integrated SPI port that can be connected directly to the
SPI pins of the AD5362 or AD5363, and programmable I/O
pins that can be used to set or read the state of the digital input
or output pins associated with the interface.
The AD5362/AD5363 should have ample supply decoupling of
10 μF in parallel with 0.1 μF on each supply located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI)—typical of the common ceramic types
that provide a low impedance path to ground at high frequencies—
to handle transient currents due to internal logic switching.
AD5362/
AD5363
SYNC
SPISELx
SCK
SCLK
MOSI
SDI
SDO
MISO
RESET
PF10
PF9
PF8
PF7
ADSP-BF531
LDAC
CLR
Digital lines running under the device should be avoided because
they can couple noise onto the device. The analog ground plane
should be allowed to run under the AD5362/AD5363 to avoid
noise coupling. The power supply lines of the AD5362/AD5363
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching digital signals should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
they should never be run near the reference inputs. It is essential
to minimize noise on the VREF0 and VREF1 lines.
BUSY
Figure 25. Interfacing to a Blackfin DSP
The Analog Devices ADSP-21065L is a floating-point DSP with
two serial ports (SPORTs). Figure 26 shows how one SPORT can
be used to control the AD5362 or AD5363. In this example, the
transmit frame synchronization (TFSx) pin is connected to the
receive frame synchronization (RFSx) pin. Similarly, the transmit
and receive clocks (TCLKx and RCLKx) are also connected. The
user can write to the AD5362/AD5363 by writing to the transmit
register of the ADSP-21065L. A read operation can be accom-
plished by first writing to the AD5362/AD5363 to tell the part
that a read operation is required. A second write operation with
an NOP instruction causes the data to be read from the
AD5362/AD5363. The DSP receive interrupt can be used to
indicate when the read operation is complete.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board. A
microstrip technique is by far the best approach, but it is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
ADSP-21065L
TFSx
AD5362/
AD5363
RFSx
SYNC
TCLKx
RCLKx
SCLK
SDI
POWER SUPPLY SEQUENCING
DTxA
DRxA
When the supplies are connected to the AD5362/AD5363, it
is important that the AGND and DGND pins be connected
to the relevant ground plane before the positive or negative
supplies are applied. In most applications, this is not an issue
because the ground pins for the power supplies are connected
to the ground pins of the AD5362/AD5363 via ground planes.
When the AD5362/AD5363 are to be used in a hot-swap card,
SDO
FLAG
0
RESET
FLAG
1
LDAC
CLR
FLAG
2
3
BUSY
FLAG
Figure 26. Interfacing to an ADSP-21065L DSP
Rev. A | Page 26 of 28
AD5362/AD5363
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
52
40
39
1
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
13
27
3.5°
0.15
0.05
0°
14
26
SEATING
PLANE
0.10
COPLANARITY
0.38
0.32
0.22
VIEW A
0.65
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCC
Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP]
(ST-52)
Dimensions shown in millimeters
0.30
8.00
BSC SQ
0.23
0.18
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
43
42
56
1
PIN 1
INDICATOR
6.25
6.10 SQ
5.95
TOP
VIEW
EXPOSED
PAD
(BOTTOM VIEW)
7.75
BSC SQ
0.50
0.40
0.30
29
28
14
15
0.25 MIN
6.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-1)
Dimensions shown in millimeters
Rev. A | Page 27 of 28
AD5362/AD5363
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-52
ST-52
CP-56-1
CP-56-1
AD5362BSTZ1
52-Lead Low Profile Quad Flat Package [LQFP]
52-Lead Low Profile Quad Flat Package [LQFP]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
AD5362BSTZ-REEL1
AD5362BCPZ1
AD5362BCPZ-REEL71
EVAL-AD5362EBZ1
AD5363BSTZ1
AD5363BSTZ-REEL1
AD5363BCPZ1
AD5363BCPZ-REEL71
EVAL-AD5363EBZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
52-Lead Low Profile Quad Flat Package [LQFP]
52-Lead Low Profile Quad Flat Package [LQFP]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
ST-52
ST-52
CP-56-1
CP-56-1
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05762-0-3/08(A)
Rev. A | Page 28 of 28
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