AD5370BCPZ-REEL7 [ADI]
40-Channel, 16-Bit, Serial Input, Voltage-Output DAC;
| 型号： | AD5370BCPZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 40-Channel, 16-Bit, Serial Input, Voltage-Output DAC 转换器 |
| 文件： | 总28页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40-Channel,16-Bit,
Serial Input, Voltage Output DAC
AD5370
2.5 V to 5.5 V digital interface
FEATURES
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
40-channel DAC in a 64-lead LFCSP and a 64-lead LQFP
Guaranteed monotonic to 16 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage span of −4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DV
V
V
SS AGND DGND
CC
DD
LDAC
VREF0
GROUP 0
16
BUFFER
BUFFER
16
16
16
CONTROL
REGISTER
OFS0
OFFSET
DAC 0
REGISTER
8
8
TO
A/B SELECT
REGISTER
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
MUX2
16
16
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
X2A
X1A
REGISTER
16
16
16
16
REGISTER
DAC 0
REGISTER
DAC 0
X1B
REGISTER
X2B
REGISTER
16
16
M REGISTER
C REGISTER
16
OUTPUT BUFFER
AND
16
16
SERIAL
X2A
X1A
16
16
16
INTERFACE
16
16
REGISTER
POWER-DOWN
CONTROL
DAC 7
REGISTER
SYNC
SDI
DAC 7
REGISTER
SIGGND0
X1B
REGISTER
X2B
REGISTER
16
16
SCLK
SDO
M REGISTER
C REGISTER
16
VREF1
GROUP 1
BUSY
BUFFER
BUFFER
16
16
16
16
OFS1
REGISTER
OFFSET
DAC 1
8
8
RESET
CLR
TO
MUX2
A/B SELECT
REGISTER
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
16
16
VOUT8
X2A
REGISTER
X1A
REGISTER
16
16
16
DAC 0
REGISTER
VOUT9
DAC 0
STATE
MACHINE
X1B
REGISTER
X2B
REGISTER
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
16
16
16
M REGISTER
C REGISTER
16
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
16
16
X2A
REGISTER
X1A
REGISTER
16
16
16
16
16
DAC 7
REGISTER
DAC 7
SIGGND1
X1B
REGISTER
X2B
REGISTER
16
16
M REGISTER
C REGISTER
16
AD5370
GROUP 2 TO GROUP 4
ARE THE SAME AS GROUP 1
VOUT16
TO
VOUT39
SIGGND2 SIGGND3
SIGGND4
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD5370
TABLE OF CONTENTS
Features .............................................................................................. 1
Transfer Function....................................................................... 17
Reference Selection .................................................................... 17
Calibration................................................................................... 18
Additional Calibration............................................................... 18
Reset Function............................................................................ 19
Clear Function............................................................................ 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Performance Specifications......................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
DAC Architecture....................................................................... 15
Channel Groups.......................................................................... 15
BUSY
LDAC
Functions...................................................... 19
and
Power-Down Mode.................................................................... 19
Thermal Shutdown Function ................................................... 19
Toggle Mode................................................................................ 20
Serial Interface ................................................................................ 21
SPI Write Mode .......................................................................... 21
SPI Readback Mode ................................................................... 21
Register Update Rates................................................................ 21
Channel Addressing and Special Modes................................. 21
Special Function Mode.............................................................. 23
Power Supply Decoupling ......................................................... 25
Power Supply Sequencing ......................................................... 25
Interfacing Examples ................................................................. 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
A
/B Registers and Gain/Offset Adjustment............................ 16
Load DAC.................................................................................... 16
Offset DAC Channels ................................................................ 16
Output Amplifier........................................................................ 17
REVISION HISTORY
4/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5370
GENERAL DESCRIPTION
The AD53701 contains forty 16-bit DACs in a single 64-lead
LFCSP and a 64-lead LQFP. The device provides buffered
voltage outputs with a span that is 4× the reference voltage. The
gain and offset of each DAC channel can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into five groups of eight DACs. Three offset DAC channels
allow the output range of blocks to be adjusted. Group 0 can be
adjusted by Offset DAC 0, Group 1 can be adjusted by Offset
DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.
The AD5370 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on receipt of new data. All the
LDAC
outputs can be updated simultaneously by taking the
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect to
an external SIGGNDx input. The DAC outputs can also be
The AD5370 offers guaranteed operation over a wide supply
range, with VSS from −16.5 V to −4.5 V and VDD from +9 V to
+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
CLR
switched to SIGGNDx via the
pin.
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
Table 1. High Channel Count Bipolar DACs
Model
Resolution
16 bits
14 bits
16 bits
14 bits
16 bits
14 bits
16 bits
14 bits
14 bits
14 bits
Nominal Output Span
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (20 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
4 × VREF (12 V)
8.75 V
Output Channels
Linearity Error (LSB)
AD5360
AD5361
AD5362
AD5363
AD5370
AD5371
AD5372
AD5373
AD5378
AD5379
16
16
8
4
1
4
1
4
1
4
1
3
3
8
40
40
32
32
32
40
8.75 V
Rev. 0 | Page 3 of 28
AD5370
SPECIFICATIONS
PERFORMANCE SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = open circuit;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Type
Max
Unit
Test Conditions/Comments1
ACCURACY
Resolution
16
−4
−1
−10
−10
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error2
Full-Scale Error2
Span Error of Offset DAC
+4
+1
+10
+10
0.1
Guaranteed monotonic by design
Before calibration
Before calibration
mV
% FSR
LSB
LSB
mV
1
1
After calibration
After calibration
See the Offset DAC Channels section for
details
−35
+35
120
VOUT Temperature Coefficient
(VOUT0 to VOUT39)
DC Crosstalk2
5
ppm FSR/°C
μV
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1)2
VREF Input Current
VREF Range
−10
2
+10
5
μA
V
Per input, typically 30 nA
2% for specified operation
SIGGND INPUT (SIGGND0 to SIGGND4)2
DC Input Impedance
Input Range
50
−0.5
0.995
kΩ
V
Typically 55 kΩ
+0.5
1.005
SIGGND Gain
OUTPUT CHARACTERISTICS2
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
VSS + 1.4
−4
VDD − 1.4
+8
15
+1
2200
0.5
V
V
mA
mA
pF
ILOAD = 1 mA
VOUTx to DVCC, VDD, or VSS
−1
Input High Voltage
1.7
2.0
V
V
V
μA
μA
DVCC = 2.5 V to 3.6 V
DVCC = 3.6 V to 5.5 V
DVCC = 2.5 V to 5.5 V
Excluding the CLR pin
Input Low Voltage
Input Current
0.8
+1
−1
CLR High Impedance Leakage
Current
Input Capacitance2
−20
+20
10
pF
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage
Output High Voltage (SDO)
SDO High Impedance Leakage
Current
0.5
+5
V
V
μA
Sinking 200 ꢀA
Sourcing 200 ꢀA
DVCC − 0.5
−5
High Impedance Output
Capacitance2
10
pF
Rev. 0 | Page 4 of 28
AD5370
Parameter
Min
Type
Max
Unit
Test Conditions/Comments1
POWER REQUIREMENTS
DVCC
VDD
VSS
2.5
9
−16.5
5.5
16.5
−4.5
V
V
V
Power Supply Sensitivity2
∆Full Scale/∆VDD
∆Full Scale/∆VSS
∆Full Scale/∆DVCC
DICC
−75
−75
−90
dB
dB
dB
mA
2
DVCC = 5.5 V, VIH = DVCC, VIL = GND; normal
operating conditions
IDD
ISS
18
20
−18
−20
mA
mA
mA
mA
mW
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
VSS = −8 V, VDD = +9.5 V, DVCC = 2.5 V
Power Dissipation Unloaded (P)
280
Power-Down Mode
Control register power-down bit set
DICC
IDD
ISS
5
35
−35
μA
μA
μA
°C
Junction Temperature3
130
TJ = TA + PTOTAL × θJA
1 Temperature range for the AD5370 is −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJA represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics1
Parameter
Min Typ Max Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
20
μs
Settling to 1 LSB from a full-scale change
30
10
μs
DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate
1
5
V/μs
nV-s
mV
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
100
20
0.2
0.02
250
dB
VREF0 = VREF1 = 2 V p-p, 1 kHz
nV-s
nV-s
nV-s
nV/√Hz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
Output Noise Spectral Density @ 10 kHz
1 Guaranteed by design and characterization, not production tested.
Rev. 0 | Page 5 of 28
AD5370
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Limit at TMIN, TMAX
Parameter 1, 2, 3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
ns
μs
μs
ns
ns
μs
ns
ns
ns
Description
Min
20
8
Typ
Max
t1
t2
t3
t4
t5
t6
t7
t8
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
8
11
20
10
5
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
5
Data hold time
4
t9
42
SYNC rising edge to BUSY falling edge
BUSY pulse width low (single-channel update); see Table 8
Single-channel update cycle time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
1.5
600
20
10
3
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR/RESET pulse activation time
RESET pulse width low
0
3
20
30
140
30
400
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
RESET rising edge to BUSY falling edge
270
5
t22
25
80
t23
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 This is measured with the load circuit shown in Figure 2.
5 This is measured with the load circuit shown in Figure 3.
TIMING DIAGRAMS
DV
CC
R
200µA
I
OL
L
2.2k
Ω
TO
OUTPUT
PIN
V
V
(MIN) – V (MAX)
OL
OL
OH
TO OUTPUT
PIN
C
L
2
C
L
50pF
50pF
200µA
I
OH
BUSY
Figure 3. Load Circuit for SDO Timing Diagram
Figure 2. Load Circuit for
Timing Diagram
Rev. 0 | Page 6 of 28
AD5370
t1
SCLK
1
24
1
24
2
t3
t11
t2
t4
t6
t5
SYNC
SDI
t7
t8
DB0
DB23
t9
t10
BUSY
t12
t13
1
LDAC
t17
t14
t15
1
VOUTx
t13
2
LDAC
t17
2
VOUTx
t
16
CLR
t18
VOUTx
t19
RESET
VOUTx
t18
t20
BUSY
1
t23
LDAC ACTIVE DURING BUSY.
LDAC ACTIVE AFTER BUSY.
2
Figure 4. SPI Write Timing
Rev. 0 | Page 7 of 28
AD5370
t22
SCLK
48
t21
SYNC
SDI
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
DB23
DB0
SDO
SELECTED REGISTER DATA CLOCKED OUT
LSB FROM PREVIOUS WRITE
Figure 5. SPI Read Timing
Rev. 0 | Page 8 of 28
AD5370
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to AGND
VSS to AGND
DVCC to DGND
−0.3 V to +17 V
−17 V to +0.3 V
−0.3 V to +7 V
Digital Inputs to DGND
Digital Outputs to DGND
VREF0, VREF1 to AGND
VOUT0 through VOUT39 to AGND
SIGGND0 through SIGGND4 to AGND
AGND to DGND
−0.3 V to DVCC + 0.3 V
−0.3 V to DVCC + 0.3 V
−0.3 V to +5.5 V
VSS − 0.3 V to VDD + 0.3 V
−1 V to +1 V
ESD CAUTION
−0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial (B Version)
Storage
Operating Junction Temperature
(TJ max)
−40°C to +85°C
−65°C to +150°C
130°C
θJA Thermal Impedance
64-Lead LFCSP
25°C/W
64-Lead LQFP
45.5°C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
230°C
10 sec to 40 sec
Rev. 0 | Page 9 of 28
AD5370
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
RESET
2
BUSY
PIN 1
INDICATOR
RESET
BUSY
1
2
3
4
5
6
7
8
9
48 VOUT5
47 VOUT4
46 SIGGND0
45 VOUT3
44 VOUT2
43 VOUT1
42 VOUT0
41 VREF0
40 VOUT23
39 VOUT22
38 VOUT21
37 VOUT20
3
4
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33
VOUT34
VOUT35
SIGGND4
VOUT36
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33 10
VOUT34 11
VOUT35 12
SIGGND4 13
VOUT36 14
VOUT37 15
5
6
AD5370
TOP VIEW
(Not to Scale)
7
AD5370
TOP VIEW
(Not to Scale)
8
9
VOUT23
VOUT22
VOUT21
VOUT20
10
11
12
13
14
36 V
35 V
SS
DD
34 SIGGND2
33 VOUT19
V
16
DD
V
SS
V
DD
VOUT37 15
SIGGND2
VOUT19
V
16
DD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6. 64-Lead LFCSP Pin Configuration
Figure 7. 64-Lead LQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
RESET
Digital Reset Input.
BUSY
BUSY Input/Output (Active Low). BUSY is open-drain when an output. See the BUSY and
LDAC Functions section for more information.
3, 5 to 12, 14, 15, 19 to
24, 26 to 33, 37 to 40, 42
to 45, 47 to 50, 60 to 62
VOUT0 to VOUT39 DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog
output is capable of driving an output load of 10 kΩ to ground. Typical output impedance
of these amplifiers is 0.5 Ω.
46
25
34
4
13
41
18
SIGGND0
SIGGND1
SIGGND2
SIGGND3
SIGGND4
VREF0
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Ground for DAC 24 and DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
Reference Ground for DAC 32 to DAC 39. VOUT32 to VOUT39 are referenced to this voltage.
Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
Reference Input for DAC 8 to DAC 39. This reference voltage is referred to AGND.
VREF1
Rev. 0 | Page 10 of 28
AD5370
Pin No.
Mnemonic
Description
16, 35
VDD
Positive Analog Power Supply; +9 V to +16.5 V for specified performance. These pins
should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
17, 36
VSS
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins
should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
51, 58
52, 57
DGND
DVCC
Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
53
54
SYNC
SCLK
Active Low Input. This is the frame synchronization signal for the serial interface. See the
Timing Characteristics section for more details.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This
pin operates at clock speeds up to 50 MHz. See the Timing Characteristics section for
more details.
55
56
SDI
Serial Data Input. Data must be valid on the falling edge of SCLK. See the Timing
Characteristics section for more details.
Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is
clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
SDO
59
63
64
AGND
LDAC
CLR
Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
Load DAC Logic Input (Active Low).
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for
more information.
Exposed Paddle
The lead-free chip scale package (LFCSP) has an exposed paddle on the underside. The
paddle should be connected to VSS.
Rev. 0 | Page 11 of 28
AD5370
TYPICAL PERFORMANCE CHARACTERISTICS
2
0
–0.01
–0.02
T
V
V
= 25°C
A
= –15V
= +15V
SS
DD
VREF = +4.096V
1
0
–1
–2
0
2
4
6
8
10
0
16384
32768
49152
65535
TIME (µs)
DAC CODE
Figure 8.Typical INL Plot
LDAC
Figure 11. Analog Crosstalk Due to
0.0050
0.0025
0
T = 25°C
A
7
6
5
4
3
2
1
0
V
V
= +15V
= –15V
= 25°C
DD
SS
V
= –15V
SS
V
= +15V
T
DD
A
VREF = +4.096V
–0.0025
–0.0050
0
1
2
3
4
5
–0.6
–0.3
0
0.3
0.6
TIME (µs)
INL (LSB)
Figure 9. Typical INL Distribution
Figure 12. Digital Crosstalk
4
2
4
V
V
= +15V
= –15V
= +5V
DD
SS
DV
CC
VREF = +3V
2
0
0
–2
–2
–4
–4
0
16384
32768
49152
65535
0
20
40
60
80
DAC CODE
TEMPERATURE (°C)
Figure 13. Typical DNL Plot
Figure 10. Typical INL Error vs. Temperature
Rev. 0 | Page 12 of 28
AD5370
600
500
400
300
200
100
0
14
12
10
8
V
V
= 15V
= 15V
= 25°C
DD
SS
T
A
6
4
2
0
13.00
13.25
13.50
(mA)
13.75
14.00
0
1
2
3
4
5
I
DD
FREQUENCY (Hz)
Figure 14. Noise Spectral Density
Figure 17. Typical IDD Distribution
0.50
0.45
0.40
0.35
0.30
0.25
14
DV
= 5V
= 25°C
CC
V
V
= –12V
= +12V
SS
DD
T
A
VREF = +3V
12
10
8
DV
= +5.5V
CC
DV
= +3.6V
CC
6
DV
= +2.5V
CC
4
2
0
0.30
0.35
0.40
(mA)
0.45
0.50
–40
–20
0
20
40
60
80
I
CC
TEMPERATURE (°C)
Figure 18. Typical DICC Distribution
Figure 15.DICC vs. Temperature
14.0
I
DD
13.5
13.0
12.5
12.0
I
SS
V
V
= –12V
= +12V
SS
DD
VREF = +3V
–40 –20
0
20
40
60
80
TEMPERATURE (°C)
Figure 16. IDD/ISS vs. Temperature
Rev. 0 | Page 13 of 28
AD5370
TERMINOLOGY
Integral Nonlinearity (INL)
significant at high load currents and reduces as the load currents
are reduced. With high impedance loads, the effect is virtually
immeasurable. Multiple VDD and VSS terminals are provided to
minimize dc crosstalk.
Integral nonlinearity, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in millivolts, when the
channel is at its minimum value. Zero-scale error is mainly due
to offsets in the output amplifier.
DAC-to-DAC Crosstalk
Full-Scale Error
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register. Full-scale error is a measure
of the difference between VOUT (actual) and VOUT (ideal),
expressed in millivolts, when the channel is at its maximum
value. It does not include zero-scale error.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Gain Error
Gain error is the difference between full-scale error and zero-
scale error. It is expressed in millivolts.
Digital Feedthrough
Gain Error = Full-Scale Error − Zero-Scale Error
When the device is not selected, high frequency logic activity
on the digital inputs of the device can be capacitively coupled
both across and through the device to appear as noise on the
VOUTx pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
Output Noise Spectral Density
Output noise spectral density is a measure of internally gener-
ated random noise. Random noise is characterized as a spectral
density (voltage per √Hz). It is measured by loading all DACs
to midscale and measuring noise at the output. It is measured
in nV/√Hz.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
VDD and VSS power supplies. If the dc load current changes in
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
Rev. 0 | Page 14 of 28
AD5370
THEORY OF OPERATION
DAC ARCHITECTURE
CHANNEL GROUPS
The AD5370 contains 40 DAC channels and 40 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 16-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, of equal value, from VREF to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
output voltage by 4. The nominal output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
The 40 DAC channels of the AD5370 are arranged into five
groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 4 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5370 Registers
Word
Length Default
(Bits)
Register
Name
Value
Description
X1A
X1B
M
C
X2A
16
16
16
16
0x1555
0x1555
0x3FFF
0x2000
Not user
Input Data Register A. One for each DAC channel.
Input Data Register B. One for each DAC channel.
Gain trim register. One for each DAC channel.
Offset trim register. One for each DAC channel.
16
Output Data Register A. One for each DAC channel. These registers store the final calibrated DAC
accessible data after gain and offset trimming. They are not readable or directly writable.
Not user Output Data Register B. One for each DAC channel. These registers store the final calibrated DAC
accessible data after gain and offset trimming. They are not readable or directly writable.
Not user Data registers from which the DAC channels take their final input data. The DAC registers are
accessible updated from the X2A or X2B register. They are not readable or directly writable.
X2B
16
DAC
OFS0
OFS1
Control
14
14
3
0x1555
0x1555
0x00
Offset DAC 0 data register. Sets the offset for Group 0.
Offset DAC 1 data register. Sets the offset for Group 1 to Group 4.
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = X1B registers.
Bit 1 = enable temperature shutdown.
0 = disable temperature shutdown.
1 = enable.
Bit 0 = soft power-down.
0 = soft power-up.
1 = soft power-down.
A/B Select 0
A/B Select 1
A/B Select 2
A/B Select 3
A/B Select 4
8
8
8
8
8
0x00
0x00
0x00
0x00
0x00
Each bit in this register determines if a DAC channel in Group 0 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 1 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 2 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 3 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Each bit in this register determines if a DAC channel in Group 4 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.
Rev. 0 | Page 15 of 28
AD5370
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
LOAD DAC
All DAC channels in the AD5370 can be updated simultane-
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or X1B input register,
LDAC
ously by taking
low when each DAC register is updated
A
from either its X2A or X2B register, depending on the setting of
depending on the setting of the /B bit in the Control register.
A
the /B select registers. The DAC register is not readable or
A
A
If the /B bit is 0, data is written to the X1A register. If the /B
bit is 1, data is written to the X1B register. Note that this single
bit is a global control and affects every DAC channel in the
device. It is not possible to set up the device on a per-channel
basis so that some writes are to X1A registers and some writes
are to X1B registers.
directly writable by the user.
OFFSET DAC CHANNELS
In addition to the gain and offset trim for each DAC channel,
there are two 14-bit offset DAC channels, one for Group 0 and
one for Group 1 to Group 4. These allow the output range of all
DAC channels connected to them to be offset within a defined
range. Thus, subject to the limitations of headroom, it is possible to
set the output range of Group 0 or Group 1 to Group 4 to be
unipolar positive, unipolar negative, or bipolar, either symmetrical
or asymmetrical about 0 V. The DAC channels in the AD5370
are factory trimmed with the offset DAC channels set at their
default values. This results in optimum offset and gain performance
for the default output range and span.
X1A
X2A
REGISTER
REGISTER
DAC
REGISTER
MUX
MUX
DAC
X1B
X2B
REGISTER
REGISTER
M
REGISTER
C
REGISTER
Figure 19. Data Registers Associated with Each DAC Channel
Each DAC channel also has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is operated on
by a digital multiplier and an adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
When the output range is adjusted by changing the value of the
offset DAC channel, an extra offset is introduced due to the
gain error of the offset DAC channel. The amount of offset is
dependent on the magnitude of the reference and how much
the offset DAC channel deviates from its default value. This
offset is quoted in the Specifications section.
The worst-case offset occurs when the offset DAC channel is at
positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can be
removed by programming the channel’s C register with an
appropriate value. The extra offset caused by the offset DAC s
only needs to be taken into account when an offset DAC
channel is changed from its default value.
Although Figure 19 indicates a multiplier and an adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all channels. This has implications
for the update speed when several channels are updated at once,
as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
A
register with the /B control bit set to 0, the X2A data is recal-
Figure 20 shows the allowable code range that can be loaded to
the offset DAC channel; this is dependent on the reference value
used. Thus, for a 5 V reference, the offset DAC channel should
not be programmed with a value greater than 8192 (0x2000).
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B or to M or C
A
with /B set to 1. The X2A and X2B registers are not readable
or directly writable by the user.
5
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
RESERVED
4
3
2
1
0
A
by an 8-bit /B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC0 to DAC7).
Note that, because there are 40 bits in five registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
A
provided, which sets all bits in the /B select registers to 0 or to 1.
0
4096
8192
12288
16383
OFFSET DAC CODE
Figure 20. Offset DAC Code Range
Rev. 0 | Page 16 of 28
AD5370
The input code is the value in the X1A or X1B register that is
applied to DAC (X1A, X1B default code = 5461), as follows:
OUTPUT AMPLIFIER
The output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, which limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of 20 V
because the maximum supply voltage is 16.5 V.
INPUT _CODE×(M +1)
DAC _CODE =
+C − 215
216
DAC output voltage is calculated as follows:
DAC_CODE −
4 × OFFSET _CODE
+VSIGGND
VOUT = 4×VREF×
S1
216
DAC
CHANNEL
VOUT
R6
10kΩ
S2
R5
60kΩ
where:
CLR
CLR
DAC_CODE should be within the range of 0 to 65,535.
For 12 V span, VREF = 3.0 V.
R1
20kΩ
S3
CLR
For 20 V span, VREF = 5.0 V.
R4
SIGGND
R3
R2
20kΩ
60kΩ
M = code in gain register − default code = 216 – 1.
C = code in offset register − default code = 215.
OFFSET_CODE is the code loaded to the offset DAC. It is
20kΩ
SIGGND
OFFSET
DAC
multiplied by 4 in the transfer function because the offset DAC
is a 14-bit device. On power-up, the default code loaded to the
offset DAC is 5461 (0x1555). With a 3 V reference, this gives a
span of −4 V to +8 V.
Figure 21. Output Amplifier and Offset DAC
Figure 21 shows details of a DAC output amplifier and its
connections to its corresponding offset DAC. On power-up, S1
is open, disconnecting the amplifier from the output. S3 is
closed; thus, the output is pulled to the corresponding SIGGND
(R1 and R2 are much greater than R6). S2 is also closed to
prevent the output amplifier being open-loop. If
power-up, the output remains in this condition until
REFERENCE SELECTION
The AD5370 has two reference input pins. The voltage applied
to the reference pins determines the output voltage span on
VOUT0 to VOUT39. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT39 (Group 2 to Group 4).
The reference voltage applied to each VREF pin can be
different, if required, allowing each group to have a different
voltage span. The output voltage range and span can be adjusted
further by programming the offset and gain registers for each
channel and by programming the offset DAC channels. If the
offset and gain features are not used (that is, the M and C
registers are left at their default values), the required reference
levels can be calculated as follows:
CLR
is low at
CLR
is
taken high. The DAC registers can be programmed, and the
CLR
outputs assume the programmed values when
is taken
is high at power-up, the output remains in the
CLR
high. Even if
previously described condition until VDD > 6 V and VSS
< −4 V and the initialization sequence has finished. The outputs
then go to their power-on default values.
TRANSFER FUNCTION
OUTPUT
VOLTAGE
FULL-SCALE
ERROR
VREF = (VOUTMAX − VOUTMIN)/4
8V
+
ZERO-SCALE
ERROR
If the offset and gain features of the AD5370 are used, the
required output range is slightly different. The chosen output
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual required range.
ACTUAL
TRANSFER
FUNCTION
IDEAL
TRANSFER
FUNCTION
The required reference levels can be calculated as follows:
0
DAC CODE
16383
1. Identify the nominal output range on VOUT.
2. Identify the maximum offset span and the maximum gain
required on the full output signal range.
3. Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4. Choose the new required VOUTMAX and VOUTMIN, keeping
the VOUT limits centered on the nominal values. Note that
ZERO-SCALE
ERROR
–4V
Figure 22. DAC Transfer Function
V
DD and VSS must provide sufficient headroom.
The output voltage of a DAC in the AD5370 is dependent on the
value in the input register, the value of the M and C registers,
and the value in the offset DAC. The transfer functions for the
AD5370 are shown in the following section.
5. Calculate the value of VREF as follows:
VREF = (VOUTMAX − VOUTMIN)/4
Rev. 0 | Page 17 of 28
AD5370
Reference Selection Example
Reducing Full-scale Error
If
Full-scale error can be reduced as follows:
1. Measure the zero-scale error.
2. Set the output to the highest possible value.
•
•
•
•
Nominal Output Range = 12 V (−4 V to +8 V)
Zero-Scale Error = 70 mV
Gain Error = 3%
3. Measure the actual output voltage and compare it with the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4. Calculate the number of LSBs equivalent to the full-scale
error and subtract it from the default value of the M register.
Note that only positive full-scale error can be reduced.
5. The M and C registers should not be programmed until
both zero-scale and full-scale errors have been calculated.
SIGGND = AGND = 0 V
Then
•
•
•
Gain Error = 3%
=> Maximum Positive Gain Error = +3%
=> Output Range Including Gain Error = 12 + 0.03(12) =
12.36 V
Offset Error = 70 mV
AD5370 Calibration Example
=> Maximum Offset Error Span = 2(70 mV) = 0.14 V
=> Output Range Including Gain Error and Offset Error =
12.36 V + 0.14 V = 12.5 V
VREF Calculation
Actual Output Range = 12.5 V, that is, −4.25 V to +8.25 V;
This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but measured at −4.03 V. This
gives a zero-scale error of −30 mV.
1. 1 LSB = 12 V/65,536 = 183.11 μV
2. 30 mV = 164 LSB
VREF = (8.25 V + 4.25 V)/4 = 3.125 V
The full-scale error can now be calculated. The output is set to
+8 V and a value of +8.02 V is measured. The full-scale error is
+20 mV – (–30 mV) = +50 mV.
If the equation yields an inconvenient reference level, the user
can adopt one of the following approaches:
•
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
50 mV = 273 LSBs
The errors can now be removed.
•
Select a convenient reference level above VREF, and modify
the gain and offset registers to downsize the reference digitally.
In this way, the user can use almost any convenient reference
level but may reduce the performance by overcompaction
of the transfer function.
1. 164 LSB should be added to the default C register value,
that is (32,768 + 164) = 32,932.
2. 273 LSB should be subtracted from the default M register
value; that is, (65,535 − 273) = 65,262.
3. 65,262 should be programmed to the M register and 32,932
should be programmed to the C register.
•
Use a combination of these two approaches.
CALIBRATION
ADDITIONAL CALIBRATION
The user can perform a system calibration on the AD5370 to
reduce gain and offset errors to below 1 LSB. This is achieved
by calculating new values for the M and C registers and reprogram-
ming them.
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently removed. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1. Set the output to the lowest possible value.
2. Measure the actual output voltage and compare it with the
required value. This gives the zero-scale error.
3. Calculate the number of LSBs equivalent to the error and
add this from the default value of the C register. Note that
only negative zero-scale error can be reduced.
These limitations can be overcome by increasing the reference
value. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range for the AD5370 is −4 V to +8 V. Using a 3.1 V
reference increases the range to −4.133 V to +8.2667 V. Clearly,
in this case, the offset and gain errors are insignificant, and the
M and C registers can be used to raise the negative voltage to
−4 V and then reduce the maximum voltage to +8 V to give the
most accurate values possible.
Rev. 0 | Page 18 of 28
AD5370
A
BUSY
high. Whenever the /B select registers are written to,
RESET FUNCTION
also goes low, for approximately 600 ns.
RESET
The reset function is initiated by the
pin. On the rising
The AD5370 has flexible addressing that allows writing of data
to a single channel, all channels in a group, the same channel in
Group 0 to Group 4 or the same channel in Group 1 to Group 4,
or all channels in the device. This means that 1, 4, 5, 8, or 40
DAC register values may need to be calculated and updated.
Because there is only one multiplier shared among 40 channels,
this task must be done sequentially so that the length of the
RESET
edge of
, the AD5370 state machine initiates a reset
sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom-
mended that the user bring
properly initialize the registers.
When the reset sequence is complete (and provided that
high), the DAC output is at a potential specified by the default
register settings, which are equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
RESET
high as soon as possible to
CLR
is
BUSY
pulse varies according to the number of channels being
updated.
BUSY
Table 8.
Pulse Widths
LDAC
BUSY Pulse Width1
(μs max)
updated and
to the default state by pulsing
that, because the reset function is triggered on the rising edge,
RESET
is taken low. The AD5370 can be returned
RESET
low for at least 30 ns. Note
Action
Loading X1A, X1B, C, or M to 1 channel2
Loading X1A, X1B, C, or M to 4 channels
Loading X1A, X1B, C, or M to 5 channels
Loading X1A, X1B, C, or M to 8 channels
Loading X1A, X1B, C, or M to 40 channels
1.5
3.3
3.9
5.7
24.9
bringing
low has no effect on the operation of the AD5370.
CLEAR FUNCTION
CLR
is an active low input that should be high for normal
operation. The
resistor. When
CLR
pin has in internal 500 kΩ pull-down
1 BUSY
Pulse Width = ((Number of Channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
CLR
is low, the input to each of the DAC output
buffer stages, VOUT0 to VOUT39, is switched to the externally
CLR
The AD5370 contains an extra feature whereby a DAC register
is not updated unless its X2A or X2B register has been written
set potential on the relevant SIGGND pin. While
is low, all
is taken high again, the
LDAC
LDAC CLR
pulses are ignored. When
DAC outputs remain cleared until
of the input registers and DAC registers are not affected by taking
CLR CLR
LDAC
to since the last time
LDAC
was brought low. Normally, when
is brought low, the DAC registers are filled with the
contents of the X2A or X2B register, depending on the setting of
is taken low. The contents
low. To prevent glitches from appearing on the outputs,
A
the /B select registers. However, the AD5370 updates the DAC
should be brought low by writing to the offset DAC whenever
the output span is adjusted.
register only if the X2 data has changed, thereby removing
unnecessary digital crosstalk.
BUSY AND LDAC FUNCTIONS
POWER-DOWN MODE
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the
is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
details), but no DAC output updates can take place.
The AD5370 can be powered down by setting Bit 0 in the
control register to 1. This turns off the DAC channels, thus
reducing the current consumption. The DAC outputs are
connected to their respective SIGGND potentials. The power-
down mode does not change the contents of the registers, and
the DAC channels return to their previous voltage when the
power-down bit is cleared to 0.
BUSY
output goes low. While
BUSY
BUSY
The
resistor. In cases where multiple AD5370 devices are used in
BUSY
pin is bidirectional and has a 50 kΩ internal pull-up
THERMAL SHUTDOWN FUNCTION
one system, the
pins can be tied together. This is useful
The AD5370 can be programmed to power down the DACs if
the temperature on the die exceeds 130°C. Setting Bit 1 in the
control register to 1 (see the Special Function Mode section)
enables this function. If the die temperature exceeds 130°C, the
AD5370 enters a temperature power-down mode, which is
equivalent to setting the power-down bit in the control register.
To indicate that the AD5370 has entered temperature shutdown
mode, Bit 4 of the control register is set to 1. The AD5370 remains
in temperature shutdown mode, even if the die temperature
falls, until Bit 1 in the control register is cleared to 0.
when it is required that no DAC channel in any device be
updated until all other DAC channels are ready to be updated.
When each device finishes updating the X2 (A or B) register, it
BUSY
releases the
updating its X2 register, it holds
LDAC
pin. If another device has not finished
BUSY
low, thus delaying the
effect of
The DAC outputs are updated by taking the
LDAC BUSY LDAC
going low.
LDAC
input low. If
event is stored
BUSY
goes low while
and the DAC outputs update immediately after
LDAC
is active, the
goes
input permanently low. In
BUSY
high. A user can also hold the
this case, the DAC outputs update immediately after
goes
Rev. 0 | Page 19 of 28
AD5370
For the data generator example, the user need only set the high
and low levels for each channel once by writing to the X1A and
X1B registers. The values of X2A and X2B are calculated and
stored in their respective registers. The calculation delay
therefore happens only during the setup phase, that is, when
programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the
TOGGLE MODE
The AD5370 has two X2 registers per channel, X2A and X2B,
that can be used to switch the DAC output between two levels
with ease. This approach greatly reduces the overhead required
by a microprocessor that would otherwise have to write to each
channel individually. When the user writes to the X1A, X2A, M,
or C register, the calculation engine takes a certain amount of
time to calculate the appropriate X2A or X2B value. If the
application only requires that the DAC output switch between
two levels, as is the case with a data generator, any method that
reduces the amount of calculation time necessary is advantageous.
A
relevant /B select register to set the MUX2 register bit. Further-
more, because there are eight MUX2 control bits per register, it
is possible to update eight channels with a single write. Table 15
shows the bits that correspond to each DAC output.
Rev. 0 | Page 20 of 28
AD5370
SERIAL INTERFACE
The AD5370 contains a high speed SPI-compatible serial interface
operating at clock frequencies up to 50 MHz (20 MHz for read
operations). To minimize both the power consumption of the
device and on-chip digital noise, the interface powers up fully
only when the device is being written to, that is, on the falling
first two bits are the Special Function Code 00 to the device. The
remaining bits then determine which register is to be read back.
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See Figure 5 for the read timing diagram. Note that, due to the
timing requirements of t5 (25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
SYNC
edge of
when operating from a 2.5 V to 3.6 V DVCC supply. It is con-
SYNC
. The serial interface is 2.5 V LVTTL-compatible
trolled by four pins:
(frame synchronization input), SDI
(serial data input pin), SCLK (clocks data in and out of the device),
and SDO (serial data output pin for data readback).
SPI WRITE MODE
REGISTER UPDATE RATES
The AD5370 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the X2A and X2B registers and the DAC
registers. The X2A and X2B registers are updated when the user
writes to the X1A, X1B, M, or C register, and the DAC registers
The value of the X2A or X2B register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
The calculation is performed by a three-stage process. The first
two stages take approximately 600 ns each, and the third stage
takes approximately 300 ns. When the write to the X1, C, or M
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user
is free to write to another register, provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should not
complete the next write operation until this time has elapsed.
LDAC
are updated by
.
The serial word (see Table 10) is 24 bits long; 16 of these bits are
data bits, six bits are address bits, and two bits are mode bits that
determine what is done with the data.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5370 by clock pulses applied to SCLK. The first falling
SYNC
edge of
starts the write cycle. At least 24 falling clock edges
SYNC
must be applied to SCLK to clock in 24 bits of data before
CHANNEL ADDRESSING AND SPECIAL MODES
th
SYNC
is taken high again. If
is taken high before the 24 falling
If the mode bits are not 00, the data-word for D13 to D0 is
written to the device. Address Bit A5 to Address Bit A0
determine which channels are written to, whereas the mode bits
determine the register (X1A, X1B, C, or M) to which the data is
written, as shown in Table 9. If data is to be written to the X1A or
clock edge, the write operation is aborted.
SYNC
If a continuous clock is used,
must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5370. If more than 24 falling clock edges are applied before
SYNC
is taken high again, the input data becomes corrupted. If
A
X1B register, the setting of the /B bit in the control register
SYNC
an externally gated clock of exactly 24 pulses is used,
can
determines the register to which the data is written (that is,
0 → X1A, 1 → X1B).
be taken high any time after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC SYNC
taken low again.
Table 9. Mode Bits
. For another serial transfer to take place,
must be
M1
M0
Action
1
1
Writes to the DAC input data (X) register,
depending on the control register A/B bit
SPI READBACK MODE
1
0
0
0
1
0
Writes to the DAC offset (C) register
Writes to the DAC gain (M) register
Special function, used in combination
with other bits of the data-word
The AD5370 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the X2A, X2B, and DAC registers. To read
back a register, it is first necessary to tell the AD5370 which
register to read. This is achieved by writing a word whose
Table 10. Serial Word Bit Assignment
I23 I22 I21 I20 I19 I18 I17 I16 I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev. 0 | Page 21 of 28
AD5370
Table 11 shows the groups and channels that are addressed for every combination of Address Bit A5 to Address Bit A0.
Table 11. Group and Channel Addressing
Address Bit A2 to
Address Bit A0
Address Bit A5 to Address Bit A3
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
All groups,
all channels
Group 0,
Channel 0 Channel 0
Group 1,
Group 2,
Channel 0 Channel 0
Group 3,
Group 4,
Channel 0
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 0
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 1
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 2
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 3
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 4
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 5
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 6
Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 7
Group 1,
Group 2,
Group 3,
Group 4;
Channel 0
Group 0,
all channels
Group 0,
Channel 1 Channel 1
Group 1,
Group 2,
Channel 1 Channel 1
Group 3,
Group 4,
Channel 1
Group 1,
Group 2,
Group 3,
Group 4;
Channel 1
Group 1,
all channels
Group 0,
Channel 2 Channel 2
Group 1,
Group 2,
Channel 2 Channel 2
Group 3,
Group 4,
Channel 2
Group 1,
Group 2,
Group 3,
Group 4;
Channel 2
Group 2,
all channels
Group 0,
Channel 3 Channel 3
Group 1,
Group 2,
Channel 3 Channel 3
Group 3,
Group 4,
Channel 3
Group 1,
Group 2,
Group 3,
Group 4;
Channel 3
Group 3,
all channels
Group 0,
Channel 4 Channel 4
Group 1,
Group 2,
Channel 4 Channel 4
Group 3,
Group 4,
Channel 4
Group 1,
Group 2,
Group 3,
Group 4;
Channel 4
Group 4,
all channels
Group 0,
Channel 5 Channel 5
Group 1,
Group 2,
Channel 5 Channel 5
Group 3,
Group 4,
Channel 5
Group 1,
Group 2,
Group 3,
Group 4;
Channel 5
Reserved
Reserved
Group 0,
Channel 6 Channel 6
Group 1,
Group 2,
Channel 6 Channel 6
Group 3,
Group 4,
Channel 6
Group 1,
Group 2,
Group 3,
Group 4;
Channel 6
Group 0,
Channel 7 Channel 7
Group 1,
Group 2,
Channel 7 Channel 7
Group 3,
Group 4,
Channel 7
Group 1,
Group 2,
Group 3,
Group 4;
Channel 7
Rev. 0 | Page 22 of 28
AD5370
SPECIAL FUNCTION MODE
If the mode bits are 00, the special function mode is selected, as shown in Table 12. Bit I21 to Bit I16 of the serial data-word select the special
function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback.
The codes for the special functions are shown in Table 13. Table 14 shows the addresses for data readback.
Table 12. Special Function Mode
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
0
0
S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
Table 13. Special Function Codes
Special Function Code
S5 S4 S3 S2 S1 S0 Data (F15 to F0)
Action
0
0
0
0
0
0
0
0
0
0
0
1
0000 0000 0000 0000
XXXX XXXX XXXX X [F2:F0]
NOP.
Write to the Control register.
F4 = overtemperature indicator (read-only bit). This bit should be 0 when
writing to the Control register.
F3 = reserved. This bit should be 0 when writing to the Control register.
F2 = 1: select register X1B for input.
F2 = 0: select register X1A for input.
F1 = 1: enable temperature shutdown.
F1 = 0: disable temperature shutdown.
F0 = 1: soft power-down.
F0 = 0: soft power-up.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
XX[F13:F0]
XX[F13:F0]
Reserved
See Table 14
XXXX XXXX [F7:F0]
XXXX XXXX [F7:F0]
XXXX XXXX [F7:F0]
XXXX XXXX [F7:F0]
XXXX XXXX [F7:F0]
XXXX XXXX [F7:F0]
Write data in F13:F0 to OFS0 register.
Write data in F13:F0 to OFS1 register.
Reserved.
Select register for readback.
Write data in F7:F0 to A/B Select Register 0.
Write data in F7:F0 to A/B Select Register 1.
Write data in F7:F0 to A/B Select Register 2.
Write data in F7:F0 to A/B Select Register 3.
Write data in F7:F0 to A/B Select Register 4.
Block write A/B select registers.
F7:F0 = 0, write all 0s (all channels use X2A register).
F7:F0 = 1, write all 1s (all channels use X2B register).
0
1
1
1
0
0
Reserved
Rev. 0 | Page 23 of 28
AD5370
Table 14. Address Codes for Data Readback1
F15
F14
F13
F12
F11
F10
F9
F8
F7
Register Read
X1A register
0
0
0
Bit F12 to Bit F7 select the channel to be read back from;
Channel 0 = 001000 to Channel 39 = 101111
0
0
1
X1B register
0
1
0
C register
0
1
1
M register
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
Control register
OFS0 data register
OFS1 data register
Reserved
A/B Select Register 0
A/B Select Register 1
A/B Select Register 2
A/B Select Register 3
A/B Select Register 4
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1 F6 to F0 are don’t cares for the data readback function.
A
Table 15. DAC Channels Selected by /B Select Registers
A/B Select
Bits1
Register
F7
F6
F5
F4
F3
F2
F1
F0
0
1
2
3
4
VOUT7
VOUT15
VOUT23
VOUT31
VOUT39
VOUT6
VOUT14
VOUT22
VOUT30
VOUT38
VOUT5
VOUT13
VOUT21
VOUT29
VOUT37
VOUT4
VOUT3
VOUT2
VOUT1
VOUT9
VOUT17
VOUT25
VOUT33
VOUT0
VOUT8
VOUT16
VOUT24
VOUT32
VOUT12
VOUT20
VOUT28
VOUT36
VOUT11
VOUT19
VOUT27
VOUT35
VOUT10
VOUT18
VOUT26
VOUT34
1 If the bit is 0, Register A is selected. If the bit is 1, Register B is selected.
Rev. 0 | Page 24 of 28
AD5370
Avoid crossover of digital and analog signals. Traces on opposite
POWER SUPPLY DECOUPLING
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best approach, but it is not always possible
with a double-sided board. In this technique, the component side
of the board is dedicated to ground plane, and signal traces are
placed on the solder side.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5370 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of
the board. If the AD5370 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (VSS, VDD, DVCC), it is recommended to tie these
pins together and to decouple each supply once.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5370, it is important
that the AGND and DGND pins be connected to the relevant
ground plane before the positive or negative supplies are applied.
In most applications, this is not an issue because the ground pins
for the power supplies are connected to the ground pins of the
AD5370 via ground planes. When the AD5370 is used in a hot
swap card, care should be taken to ensure that the ground pins
are connected to the supply grounds before the positive or
negative supply is connected. This is required to prevent currents
from flowing in directions other than toward an analog or
digital ground.
The AD5370 should have ample supply decoupling of 10 μF in
parallel with 0.1 μF on each supply located as close to the package
as possible, ideally right up against the device. The 10 μF capacitors
are the tantalum bead type. The 0.1 μF capacitor should have
low effective series resistance (ESR) and low effective series
inductance (ESI)—such as is typical of the common ceramic types
that provide a low impedance path to ground at high frequencies—
to handle transient currents due to internal logic switching.
Digital lines running under the device should be avoided
because they can couple noise onto the device. The analog
ground plane should be allowed to run under the AD5370 to
avoid noise coupling. The power supply lines of the AD5370
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast-switching digital signals should be shielded with digital
ground to avoid radiating noise to other parts of the board,
and they should never be run near the reference inputs. It is
essential to minimize noise on all VREF lines.
Rev. 0 | Page 25 of 28
AD5370
The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTs). Figure 24 shows how one SPORT
can be used to control the AD5370. In this example, the transmit
frame synchronization (TFS) pin is connected to the receive
frame synchronization (RFS) pin. The transmit and receive
clocks (TCLK and RCLK) are also connected together. The user
can write to the AD5370 by writing to the transmit register. A read
operation can be accomplished by first writing to the AD5370
to tell the part that a read operation is required. A second write
operation with an NOP instruction causes the data to be read
from the AD5370. The DSP receive interrupt can be used to
indicate when the read operation is complete.
INTERFACING EXAMPLES
The SPI interface of the AD5370 is designed to allow the parts to be
easily connected to industry-standard DSPs and microcontrollers.
Figure 23 shows how the AD5370 can be connected to the
Analog Devices, Inc., Blackfin® DSP. The Blackfin has an integrated
SPI port that can be connected directly to the SPI pins of the
AD5370, as well as programmable input/output pins that can be
used to set or read the state of the digital input or output pins
associated with the interface.
AD5370
SYNC
SCLK
SPISELx
SCK
ADSP-21065L
TFSx
AD5370
MOSI
SDI
SYNC
SDO
RFSx
MISO
TCLKx
RCLKx
RESET
PF10
PF9
PF8
PF7
SCLK
SDI
ADSP-BF531
LDAC
CLR
DTxA
DRxA
SDO
BUSY
FLAG
0
RESET
FLAG
1
LDAC
CLR
Figure 23. Interfacing to a Blackfin DSP
FLAG
2
3
BUSY
FLAG
Figure 24. Interfacing to an ADSP-21065L DSP
Rev. 0 | Page 26 of 28
AD5370
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
0.50
BSC
7.25
7.10 SQ
6.95
8.75
BSC SQ
TOP VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 25. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
12.20
12.00 SQ
0.75
11.80
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
17
32
PLANE
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 26. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
Package Description
Package Option
AD5370BCPZ1
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
CP-64-3
CP-64-3
ST-64-2
ST-64-2
AD5370BCPZ-REEL71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
AD5370BSTZ1
AD5370BSTZ-REEL1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
AD5370
NOTES
© 2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05813-0-4/08(0)
Rev. 0 | Page 28 of 28
相关型号：
©2020 ICPDF网 联系我们和版权申明