AD5399SRM-REEL7 [ADI]
IC SERIAL INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO10, MICRO, SOIC-10, Digital to Analog Converter;
| 型号： | AD5399SRM-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO10, MICRO, SOIC-10, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Twos Complement, Dual 12-Bit DAC
with Internal REF and Fast Settling Time
AD5399
FUNCTIONAL BLOCK DIAGRAM
FEATURES
2-channel 12-bit DAC
V
TP
V
(V ) = 2V
BZ REF
Twos complement facilitates bipolar applications
Bipolar zero with 2 V dc offset
Built-in 2.000 V precision reference with 10 ppm/°C typ TC
Buffered voltage output: 0 V to 4 V
Single-supply operation: 4.5 V to 5.5 V
Fast 0.8 µs settling time typ
AD5399
V
DD
×2
V
+ 2V = 4V
V
BZ
OUTA
V
2V
REF
V
– 2V = 0V
BZ
×2
V
OUTB
DECODER SW
DRIVER A
DECODER SW
DRIVER B
Ultracompact MSOP-10 package
Monotonic DNL < 1 LSB
AGND
12
12
Optimized accuracy at zero scale
Power-on reset to VREF
3-wire serial data input
CS
ADDR
DECODE
DAC A
REGISTER
DAC B
REGISTER
EN
CLK
12
A0
16-BIT
Extended temperature range: –40°C to +105°C
SDI
POWER-ON
RESET
D15...D0
DGND
APPLICATIONS
Figure 1.
Single-supply bipolar converter operations
General-purpose DSP applications
Digital gain and offset controls
Instrumentation level settings
Disk drive control
V
OUT = ((D – 2ꢀ48)/4ꢀ96 × 4 V) + 2 V for ꢀ ≤ D ≤ 4ꢀ95, where D
is the decimal code.
Table 1. Examples of Twos Complement Codes
Precision motor control
Twos Complement
D
Scale
VOUT (V)
4.000
3.999
2.001
2.000
1.999
0.001
0.000
2047
2046
1
4095
4094
2049
2048
2047
1
+FS
GENERAL DESCRIPTION
+FS – 1 LSB
BZS + 1 LSB
BZS
BZS – 1 LSB
–FS + 1 LSB
–FS
The AD5399 is the industry-first dual 12-bit digital-to-analog
converter that accepts twos complement digital coding with 2 V
dc offset for single-supply operation. Augmented with a built-in
precision reference and a solid buffer amplifier, the AD5399 is
the smallest self-contained 12-bit precision DAC that fits many
general-purpose as well as DSP specific applications. The twos
complement programming facilitates the natural coding
implementation commonly found in DSP applications, and
allows operation in single supply. The AD5399 provides a 2 V
reference output, VREF, for bipolar zero monitoring. It can also
be used for other on-board components that require a precision
reference. The device is specified for operation from 5 V 1ꢀ0
single supply with bipolar output swing from ꢀ V to 4 V
centered at 2 V.
0
4095
2049
2048
0
FS = Full Scale, BZS = Bipolar Zero Scale.
4.0
3.5
3.0
V
= [(0 – 2048)/4096 × 4V] + 2V
OUT
2.5
2.0
1.5
1.0
0.5
0
The AD5399 is available in the compact 1.1 mm low profile
MSOP-1ꢀ package. All parts are guaranteed to operate over the
extended industrial temperature range of –4ꢀ°C to +1ꢀ5°C.
0
512
1024
1536
2048
2560
3072
3584
4096
TWOS COMPLEMENT CODE
Figure 2. Output vs. Twos Complement Code
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5399
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ..............................................7
Operation......................................................................................... 1ꢀ
Power-Up/Power-Down Sequence .......................................... 1ꢀ
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
6/04—Data sheet changed from Rev. C to Rev. D
Correction to Table 7 Caption ...................................................... 11
3/04—Data sheet changed from Rev. B to Rev. C
Changes to Specifications................................................................ 3
Changes to Table 4............................................................................ 5
Replaced Figures 4 and 5 ................................................................. 6
Changes to Operation Section...................................................... 1ꢀ
Changes to Table 6.......................................................................... 1ꢀ
11/03—Data sheet changed from Rev. A to Rev. B
Changes to Table 5 notes ................................................................. 5
Changes to Figures 8 and 9.............................................................. 7
Changes to Figure 12........................................................................ 8
Added Power-Up/Power-Down section...................................... 1ꢀ
3/03—Data sheet changed from Rev. 0 to Rev. A
Change to Table 1 ............................................................................. 1
2/03—Revision 0: Initial Version
Rev. D | Page 2 of 12
AD5399
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V 1ꢀ0, –4ꢀ°C < TA < +1ꢀ5°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS
Resolution
N
12
Bits
Differential Nonlinearity Error
DNL
–1
0.5
0.5
0.02
–0.15
–0.15
–0.15
+1
LSB
LSB
%FS
%FS
%FS
%FS
Codes 2048 to 2052, due to int. op amp offset
–1.2
–0.4
–0.75
–0.75
–0.75
+1.2
+0.4
+0.75
+0.75
+0.75
Integral Nonlinearity Error
Positive Full-Scale Error
Bipolar Zero-Scale Error
Negative Full-Scale Error
ANALOG OUTPUTS
INL
V+FSE
VBZSE
V–FSE
Code = 0xF
Code = 0x000
Code = 0x800
Nominal Positive Full-Scale
Positive Full-Scale Tempco2
VOUTA/B
TCVOUTA/B
Code = 0x7FF
Code = 0x7FF, TA = 0°C to 70°C
Code = 0xFF, TA = –40°C to +105°C
4
V
–40
–60
1.995
10
10
2.000
1
+40
+60
2.004
ppm/°C
ppm/°C
V
Nominal VBZ Output Voltage
Bipolar Zero Output Resistance2
VBZ Output Voltage Tempco
VBZ
RBZ
Ω
TCVBZ
TA = 0°C to 70°C
TA = –40°C to +105°C
Code 0x7FF to Code 0x800
–40
–60
10
10
4
+40
+60
ppm/°C
ppm/°C
V
Nominal Peak-to-Peak Output Swing
DIGITAL INPUTS
|V+FS| + |V–FS|
Input Logic High
Input Logic Low
Input Current
Input Capacitance2
VIH
VIL
IIL
VDD = 5 V
VDD = 5 V
VIN = 0 V or 5 V, VDD = 5 V
2.4
4.5
V
V
µA
pF
0.8
1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
VDD RANGE
IDD
IDD_SHDN
5.5
2.6
100
500
13
V
VIH = VDD or VIL = 0 V
1.8
10
100
9
mA
µA
µA
mW
Supply Current in Shutdown
VIH = VDD or VIL = 0 V, B14 = 0, TA = 0°C to 105°C
VIH = VDD or VIL = 0 V, B14 = 0, TA = –40°C to 0°C
VIH = VDD or VIL = 0 V, VDD = 5.5 V
∆VDD = 5 V 10%
Power Dissipation3
PDISS
PSS
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS2
Settling Time
–0.006 +0.003 +0.006 %/%
tS
Q
G
0.1% error band
No oscillation
0.8
10
10
µs
Digital Feedthrough
nV-s
nV-s
pF
Bipolar Zero-Scale Glitch
Capacitive Load Driving Capability
INTERFACE TIMING CHARACTERISTICS2, 4
SCLK Cycle Frequency
SCLK Clock Cycle Time
Input Clock Pulse Width
Data Setup Time
CL
1000
33
tCYC
t1
t2, t3
t4
MHz
ns
ns
30
15
5
Clock level low or high
ns
Data Hold Time
t5
0
ns
CS
to SCLK Active Edge Setup Time
CS
t6
5
ns
SCLK to Hold Time
t7
0
ns
CS
Repeat Programming, High Time
t8
30
ns
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
4 See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using VDD = 5 V. Input logic should have a 1 V/µs minimum slew rate.
Rev. D | Page 3 of 12
AD5399
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
VOUTA, VOUTB, VBZ to GND
–0.3 V, +7.5 V
0 V, VDD
0 V, VDD + 0.3 V
–40°C to +105°C
150°C
–65°C to +150°C
300°C
(TJ MAX – TA)/θJA
206°C/W
Digital Input Voltages to GND
Operating Temperature Range
Maximum Junction Temperature (TJ MAX
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance, θJA, MSOP-10
)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 4 of 12
AD5399
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
SDI
1
2
3
4
5
10 CS
V
V
9
8
7
6
TP
AD5399
DGND
TOP VIEW
DD
(Not to Scale)
V
AGND
OUTB
V
V
BZ
OUTA
Figure 3. MSOP-10 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
CLK
SDI
DGND
VOUTB
VOUTA
VBZ
AGND
VDD
VTP
Serial Clock Input. Positive edge triggered.
Serial Data Input. MSB first format.
Digital Ground.
DAC B Voltage Output (A0 = Logic 1).
DAC A Voltage Output (A0 = Logic 0).
2 V, Virtual Bipolar Zero (Active Output).
Analog Ground.
Positive Power Supply. Specified for operation at 5 V.
Connect to VDD. Reserved for factory testing.
9
10
CS
Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low.
After the 16th clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be
brought high any time after the 16th clock positive edge in order to allow the next programming cycle.
Table 5. Serial Data-Word Format
ADDR
DATA
B11
B15
A0
B14
X
B13
SD
B12
0
B10
D10
…
…
B3
B2
B1
B0
D11
D3
D2
D1
D0
LSB
MSB
Aꢀ
Address Bit. Logic low selects DAC A and logic high selects DAC B.
Both channels are shut down when the SD bit is high. However, the Aꢀ bit must be at the same state for shutdown
activation and deactivation. See the Shutdown Function section.
X
Don’t Care.
SD
Shutdown Bit. Logic high puts both DAC outputs and VBZ into high impedance. Aꢀ bit must be at the same state for
shutdown activation and deactivation.
ꢀ
B12 must be ꢀ.
Data Bits.
Dꢀ–D11
Rev. D | Page 5 of 12
AD5399
TIMING CHARACTERISTICS
1
SDI
SCLK
CS
A0
X
SD
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
Figure 4. Timing Diagram
1
SDI
0
Dx
Dx
Dx
Dx
t5
t4
1
t2
SCLK
t3
t7
0
1
t1
t6
CS
0
t8
tS
±1LSB
1
ERROR
BAND
V
OUT
0
Figure 5. Detailed Timing Diagram
Rev. D | Page 6 of 12
AD5399
TYPICAL PERFORMANCE CHARACTERISTICS
10
2.3
2.2
2.1
2.0
1.9
1.8
V
= 5V
V
= 5V
DD
= 25°C
DD
T
A
8
6
DAC B
4
2
0
–2
–4
–6
–8
–10
DAC A
0
512
1024
1536
2048
2560
3072
3584
4096
–60
–40
–20
0
20
40
60
80
100
120
CODE (Decimal)
TEMPERATURE (°C)
Figure 6. Integral Nonlinearity Errors
Figure 9. Supply Current vs. Temperature
1.00
0.75
0.50
0.25
0
2.4
2.3
2.2
2.1
2.0
1.9
1.8
V
T
= 5V
= 25°C
V
= 5V
= 25°C
DD
DD
T
A
A
DAC A, B
–0.25
–0.50
–0.75
–1.00
0
512
1024
1536
2048
2560
3072
3584
4096
2
3
4
5
6
7
CODE (Decimal)
DIGITAL INPUT VOLTAGE, V (V)
IH
Figure 7. Differential Nonlinearity Errors
Figure 10. Supply Current vs. Digital Input Voltage
1.96
1.92
1.88
1.84
1.80
1.76
4.5
T
= 25°C
V
= 5V
DD
= 25°C
A
T
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CODE = 0x555
CODE = 0x7FF
CODE = 0x000
2
3
4
5
6
7
10k
100k
1M
10M
100M
SUPPLY VOLTAGE (V)
CLOCK FREQUENCY (Hz)
Figure 8. Supply Current vs. Supply Voltage
Figure 11. Supply Current vs. Clock Frequency
Rev. D | Page 7 of 12
AD5399
1000
70
60
50
40
30
20
10
0
V
= 5V
SS = 345
25°C to 85°C
DD
100
10
1
0.1
–60 –40 –20
0
20
40
60
80
100 120 140
–45–40–35–30–25–20–15–10 –5
0
5 10 15 20 25 30 35 40
SHUTDOWN TEMPERATURE (°C)
TEMPCO (ppm/°C)
Figure 12. Shutdown Current vs. Temperature
Figure 15. VBZ Temperature Coefficient (TA = 25°C to 85°C)
20
100
SS = 345
25°C to 105°C
V
T
= 5V
= 25°C
DD
CURRENT SINKING
CODE = 0x000 = 2V
A
18
16
14
12
10
8
80
60
40
20
0
CURRENT SOURCING
CODE = 0x000 = 2V
6
4
CURRENT SINKING
CODE = 0x800 = 0V
2
0
–6
–4
–2
0
2
4
6
8
10
–15 –10 –5
0
5
10 15 20 25 30 35 40 45 50
TEMPCO (ppm/°C)
∆V
(mV)
OUT
Figure 13. Load Current vs. Voltage Drop
Figure 16. VBZ Temperature Coefficient (TA = 25°C to 105°C)
40
0.5
SS = 345
V
= 5V
DD
–40°C to +25°C
BURN-IN TEMPERATURE = 125°C
0.4
0.3
35
30
25
20
15
10
5
0.2
V
+FS
0.1
0
V
–FS
–0.1
–0.2
–0.3
–0.4
–0.5
V
V
BZ
BZS
0
0
200
400
600
800
1000
1200
–45–40–35–30–25–20–15–10 –5
0
5 10 15 20 25 30 35 40
HOURS OF OPERATION
TEMPCO (ppm/°C)
Figure 14. Long-Term Drift
Figure 17. VBZ Temperature Coefficient (TA = –40°C to +25°C)
Rev. D | Page 8 of 12
AD5399
VOUT: 0.5V/DIV
100
90
100
90
VOUT: 1V/DIV
TRACE 1: NO LOAD
TRACE 2 (WITH RINGING):
CL = 2nF
RL = 1kΩ
CLK: 5V/DIV
CLK: 5V/DIV
10
10
0%
0%
Figure 18. Large Signal Settling (0.5 µs/DIV)
Figure 20. Capacitive Load Output Performance (2 µs/DIV)
100
90
CS: 5V/DIV
VOUT: 50mV/DIV
10
0%
Figure 19. Midscale Glitch and Digital Feedthrough (2 µs/DIV)
Rev. D | Page 9 of 12
AD5399
OPERATION
The AD5399 provides a 12-bit, twos complement, dual voltage
output, digital-to-analog converter (DAC). It has an internal
reference with 2 V bipolar zero dc offset, where ꢀ ≤ VOUT ≤ 4 V.
1kΩ
LOGIC
Figure 21. Equivalent ESD Protection Circuit
The output transfer equation is
5V
V
V
DD
V
OUT = ((D – 2ꢀ48)/4ꢀ96 × 4 V) + 2 V
C1
10µF
C2
0.1µF
TP
AD5399
V
)
OUTA
CS
where:
(D–2048)/4096 × 4V + 2V
V
(V
CLK
SDI
BZ REF
2V
D is the 12-bit decimal code and not the twos complement code.
OUT is with respect to ground.
DGND AGND
V
In data programming, the data is loaded MSB first on the
Figure 22. Basic Connection
positive clock edge (SCLK) after chip select ( ) goes from high
CS
POWER-UP/POWER-DOWN SEQUENCE
to low. The digital word is 16 bits wide, with the MSB, B15, as an
address bit (DAC A: Aꢀ = ꢀ; DAC B: Aꢀ = 1). B14 is don’t care,
B13 is a shutdown bit, B12 must be logic low, and the last 12 bits
are data bits. An internal counter allows data transferred from
the shift register to the output after the 16th positive clock edge
Like most CMOS devices, it is recommended to power VDD and
ground prior to any digital signals. The ideal power-up
sequence is GND, VDD, and digital signals. The reverse sequence
applies to the power-down condition.
while
stays low (see Figure 5). After the 16th clock pulse, it is
CS
Layout and Power Supply Bypassing
not necessary to bring
high to shift the data to the output.
CS
It is a good practice to employ compact, minimum lead-length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
However, should be brought high anytime after the 16th clock
CS
positive edge in order to allow the next programming cycle.
Table 6. Input Logic Control Truth Table
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with ꢀ.ꢀ1 µF to ꢀ.1 µF disc or chip
ceramic capacitors. Low ESR 1 µF to 1ꢀ µF tantalum or electro-
lytic capacitors should also be applied at VDD to minimize any
transient disturbance and to filter any low frequency ripple (see
Figure 23). Users should not apply switching regulators for VDD
due to the power supply rejection ratio degradation over
frequency.
CLK
CS
Register Activity
L
H
P
16th
H
H
L
No Shift Register Effect
No Shift Register Effect
Shift One SDI Bit into the SR
Transfer SR Data into DAC Register and Update
the Output
P
L
P = Positive Edge, X = Don't Care, SR = Shift Register.
The data setup and data hold times in the Specifications table
determine the timing requirements. The internal power-on reset
circuit clears the serial input registers to all ꢀs, and sets the two
DAC registers to a VBZ (zero code) of 2 V.
AD5399
V
V
DD
DD
+
C2
C1
Software shutdown B13 turns off the internal REF and
amplifiers. The output is close to zero potential, and the digital
circuitry remains active such that new data can be written.
Therefore, the DAC register is refreshed with the new data once
the shutdown bit is deactivated.
10µF
0.1µF
AGND
DGND
Figure 23. Power Supply Bypassing and Grounding Connection
All digital inputs are ESD protected with a series input resistor
and parallel Zener, as shown in Figure 21, that apply to digital
Grounding
input pins CLK, SDA, and . The basic connection is shown in
CS
The DGND and AGND pins of the AD5399 refer to the digital
and analog ground references. To minimize the digital ground
bounce, the DGND terminal should be joined remotely at a
single point to the analog ground plane, as shown in Figure 23.
Figure 22.
Rev. D | Page 10 of 12
AD5399
Shutdown Function
The AD5399 shutdown function allows both DACs to be
shutdown simultaneously. However, the Aꢀ and SD bits work in
tandem, and the Aꢀ logic state must be the same for shutdown
activation and deactivation (see Table 7).
For users whose logic signals may be in three-state (random
levels) during power-up initialization, it is recommended to put
a pull-up resistor at the pin to disable chip select (Figure 24).
This avoids inadvertent shutdown as well as the inability to
deactivate shutdown due to an unknown Aꢀ state. The resistor
value depends on the digital controller’s output impedance.
CS
Table 7. Shutdown Activation and Deactivation Sequence.
Sequence Data-Word
5V
V
of Events
in Binary
Shutdown Status
DD
C1
10µF
C2
0.1µF
R1
300kΩ
V
TP
AD5399
1
0X10 XXXX
XXXX XXXX
Activate shutdown on both DACs.
V
OUTA
CS
CLK
SDI
(D–2048)/4096 × 4V + V
BZ
V
(V
)
BZ REF
2V
2
3
1X00 XXXX
XXXX XXXX
0X00 XXXX
XXXX XXXX
Both DACs remain at shutdown.
DGND AGND
Deactivate shutdown. Both DACs
resume normal operation.
CS
Figure 24. Disable for Random Logic Mode
The A0 bit (MSB) must be in the same state when activating and deactivating
shutdown.
Rev. D | Page 11 of 12
AD5399
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 25. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Models
AD5399YRM
AD5399YRM-REEL7
Temperature Range
Package Description
Package Option
Branding
DSB
DSB
Ordering Quantity
–40°C to +105°C
–40°C to +105°C
MSOP
MSOP
RM-10
RM-10
50
1,000
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03469–0–6/04(D)
Rev. D | Page 12 of 12
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