AD5410ACPZ-REEL7 [ADI]
Single-Channel, 12-Bit, Serial Input, 4 mA to 20 mA, Current Source DAC, HART Connectivity;
| 型号： | AD5410ACPZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Single-Channel, 12-Bit, Serial Input, 4 mA to 20 mA, Current Source DAC, HART Connectivity 转换器 |
| 文件： | 总30页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Channel, 12-/16-Bit, Serial Input, 4 mA to
20 mA, Current Source DAC, HART Connectivity
Data Sheet
AD5410/AD5420
FEATURES
GENERAL DESCRIPTION
12-/16-bit resolution and monotonicity
The AD5410/AD5420 are low cost, precision, fully integrated
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
0.01% FSR typical total unadjusted error (TUE)
3 ppm/°C typical output drift
Flexible serial digital interface
12-/16-bit converters offering a programmable current source
output designed to meet the requirements of industrial process
control applications. The output current range is programmable
at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of
0 mA to 24 mA. The output is open-circuit protected. The device
operates with a power supply (AVDD) range from 10.8 V to
60 V. Output loop compliance is 0 V to AVDD − 2.5 V.
On-chip output fault detection
On-chip reference (10 ppm/°C maximum)
Feedback/monitoring of output current
Asynchronous clear function
The flexible serial interface is SPI, MICROWIRE™, QSPI™, and
DSP compatible and can be operated in 3-wire mode to mini-
mize the digital isolation required in isolated applications.
Power supply (AVDD) range
10.8 V to 40 V; AD5410AREZ/AD5420AREZ
10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ
Output loop compliance to AVDD − 2.5 V
Temperature range: −40°C to +85°C
24-lead TSSOP and 40-lead LFCSP packages
The device also includes a power-on reset function, ensuring
that the device powers up in a known state, and an asynchronous
CLEAR pin that sets the output to the low end of the selected
current range.
The total unadjusted error is typically 0.01% FSR.
APPLICATIONS
COMPANION PRODUCTS
Process control
Actuator control
PLC
HART Modem: AD5700, AD5700-1
HART network connectivity
FUNCTIONAL BLOCK DIAGRAM
DV
CC
SELECT
DV
CAP1
CAP2
AV
DD
CC
R3
SENSE
AD5410/AD5420
R2
R3
CLEAR
BOOST
LATCH
SCLK
SDIN
I
INPUT SHIFT
OUT
12/16
REGISTER
AND CONTROL
LOGIC
12-/16-BIT
DAC
FAULT
SDO
POWER-
ON
RESET
R
SET
VREF
R
SET
REFOUT
REFIN
GND
Figure 1.
Rev. J
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Technical Support
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AD5410/AD5420
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
AD5410/AD5420 Features ............................................................ 22
Fault Alert.................................................................................... 22
Asynchronous Clear (CLEAR)................................................. 22
Internal Reference ...................................................................... 22
External Current Setting Resistor ............................................ 22
Digital Power Supply.................................................................. 22
External Boost Function ........................................................... 22
HART Communication............................................................. 23
Digital Slew Rate Control.......................................................... 23
IOUT Filtering Capacitors............................................................ 25
Feedback/Monitoring of Output Current............................... 25
Applications Information.............................................................. 27
Driving Inductive Loads............................................................ 27
Transient Voltage Protection .................................................... 27
Layout Guidelines....................................................................... 27
Galvanically Isolated Interface ................................................. 27
Microprocessor Interfacing....................................................... 28
Thermal and Supply Considerations....................................... 28
Industrial, HART Compatible Analog Output Application. 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
General Description......................................................................... 1
Companion Products....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
AC Performance Characteristics................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Architecture................................................................................. 17
Serial Interface ............................................................................ 17
Power-On State ........................................................................... 20
Transfer Function ....................................................................... 20
Data Register............................................................................... 20
Control Register.......................................................................... 20
Reset Register.............................................................................. 21
Status Register............................................................................. 21
Rev. J | Page 2 of 30
Data Sheet
AD5410/AD5420
REVISION HISTORY
11/2017—Rev. I to Rev. J
11/2011—Rev. B to Rev. C
Changes to Figure 6...........................................................................9
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................30
Changes to Table 10 ........................................................................18
2/2010—Rev. A to Rev. B
Changes to Figure 46 .....................................................................23
4/2017—Rev. H to Rev. I
Changes to Table 4 ............................................................................8
Changes to Figure 5 and Figure 6....................................................9
8/2009—Rev. 0 to Rev. A
Changes to Features and General Description .............................1
Changes to Table 1 ............................................................................3
Changes to Table 2 ............................................................................5
Changes to Introduction to Table 4 and to Table 4 ......................7
Added Figure 6, Changes to Figure 5 and Table 5 ........................8
Added Feedback/Monitoring of Output Current Section,
Including Figure 45 to Figure 47; Renumbered Subsequent
Figures ..............................................................................................23
Changes to Thermal and Supply Considerations Section and
Table 21 .............................................................................................26
Updated Outline Dimensions........................................................28
Changes to Ordering Guide...........................................................28
4/2015—Rev. G to Rev. H
Changes to Table 3 ............................................................................6
Changes to Table 5 ............................................................................9
10/2014—Rev. F to Rev. G
Changes to Power-On State Section .............................................20
10/2013—Rev. E to Rev. F
Moved Revision History...................................................................3
Changes to Figure 51 ......................................................................27
Changes to Figure 55 ......................................................................29
3/2009—Revision 0: Initial Version
3/2013—Rev. D to Rev. E
Changes to Table 4 ............................................................................7
Added Figure 40, Renumbered Sequentially...............................19
Changes to Table 10 ........................................................................20
Changes to Thermal and Supply Considerations Section
and Table 21 .....................................................................................27
Updated Outline Dimensions........................................................29
5/2012—Rev. C to Rev. D
Reorganized Layout ...........................................................Universal
Changes to Product Title..................................................................1
Added Companion Products Section; Changes to Features
Section and Applications Section....................................................1
Changes to Table 5 ............................................................................9
Change to Figure 8 ..........................................................................11
Added HART Communication Section and Figure 41,
Renumbered Sequentially ..............................................................21
Changes to Industrial, HART Compatible Analog Output
Application Section and Figure 54................................................27
Rev. J | Page 3 of 30
AD5410/AD5420
SPECIFICATIONS
Data Sheet
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX
,
unless otherwise noted.
Table 1.
Parameter1
Min
0
0
Typ
Max
24
20
Unit
mA
mA
mA
Test Conditions/Comments
OUTPUT CURRENT RANGES
4
20
ACCURACY, INTERNAL RSET
Resolution
16
Bits
AD5420
12
Bits
AD5410
Total Unadjusted Error (TUE)
−0.3
−0.13
−0.5
−0.3
−0.024
−0.032
−1
+0.3
+0.13
+0.5
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
AD5420
AD5420, TA = 25°C
AD5410
AD5410, TA = 25°C
AD5420
AD5410
0.08
0.15
+0.3
Relative Accuracy (INL)2
+0.024
+0.032
+1
+0.27
+0.12
Differential Nonlinearity (DNL)
Offset Error
Guaranteed monotonic
−0.27
−0.12
0.08
16
TA = 25°C
Offset Error Temperature Coefficient (TC)3
Gain Error
−0.18
−0.03
−0.22
−0.06
+0.18
0.006 +0.03
+0.22
0.012 +0.06
10
AD5420
AD5420, TA = 25°C
AD5410
AD5410, TA = 25°C
Gain Error Temperature Coefficient (TC)3
Full-Scale Error
ppm FSR/°C
% FSR
% FSR
−0.2
−0.1
+0.2
+0.1
0.08
12
TA = 25°C
Full-Scale Error Temperature Coefficient (TC)3
ACCURACY, EXTERNAL RSET
Resolution
ppm FSR/°C
Assumes an ideal 15 kΩ resistor
AD5420
16
Bits
12
Bits
AD5410
Total Unadjusted Error (TUE)
−0.15
−0.06
−0.3
−0.1
−0.012
−0.032
−1
+0.15
+0.06
+0.3
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
AD5420
AD5420, TA = 25°C
AD5410
AD5410, TA = 25°C
0.01
0.02
+0.1
Relative Accuracy (INL)2
+0.012
+0.032
+1
AD5420
AD5410
Guaranteed monotonic
Differential Nonlinearity (DNL)
Offset Error
−0.1
−0.03
+0.1
0.006 +0.03
TA = 25°C
TA = 25°C
TA = 25°C
Offset Error Temperature Coefficient (TC)3
Gain Error
3
−0.08
−0.05
+0.08
0.003 +0.05
4
Gain Error Temperature Coefficient (TC)3
Full-Scale Error
−0.15
−0.06
+0.15
+0.06
0.01
7
Full-Scale Error Temperature Coefficient (TC)3
OUTPUT CHARACTERISTICS3
Current Loop Compliance Voltage
Output Current Drift vs. Time
0
AVDD − 2.5
V
50
20
ppm FSR
ppm FSR
Ω
mH
µA/V
Internal RSET, drift after 1000 hours at 125°C
External RSET, drift after 1000 hours at 125°C
Resistive Load
Inductive Load
DC Power Supply Rejection Ratio (PSRR)
1200
1
50
TA = 25°C
Rev. J | Page 4 of 30
Data Sheet
AD5410/AD5420
Parameter1
Min
Typ
50
Max
Unit
MΩ
Test Conditions/Comments
Output Impedance
Output Current Leakage
R3 Resistor Value
60
40
pA
Ω
Output disabled
TA = 25°C
36
44
R3 Resistor Temperature Coefficient (TC)
IBIAS Current
IBIAS Current Temperature Coefficient (TC)
REFERENCE INPUT/OUTPUT
Reference Input3
30
444
30
ppm/°C
µA
ppm/°C
399
489
Reference Input Voltage
DC Input Impedance
Reference Output
Output Voltage
Reference TC3, 4
Output Noise (0.1 Hz to 10 Hz)3
Noise Spectral Density3
Output Voltage Drift vs. Time3
Capacitive Load3
4.95
25
5
30
5.05
V
kΩ
For specified performance
TA = 25°C
4.995
5.000
1.8
18
5.005
10
V
ppm/°C
µV p-p
nV/√Hz
ppm
nF
100
50
At 10 kHz
Drift after 1000 hours, TA = 125°C
600
5
Load Current3
mA
Short-Circuit Current3
Load Regulation3
7
mA
95
ppm/mA
DIGITAL INPUTS3
JEDEC compliant
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
2
V
V
µA
pF
0.8
+1
−1
Per pin
Per pin
Pin Capacitance
10
DIGITAL OUTPUTS3
SDO
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
FAULT
0.4
+1
V
V
µA
pF
Sinking 200 µA
Sourcing 200 µA
DVCC − 0.5
−1
5
Output Low Voltage, VOL
Output Low Voltage, VOL
Output High Voltage, VOH
POWER REQUIREMENTS
AVDD
0.4
V
V
V
10 kΩ pull-up resistor to DVCC
2.5 mA load current
10 kΩ pull-up resistor to DVCC
0.6
3.6
10.8
10.8
40
60
V
V
TSSOP package
LFCSP package
DVCC
Input Voltage
Output Voltage
Output Load Current3
Short-Circuit Current3
AIDD
2.7
5.5
V
V
Internal supply disabled
DVCC can be overdriven up to 5.5 V
4.5
5
mA
mA
mA
mA
mA
mW
mW
20
3
4
1
Output disabled
Output enabled
VIH = DVCC, VIL = GND
AVDD = 40 V, IOUT = 0 mA
AVDD = 15 V, IOUT = 0 mA
DICC
Power Dissipation
144
50
1 Temperature range: −40°C to +85°C; typical at +25°C.
2 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410.
3 Guaranteed by design and characterization but not production tested.
4 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.
Rev. J | Page 5 of 30
AD5410/AD5420
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Current Settling Time2
10
40
−75
µs
µs
dB
16 mA step, to 0.1% FSR
16 mA step, to 0.1% FSR, L = 1 mH
200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage
AC PSRR
1 Guaranteed by design and characterization; not production tested.
2 Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.
TIMING CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
WRITE MODE
t1
t2
t3
t4
t5
t6
t7
t8
33
13
13
13
5
5
5
40
20
5
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
µs max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
CLEAR pulse width
CLEAR activation time
t9
t10
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
90
40
40
13
40
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
5
40
35
35
t19
t20
Serial output delay time (CL SDO = 50 pF)4
LATCH rising edge to SDO tristate
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
90
40
40
13
40
5
5
40
35
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO = 50 pF)4
1 Guaranteed by characterization but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CLSDO = capacitive load on SDO output.
Rev. J | Page 6 of 30
Data Sheet
AD5410/AD5420
t1
SCLK
1
2
24
t2
t3
t4
t5
LATCH
t7
t8
DB0
t6
SDIN
DB23
t9
CLEAR
t10
I
OUT
Figure 2. Write Mode Timing Diagram
t11
2
SCLK
1
9
23
1
2
24
22
24
8
t13
t12
t14
t15
LATCH
t18
t17
t16
SDIN
SDO
DB23
DB0
DB23
X
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
t20
t19
X
X
X
DB15
DB0
UNDEFINED DATA
FIRST 8 BITS ARE
DON’T CARE BITS
SELECTED REGISTER
DATA CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
t21
26
48
25
SCLK
1
2
24
t22
t23
t24
t25
LATCH
SDIN
t27
t28
t26
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N – 1
t29
DB23
DB0
DB23
SDO
DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Mode Timing Diagram
Rev. J | Page 7 of 30
AD5410/AD5420
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
80 mA do not cause SCR latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
Rating
AVDD to GND
DVCC to GND
−0.3 V to +60 V
−0.3 V to +7 V
Digital Inputs to GND
−0.3 V to DVCC + 0.3 V or +7 V
(whichever is less)
Digital Outputs to GND
−0.3 V to DVCC + 0.3 V or +7 V
(whichever is less)
ESD CAUTION
REFIN, REFOUT to GND
IOUT to GND
−0.3 V to +7 V
−0.3 V to AVDD
Operating Temperature Range
Industrial
−40°C to +85°C1
−65°C to +150°C
125°C
Storage Temperature Range
Junction Temperature (TJ max)
24-Lead TSSOP_EP Package
Thermal Impedance, θJA
Thermal Impedance, θJC
40-Lead LFCSP Package
Thermal Impedance, θJA
Thermal Impedance, θJC
Power Dissipation
35°C/W2
9°C/W
33°C/W2
4°C/W
(TJ max − TA)/θJA
JEDEC industry standard
J-STD-020
Lead Temperature
Soldering
1 Power dissipated on chip must be derated to keep junction temperature
below 125°C. The assumption is that the maximum power dissipation
condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip
current.
2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. Ref: JEDEC JESD51 documents.
Rev. J | Page 8 of 30
Data Sheet
AD5410/AD5420
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
GND
AV
DD
DV
NC
CC
FAULT
CAP2
CAP1
BOOST
NC
FAULT
GND
1
2
3
4
5
6
7
8
9
30 NC
29 CAP2
GND
GND
28
CAP1
27 BOOST
AD5410/
AD5420
GND
AD5410/AD5420
CLEAR
LATCH
SCLK
SDIN
I
OUT
I
CLEAR
LATCH
SCLK
SDIN
26
25
OUT
SENSE
TOP VIEW
R3
TOP VIEW
R3
(Not to Scale)
SENSE
24 NC
(Not to Scale)
DV
NC
NC
SELECT
23
22
21
CC
NC
DV
SDO
9
SELECT
NC 10
CC
10
11
12
REFIN
REFOUT
SDO
GND
GND
R
SET
NOTES
1. NC = NO CONNECT.
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO
THE GROUND REFERENCE.
2. THE EXPOSED PAD MUST BE CONNECTED TO
THE GROUND REFERENCE.
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP Pin No. LFCSP Pin No.
Mnemonic
Description
1, 4, 5, 11, 12
2
3
3, 4, 12 to 15, 37 GND
Ground Reference Pin. These pins must be connected to ground.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Fault Alert. This pin is asserted low when an open circuit is detected between IOUT and
GND or an overtemperature is detected. The FAULT pin is an open-drain output and
must be connected to DVCC through a pull-up resistor (typically 10 kΩ).
39
2
DVCC
FAULT
6
7
8
5
6
7
CLEAR
LATCH
SCLK
Active High Input. Asserting this pin sets the output current to the zero-scale value,
which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA
to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.
Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data
into the relevant register. In the case of the data register, the output current is also
updated.
Serial Clock Input. Data is clocked into the input shift register on the rising edge of
SCLK. This operates at clock speeds of up to 30 MHz.
9
10
8
9
SDIN
SDO
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. This pin is used to clock data from the device in daisy-chain or
readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and
Figure 4.
13
14
16
17
RSET
An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the overall performance of the device. See the Specifications and
AD5410/AD5420 Features sections.
Internal Reference Voltage Output. VREFOUT = 5 V 5 mV at TA = 25°C. Typical temperature
drift is 1.8 ppm/°C.
REFOUT
REFIN
DVCC
SELECT
15
16
18
23
External Reference Voltage Input. VREFIN = 5 V 50 mV for specified performance.
This pin, when connected to GND, disables the internal supply, and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. In this case, it is recommended to connect a 0.1 μF capacitor between DVCC and
GND. See the AD5410/AD5420 Features section.
17, 23
1, 10, 11, 19 to
22, 24, 30 to 35,
38, 40
NC
Do not connect to these pins.
Rev. J | Page 9 of 30
AD5410/AD5420
Data Sheet
TSSOP Pin No. LFCSP Pin No.
Mnemonic
Description
18
25
R3SENSE
The voltage measured between this pin and the BOOST pin is directly proportional to
the output current and can be used as a monitor/feedback feature. This should be used
as a voltage sense output only; current should not be sourced from this pin. See the
AD5410/AD5420 Features section.
19
20
26
27
IOUT
BOOST
Current Output Pin.
Optional External Transistor Connection. Connecting an external transistor reduces the
power dissipated in the AD5410/AD5420. See the AD5410/AD5420 Features section.
21
22
28
29
CAP1
CAP2
AVDD
Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features
section.
Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features
section. Also HART Input Connection, see Device Features Section.
24
36
Positive Analog Supply Pin. Voltage ranges from 10.8 V to 40 V.
25 (EPAD)
41 (EPAD)
Exposed pad The exposed pad must be connected to the ground reference.
Rev. J | Page 10 of 30
Data Sheet
AD5410/AD5420
TYPICAL PERFORMANCE CHARACTERISTICS
0.004
0.002
0
AV
= 24V
EXTERNAL R
DD
SET
0.004
0mA TO 24mA RANGE
INTERNAL R
SET
EXTERNAL R
, BOOST TRANSISTOR
, BOOST TRANSISTOR
SET
0.002
0
INTERNAL R
SET
–0.002
–0.004
–0.006
–0.008
–0.010
–0.002
–0.004
–0.006
–0.008
–0.010
AV = 2.4V
DD
T
= 25°C
A
R
= 250Ω
LOAD
0
10,000
20,000
30,000
CODE
40,000
50,000
60,000
60,000
60,000
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 7. Integral Nonlinearity Error vs. Code
Figure 10. Integral Nonlinearity Error vs. Temperature, Internal RSET
1.0
0.8
0.003
AV = 24V
DD
AV
= 24V
DD
0mA TO 24mA RANGE
T
R
= 25°C
A
= 250Ω
LOAD
0.002
0.001
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.001
–0.002
–0.003
EXTERNAL R
INTERNAL R
EXTERNAL R
INTERNAL R
SET
SET
, BOOST TRANSISTOR
SET
, BOOST TRANSISTOR
SET
0
10,000
20,000
30,000
CODE
40,000
50,000
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Differential Nonlinearity Error vs. Code
Figure 11. Integral Nonlinearity Error vs. Temperature, External RSET
0.05
0.03
1.0
AV
= 24V
DD
ALL RANGES
INTERNAL AND EXTERNAL R
0.8
0.6
SET
0.01
–0.01
–0.03
–0.05
–0.07
–0.09
–0.11
–0.13
–0.15
0.4
0.2
0
AV
= 24V
DD
= 25°C
T
A
–0.2
–0.4
–0.6
–0.8
–1.0
R
= 250Ω
LOAD
EXTERNAL R
SET
INTERNAL R
SET
EXTERNAL R
, BOOST TRANSISTOR
, BOOST TRANSISTOR
SET
INTERNAL R
SET
0
10,000 20,000
30,000
CODE
40,000
50,000
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 9. Total Unadjusted Error vs. Code
Figure 12. Differential Nonlinearity Error vs. Temperature
Rev. J | Page 11 of 30
AD5410/AD5420
Data Sheet
0.10
0.015
0.010
0.005
0
T
= 25°C
A
0mA TO 24mA RANGE
0.05
0
AV
= 24V
DD
–0.05
–0.10
–0.15
–0.20
–0.25
4mA TO 20mA INTERNAL R
0mA TO 20mA INTERNAL R
0mA TO 24mA INTERNAL R
4mA TO 20mA EXTERNAL R
0mA TO 20mA EXTERNAL R
0mA TO 24mA EXTERNAL R
SET
SET
SET
–0.005
–0.010
–0.015
SET
SET
SET
10
15
20
25
DD
30
35
40
40
40
–40
–20
0
20
40
60
80
AV
(V)
TEMPERATURE (°C)
Figure 16. Integral Nonlinearity Error vs. AVDD, External RSET
Figure 13. Total Unadjusted Error vs. Temperature
0.020
0.10
0.05
0.015
0.010
0.005
0
AV
= 24V
DD
T = 25°C
A
0mA TO 24mA RANGE
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.005
–0.010
–0.015
–0.020
4mA TO 20mA INTERNAL R
0mA TO 20mA INTERNAL R
0mA TO 24mA INTERNAL R
4mA TO 20mA EXTERNAL R
0mA TO 20mA EXTERNAL R
0mA TO 24mA EXTERNAL R
SET
SET
SET
SET
SET
SET
10
15
20
25
DD
30
35
–40
–20
0
20
40
60
80
AV
(V)
TEMPERATURE (°C)
Figure 17. Integral Nonlinearity Error vs. AVDD, Internal RSET
Figure 14. Offset Error vs. Temperature
1.0
0.06
0.04
T
= 25°C
0mA TO 24mA RANGE
0.8
0.6
A
AV
= 24V
DD
0.02
0.4
0
0.2
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
4mA TO 20mA INTERNAL R
0mA TO 20mA INTERNAL R
0mA TO 24mA INTERNAL R
4mA TO 20mA EXTERNAL R
0mA TO 20mA EXTERNAL R
0mA TO 24mA EXTERNAL R
SET
SET
SET
SET
SET
SET
10
15
20
25
AV (V)
30
35
–40
–20
0
20
40
60
80
DD
TEMPERATURE (°C)
Figure 18. Differential Nonlinearity Error vs. AVDD, External RSET
Figure 15. Gain Error vs. Temperature
Rev. J | Page 12 of 30
Data Sheet
AD5410/AD5420
1.0
0.8
2.5
2.0
1.5
1.0
0.5
0
AV
= 15V
DD
= 24mA
I
OUT
T
= 25°C
A
R
= 500Ω
LOAD
0.6
0.4
0mA TO 24mA RANGE
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
10
15
20
25
DD
30
35
40
–40
–20
0
20
40
60
80
AV
(V)
TEMPERATURE (°C)
Figure 19. Differential Nonlinearity Error vs. AVDD, Internal RSET
Figure 22. Compliance Voltage Headroom vs. Temperature
0.025
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
A
AV
= 24V
DD
0.020
0.015
0.010
0.005
0
0mA TO 24mA RANGE
T
R
= 25°C
= 250Ω
A
LOAD
–0.005
–0.010
–0.015
10
15
20
25
DD
30
35
40
0
100
200
300
400
500
600
AV
(V)
TIME (µs)
Figure 20. Total Unadjusted Error vs. AVDD, External RSET
Figure 23. Output Current vs. Time on Power-Up
0.05
20
10
0.03
0.01
AV
= 24V
= 25°C
DD
0
–0.01
–0.03
–0.05
–0.07
–0.09
–0.11
–0.13
–0.15
T
A
R
= 250Ω
LOAD
–10
–20
–30
–40
–50
T
= 25°C
A
0mA TO 24mA RANGE
10
15
20
25
AV (V)
30
35
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DD
TIME (µs)
Figure 21. Total Unadjusted Error vs. AVDD, Internal RSET
Figure 24. Output Current vs. Time on Output Enable
Rev. J | Page 13 of 30
AD5410/AD5420
Data Sheet
900
T
= 25°C
800
700
600
500
400
300
200
100
0
A
AV
DD
DV
= 5V
CC
3
REFERENCE OUTPUT
DV
= 3V
2.5
CC
1
CH1 2.00V
CH3 5.00V
M200µs
CH3
2.1V
0
0.5
1.0
1.5
2.0
3.0
3.5
4.0
4.5
5.0
LOGIC VOLTAGE (V)
Figure 28. Reference Turn-on Transient
Figure 25. DICC vs. Logic Input Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
OUT
= 25°C
A
I
= 0mA
1
10
15
20
25
AV (V)
30
35
40
CH1 2µV
M2.00s
LINE
1.8V
DD
Figure 29. Reference Noise (0.1 Hz to 10 Hz Bandwidth)
Figure 26. AIDD vs. AVDD
9
8
7
6
5
4
3
2
1
0
T
= 25°C
A
1
CH1 20µV
M2.00s
LINE
0V
–21 –19 –17 –15 –13 –11 –9
–7
–5
–3
–1
1
LOAD CURRENT (mA)
Figure 30. Reference Noise (100 kHz Bandwidth)
Figure 27. DVCC Output Voltage vs. Load Current
Rev. J | Page 14 of 30
Data Sheet
AD5410/AD5420
70
60
50
40
30
20
5.0005
5.0000
4.9995
4.9990
4.9985
4.9980
4.9975
4.9970
4.9965
4.9960
4.9955
T
AV
= 25°C
A
= 24V
DD
T
= 25°C
= 40V
A
AV
10
0
DD
OUTPUT DISABLED
–10
0
5
10
15
20
25
30
35
40
45
0
1
2
3
4
5
6
7
8
9
COMPLIANCE VOLTAGE (V)
LOAD CURRENT (mA)
Figure 31. Output Leakage Current vs. Compliance Voltage
Figure 34. Reference Output Voltage vs. Load Current
5.003
30
20
0x8000 TO 0x7FFF
0x7FFF TO 0x8000
50 DEVICES SHOWN
AV = 24V
AV
= 24V
DD
= 25°C
DD
T
A
5.002
5.001
5.000
4.999
4.998
4.997
R
= 250Ω
LOAD
10
0
–10
–20
–30
–40
–20
0
20
40
60
80
0
2
4
6
8
10
12
14
16
18
20
TIME (µs)
TEMPERATURE (°C)
Figure 32. Reference Output Voltage vs. Temperature
Figure 35. Digital-to-Analog Glitch
45
40
35
30
25
20
15
10
5
25
20
15
10
5
AV
= 24V
DD
T
AV
R
= 25°C
A
= 24V
DD
= 300Ω
LOAD
0
0
0
1
2
3
4
5
6
7
8
9
10
–1
0
1
2
3
4
5
6
7
8
TEMPERATURE COEFFICIENT (ppm/°C)
TIME (µs)
Figure 33. Reference Temperature Coefficient Histogram
Figure 36. 4 mA to 20 mA Output Current Step
Rev. J | Page 15 of 30
AD5410/AD5420
TERMINOLOGY
Data Sheet
Gain Error Temperature Coefficient (TC)
Relative Accuracy or Integral Nonlinearity (INL)
This is a measure of the change in gain error with changes in
temperature. Gain error TC is expressed in ppm FSR/°C.
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation, in % FSR, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 7.
Current Loop Compliance Voltage
This is the maximum voltage at the IOUT pin for which the
output current is equal to the programmed value.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 8.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The voltage
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range, expressed in ppm/°C as follows:
Total Unadjusted Error (TUE)
Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account, namely INL error,
offset error, gain error, and output drift over supplies and
temperature. TUE is expressed in % FSR. A typical TUE vs.
code plot can be seen in Figure 9.
VREFmax −VREFmin
REFnom ×TempRange
TC =
×106
V
where:
REFmax is the maximum reference output measured over the
total temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 5 V.
Monotonicity
V
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5410/AD5420
are monotonic over their full operating temperature range.
V
Full-Scale Error
V
Full-scale error is a measure of the output error when full-scale
code is loaded to the data register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed as a percentage
of the full-scale range (% FSR).
TempRange is the specified temperature range, −40°C to +85°C.
Reference Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.
Full-Scale Error Temperature Coefficient (TC)
This is a measure of the change in full-scale error with changes
in temperature. Full-scale error TC is expressed in ppm FSR/°C.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from the ideal
expressed in % FSR. A plot of gain error vs. temperature can be
seen in Figure 15.
Rev. J | Page 16 of 30
Data Sheet
AD5410/AD5420
THEORY OF OPERATION
The AD5410/AD5420 are precision digital-to-current loop output
converters designed to meet the requirements of industrial
process control applications. They provide a high precision,
fully integrated, low cost single-chip solution for generating
current loop outputs. The current ranges available are 0 mA
to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired
output configuration is user selectable via the control register.
SCLK. The input shift register consists of eight address bits and
16 data bits, as shown in Table 6. The 24-bit word is uncondition-
ally latched on the rising edge of LATCH. Data continues to be
clocked in irrespective of the state of LATCH. On the rising edge
of LATCH, the data that is present in the input shift register is
latched; that is, the last 24 bits to be clocked in before the rising
edge of LATCH is the data that is latched. The timing diagram
for this operation is shown in Figure 2.
ARCHITECTURE
Standalone Operation
The DAC core architecture of the AD5410/AD5420 consists of
two matched DAC sections. A simplified circuit diagram is shown
in Figure 37. The four MSBs of the 12-bit or 16-bit data-word
are decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 8/12 bits of the data-
word drive Switch S0 to Switch S7 or Switch S0 to Switch S11 of an
8-/12-bit voltage mode R-2R ladder network.
The serial interface works with both a continuous and noncon-
tinuous SCLK. A continuous SCLK source can be used only if
LATCH is taken high after the correct number of data bits has
been clocked in. In gated clock mode, a burst clock containing
the exact number of clock cycles must be used, and LATCH
must be taken high after the final clock to latch the data. The
first rising edge of SCLK that clocks in the MSB of the data-
word marks the beginning of the write cycle. Exactly 24 rising
clock edges must be applied to SCLK before LATCH is brought
high. If LATCH is brought high before the 24th rising SCLK
edge, the data written is invalid. If more than 24 rising SCLK
edges are applied before LATCH is brought high, the input data
is also invalid.
V
OUT
2R
E1
2R
E2
2R
E15
2R
S0
2R
S1
2R
2R
S7/S11
V
REFIN
Table 6. Input Shift Register Format
MSB
8-/12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
LSB
Figure 37. DAC Ladder Structure
DB23 to DB16
DB15 to DB0
Address byte
Data-word
The voltage output from the DAC core is converted to a current
(see Figure 38) that is then mirrored to the supply rail so that
the application simply sees a current source output with respect
to ground.
Table 7. Address Byte Functions
Address Byte
Function
00000000
00000001
No operation (NOP)
Data register
AV
DD
00000010
Readback register value as per read address
(see Table 8)
R2
R3
01010101
01010110
Control register
Reset register
T2
A2
I
12-/16-BIT
DAC
T1
OUT
Daisy-Chain Operation
A1
For systems that contain several devices, the SDO pin can be used
to daisy-chain several devices together, as shown in Figure 39.
This daisy-chain mode can be useful in system diagnostics and
in reducing the number of serial interface lines. Daisy-chain
mode is enabled by setting the DCEN bit of the control register.
The first rising edge of SCLK that clocks in the MSB of the data-
word marks the beginning of the write cycle. SCLK is continuously
applied to the input shift register. If more than 24 clock pulses
are applied, the data ripples out of the input shift register and
appears on the SDO line. This data, having been clocked out on
the previous falling SCLK edge, is valid on the rising edge of
SCLK. By connecting the SDO of the first device to the SDIN
input of the next device in the chain, a multidevice interface is
constructed. Each device in the system requires 24 clock pulses.
R
SET
Figure 38. Voltage-to-Current Conversion Circuitry
SERIAL INTERFACE
The AD5410/AD5420 are controlled over a versatile 3-wire
serial interface that operates at clock rates of up to 30 MHz. They
are compatible with SPI, QSPI, MICROWIRE, and DSP
standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of
Rev. J | Page 17 of 30
AD5410/AD5420
Data Sheet
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of AD5410/AD5420 devices in the
chain. When the serial transfer to all devices is complete,
LATCH is taken high. This latches the input data in each device
in the daisy chain. The serial clock can be a continuous or a
gated clock.
Readback Operation
Readback mode is invoked by setting the address byte and read
address as shown in Table 9 and Table 8 when writing to the
input shift register. The next write to the AD5410/AD5420
should be a NOP command, which clocks out the data from the
previously addressed register, as shown in Figure 3. By default,
the SDO pin is disabled. After having addressed the AD5410/
AD5420 for a read operation, a rising edge on LATCH enables
the SDO pin in anticipation of data being clocked out. After the
data has been clocked out on SDO, a rising edge on LATCH
disables (tristate) the SDO pin once again. To read back the
data register, for example, the following sequence should be
implemented:
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.
AD5410/
AD5420*
CONTROLLER
DATA OUT
SDIN
1. Write 0x020001 to the AD5410/AD5420 input shift
register. This configures the part for read mode with the
data register selected.
SERIAL CLOCK
CONTROL OUT
SCLK
LATCH
2. Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the data register is clocked
out on the SDO line.
DATA IN
SDO
SDIN
Table 8. Read Address Decoding
AD5410/
AD5420*
Read Address
Function
SCLK
00
01
10
Read status register
Read data register
Read control register
LATCH
SDO
SDIN
AD5410/
AD5420*
SCLK
LATCH
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Daisy Chaining the AD5410/AD5420
Table 9. Input Shift Register Contents for a Read Operation
MSB
LSB
DB0
Read address
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
DB15 to DB2
DB1
0
0
0
0
0
0
1
0
X1
1 X = don’t care.
Rev. J | Page 18 of 30
Data Sheet
AD5410/AD5420
POWER-ON
SOFTWARE RESET
CONTROL REGISTER WRITE (ONE WRITE COMMAND)
• SELECT R
EXTERNAL/INTERNAL
SET
• SET THE REQUIRED RANGE
• CONFIGURE THE SLEW RATE CONTROL (IF REQUIRED)
• CONFIGURE DAISY CHAIN MODE (IF REQUIRED)
• ENABLE THE OUTPUT
CONTROL REGISTER WRITE
• DISABLE OUTPUT
DATA REGISTER WRITE
• WRITE REQUIRED CODE TO DATA REGISTER
R
CONFIGURATION CHANGE
RANGE CHANGE
SET
Figure 40. Programming Sequence to Write/Enable the Output Correctly
Rev. J | Page 19 of 30
AD5410/AD5420
Data Sheet
POWER-ON STATE
DATA REGISTER
Upon power-on of the AD5410/AD5420, the power-on reset
circuit ensures that all registers are loaded with zero code. As
such, the output is disabled (tristate). Also upon power-on,
internal calibration registers are read, and the data is applied to
internal calibration circuitry. For a reliable read operation, there
must be sufficient voltage on the AVDD supply when the read event
is triggered by the DVCC power supply powering up. Powering
up the DVCC supply after the AVDD supply has reached at least 5 V
ensures this. If DVCC and AVDD are powered up simultaneously,
then the supplies should be powered up at a rate greater than,
typically, 5000 V/sec. If the internal DVCC is enabled, the
supplies should be powered up at a rate greater than, typically,
2000 V/sec. If this cannot be achieved, simply issue a reset
command to the AD5410/AD5420 after power-on. This per-
forms a power-on reset event, reading the calibration registers
and ensuring specified operation of the AD5410/AD5420. To
ensure correct calibration and to allow the internal reference to
settle to its correct trim value, 40 µs should be allowed after a
successful power on reset.
The data register is addressed by setting the address byte of the
input shift register to 0x01. The data to be written to the data
register is entered in Position DB15 to Position DB4 for the
AD5410 and in Position DB15 to Position DB0 for the AD5420,
as shown in Table 12 and Table 13, respectively.
CONTROL REGISTER
The control register is addressed by setting the address byte of
the input shift register to 0x55. The data to be written to the
control register is entered in Position DB15 to Position DB0,
as shown in Table 14. The control register bit functions are
described in Table 10.
Table 10. Control Register Bit Functions
Bit
Description
REXT
Setting this bit selects the external current setting
resistor. See the AD5410/AD5420 Features section
for further details. When using an external current
setting resistor, it is recommended to only set REXT
when also setting the OUTEN bit. Alternately, REXT
can be set before the OUTEN bit is set, but the range
(see Table 11) must be changed on the write in which
the output is enabled. See Figure 40 for best practice.
TRANSFER FUNCTION
For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA
current output ranges, the output current is respectively
expressed as
OUTEN
SR Clock
SR Step
Output enable. This bit must be set to enable the
output.
Digital slew rate control. See the AD5410/AD5420
Features section.
Digital slew rate control. See the AD5410/AD5420
Features section.
20 mA
2N
IOUT
IOUT
IOUT
=
=
=
× D
SREN
DCEN
Digital slew rate control enable.
Daisy-chain enable.
24 mA
2N
× D
R2, R1, R0
Output range select. See Table 11.
16 mA
2N
× D + 4 mA
Table 11. Output Range Options
R2
R1
R0
Output Range Selected
where:
1
1
1
0
1
1
1
0
1
4 mA to 20 mA current range
0 mA to 20 mA current range
0 mA to 24 mA current range
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
Table 12. Programming the AD5410 Data Register
MSB
LSB
DB0
X1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB8
DB7
DB6
DB5
DB4
DB4
DB3
DB2
DB1
12-bit data-word
X1
X1
X1
1 X = don’t care.
Table 13. Programming the AD5420 Data Register
MSB
LSB
DB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB7
DB6
DB5
DB3
DB2
DB1
16-bit data-word
Table 14. Programming the Control Register
MSB
LSB
DB2 DB1 DB0
R2 R1 R0
DB15
DB14
DB13 DB12
REXT OUTEN
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
SR clock SR step SREN
DB3
DCEN
0
0
Rev. J | Page 20 of 30
Data Sheet
AD5410/AD5420
Table 15. Status Register Bit Functions
RESET REGISTER
Bit
Description
The reset register is addressed by setting the address byte of the
input shift register to 0x56. The reset register contains a single
reset bit at Position DB0, as shown in Table 16. Writing a logic
high to this bit performs a reset operation, restoring the part to
its power-on state.
IOUT Fault
Slew Active
This bit is set if a fault is detected on the IOUT pin.
This bit is set while the output value is slewing
(slew rate control enabled).
Overtemp
This bit is set if the AD5410/AD5420 core
temperature exceeds approximately 150°C.
STATUS REGISTER
The status register is a read-only register. The status register bit
functionality is shown in Table 15 and Table 17.
Table 16. Programming the Reset Register
MSB
LSB
DB0
Reset
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
Reserved
Table 17. Decoding the Status Register
MSB
LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
Reserved IOUT fault Slew active Overtemp
Rev. J | Page 21 of 30
AD5410/AD5420
Data Sheet
AD5410/AD5420 FEATURES
FAULT ALERT
EXTERNAL CURRENT SETTING RESISTOR
In Figure 38, RSET is an internal sense resistor as part of the
voltage-to-current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of RSET. An external precision 15 kΩ low drift resistor
can be connected from the RSET pin of the AD5410/AD5420 to
ground; this improves the overall performance of the AD5410/
AD5420. The external resistor is selected via the control
register. See Table 14.
FAULT
The AD5410/AD5420 are equipped with a
an open-drain output allowing several AD5410/AD5420
devices to be connected together to one pull-up resistor for
pin, which is
FAULT
global fault detection. The
pin is forced active by any
one of the following fault scenarios:
•
The voltage at IOUT attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The IOUT current is controlled by a PMOS
transistor and internal amplifier, as shown in Figure 38.
The internal circuitry that develops the fault output avoids
using a comparator with window limits because this requires
DIGITAL POWER SUPPLY
By default, the DVCC pin accepts a power supply of 2.7 V to
5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V
power supply can be output on the DVCC pin for use as a digital
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DVCC SELECT
pin unconnected. To disable the internal supply, DVCC SELECT
should be tied to 0 V. DVCC is capable of supplying up to 5 mA
of current. See Figure 27 for a load regulation graph.
FAULT
an actual output error before the
output becomes
active. Instead, the signal is generated when the internal
amplifier in the output stage has less than approximately
1 V of remaining drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus, the
FAULT
output activates slightly before the compliance limit is
reached. Because the comparison is made within the feed-
back loop of the output amplifier, the output accuracy is
maintained by its open-loop gain and an output error does
EXTERNAL BOOST FUNCTION
FAULT
not occur before the
output becomes active.
The addition of an external boost transistor, as shown in Figure 41,
reduces the power dissipated in the AD5410/AD5420 by reducing
the current flowing in the on-chip output transistor (dividing it
by the current gain of the external circuit). A discrete NPN
transistor with a breakdown voltage, BVCEO, greater than 40 V
can be used.
•
If the core temperature of the AD5410/AD5420 exceeds
approximately 150°C.
The IOUT fault and overtemp bits of the status register are used
FAULT
FAULT
in conjunction with the
fault condition caused the
and Table 15.
pin to inform the user which
pin to be asserted. See Table 17
The external boost capability allows the AD5410/AD5420 to be
used at the extremes of the supply voltage, load current, and
temperature range. The boost transistor can also be used to
reduce the amount of temperature-induced drift in the part.
This minimizes the temperature-induced drift of the on-chip
voltage reference, which improves drift and linearity.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that clears the current output to
the bottom of its programmed range. It is necessary to maintain
CLEAR high for a minimum amount of time (see Figure 2) to
complete the operation. When the CLEAR signal is returned
low, the output remains at the cleared value. The preclear value
can be restored by pulsing the LATCH signal low without
clocking any data. A new value cannot be programmed until the
CLEAR pin is returned low.
MJD31C
OR
2N3053
BOOST
AD5410/
AD5420
I
OUT
1kΩ
INTERNAL REFERENCE
0.022µF
R
L
The AD5410/AD5420 contain an integrated +5 V voltage
reference with initial accuracy of 5 mV maximum and a
temperature drift coefficient of 10 ppm/°C maximum. The
reference voltage is buffered and externally available for use
elsewhere within the system. See Figure 34 for a load regulation
graph of the integrated reference.
Figure 41. External Boost Configuration
Rev. J | Page 22 of 30
Data Sheet
AD5410/AD5420
HART COMMUNICATION
Table 18. Slew Rate Update Clock Values
The AD5410/AD5420 contain a CAP2 pin, into which a HART
signal can be coupled. The HART signal appears on the current
output if the output is enabled. To achieve a 1 mA p-p current, the
signal amplitude at the CAP2 pin must be 48 mV p-p. Assuming
that the modem output amplitude is 500 mV p-p, its output
must be attenuated by 500/48 = 10.42. If this voltage is used, the
current output should meet the HART amplitude specifications.
Figure 42 shows the recommended circuit for attenuating and
coupling in the HART signal.
SR Clock
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)
257,730
198,410
152,440
131,580
115,740
69,440
37,590
25,770
20,160
16,030
10,290
8280
AVDD
C2
CAP2
C1
HART MODEM
OUTPUT
6900
5530
4240
3300
Figure 42. Coupling HART Signal
In determining the absolute values of the capacitors, ensure that
the FSK output from the modem is passed undistorted. Thus,
the bandwidth presented to the modem output signal must pass
1200 Hz and 2200 Hz frequencies. The recommended values
are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew
rate of the output is necessary to meet the analog rate of change
requirements for HART.
Table 19. Slew Rate Step Size Options
SR Step AD5410 Step Size (LSB)
AD5420 Step Size (LSB)
000
001
010
011
100
101
110
111
1/16
1/8
1/4
1/2
1
1
2
4
8
16
32
64
128
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5410/AD5420 allows the
user to control the rate at which the output current changes.
With the slew rate control feature disabled, the output current
changes at a rate of approximately 16 mA in 10 μs (see Figure 36).
This varies with load conditions. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are SR clock and SR step.
SR clock defines the rate at which the digital slew is updated,
SR step defines by how much the output value changes at each
update. Both parameters together define the rate of change of
the output current. Table 18 and Table 19 outline the range of
values for both the SR clock and SR step parameters. Figure 43
shows the output current changing for ramp times of 10 ms,
50 ms, and 100 ms.
2
4
8
25
20
15
10
5
T
= 25°C
A
AV
= 24V
DD
R
= 300Ω
LOAD
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
0
–10
0
10 20 30 40 50 60 70 80 90 100 110
TIME (ms)
Figure 43. Output Current Slewing Under Control of the Digital Slew Rate
Control Feature
Rev. J | Page 23 of 30
AD5410/AD5420
Data Sheet
The time it takes for the output current to slew over a given
output range can be expressed as follows:
value with a write to the control register. To avoid halting the
output slew, the slew active bit can be read to check that the
slew has completed before writing to any of the AD5410/
AD5420 registers (see Table 17). The update clock frequency for
any given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 20 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 20
were obtained using Equation 1. The digital slew rate control
feature results in a staircase formation on the current output, as
shown in Figure 47. Figure 47 also shows how the staircase can
be removed by connecting capacitors to the CAP1 and CAP2
pins, as described in the IOUT Filtering Capacitors section.
Slew Time =
Output Change
(1)
Step Size×Update Clock Frequency ×LSB Size
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate. If the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
Table 20. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range
Step Size (LSBs)
Update Clock Frequency (Hz)
1
2
4
8
16
32
64
128
257,730
198,410
152,440
131,580
115,740
69,440
37,590
25,770
20,160
16,030
10,290
8280
0.25
0.33
0.43
0.50
0.57
0.9
1.7
2.5
3.3
4.1
6.4
7.9
9.5
12
0.13
0.17
0.21
0.25
0.28
0.47
0.87
1.3
1.6
2.0
3.2
4.0
0.06
0.08
0.11
0.12
0.14
0.24
0.44
0.64
0.81
1.0
1.6
2.0
2.4
3.0
3.9
5.0
0.03
0.04
0.05
0.06
0.07
0.12
0.22
0.32
0.41
0.51
0.80
1.0
0.016
0.021
0.027
0.031
0.035
0.06
0.11
0.16
0.20
0.26
0.40
0.49
0.59
0.74
0.97
1.24
0.008
0.010
0.013
0.016
0.018
0.03
0.05
0.08
0.10
0.13
0.20
0.25
0.30
0.37
0.48
0.62
0.004
0.005
0.007
0.008
0.009
0.015
0.03
0.04
0.05
0.06
0.10
0.12
0.15
0.19
0.24
0.31
0.0020
0.0026
0.0034
0.0039
0.0044
0.007
0.014
0.020
0.025
0.03
0.05
0.06
0.07
0.09
0.12
0.16
6900
5530
4240
3300
4.8
5.9
7.7
9.9
1.2
1.5
1.9
2.5
15
20
Rev. J | Page 24 of 30
Data Sheet
AD5410/AD5420
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
IOUT FILTERING CAPACITORS
T
AV
R
= 25°C
A
= 24V
Capacitors can be placed between CAP1 and AVDD, and CAP2
and AVDD, as shown in Figure 44.
DD
= 300Ω
LOAD
AV
DD
C1
C2
AV
DD
CAP1
CAP2
AD5410/
AD5420
I
NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2
OUT
GND
–1
0
1
2
3
4
5
6
7
8
Figure 44. IOUT Filtering Capacitors
TIME (ms)
The capacitors form a filter on the current output circuitry, as
shown in Figure 45, reducing the bandwidth and the slew rate
of the output current. Figure 46 shows the effect the capacitors
have on the slew rate of the output current. To achieve significant
reductions in the rate of change, very large capacitor values are
required, which may not be suitable in some applications. In
this case, the digital slew rate control feature should be used.
The capacitors can be used in conjunction with the digital slew
rate control feature as a means of smoothing out the steps caused
by the digital code increments, as shown in Figure 47.
C1
Figure 47. Smoothing Out the Steps Caused by the Digital Slew Rate Control
Feature
FEEDBACK/MONITORING OF OUTPUT CURRENT
For feedback or monitoring of the output current value, a sense
resistor can be placed in series with the IOUT output pin and the
voltage drop across it measured. As well as being an additional
component, the resistor increases the compliance voltage required.
An alternative method is to use a resistor that is already in place.
R3 is such a resistor and is internal to the AD5410/AD5420, as
shown in Figure 48. By measuring the voltage between the R3SENSE
and BOOST pins, the value of the output current can be calculated
as follows:
C2
AV
DD
CAP1
CAP2
VR3
(2)
IOUT
IBIAS
40Ω
R3
BOOST
4kΩ
where:
VR3 is the voltage drop across R3 measured between the R3SENSE
and BOOST pins.
DAC
12.5kΩ
I
IBIAS is a constant bias current flowing through R3 with a typical
OUT
value of 444 μA.
R3 is the resistance value of resistor R3 with a typical value of 40 Ω.
R
SET
AV
DD
Figure 45. IOUT Filter Circuitry
R
METAL
R3
SENSE
25
R3
40Ω
BOOST
20
15
10
5
I
OUT
T
AV
R
= 25°C
A
I
444µA
BIAS
= 24V
DD
= 300Ω
LOAD
NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2
Figure 48. Structure of Current Output Circuit
0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ms)
Figure 46. Slew Controlled 4 mA to 20 mA Output Current Step Using
External Capacitors on the CAP1 and CAP2 Pins
Rev. J | Page 25 of 30
AD5410/AD5420
Data Sheet
R3 and IBIAS both have a tolerance of 10% and a temperature
coefficient of 30 ppm/°C. Connecting to R3SENSE rather than
AVDD avoids incorporating into R3 internal metal connections
that have large temperature coefficients and result in large
errors. See Figure 49 for a plot of R3 vs. ambient temperature
and Figure 50 for a plot of R3 vs. output current.
40.98
To eliminate errors due to the tolerances of R3 and IBIAS, a two-
measurement calibration can be performed as the following
example illustrates:
1. Program code 0x1000 and measure IOUT and VR3. In this
example, the measured values are
I
OUT = 1.47965 mA
VR3 = 79.55446 mV
I
= 12mA
OUT
R3 = V /(12mA + 444µA)
40.96
40.94
40.92
40.90
40.88
40.86
40.84
40.82
40.80
40.78
2. Program Code 0xF000 and measure IOUT and VR3 again.
The measured values this time are
R3
I
V
OUT = 22.46754 mA
R3 = 946.39628 mV
Using this information and Equation 2, two simultaneous
equations can be generated from which the values of R3 and
I
BIAS can be calculated as follows:
VR3
IOUT
=
− IBIAS
R3
VR3
⇒ IBIAS
=
− IOUT
–40
–20
0
20
40
60
80
100
R3
AMBIENT TEMPERATURE (°C)
Figure 49. R3 Resistor Value vs. Temperature
Simultaneous Equation 1
42.0
41.8
41.6
41.4
41.2
41.0
40.8
40.6
40.4
40.2
40.0
T
= 25°C
A
0.07955446
R3 = V /(I
R3 OUT
+ 444µA)
IBIAS
=
− 0.00147965
− 0.02246754
R3
Simultaneous Equation 2
0.94639628
IBIAS
=
R3
From these two equations,
R3 = 41.302 Ω and IBIAS = 446.5 μA
And Equation 2 becomes
VR3
IOUT
=
– 446.5 µA
41.302
0
5
10
15
20
25
I
(mA)
OUT
Figure 50. R3 Resistor Value vs. IOUT
Rev. J | Page 26 of 30
Data Sheet
AD5410/AD5420
APPLICATIONS INFORMATION
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 μF
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Alternatively, the capacitor can be connected from CAP1 and/or
CAP2 to AVDD to reduce the slew rate of the current. The digital
slew rate control feature may also prove useful in this situation.
The power supply lines of the AD5410/AD5420 should use as
large a trace as possible to provide low impedance paths and to
reduce the effects of glitches on the power supply line. Fast-
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the reference inputs. A ground line
routed between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because noise
can couple through to the DAC output.
TRANSIENT VOLTAGE PROTECTION
The AD5410/AD5420 contain ESD protection diodes that prevent
damage from normal handling. The industrial control environ-
ment can, however, subject I/O circuits to much higher transients.
To protect the AD5410/AD5420 from excessively high voltage
transients, external power diodes and a surge current limiting
resistor may be required, as shown in Figure 51. The constraint
on the resistor value is that during normal operation, the output
level at IOUT must remain within its voltage compliance limit of
AVDD − 2.5 V, and the two protection diodes and resistor must
have appropriate power ratings. Further protection can be pro-
vided with transient voltage suppressors (TVS), or transorbs.
These are available as both unidirectional suppressors (protect
against positive high voltage transients) and bidirectional
suppressors (protect against both positive and negative high
voltage transients) and are available in a wide range of standoff
and breakdown voltage ratings. It is recommended that all field
connected nodes be protected.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board.
A microstrip technique is by far the best method but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5410/AD5420 is ideal for isolated interfaces because
the number of interface lines is kept to a minimum. Figure 52
shows a 4-channel isolated interface to the AD5410/AD5420
using an ADuM1400. For further information, visit
AV
DD
AV
DD
R
AD5410/
AD5420
P
I
OUT
R
L
GND
www.analog.com.
Figure 51. Output Transient Voltage Protection
CONTROLLER
ADuM1400*
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board (PCB) on
which the AD5410/AD5420 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5410/AD5420 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
SERIAL
CLOCK
OUT
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SCLK
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SERIAL
DATA
OUT
TO
SDIN
SYNC
OUT
TO
LATCH
TO
CLEAR
CONTROL
OUT
*ADDITIONAL PINS OMITTED FOR CLARITY.
The AD5410/AD5420 should have ample supply bypassing of
10 μF in parallel with 0.1 μF on each supply, located as close to
the package as possible, ideally right up against the device.
The 10 μF capacitors are the tantalum bead type. The 0.1 μF
Figure 52. Isolated Interface
Rev. J | Page 27 of 30
AD5410/AD5420
Data Sheet
2.5
2.0
1.5
1.0
0.5
0
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5410/AD5420 is via a serial
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communication channel is a 3-wire (mini-
mum) interface consisting of a clock signal, a data signal, and a
latch signal. The AD5410/AD5420 require a 24-bit data-word
with data valid on the rising edge of SCLK.
LFCSP
TSSOP
For all interfaces, the DAC output update is initiated on the
rising edge of LATCH. The contents of the registers can be read
using the readback function.
THERMAL AND SUPPLY CONSIDERATIONS
40
45
50
55
60
65
70
75
80
85
The AD5410/AD5420 are designed to operate at a maximum
junction temperature of 125°C. It is important that the device
not be operated under conditions that cause the junction tempera-
ture to exceed this value. Excessive junction temperature can
occur if the AD5410/AD5420 are operated from the maximum
AVDD, while driving the maximum current (24 mA) directly to
ground. In this case, the ambient temperature should be controlled
or AVDD should be reduced.
AMBIENT TEMPERATURE (°C)
Figure 53. Maximum Power Dissipation vs. Ambient Temperature
65
LFCSP
60
55
50
45
At the maximum ambient temperature of 85°C, the 24-lead
TSSOP can dissipate 1.14 W, and the 40-Lead LFCSP can
dissipate 1.21 W.
TSSOP
40
35
30
25
To ensure that the junction temperature does not exceed 125°C
while driving the maximum current of 24 mA directly into
ground (also adding an on-chip current of 4 mA), AVDD should
be reduced from the maximum rating to ensure that the package
is not required to dissipate more power than previously stated
(see Table 21, Figure 53, and Figure 54).
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (°C)
Figure 54. Maximum Supply Voltage vs. Ambient Temperature
Table 21. Thermal and Supply Considerations
Consideration
TSSOP
LFCSP
TJmax TA
125 85
TJ max TA 125 85
Maximum Allowed Power
Dissipation When Operating at an
Ambient Temperature of 85°C
1.21 W
1.14 W
θJA
35
θJA
33
TJmax PD θJA 125
40 0.028
35 86C
TJmax
PD θJA
125 600.028 33 70C
Maximum Allowed Ambient
Temperature When Operating
from a Supply of 40 V/60 V and
Driving 24 mA Directly to Ground
T max TA
T max TA
J
Maximum Allowed Supply Voltage
When Operating at an Ambient
Temperature of 85°C and Driving
24 mA Directly to Ground
125 85
125 85
J
40 V
43 V
AIDD θJA 0.02835
AIDD θJA 0.02833
Rev. J | Page 28 of 30
Data Sheet
AD5410/AD5420
supply connections. A 24 V TVS is placed on the IOUT connection,
and a 36 V TVS is placed on the field supply input. For added
protection, clamping diodes are connected from the IOUT pin to the
AVDD and GND power supply pins. The recommended external
band-pass filter for the AD5700 HART modem includes a 150 kΩ
resistor, which limits current to a sufficiently low level to adhere
to intrinsic safety requirements. In this case, the input has higher
transient voltage protection and should, therefore, not require
additional protection circuitry, even in the most demanding of
industrial environments.
INDUSTRIAL, HART COMPATIBLE ANALOG
OUTPUT APPLICATION
Many industrial control applications have requirements for
accurately controlled current output signals, and the AD5410/
AD5420 are ideal for such applications. Figure 55 shows the
AD5410/AD5420 in a circuit design for an output module spe-
cifically for use in an industrial control application. The design
provides for a HART-enabled current output, with the HART
capability provided by the AD5700/AD5700-1 HART modem, the
industry’s lowest power and smallest footprint HART-compliant IC
modem. For additional space-savings, the AD5700-1 offers a 0.5%
precision internal oscillator. The HART_OUT signal from the
AD5700 is attenuated and ac-coupled into the CAP2 pin of the
AD5420. Further information on this configuration can be found
in Application Note AN-1065. An alternative method of coupling
the HART signal into the RSET pin (only applicable of the external
RSET is used), is available in Circuit Note CN-0270. Use of
either configuration results in the AD5700 HART modem output
modulating the 4 mA to 20 mA analog current without affecting
the dc level of the current. This circuit adheres to the HART
physical layer specifications as defined by the HART
Isolation between the AD5410/AD5420 and the backplane
circuitry is provided with the ADuM1400 and ADuM1200
iCoupler digital isolators; further information on iCoupler
products is available at www.analog.com. The internally generated
digital power supply of the AD5410/AD5420 powers the field
side of the digital isolators, removing the need to generate a
digital power supply on the field side of the isolation barrier.
The AD5410/AD5420 digital supply out-put supplies up to 5 mA,
which is more than enough to supply the 2.8 mA requirement
of the ADuM1400 and ADuM1200 operating at a logic signal
frequency of up to 1 MHz. To reduce the number of isolators
required, nonessential signals such as CLEAR can be connected
Communication Foundation.
FAULT
to GND and
, and SDO can be left unconnected, reducing
The module is powered from a field supply of 24 V. This supplies
AVDD directly. For transient overvoltage protection, transient
voltage suppressors (TVS) are placed on both the IOUT and field
the isolation requirements to just three signals. Doing so,
however, disables the fault alert features of the part.
24V
FIELD
SUPPLY
10µF
SMAJ36CA
36V
FIELD
GROUND
0.1µF
BACKPLANE SUPPLY
0.1µF
0.1µF
C3
ADuM1400
10kΩ
V
NC
V
V
V
V
GND
GND
V
DD1
DD2
E2
MICROCONTROLLER
AV
CAP1
V
DV
CC
DV
DD
CC
SELECT
V
V
V
V
GND
GND
OA
OB
OC
OD
IA
DIGITAL
OUTPUTS
IB
AD5410/AD5420
IC
ID
CLEAR
I
OUT
2
2
1
1
18Ω
LATCH
SCLK
SDIN
I
OUT
V
V
V
V
DD1
DD2
OA
V
V
UART
DIGITAL
IA
FAULT
SDO
INTERFACE INTPUTS
OB
IB
GND
GND
2
1
CAP2
GND REFOUT REFIN
ADuM1200
C1
2.2nF
C2
22nF
0.1µF
0.1µF
AV
DD
ADuM1402
V
CC
V
V
V
V
DD1
DD2
E2
HART_OUT
E1
TXD
RTS
RXD
CD
V
V
V
V
V
OA
OB
IA
V
V
V
IB
IC
ID
OC
OC
GND
GND
GND
GND
2
2
1
1
AD5700/AD5700-1
REF
1µF
1.2MΩ
150kΩ
ADC_IP
AGND DGND
300pF
1.2MΩ
150pF
Figure 55. AD5410/AD5420 in an Industrial Analog Output Application
Rev. J | Page 29 of 30
AD5410/AD5420
Data Sheet
OUTLINE DIMENSIONS
5.02
5.00
4.95
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
3.25
3.20
3.15
EXPOSED
PAD
(Pins Up)
6.40 BSC
1
BOTTOM VIEW
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.05
1.00
0.80
1.20 MAX
8°
0°
SECTION OF THIS DATA SHEET.
0.20
0.09
0.15
0.05
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 56. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
6.10
6.00 SQ
0.60 MAX
5.90
0.60 MAX
PIN 1
INDICATOR
31
30
40
1
5.85
5.75 SQ
5.65
0.50
BSC
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
10
11
21
20
0.50
0.40
0.30
0.20 MIN
TOP VIEW
4.50 REF
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 57. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.85 mm Package Height
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD5410AREZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Resolution
12 Bits
12 Bits
12 Bits
12 Bits
16 Bits
16 Bits
16 Bits
16 Bits
TUE (%)
Package Description
24-Lead TSSOP_EP
24-Lead TSSOP_EP
40-Lead LFCSP
Package Option
RE-24
RE-24
CP-40-1
CP-40-1
RE-24
RE-24
CP-40-1
CP-40-1
0.3 maximum
0.3 maximum
0.3 maximum
0.3 maximum
0.15 maximum
0.15 maximum
0.15 maximum
0.15 maximum
AD5410AREZ-REEL7
AD5410ACPZ-REEL
AD5410ACPZ-REEL7
AD5420AREZ
AD5420AREZ-REEL7
AD5420ACPZ-REEL
AD5420ACPZ-REEL7
EVAL-AD5420EBZ
40-Lead LFCSP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
40-Lead LFCSP
40-Lead LFCSP
Evaluation Board
1 Z = RoHS Compliant Part.
2 The EVAL-AD5420EBZ evaluation board can be used to evaluate the AD5410 with the units installed in place of the AD5420.
©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07027-0-11/17(J)
Rev. J | Page 30 of 30
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