AD5421_13 [ADI]
16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC; 16位,串行输入,环路供电4 mA至20 mA DAC型号: | AD5421_13 |
厂家: | ADI |
描述: | 16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC |
文件: | 总36页 (文件大小:726K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16-Bit, Serial Input,
Loop-Powered, 4 mA to 20 mA DAC
Data Sheet
AD5421
FEATURES
GENERAL DESCRIPTION
16-bit resolution and monotonicity
Pin selectable NAMUR-compliant ranges
4 mA to 20 mA
3.8 mA to 21 mA
3.2 mA to 24 mA
The AD5421 is a complete, loop-powered, 4 mA to 20 mA
digital-to-analog converter (DAC) designed to meet the needs
of smart transmitter manufacturers in the industrial control
industry. The DAC provides a high precision, fully integrated,
low cost solution in compact TSSOP and LFCSP packages.
NAMUR-compliant alarm currents
Downscale alarm current = 3.2 mA
Upscale alarm current = 22.8 mA/24 mA
Total unadjusted error (TUE): 0.05% maximum
INL error: 0.0035% FSR maximum
Output TC: 3 ppm/°C typical
Quiescent current: 300 µA maximum
Flexible SPI-compatible serial digital interface
with Schmitt triggered inputs
The AD5421 includes a regulated voltage output that is used to
power itself and other devices in the transmitter. This regulator
provides a regulated 1.8 V to 12 V output voltage. The AD5421
also contains 1.22 V and 2.5 V references, thus eliminating the
need for a discrete regulator and voltage reference.
The AD5421 can be used with standard HART® FSK protocol
communication circuitry without any degradation in specified
performance. The high speed serial interface is capable of opera-
ting at 30 MHz and allows for simple connection to commonly
used microprocessors and microcontrollers via a SPI-compatible,
3-wire interface.
On-chip fault alerts via FAULT pin or alarm current
Automatic readback of fault register on each write cycle
Slew rate control function
Gain and offset adjust registers
On-chip reference TC: 4 ppm/°C maximum
Selectable regulated voltage output
Loop voltage range: 5.5 V to 52 V
Temperature range: −40°C to +105°C
TSSOP and LFCSP packages
The AD5421 is guaranteed monotonic to 16 bits. It provides
0.0015% integral nonlinearity, 0.0012% offset error, and
0.0006% gain error under typical conditions.
The AD5421 is available in a 28-lead TSSOP and a 32-lead
LFCSP specified over the extended industrial temperature range
of −40°C to +105°C.
APPLICATIONS
COMPANION LOW POWER PRODUCTS
Industrial process control
4 mA to 20 mA loop-powered transmitters
Smart transmitters
HART Modem: AD5700, AD5700-1
Microcontroller: ADuCM360
HART network connectivity
FUNCTIONAL BLOCK DIAGRAM
IODV
DV
V
REG_SEL0 REG_SEL1 REG_SEL2 REG
REG
OUT IN
DD
DD
LOOP
LOOP
VOLTAGE
MONITOR
VOLTAGE
REGULATOR
DRIVE
FAULT
SYNC
SCLK
SDIN
SDO
INPUT
R
24kΩ
SET
REGISTER
CONTROL
LOGIC
16
16-BIT
DAC
GAIN/OFFSET
ADJUSTMENT
REGISTERS
LDAC
COM
RANGE0
RANGE1
TEMPERATURE
SENSOR
11.5kΩ
52Ω
LOOP–
ALARM_CURRENT_DIRECTION
VREF
AD5421
R
/R
INT EXT
REFOUT2 REFOUT1
REFIN
C
R
R
EXT1 EXT2
IN
Figure 1.
Rev. F
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Technical Support
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AD5421
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
On-Chip ADC ............................................................................ 23
Voltage Regulator ....................................................................... 23
Loop Current Slew Rate Control.............................................. 23
Power-On Default ...................................................................... 24
HART Communications ........................................................... 24
Serial Interface ................................................................................ 26
Input Shift Register .................................................................... 26
Register Readback ...................................................................... 26
DAC Register .............................................................................. 27
Control Register ......................................................................... 28
Fault Register .............................................................................. 29
Offset Adjust Register................................................................ 30
Gain Adjust Register .................................................................. 30
Applications Information .............................................................. 32
Determining the Expected Total Error.................................... 32
Thermal and Supply Considerations ....................................... 34
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
General Description ......................................................................... 1
Companion Low Power Products .................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
AC Performance Characteristics ................................................ 9
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Fault Alerts .................................................................................. 21
External Current Setting Resistor ............................................ 22
Loop Current Range Selection.................................................. 22
Connection to Loop Power Supply .......................................... 22
Rev. F | Page 2 of 36
Data Sheet
AD5421
REVISION HISTORY
1/13—Rev. E to Rev. F
12/11—Rev. A to Rev. B
Moved Revision History Section.....................................................3
Change to Table 7............................................................................11
Changes to Table 8 ..........................................................................13
Changes to On-Chip ADC Section...............................................23
Changes to Table 19 and On-Chip ADC Transfer Function
Equations Section............................................................................29
Added 32-Lead LFCSP...................................................... Universal
Changes to the Specifications Section, Table 1 .............................3
Changes to Table 7 ..........................................................................10
Added Figure 5, Renumbered Sequentially.................................11
Changes to Table 8 ..........................................................................11
Changes to Figure 33 ......................................................................17
Changes to the On-Chip ADC Section........................................22
Changes to Figure 46 ......................................................................23
Changes to Figure 48 ......................................................................24
Changes to the Register Readback Section..................................25
Updated Outline Dimensions........................................................33
Changes to Ordering Guide...........................................................34
7/12—Rev. D to Rev. E
Changes to Figure 1 and Companion Products Section ..............1
Changes to Pin LOOP− Description ............................................12
Changes to Applications Information Section and Figure 49 ...31
Added Figure 50 ..............................................................................32
5/12—Rev. C to Rev. D
5/11—Rev. 0 to Rev. A
Changes to Features Section and Applications Section; Added
Companion Products Section..........................................................1
Changes to Line Regulation Parameter, Table 1............................5
Updated Outline Dimensions........................................................33
Changes to REGIN, REFOUT1, and REFOUT2 Pin Descriptions
in Table 8 ..........................................................................................10
Change to Figure 45........................................................................22
Changes to Input Shift Register Section, Table 11, and Register
Readback Section ............................................................................24
Changes to Figure 48 ......................................................................30
12/11—Rev. B to Rev. C
Change to REFOUT1 Pin, Capacitive Load Parameter, Test
Conditions, Table 1 ...........................................................................4
Change to REGOUT Output, Capacitive Load Parameter, Test
Conditions, Table 1 ...........................................................................5
Changes to ESD Parameter, Table 6..............................................10
2/11—Revision 0: Initial Version
Rev. F | Page 3 of 36
AD5421
Data Sheet
SPECIFICATIONS
Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications
T
MIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
ACCURACY, INTERNAL RSET
Resolution
Total Unadjusted Error (TUE)2
16
Bits
−0.126
−0.041
−0.18
−0.06
−0.27
−0.08
+0.126
+0.041
+0.18
+0.06
+0.27
+0.08
% FSR
% FSR
% FSR
% FSR
% FSR
C grade
C grade, TA = 25°C
B grade
B grade, TA = 25°C
A grade
0.0064
0.011
0.011
A grade, TA = 25°C
Drift after 1000 hours at TA = 125°C
C grade
B grade
A grade
Guaranteed monotonic
B grade and C grade
B grade and C grade, TA = 25°C
A grade
TUE Long-Term Stability
Relative Accuracy (INL)
210
ppm FSR
% FSR
% FSR
% FSR
LSB
% FSR
% FSR
% FSR
−0.0035
−0.012
−0.024
−1
−0.056
−0.008
−0.11
0.0015
0.006
0.01
+0.0035
+0.012
+0.024
+1
+0.056
+0.008
+0.11
Differential Nonlinearity (DNL)
Offset Error
0.0008
0.0008
Offset Error TC3
Gain Error
1
4
5
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
mA
mA
−0.107
−0.035
−0.2
+0.107
+0.035
+0.2
B grade and C grade
B grade and C grade, TA = 25°C
A grade
0.0058
0.0058
Gain Error TC3
Full-Scale Error
−0.126
−0.041
−0.25
+0.126
+0.041
+0.25
B grade and C grade
B grade and C grade, TA = 25°C
A grade
0.0065
0.0065
Full-Scale Error TC3
Downscale Alarm Current
Upscale Alarm Current
3.19
22.77
3.21
22.83
4 mA to 20 mA and 3.8 mA to 21 mA
ranges
23.97
24.03
mA
3.2 mA to 24 mA range
ACCURACY, EXTERNAL RSET (24 kΩ)
Assumes ideal resistor, B grade and
C grade only; not specified for A grade
Resolution
16
Bits
Total Unadjusted Error (TUE)2
−0.048
−0.027
−0.08
−0.04
+0.048
+0.027
+0.08
% FSR
% FSR
% FSR
% FSR
ppm FSR
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
C grade
C grade, TA = 25°C
B grade
B grade, TA = 25°C
Drift after 1000 hours at TA = 125°C
C grade
0.002
0.003
40
0.0015
+0.04
TUE Long-Term Stability
Relative Accuracy (INL)
−0.0035
−0.012
−1
−0.021
−0.007
+0.0035
+0.012
+1
+0.021
+0.007
0.006
B grade
Guaranteed monotonic
Differential Nonlinearity (DNL)
Offset Error
0.0012
0.5
TA = 25°C
TA = 25°C
Offset Error TC3
Gain Error
−0.03
−0.023
+0.03
+0.023
0.0006
Rev. F | Page 4 of 36
Data Sheet
AD5421
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
Gain Error TC3
Full-Scale Error
1
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
mA
mA
−0.047
−0.028
+0.047
+0.028
0.0017
TA = 25°C
Full-Scale Error TC3
Downscale Alarm Current
Upscale Alarm Current
1
3.08
22.78
3.21
23
4 mA to 20 mA and 3.8 mA to 21 mA
ranges
23.99
24.01
mA
3.2 mA to 24 mA range
OUTPUT CHARACTERISTICS3
Loop Compliance Voltage4
LOOP− + 5.5
LOOP− + 12.5
V
V
REGOUT < 5.5 V, loop current = 24 mA
REGOUT = 12 V, loop current = 24 mA
Loop Current Long-Term Stability
100
15
ppm FSR
Drift after 1000 hours at TA = 125°C,
loop current = 12 mA, internal RSET
Drift after 1000 hours at TA = 125°C,
loop current = 12 mA, external RSET
Loop current = 12 mA, load current
from REGOUT = 5 mA
ppm FSR
µA/mA
Loop Current Error vs. REGOUT Load
Current
1.2
Resistive Load
Inductive Load
Power Supply Sensitivity
Output Impedance
Output TC
0
2
kΩ
See Figure 20 for a load line graph
Stable operation
Loop current = 12 mA
50
mH
µA/V
MΩ
0.1
12
400
3
1
ppm FSR/°C Loop current = 12 mA, internal RSET
ppm FSR/°C Loop current = 12 mA, external RSET
Output Noise
0.1 Hz to 10 Hz
500 Hz to 10 kHz
50
0.2
nA p-p
mV rms
HART bandwidth; measured across
500 Ω load
Noise Spectral Density
195
256
nA/√Hz
nA/√Hz
At 1 kHz
At 10 kHz
REFERENCE INPUT (REFIN PIN)3
Reference Input Voltage5
DC Input Impedance
REFERENCE OUTPUTS
REFOUT1 Pin
2.5
800
V
MΩ
For specified performance
75
Output Voltage
Temperature Coefficient
2.498
2.5
1.5
2
2.503
4
8
10
V
TA = 25°C
C grade
B grade
A grade
ppm/°C
ppm/°C
ppm/°C
µV p-p
nV/√Hz
nV/√Hz
ppm
4
Output Noise (0.1 Hz to 10 Hz)3
Noise Spectral Density3
7.5
245
70
200
10
4
At 1 kHz
At 10 kHz
Drift after 1000 hours at TA = 125°C
Recommended operation
Output Voltage Drift vs. Time3
Capacitive Load3
Load Current3, 6
nF
mA
Short-Circuit Current3
Power Supply Sensitivity3
Thermal Hysteresis3
6.5
2
285
5
0.1
0.1
mA
µV/V
ppm
ppm
mV/mA
Ω
Short circuit to COM
12
First temperature cycle
Second temperature cycle
Measured at 0 mA and 1 mA loads
Load Regulation3
Output Impedance
REFOUT2 Pin
Output Voltage
Output Impedance
0.2
1.28
1.18
1.227
72
V
kΩ
TA = 25°C
Rev. F | Page 5 of 36
AD5421
Data Sheet
Parameter1
Min
Typ
Max
12
Unit
Test Conditions/Comments
REGOUT OUTPUT
Output Voltage
Voltage regulator output
See Table 10
1.8
V
Output Voltage TC3
Output Voltage Accuracy
Externally Available Current3, 6
110
2
ppm/°C
%
mA
−4
3.15
+4
Assuming 4 mA flowing in the loop
and during HART communications
Short-Circuit Current
Line Regulation3
23
500
10
8
50
10
mA
μV/V
μV/V
mV/mA
mH
Internal NMOS
External NMOS
Load Regulation3
Inductive Load
Capacitive Load
ADC ACCURACY
Die Temperature
VLOOP Input
Stable operation
Recommended operation
2
µF
5
1
°C
%
DVDD OUTPUT
Can be overdriven up to 5.5 V
Output Voltage
Externally Available Current3, 6
3.17
3.15
3.3
3.48
V
mA
Assuming 4 mA flowing in the loop
and during HART communications
Short-Circuit Current
Load Regulation
DIGITAL INPUTS3
7.7
45
mA
mV/mA
Measured at 0 mA and 3 mA loads
SCLK, SYNC, SDIN, LDAC
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
0.7 × IODVDD
V
V
V
V
V
µA
pF
0.25 × IODVDD
+0.015
0.21
0.63
1.46
IODVDD = 1.8 V
IODVDD = 3.3 V
IODVDD = 5.5 V
Per pin
Input Current
Pin Capacitance
−0.015
5
Per pin
DIGITAL OUTPUTS3
SDO Pin
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
0.4
V
V
µA
IODVDD − 0.5
−0.01
+0.01
High Impedance Output
Capacitance
5
pF
FAULT Pin
Output Low Voltage, VOL
Output High Voltage, VOH
FAULT THRESHOLDS
ILOOP Under
ILOOP Over
Temp 140°C
0.4
V
V
IODVDD − 0.5
ILOOP − 0.01% FSR
ILOOP + 0.01% FSR
133
mA
mA
°C
Fault removed when temperature
≤ 125°C
Temp 100°C
90
°C
Fault removed when temperature
≤ 85°C
VLOOP 6V
VLOOP 12V
0.3
0.6
V
V
Fault removed when VLOOP ≥ 0.4 V
Fault removed when VLOOP ≥ 0.7 V
Rev. F | Page 6 of 36
Data Sheet
AD5421
Parameter1
POWER REQUIREMENTS
REGIN
IODVDD
Quiescent Current
Min
Typ
Max
Unit
Test Conditions/Comments
5.5
1.71
52
5.5
300
V
V
µA
With respect to LOOP−
With respect to COM
260
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421.
System level total error can be reduced using the offset and gain registers.
3 Guaranteed by design and characterization; not production tested.
4 The voltage between LOOP− and REGIN must be 5.5 V or greater.
5 The AD5421 is factory calibrated with an external 2.5 V reference connected to REFIN.
6 This is the current that the output is capable of sourcing. The load current originates from the loop and, therefore, contributes to the total current consumption figure.
Rev. F | Page 7 of 36
AD5421
Data Sheet
Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges;
all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
C Grade
Typ
Parameter1, 2
Min
Max
Unit
Test Conditions/Comments
ACCURACY, INTERNAL RSET
Total Unadjusted Error (TUE)3
−0.157
−0.117
−0.004
−0.004
−0.04
+0.157
+0.117
+0.004
+0.004
+0.04
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
0.0172
TA = 25°C
TA = 25°C
TA = 25°C
Relative Accuracy (INL)
Offset Error
0.0015
0.0025
−0.025
+0.025
Offset Error TC
Gain Error
1
5
6
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
−0.128
−0.093
+0.128
+0.093
0.0137
0.0172
TA = 25°C
Gain Error TC
Full-Scale Error
−0.157
−0.117
+0.157
+0.117
TA = 25°C
Full-Scale Error TC
ppm FSR/°C
ACCURACY, EXTERNAL RSET (24 kΩ)
Total Unadjusted Error (TUE)3
Assumes ideal resistor
TA = 25°C
−0.133
−0.133
−0.004
−0.004
−0.029
−0.029
+0.133
+0.133
+0.004
+0.004
+0.029
+0.029
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
0.0252
0.0015
0.0038
Relative Accuracy (INL)
Offset Error
TA = 25°C
TA = 25°C
Offset Error TC
Gain Error
0.5
ppm FSR/°C
% FSR
−0.11
+0.11
−0.106
0.0197
+0.106
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
TA = 25°C
TA = 25°C
Gain Error TC
Full-Scale Error
2
2
−0.133
−0.133
+0.133
+0.133
0.0252
Full-Scale Error TC
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Specifications guaranteed by design and characterization; not production tested.
3 Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421.
System level total error can be reduced using the offset and gain registers.
Rev. F | Page 8 of 36
Data Sheet
AD5421
AC PERFORMANCE CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Loop Current Settling Time
Loop Current Slew Rate
AC Loop Voltage Sensitivity
50
400
1.3
µs
µA/µs
µA/V
To 0.1% FSR, CIN = open circuit
CIN = open circuit
1200 Hz to 2200 Hz, 5 V p-p, RL = 3 kΩ
1 Temperature range: −40°C to +105°C; typical at +25°C.
TIMING CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX
.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX Unit
Description
t1
t2
t3
t4
33
17
17
17
10
25
5
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
ns min
ns min
ns min
ns min
µs min
ns min
ns min
µs min
ns min
ns max
ns min
ns max
t5
t6
t7
t8
t9
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
5
25
10
70
0
t10
t11
t12
t13
SCLK rising edge to SDO valid (CL SDO = 30 pF)
SYNC falling edge to SCLK rising edge setup time
SYNC rising edge to SDO tristate (CL SDO = 30 pF)
70
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 2 and Figure 3.
Table 5. SPI Watchdog Timeout Periods
Parameter1
T0
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T2
0
1
0
1
0
1
0
1
Min
43
87
436
873
1746
2619
3493
4366
Typ
50
100
Max
59
117
Unit
ms
ms
ms
ms
ms
ms
ms
ms
500
582
1000
2000
3000
4000
5000
1163
2326
3489
4652
5814
1 Specifications guaranteed by design and characterization; not production tested.
Rev. F | Page 9 of 36
AD5421
Data Sheet
Timing Diagrams
t1
t12
SCLK
8
9
1
10
11
t2
12
22
24
2
23
t3
D15
t8
D15
SDIN
D23
D16
D14
D13
D2
D1
D0
t13
t4
t7
D14
t11
D13
D2
D1
D0
t5
SDO
t6
SYNC
t9
t10
LDAC
Figure 2. Serial Interface Timing Diagram
8
9
1
8
9
24
SCLK
SDIN
1
24
D16
D23
D15
D0
D23
D16
D15
D0
INPUT WORD SPECIFIES REGISTER TO BE READ
UNDEFINED DATA
NOP OR REGISTER ADDRESS
D15
D0
SDO
SPECIFIED REGISTER DATA CLOCKED OUT
SYNC
Figure 3. Readback Timing Diagram
Rev. F | Page 10 of 36
Data Sheet
AD5421
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up
to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
REGIN to COM
REGOUT to COM
−0.3 V to +60 V
−0.3 V to +14 V
Digital Inputs to COM,
−0.3 V to DVDD + 0.3 V
THERMAL RESISTANCE
RANGE0, RANGE1, RINT/REXT
ALARM_CURRENT_DIRECTION,
REG_SEL0, REG_SEL1, REG_SEL2
Digital Inputs to COM
,
or +7 V (whichever is less)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−0.3 V to IODVDD + 0.3 V
or +7 V (whichever is less)
SCLK, SDIN, SYNC, LDAC
Table 7. Thermal Resistance
Package Type
Digital Outputs to COM,
SDO, FAULT
REFIN to COM
REFOUT1, REFOUT2
VLOOP to COM
LOOP− to COM
DVDD to COM
IODVDD to COM
REXT1, CIN to COM
REXT2 to COM
DRIVE to COM
−0.3 V to IODVDD + 0.3 V
or +7 V (whichever is less)
θJA
32
40
θJC
9
Unit
°C/W
°C/W
28-Lead TSSOP_EP (RE-28-2)
32-Lead LFCSP_WQ (CP-32-11)
−0.3 V to +7 V
−0.3 V to +4.7 V
−0.3 V to +60 V
−5 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +4.3 V
−0.3 V to +0.3 V
−0.3 V to +11 V
7
ESD CAUTION
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
−40°C to +105°C
−65°C to +150°C
125°C
Junction Temperature (TJ MAX
)
Power Dissipation
(TJ MAX − TA)/θJA
Lead Temperature,
Soldering (10 sec)
JEDEC Industry Standard
J-STD-020
ESD
Human Body Model
Field Induced Charged Device
Model
3 kV
2 kV
Machine Model
200 V
Rev. F | Page 11 of 36
AD5421
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IODV
REG
DD
OUT
2
SDO
SCLK
SYNC
SDIN
REG
IN
3
DRIVE
4
V
LOOP
AD5421
TOP VIEW
(Not to Scale)
5
LOOP–
SDIN 1
LDAC 2
FAULT 3
COM 4
24
V
LOOP
PIN 1
23 LOOP–
6
LDAC
FAULT
R
INDICATOR
EXT2
22
21
20
R
R
C
EXT2
EXT1
IN
7
R
EXT1
IN
AD5421
TOP VIEW
(Not to Scale)
8
DV
C
DD
DV
5
DD
ALARM CURRENT DIRECTION 6
/R
9
ALARM_CURRENT_DIRECTION
REFOUT1
REFOUT2
REFIN
19 REFOUT1
18 REFOUT2
17 REFIN
10
11
12
13
14
R
/R
R
7
INT EXT
INT EXT
RANGE 0 8
RANGE0
RANGE1
COM
REG_SEL0
REG_SEL1
REG_SEL2
COM
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE SAME
POTENTIAL AS THE COM PIN AND TO A COPPER PLANE FOR
OPTIMUM THERMAL PERFORMANCE.
NOTES
1. NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE
SAME POTENTIAL AS THE COM PIN AND TO A COPPER
PLANE FOR OPTIMUM THERMAL PERFORMANCE.
Figure 4. TSSOP Pin Configuration
Figure 5. LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
29
IODVDD
Digital Interface Supply Pin. Digital thresholds are referenced to the voltage applied to this pin. A
voltage from 1.71 V to 5.5 V can be applied to this pin.
2
3
4
30
31
32
SDO
Serial Data Output. Used to clock data from the input shift register. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This
input operates at clock speeds up to 30 MHz.
Frame Synchronization Input, Active Low. This is the frame synchronization signal for the serial
interface. When SYNC is low, data is transferred on the falling edge of SCLK. The input shift
register data is latched on the rising edge of SYNC.
SCLK
SYNC
5
6
1
2
SDIN
LDAC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Load DAC Input, Active Low. This pin is used to update the DAC register and, consequently, the
output current. If LDAC is tied permanently low, the DAC register is updated on the rising edge
of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output
update is delayed until the falling edge of LDAC. The LDAC pin should not be left unconnected.
7
3
FAULT
DVDD
Fault Alert Output Pin, Active High. This pin is asserted high when a fault is detected. Detectable
faults are loss of SPI interface control, communication error (PEC), loop current out of range,
insufficient loop voltage, and overtemperature. For more information, see the Fault Alerts
section.
3.3 V Digital Power Supply Output. This pin should be decoupled to COM with 100 nF and 4.7 µF
capacitors.
Alarm Current Direction Select. This pin is used to select whether the alarm current is upscale
(22.8 mA/24 mA) or downscale (3.2 mA). Connecting this pin to DVDD selects an upscale alarm
current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA).
For more information, see the Power-On Default section.
8
9
5
6
ALARM_
CURRENT_
DIRECTION
10
7
RINT/REXT
Current Setting Resistor Select. When this pin is connected to DVDD, the internal current setting
resistor is selected. When this pin is connected to COM, the external current setting resistor is
selected. An external resistor can be connected between the REXT1 and REXT2 pins.
11, 12
8, 10
RANGE0,
RANGE1
Digital Input Pins. These two pins select the loop current range (see the Loop Current Range
Selection section).
Rev. F | Page 12 of 36
Data Sheet
AD5421
Pin No.
TSSOP
LFCSP
Mnemonic
Description
13, 14
4, 11, 12
COM
Ground Reference Pin for the AD5421. It is recommended that a 4.7 V Zener diode be placed
between the LOOP− and COM pins. See the Applications Information section for more
information.
15, 16,
17
13, 14, 15
REG_SEL2,
REG_SEL1,
REG_SEL0
These three pins together select the regulator output (REGOUT) voltage (see the Voltage Regulator
section).
18
19
17
18
REFIN
REFOUT2
Reference Voltage Input. VREFIN = 2.5 V for specified performance.
Internal Reference Voltage Output (1.22 V). It is recommended to connect a 100 nF capacitor
from this pin to COM.
20
21
19
20
REFOUT1
CIN
Internal Reference Voltage Output (2.5 V). It is recommended to connect a 100 nF capacitor from
this pin to COM.
External Capacitor Connection and HART FSK Input. An external capacitor connected from CIN to
COM implements an output slew rate control function (see the Loop Current Slew Rate Control
section). HART FSK signaling can also be coupled through a capacitor to this pin (see the HART
Communications section).
22, 23
24
21, 22
23
REXT1, REXT2
LOOP−
Connection for External Current Setting Resistor. A precision 24 kΩ resistor can be connected
between these pins for improved performance.
Loop Current Return Pin. As shown in Figure 1, the COM and LOOP− pins can be used to sense
the loop current across the internal 52 Ω resistor. Note that the voltage measured at LOOP− will
be negative with respect to COM.
25
23
VLOOP
Voltage Input Pin. Voltage input range is 0 V to 2.5 V. The voltage applied to this pin is digitized to
eight bits, which are available in the fault register. This pin can be used for general-purpose
voltage monitoring, but it is intended for monitoring of the loop supply voltage. Connecting the
loop voltage to this pin via a 20:1 resistor divider allows the AD5421 to monitor and feedback
the loop voltage. The AD5421 also generates an alert if the loop voltage is close to the minimum
operating value (see the Loop Voltage Fault section).
26
27
26
27
DRIVE
REGIN
Gate Connection for External Depletion Mode MOSFET. For more information, see the
Connection to Loop Power Supply section.
Voltage Regulator Input. The loop voltage can be connected directly to this pin. Or, to reduce on-
chip power dissipation, an external pass transistor can be connected at this pin to stand off the
loop voltage. For more information, see the Connection to Loop Power Supply section.
28
28
REGOUT
Voltage Regulator Output. Pin selectable values are from 1.8 V to 12 V via the REG_SEL0,
REG_SEL1, and REG_SEL2 pins (see the Voltage Regulator section). If REGOUT is driving a
microconverter supply (see Figure 49), this pin should be decoupled to COM with a >1 μF
capacitor.
N/A1
EPAD
9, 16, 25
EPAD
NC
No Connect. Do not connect to this pin.
Exposed Pad The exposed paddle should be connected to the same potential as the COM pin and to a copper
plane for optimum thermal performance.
1 N/A means not applicable.
Rev. F | Page 13 of 36
AD5421
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
0.015
0.010
0.005
0
EXT V
EXT V
, INT R
SET
REF
, EXT R
REF
SET
INT V
INT V
, INT R
REF
SET
, EXT R
REF
SET
–0.2
V
= 24V
LOOP
EXT NMOS
–0.4
–0.6
–0.8
–1.0
R
T
= 250Ω
LOAD
= 25°C
–0.005
–0.010
V
= 24V
LOOP
4mA TO 20mA RANGE
= 250Ω
A
4mA TO 20mA RANGE
EXT V
EXT R
R
LOAD
EXT NMOS
REF
SET
0
10k
20k
30k
40k
50k
60k
–40
–15
10
35
60
85
DAC CODE
TEMPERATURE (°C)
Figure 6. Integral Nonlinearity Error vs. Code
Figure 9. Offset Error vs. Temperature
1.0
0.8
0.03
0.02
0.6
0.01
0.4
0
0.2
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
0
V
= 24V
LOOP
–0.2
–0.4
–0.6
–0.8
–1.0
4mA TO 20mA RANGE
R
= 250Ω
V
= 24V
LOAD
LOOP
EXT NMOS
EXT NMOS
= 250Ω
R
LOAD
= 25°C
EXT V
EXT V
INT V
, INT R
SET
REF
T
A
, EXT R
REF
SET
4mA TO 20mA RANGE
EXT V
EXT R
, INT R
REF
SET
REF
INT V
, EXT R
REF
SET
SET
0
10k
20k
30k
40k
50k
60k
–40
–15
10
35
60
85
DAC CODE
TEMPERATURE (°C)
Figure 7. Differential Nonlinearity Error vs. Code
Figure 10. Gain Error vs. Temperature
0.01
0
0.0012
0.0010
0.0008
0.0006
0.0004
0.0002
0
R
= 250Ω
LOAD
= 25°C
T
A
4mA TO 20mA RANGE
MAX INL
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
EXT V
EXT V
, INT R
SET
REF
V
= 24V
LOOP
4mA TO 20mA RANGE
, EXT R
REF
SET
INT V
INT V
, INT R
REF
SET
R
= 250Ω
LOAD
V
V
V
V
V
V
EXT, R
EXT, R
EXT, R
INT, R
INT, R
INT, R
EXT, NMOS EXT, 24V
, EXT R
–0.0002
–0.0004
–0.0006
–0.0008
REF
REF
REF
REF
REF
REF
SET
SET
SET
REF
SET
EXT, NMOS INT, 24V
EXT, NMOS INT, 52V
INT, NMOS EXT, 24V
INT, NMOS INT, 24V
INT, NMOS INT, 52V
MIN INL
SET
SET
SET
0
10k
20k
30k
40k
50k
60k
–40
–15
10
35
60
85
DAC CODE
TEMPERATURE (°C)
Figure 8. Total Unadjusted Error vs. Code
Figure 11. Integral Nonlinearity Error vs. Temperature
Rev. F | Page 14 of 36
Data Sheet
AD5421
0.5
0.4
0.0006
0.0004
0.0002
0
MAX INL
0.3
MAX DNL
0.2
V
= 24V
0.1
LOOP
4mA TO 20mA RANGE
= 250Ω
R
0
LOAD
–0.1
–0.2
–0.3
–0.4
–0.5
MIN INL
–0.0002
–0.0004
–0.0006
MIN DNL
R
= 250Ω
LOAD
= 25°C
T
A
3.8mA TO 21mA RANGE
EXT V
REF
EXT R
SET
–40
–15
10
35
60
85
0
10
20
30
40
50
60
TEMPERATURE (°C)
LOOP SUPPLY VOLTAGE (V)
Figure 12. Differential Nonlinearity Error vs. Temperature
Figure 15. Integral Nonlinearity Error vs. Loop Supply Voltage
0.04
0.0029
0.03
0.02
0.0027
0.0025
0.0023
0.0021
0.0019
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
V
= 24V
LOOP
4mA TO 20mA RANGE
= 250Ω
R
LOAD
EXT NMOS
R
= 250Ω
LOAD
= 25°C
EXT V
, INT R
SET
, EXT R
REF
REF
T
A
EXT V
SET
0.0017 3.8mA TO 21mA RANGE
INT V
INT V
, INT R
REF
REF
SET
EXT V
REF
EXT R
, EXT R
SET
SET
0.0015
–40
–15
10
35
60
85
0
10
20
30
40
50
60
TEMPERATURE (°C)
LOOP SUPPLY VOLTAGE (V)
Figure 13. Total Unadjusted Error vs. Temperature
Figure 16. Total Unadjusted Error vs. Loop Supply Voltage
0.04
0.03
0.0024
0.0022
0.0020
0.0018
0.0016
0.0014
0.0012
0.0010
R
= 250Ω
LOAD
= 25°C
T
A
3.8mA TO 21mA RANGE
EXT V
REF
EXT R
0.02
SET
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
V
= 24V
LOOP
4mA TO 20mA RANGE
= 250Ω
R
LOAD
EXT NMOS
EXT V
, INT R
SET
, EXT R
REF
REF
EXT V
SET
INT V
INT V
, INT R
REF
REF
SET
, EXT R
SET
–40
–15
10
35
60
85
0
10
20
30
40
50
60
TEMPERATURE (°C)
LOOP SUPPLY VOLTAGE (V)
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Offset Error vs. Loop Supply Voltage
Rev. F | Page 15 of 36
AD5421
Data Sheet
0.0015
0.0010
0.0005
0
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
R
= 250Ω
R
= 250Ω
LOAD
LOAD
= 25°C
T
3.2mA TO 24mA RANGE
EXT V
A
3.8mA TO 21mA RANGE
REF
EXT V
I
= 24mA
LOOP
REF
EXT R
SET
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
0
10
20
30
40
50
60
–40
–20
0
20
40
60
80
100
LOOP SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 18. Gain Error vs. Loop Supply Voltage
Figure 21. Compliance Voltage Headroom vs. Temperature
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
7
6
5
4
3
2
1
0
V
= 24V
LOOP
EXT NMOS
= 250Ω
R
LOAD
T
= 25°C
= 20mA
A
I
LOOP
R
= 250Ω
LOAD
= 25°C
T
A
0
3.8mA TO 21mA RANGE
EXT V
REF
EXT R
SET
–0.0005
0
10
20
30
40
50
60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOOP SUPPLY VOLTAGE (V)
REG
LOAD CURRENT (mA)
OUT
Figure 19. Full-Scale Error vs. Loop Supply Voltage
Figure 22. Loop Current Error vs. REGOUT Load Current
2000
1750
1500
1250
1000
750
8
T
= 25°C
A
EXT V
REF
= 24mA
6
4
I
LOOP
EXT R
SET
2
0
–2
–4
–6
–8
OPERATING AREA
V
= 24V
LOOP
EXT NMOS
500
EXT V
REF
I
= 4mA
LOOP
250
R
= 250Ω
LOAD
= 25°C
T
A
0
0
10
20
30
40
50
0
1
2
3
4
5
6
7
8
9
10
LOOP SUPPLY VOLTAGE (V)
TIME (Seconds)
Figure 20. Load Resistance Load Line vs. Loop Supply Voltage
(Voltage Between LOOP− and REGIN
Figure 23. Loop Current Noise, 0.1 Hz to 10 Hz Bandwidth
)
Rev. F | Page 16 of 36
Data Sheet
AD5421
1.0
0.244
0.242
0.240
0.238
0.236
0.234
0.232
0.230
0.228
0.226
V
= 24V
I
R
T
= 4mA
1.33mV p-p
= 500Ω 0.2mV rms
IODV = 1.8V
DD
LOOP
EXT NMOS
INT V
LOOP
T
= 25°C
0.8
0.6
LOAD
= 25°C
A
A
REF
DECREASING
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
INCREASING
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.5
1.0
1.5
2.0
TIME (Seconds)
DIGITAL LOGIC VOLTAGE (V)
Figure 24. Loop Current Noise, 500 Hz to 10 kHz Bandwidth
(HART Bandwidth)
Figure 27. IODVDD Current vs. Digital Logic Voltage, Increasing and
Decreasing, IODVDD = 1.8 V
6
0.60
IODV = 3.3V
DD
T
= 25°C
FALLING
5
A
0.55
0.50
0.45
0.40
DECREASING
4
INCREASING
V
= 24V
LOOP
EXT NMOS
= 250Ω
R
3
2
1
0
LOAD
= 25°C
= OPEN CIRCUIT
T
A
C
IN
RISING
–30
–40
–20
–10
0
10
20
30
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
DIGITAL LOGIC VOLTAGE (V)
Figure 25. Full-Scale Loop Current Step
Figure 28. IODVDD Current vs. Digital Logic Voltage, Increasing and
Decreasing, IODVDD = 3.3 V
6
5
4
3
2
1
1.3
IODV = 5V
DD
T
= 25°C
A
FALLING
1.2
1.1
1.0
0.9
0.8
0.7
0.6
DECREASING
V
= 24V
LOOP
EXT NMOS
= 250Ω
INCREASING
R
LOAD
= 25°C
= 22nF
T
A
C
IN
RISING
–0.5
0
–1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
TIME (ms)
DIGITAL LOGIC VOLTAGE (V)
Figure 26. Full-Scale Loop Current Step, CIN = 22 nF
Figure 29. IODVDD Current vs. Digital Logic Voltage, Increasing and
Decreasing, IODVDD = 5 V
Rev. F | Page 17 of 36
AD5421
Data Sheet
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
REG
LOAD CURRENT (mA)
OUT
0.10
0
0.05
0.15
0.20
0.25
0
1.85
V
= 24V
LOOP
EXT NMOS
= 25°C
–50
–100
–150
–200
–5
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
T
A
–10
–15
–20
–25
–30
–35
–40
–45
–50
V
= 24V
LOOP
EXT NMOS
T = 25°C
A
–250
5
0
1
2
3
4
DV
LOAD CURRENT (mA)
DD
1.76
0
2
4
6
8
10
12
REG
LOAD CURRENT (mA)
OUT
Figure 33. DVDD Output Voltage vs. Load Current
Figure 30. REGOUT Voltage vs. Load Current
263.5
4
T
= 25°C
A
263.0
262.5
262.0
261.5
261.0
260.5
260.0
259.5
259.0
258.5
3
2
1
0
–1
–2
–3
–4
V
= 24V
LOOP
EXT NMOS
T
= 25°C
A
0
10
20
30
40
50
60
0
1
2
3
4
5
6
7
8
9
10
LOOP SUPPLY VOLTAGE (V)
TIME (Seconds)
Figure 31. Quiescent Current vs. Loop Supply Voltage
Figure 34. REFOUT1 Voltage Noise, 0.1 Hz to 10 Hz Bandwidth
266
265
264
263
262
261
260
259
258
257
1
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 24V
LOOP
EXT NMOS
V
V
= IODV
= COM
= 25°C
IH
IL
A
DD
0
T
–1
–2
–3
–4
V
= 24V
LOOP
EXT NMOS
T
= 25°C
A
–5
–40
–20
0
20
40
60
80
100
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
REFOUT1 LOAD CURRENT (mA)
Figure 32. Quiescent Current vs. Temperature
Figure 35. REFOUT1 Voltage vs. Load Current
Rev. F | Page 18 of 36
Data Sheet
AD5421
2.5012
250
200
150
100
50
60 DEVICES SHOWN
V
= 24V
LOOP
EXT NMOS
R
2.5010
2.5008
2.5006
2.5004
2.5002
2.5000
2.4998
2.4996
2.4994
= 250Ω
LOAD
= 3.2mA
I
LOOP
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
DIE TEMPERATURE (°C)
Figure 36. REFOUT1 Voltage vs. Temperature, 60 Devices Shown
(C Grade Device)
Figure 38. On-Chip ADC Code vs. Die Temperature
30
250
200
150
100
50
V
= 24V
LOOP
MEAN TC = 1.5ppm/°C
EXT NMOS
T
= 25°C
A
25
20
15
10
5
0
0
0
0.5
1.0
1.5
2.0
2.5
V
PIN INPUT VOLTAGE (V)
LOOP
TEMPERATURE COEFFICIENT (ppm/°C)
Figure 37. REFOUT1 Temperature Coefficient Histogram
(C Grade Device)
Figure 39. On-Chip ADC Code vs. VLOOP Pin Input Voltage
Rev. F | Page 19 of 36
AD5421
Data Sheet
TERMINOLOGY
Total Unadjusted Error
Loop Compliance Voltage Headroom
Total unadjusted error (TUE) is a measure of the total output
error. TUE consists of INL error, offset error, gain error, and
output drift over temperature, in the case of maximum TUE.
TUE is expressed in % FSR.
Loop compliance voltage headroom is the minimum voltage
between the LOOP− and REGIN pins for which the output
current is equal to the programmed value.
Output Temperature Coefficient (TC)
Output TC is a measure of the change in the output current
at 12 mA with changes in temperature and is expressed in
ppm FSR/°C.
Relative Accuracy or Integral Nonlinearity (INL) Error
Relative accuracy, or integral nonlinearity (INL) error, is a
measure of the maximum deviation in the output current from
a straight line passing through the endpoints of the transfer
function. INL error is expressed in % FSR.
Voltage Reference Thermal Hysteresis
Voltage reference thermal hysteresis is the difference in output
voltage measured at +25°C compared to the output voltage
measured at +25°C after cycling the temperature from +25°C to
−40°C to +105°C and back to +25°C. The hysteresis is specified
for the first and second temperature cycles and is expressed in mV.
Differential Nonlinearity (DNL) Error
Differential nonlinearity (DNL) error is the difference between
the measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of
1 LSB maximum ensures monotonicity.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The voltage refer-
ence TC is calculated using the box method, which defines the
TC as the maximum change in the reference output voltage over
a given temperature range. Voltage reference TC is expressed in
ppm/°C as follows:
Offset Error
Offset error is a measure of the output error when zero code is
loaded to the DAC register and is expressed in % FSR.
Offset Error Temperature Coefficient (TC)
Offset error TC is a measure of the change in offset error with
changes in temperature and is expressed in ppm FSR/°C.
VREF_MAX VREF_MIN
Gain Error
6
TC
10
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer function from the ideal
and is expressed in % FSR.
V
REF_NOM Temp_Range
where:
VREF_MAX is the maximum reference output voltage measured
over the total temperature range.
VREF_MIN is the minimum reference output voltage measured
over the total temperature range.
VREF_NOM is the nominal reference output voltage, 2.5 V.
Temp_Range is the specified temperature range
(−40°C to +105°C).
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature and is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register and is expressed in % FSR.
Full-Scale Error Temperature Coefficient (TC)
Full-scale error TC is a measure of the change in full-scale error
with changes in temperature and is expressed in ppm FSR/°C.
Rev. F | Page 20 of 36
Data Sheet
AD5421
THEORY OF OPERATION
The AD5421 is an integrated device designed for use in loop-
powered, 4 mA to 20 mA smart transmitter applications. In a
single chip, the AD5421 provides a 16-bit DAC and current
amplifier for digital control of the loop current, a voltage
regulator to power the entire transmitter, a voltage reference,
fault alert functions, a flexible SPI-compatible serial interface,
gain and offset adjust registers, as well as other features and
functions. The features of the AD5421 are described in the
following sections.
In the case of data readback, if the AD5421 is addressed with a
32-bit frame, it generates the 8-bit frame check sequence and
appends it to the end of the 24-bit data stream to create a 32-bit
data stream.
UPDATE ON SYNC HIGH
SYNC
SCLK
MSB
D23
LSB
D0
FAULT ALERTS
SDIN
24-BIT DATA
The AD5421 provides a number of fault alert features. All
faults are signaled to the controller via the FAULT pin and the
fault register. In the case of a loss of communication between
the AD5421 and the microcontroller (SPI fault), the AD5421
programs the loop current to an alarm value. If the controller
detects that the FAULT pin is set high, it should then read the
fault register to determine the cause of the fault.
24-BIT DATA TRANSFER—NO ERROR CHECKING
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SCLK
SDIN
MSB
D31
LSB
D8
D7
D0
8-BIT FCS
SPI Fault
24-BIT DATA
The SPI fault is asserted if there is no valid communication to
any register of the AD5421 for more than a user-defined period.
The user can program the time period using the SPI watchdog
timeout bits of the control register. The SPI fault bit of the fault
register indicates the fault on the SPI bus. Because this fault is
caused by a loss of communication between the controller and
the AD5421, the loop current is also forced to the alarm value.
FAULT PIN GOES HIGH
IF ERROR CHECK FAILS
FAULT
32-BIT DATA TRANSFER WITH ERROR CHECKING
Figure 40. PEC Timing
Current Loop Fault
The current loop (ILOOP) fault is asserted when the actual loop
current is not within 0.01% FSR of the programmed loop
current. If the measured loop current is less than the programmed
loop current, the ILOOP Under bit of the fault register is set. If the
measured loop current is greater than the programmed loop
current, the ILOOP Over bit of the fault register is set. The FAULT
pin is set to logic high in either case.
The direction of the alarm current (downscale or upscale)
is selected via the ALARM_CURRENT_DIRECTION pin.
Connecting this pin to DVDD selects an upscale alarm current
(22.8 mA/24 mA); connecting this pin to COM selects a
downscale alarm current (3.2 mA).
Packet Error Checking
To verify that data has been received correctly in noisy environ-
ments, the AD5421 offers the option of error checking based on
an 8-bit cyclic redundancy check (CRC). Packet error checking
(PEC) is enabled by writing to the AD5421 with a 32-bit serial
frame, where the least significant eight bits are the frame check
sequence (FCS). The device controlling the AD5421 should
generate the 8-bit FCS using the following polynomial:
An ILOOP Over condition occurs when the value of the load current
sourced from the AD5421 (via REGOUT, REFOUT1, REFOUT2,
or DVDD) is greater than the loop current that is programmed
to flow in the loop. An ILOOP under condition occurs when there
is insufficient compliance voltage to support the programmed
loop current, caused by excessive load resistance or low loop
supply voltage.
C(x) = x8 + x2 + x + 1
Overtemperature Fault
The 8-bit FCS is appended to the end of the data-word, and
There are two overtemperature alert bits in the fault register:
Temp 100°C and Temp 140°C. If the die temperature of the
AD5421 exceeds either 100°C or 140°C, the appropriate bit is
set. If the Temp 140°C bit is set in the fault register, the FAULT
pin is set to logic high.
SYNC
32 data bits are sent to the AD5421 before
is taken high.
If the check is valid, the data is accepted. If the check fails, the
FAULT pin is asserted and the PEC bit of the fault register is set.
After the fault register is read, the PEC bit is reset low and the
FAULT pin returns low.
Rev. F | Page 21 of 36
AD5421
Data Sheet
Loop Voltage Fault
LOOP CURRENT RANGE SELECTION
There are two loop voltage alert bits in the fault register:
To select the loop current range, connect the RANGE0
and RANGE1 pins to the COM and DVDD pins, as shown
in Table 9.
V
LOOP 12V and VLOOP 6V. If the voltage between the VLOOP and
COM pins falls below 0.6 V (corresponding to a 12 V loop
supply value), the VLOOP 12V bit is set; this bit is cleared when
the voltage returns above 0.7 V. Similarly, if the voltage between
the VLOOP and COM pins falls below 0.3 V (corresponding to a
6 V loop supply value), the VLOOP 6V bit is set; this bit is cleared
when the voltage returns above 0.4 V. If the VLOOP 6V bit is set in
the fault register, the FAULT pin is set to logic high.
Table 9. Selecting the Loop Current Range
RANGE1 Pin
RANGE0 Pin
Loop Current Range
COM
COM
4 mA to 20 mA
COM
DVDD
DVDD
DVDD
COM
DVDD
3.8 mA to 21 mA
3.2 mA to 24 mA
3.8 mA to 21 mA
Figure 41 illustrates how a resistor divider enables the monitor-
ing of the loop supply with the VLOOP input. The recommended
resistor divider consists of a 1 MΩ and a 19 MΩ resistor that
provide a 20:1 ratio, allowing the 2.5 V input range of the VLOOP
pin to monitor loop supplies up to 50 V. With a 20:1 divider ratio,
the preset VLOOP 6V and VLOOP 12V alert bits of the fault register
generate loop supply faults according to their stated values. If
another divider ratio is used, the fault bits generate faults at values
that are not equal to 6 V and 12 V.
CONNECTION TO LOOP POWER SUPPLY
The AD5421 is powered from the 4 mA to 20 mA current loop.
Typically, the power supply is located far from the transmitter
device and has a value of 24 V. The AD5421 can be connected
directly to the loop power supply and can tolerate a voltage up
to a maximum of 52 V (see Figure 42).
REG
IN
V
LOOP
AD5421
REG
IN
DRIVE
R
AD5421
V
L
19MΩ
1MΩ
LOOP
LOOP–
COM
V
LOOP
R
L
LOOP–
COM
Figure 42. Direct Connection of the AD5421 to Loop Power Supply
Figure 42 shows how the AD5421 is connected directly to the
loop power supply. An alternative power connection is shown
in Figure 43, which shows a depletion mode N-channel MOSFET
connected between the AD5421 and the loop power supply. The
use of this device keeps the voltage drop across the AD5421 at
approximately 12 V, limiting the worst-case on-chip power dissi-
pation to 288 mW (12 V × 24 mA = 288 mW). If the AD5421 is
connected directly to the loop supply as shown in Figure 42, the
potential worst-case on-chip power dissipation for a 24 V loop
power supply is 576 mW (24 V × 24 mA = 576 mW). The power
dissipation changes in proportion to the loop power supply voltage.
Figure 41. Resistor Divider Connection at VLOOP Pin
EXTERNAL CURRENT SETTING RESISTOR
The 24 kΩ resistor RSET, shown in Figure 1, converts the DAC
output voltage to a current, which is then mirrored with a gain
of 221 to the LOOP− pin. The stability of the loop current over
temperature is dependent on the temperature coefficient of RSET
.
Table 1 and Table 2 outline the performance specifications of
the AD5421 with both the internal RSET resistor and an external,
24 kΩ RSET resistor. Using the internal RSET resistor, a total unad-
justed error of better than 0.126% FSR can be expected. Using
an external resistor gives improved performance of 0.048% FSR.
This specification assumes an ideal resistor; the actual performance
depends on the absolute value and temperature coefficient of
the resistor used. For more information, see the Determining
the Expected Total Error section.
T1
DN2540
BSP129
200kΩ
REG
IN
V
LOOP
AD5421
DRIVE
R
L
LOOP–
COM
Figure 43. MOSFET Connecting the AD5421 to Loop Power Supply
Rev. F | Page 22 of 36
Data Sheet
AD5421
The resistance of the DAC is typically 15.22 kΩ for the 4 mA
ON-CHIP ADC
to 20 mA and 3.8 mA to 21 mA loop current ranges. The DAC
resistance changes to 16.11 kΩ when the 3.2 mA to 24 mA loop
current range is selected.
The AD5421 contains an on-chip ADC used to measure and
feed back to the fault register either the temperature of the die
or the voltage between the VLOOP and COM pins. The select ADC
input bit (Bit D8) of the control register selects the parameter
to be converted. A conversion is initiated with command byte
00001000 (necessary only if auto fault readback is disabled). This
command byte powers on the ADC and performs the conversion.
A read of the fault register returns the conversion result. If auto
readback of the fault register is required, the ADC must first be
powered up by setting the on-chip ADC bit (Bit D7) of the
control register.
The time constant of the circuit is expressed as
τ = RDAC × CSLEW
Taking five time constants as the required time to reach the final
value, CSLEW can be determined for a desired response time, t,
as follows:
t
CSLEW
=
5 × RDAC
Because the FAULT pin can go high for as long as 30 μs, care is
required when performing a die temperature measurement after
a readback of the VLOOP voltage. When switching from a VLOOP
measurement to a die temperature measurement, the FAULT
pin should not be read within 30 μs of switching, as a false
trigger may occur (fault register contents are unaffected).
where:
t is the desired time for the output current to reach its final
value.
R
DAC is the resistance of the DAC core, either 15.22 kΩ or
16.11 kΩ, depending on the selected loop current range.
For a response time of 5 ms,
5ms
VOLTAGE REGULATOR
CSLEW
=
≈ 68 nF
The on-chip voltage regulator provides a regulated voltage out-
put to supply the AD5421 and the remainder of the transmitter
circuitry. The output voltage range is from 1.8 V to 12 V and is
selected by the states of three digital input pins (see Table 10).
The regulator output is accessed at the REGOUT pin.
5 × 15,220
For a response time of 10 ms,
10 ms
CSLEW
=
≈133nF
5 × 15,220
Table 10. Setting the Voltage Regulator Output
Regulated Output
REG_SEL2 REG_SEL1 REG_SEL0 Voltage (V)
The responses for both of these configurations are shown
in Figure 45.
6
C
= 68nF
COM
COM
COM
COM
DVDD
DVDD
DVDD
COM
COM
DVDD
DVDD
COM
COM
DVDD
COM
DVDD
COM
DVDD
COM
DVDD
COM
1.8
2.5
3.0
3.3
5.0
9.0
12.0
SLEW
5
4
3
2
1
0
C
= 267nF
SLEW
= 133nF
C
SLEW
LOOP CURRENT SLEW RATE CONTROL
The rate of change of the loop current can be controlled by
connecting an external capacitor between the CIN pin and
COM. This reduces the rate of change of the loop current.
The output resistance of the DAC (RDAC) together with the
–2
2
6
10
TIME (ms)
14
18
22
C
SLEW capacitor generate a time constant that determines the
Figure 45. 4 mA to 20 mA Step with Slew Rate Control
response of the loop current (see Figure 44).
The CIN pin can also be used as a coupling input for HART
FSK signaling. The HART signal must be ac-coupled to the CIN
input. The capacitor through which the HART signal is coupled
must be considered in the preceding calculations, where the
total capacitance is CSLEW + CHART. For more information, see
the HART Communications section.
R
DAC
V-TO-I
CIRCUITRY
LOOP–
C
IN
C
SLEW
Figure 44. Slew Capacitor Circuit
Rev. F | Page 23 of 36
AD5421
Data Sheet
To achieve a 500 Hz high-pass 3 dB frequency cutoff, the com-
bined values of CHART and CSLEW should be 21 nF. To ensure the
correct HART signal amplitude on the current loop, the final
values for the capacitors are CHART = 4.7 nF and CSLEW = 16.3 nF.
POWER-ON DEFAULT
The AD5421 powers on with all registers loaded with their default
values and with the loop current in the alarm state set to 3.2 mA
or 22.8 mA/24 mA (depending on the state of the ALARM_
CURRENT_DIRECTION pin and the selected range). The
AD5421 remains in this state until it is programmed with new
values. The SPI watchdog timer is enabled by default with a
timeout period of 1 sec. If there is no communication with the
AD5421 within 1 sec of power-on, the FAULT pin is set.
Output Noise During Silence and Analog Rate of Change
The AD5421 has a direct influence on two important specifi-
cations relating to the HART communications protocol: output
noise during silence and analog rate of change. Figure 24 shows
the measurement of the AD5421 output noise in the HART
extended bandwidth; the noise measurement is 0.2 mV rms,
within the required 2.2 mV rms value.
HART COMMUNICATIONS
The AD5421 can be interfaced to a Highway Addressable
Remote Transducer (HART) modem to enable HART digital
communications over the 2-wire loop connection. Figure 46
shows how the modem frequency shift keying (FSK) output is
connected to the AD5421.
To meet the analog rate of change specification, the rate of
change of the 4 mA to 20 mA current must be slow enough so
that it does not interfere with the HART digital signaling. This
is determined by forcing a full-scale loop current change
through a 500 Ω load resistor and applying the resulting voltage
signal to the HART digital filter (HCF_TOOL-31). The peak
amplitude of the signal at the filter output must be less than
150 mV. To achieve this, the rate of change of the loop current
must be restricted to less than approximately 1.3 mA/ms.
200kΩ
REG
IN
V
LOOP
AD5421
The output of the AD5421 naturally slews at approximately
880 mA/ms, a rate that is far too great to comply with the
HART specifications. To reduce the slew rate, a capacitor can be
DRIVE
R
L
LOOP–
COM
C
connected from the C
IN pin to COM, as described in the Loop
IN
Current Slew Rate Control section. To reduce the slew rate
enough so that the HART specification is met, a capacitor value
in the region of 4.7 µF is required, resulting in a full-scale transition
time of 500 ms. Many applications regard this time as too slow,
in which case the slew rate needs to be digitally controlled by
writing a sequence of codes to the DAC register so that the
output response follows the desired curve.
C
C
HART
SLEW
HART
MODEM
HART_OUT
HART_IN
Figure 46. Connecting a HART Modem to the AD5421
Figure 47 shows a digitally controlled full-scale step and the
resulting filter output. In Figure 47, it can be seen that the peak
amplitude of the filter output signal is less than the required
150 mV, and the transition time is approximately 30 ms.
To achieve a 1 mA p-p FSK current signal on the loop, the voltage
at the CIN pin must be 111 mV p-p. Assuming a 500 mV p-p
output from the HART modem, this means that the signal must
be attenuated by a factor of 4.5. The following equation can be
used to calculate the values of the CHART and CSLEW capacitors.
150
100
50
12
10
8
CHART + CSLEW
4.5 =
CHART
From this equation, the ratio of CHART to CSLEW is 1 to 3.5. This
ratio of the capacitor values sets the amplitude of the HART
FSK signal on the loop. The absolute values of the capacitors set
the response time of the loop current, as well as the bandwidth
presented to the HART signal connected at the CIN pin. The
bandwidth must pass frequencies from 500 Hz to 10 kHz. The
two capacitors and the internal impedance, RDAC, form a high-
pass filter. The 3 dB frequency of this high-pass filter should be
less than 500 Hz and can be calculated as follows:
0
6
–50
–100
–150
4
2
0
–50
–30
–10
10
30
50
TIME (ms)
1
Figure 47. Digitally Controlled Full-Scale Step and Resulting HART Digital
Filter Output Signal
f3dB
=
2× π× RDAC
×
CHART + CSLEW
Rev. F | Page 24 of 36
Data Sheet
AD5421
Figure 48 shows the circuit diagram for this measurement. The
47 nF and 168 nF capacitor values for CHART and CSLEW provide
adequate filtering of the digital steps, ensuring that they do not
cause interference.
REG
IN
V
LOOP
AD5421
R
L
LOOP–
C
COM
IN
168nF
47nF
FROM HART MODEM
Figure 48. Circuit Diagram for Figure 47
Rev. F | Page 25 of 36
AD5421
Data Sheet
SERIAL INTERFACE
The AD5421 is controlled by a versatile, 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2
shows the timing diagram. The interface operates with either
a continuous or noncontinuous gated burst clock.
Address/Command Byte
00000011
00000100
00000101
00000110
Function
Write to offset adjust register
Write to gain adjust register
Load DAC
Force alarm current
00000111
Reset (it is recommended to wait
50 µs after a device reset before
writing the next command)
Initiate VLOOP/temperature
measurement
No operation
Read DAC register
Read control register
Read offset adjust register
Read gain adjust register
Read fault register
SYNC
The write sequence begins with a falling edge of the
signal; data is clocked in on the SDIN data line on the falling
SYNC
edge of SCLK. On the rising edge of
, the 24 bits of data
00001000
are latched; the data is transferred to the addressed register and
the programmed function is executed (either a change in DAC
output or mode of operation).
00001001
10000001
10000010
10000011
10000100
10000101
If packet error checking on the SPI interface is required using
cyclic redundancy codes, an additional eight bits must be written
to the AD5421, creating a 32-bit serial interface. In this case,
SYNC
32 bits are written to the AD5421 before
is brought high.
The 16 bits of the data-word written following a load DAC, force
alarm current, reset, initiate VLOOP/temperature measurement,
or no operation command byte are don’t cares (see Table 12 and
Table 13).
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (32 bits wide if CRC error
checking of the data is required). Data is loaded into the device
MSB first as a 24-/32-bit word under the control of a serial clock
input, SCLK. The input shift register consists of an 8-bit address/
command byte, a 16-bit data-word, and an optional 8-bit CRC,
as shown in Table 12 and Table 13.
REGISTER READBACK
To read back a register, Bit D11 of the control register must be set
to Logic 1 to disable the automatic readback of the fault register.
The 16 bits of the data-word written following a read command
are don’t cares (see Table 12 and Table 13).
The address/command byte decoding is described in Table 11.
Table 11. Address/Command Byte Functions
Address/Command Byte
The register data addressed by the read command is clocked out
of SDO on the subsequent write command (see Figure 3).
Function
00000001
00000010
Write to DAC register
Write to control register
Table 12. Input Shift Register
MSB
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Address/command byte
Data-word
Table 13. Input Shift Register with CRC
MSB
LSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Address/command byte
Data-word
CRC
Rev. F | Page 26 of 36
Data Sheet
AD5421
For the 3.8 mA to 21 mA output range, the loop current can be
expressed as follows:
DAC REGISTER
The DAC register is a read/write register and is addressed
as described in Table 11. The data programmed to the DAC
register determines the loop current, as shown in the Ideal
Output Transfer Function section and in Table 15.
17.2 mA
216
ILOOP
=
× D + 3.8mA
For the 3.2 mA to 24 mA output range, the loop current can be
expressed as follows:
Ideal Output Transfer Function
The transfer function describing the relationship between the
data programmed to the DAC register and the loop current is
expressed by the following three equations.
20.8 mA
216
ILOOP
=
× D + 3.2mA
where D is the decimal value of the DAC register.
For the 4 mA to 20 mA output range, the loop current can be
expressed as follows:
16 mA
216
ILOOP
=
× D + 4 mA
Table 14. DAC Register Bit Map
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
16-bit data
Table 15. Relationship of DAC Register Code to Ideal Loop Current (Gain = 65,536; Offset = 0)
Ideal Loop Current (mA)
DAC Register Code
0x0000
0x0001
…
4 mA to 20 mA Range
3.8 mA to 21 mA Range
3.2 mA to 24 mA Range
4
3.8
3.80026
…
3.2
3.2003
…
4.00024
…
0x7FFF
0x8000
…
11.9997
12
…
12.39974
12.4
…
13.5997
13.6
…
0xFFFE
0xFFFF
19.9995
19.9997
20.99947
20.99974
23.9994
23.9997
Rev. F | Page 27 of 36
AD5421
Data Sheet
CONTROL REGISTER
The control register is a read/write register and is addressed as described in Table 11. The data programmed to the control register
determines the mode of operation of the AD5421.
Table 16. Control Register Bit Map
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
Auto fault
watchdog readback
Alarm on Set min Select On-chip Power down
VLOOP
fault
alert
Reserved
SPI watchdog timeout SPI
SPI fault
loop
current
ADC
input
ADC
internal
reference
T0
T1
T2
timer
Table 17. Control Register Bit Descriptions
Control Bits Description
SPI watchdog The T0, T1, and T2 bits allow the user to program the watchdog timeout period. The watchdog timer is reset when a valid
timeout write to any AD5421 register occurs or when a NOP command is written.
T0
0
T1
0
T2
0
Timeout Period
50 ms
0
0
0
1
0
1
1
0
1
0
1
0
100 ms
500 ms
1 sec (default)
2 sec
1
0
1
3 sec
1
1
0
4 sec
1
1
1
5 sec
SPI watchdog 0 = SPI watchdog timer is enabled (default).
timer
1 = SPI watchdog timer is disabled.
Auto fault
readback
This bit specifies whether the fault register contents are automatically clocked out on the SDO pin on each write operation.
(The fault register can always be addressed for readback.)
0 = fault register contents are clocked out on the SDO pin (default).
1 = fault register contents are not clocked out on the SDO pin.
Alarm on SPI
fault
This bit specifies whether the loop current is forced to the alarm value when an SPI fault is detected (that is, the watchdog
timer times out). When an SPI fault is detected, the SPI fault bit of the fault register and the FAULT pin are always set.
0 = loop current is forced to the alarm value when an SPI fault is detected (default).
1 = loop current is not forced to the alarm value when an SPI fault is detected.
Set min loop
current
0 = normal operation (default).
1 = loop current is set to its minimum value so that the total current flowing in the loop consists only of the operating
current of the AD5421 and its associated circuitry.
Select ADC
input
0 = on-chip ADC measures the voltage between the VLOOP and COM pins (default).
1 = on-chip ADC measures the temperature of the AD5421 die.
On-chip ADC
0 = on-chip ADC is disabled (default).
1 = on-chip ADC is enabled.
Power down
internal
reference
0 = internal voltage reference is powered up (default).
1 = internal voltage reference is powered down and an external voltage reference source is required.
VLOOP fault
alert
This bit specifies whether the FAULT pin is set when the voltage between the VLOOP and COM pins falls to approximately 0.3 V.
(The VLOOP 6V bit of the fault register is always set.)
0 = FAULT pin is not set when the VLOOP − COM voltage falls to approximately 0.3 V.
1 = FAULT pin is set when the VLOOP − COM voltage falls to approximately 0.3 V.
Rev. F | Page 28 of 36
Data Sheet
AD5421
FAULT REGISTER
The read-only fault register is addressed as described in Table 11. The bits in the fault register indicate a range of possible fault conditions.
Table 18. Fault Register Bit Map
MSB
D15
SPI
LSB
D0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
PEC
ILOOP
Over
ILOOP
Under
Temp
140°C
Temp
100°C
VLOOP
6V
VLOOP
12V
VLOOP/temperature value
Table 19. Fault Register Bit Descriptions
FAULT
Pin Set
Fault Alert
Description
SPI
Yes
This bit is set high to indicate the loss of the SPI interface signaling. This fault occurs if there is no valid
communication to the AD5421 over the SPI interface for more than the user-defined timeout period. The
occurrence of this fault also forces the loop current to the alarm value if Bit D10 of the control register is at
Logic 0. The alarm current direction is determined by the state of the ALARM_CURRENT_DIRECTION pin.
PEC (packet
error check)
Yes
This bit is set high when an error in the SPI communication is detected using cyclic redundancy check (CRC)
error detection. See the Packet Error Checking section for more information.
ILOOP Over
Yes
Yes
Yes
This bit is set high when the actual loop current is greater than the programmed loop current.
This bit is set high when the actual loop current is less than the programmed loop current.
ILOOP Under
Temp 140°C
This bit is set high to indicate an overtemperature fault. This bit is set if the die temperature of the AD5421
exceeds approximately 140°C. This bit is cleared when the temperature returns below approximately 125°C.
Temp 100°C
VLOOP 6V
No
This bit is set high to indicate an increasing temperature of the AD5421. This bit is set if the die temperature of the
AD5421 exceeds approximately 100°C. This bit is cleared when the temperature returns below approximately 85°C.
Yes
This bit is set high when the voltage between the VLOOP and COM pins falls below approximately 0.3 V (representing
a 6 V loop supply voltage with 20:1 resistor divider connected at VLOOP). This bit is cleared when the voltage returns
above approximately 0.4 V.
VLOOP 12V
No
This bit is set high when the voltage between the VLOOP and COM pins falls below approximately 0.6 V (representing
a 12 V loop supply voltage with 20:1 resistor divider connected at VLOOP). This bit is cleared when the voltage returns
above approximately 0.7 V.
VLOOP/temper- N/A
ature value
These eight bits represent either the voltage between the VLOOP and COM pins or the AD5421 die temperature,
depending on the setting of Bit D8 of the control register (see the On-Chip ADC Transfer Function Equations
section).
8-Bit Value
00000000
…
VLOOP − COM Voltage (V)
Die Temperature (°C)
0
…
2.49
+312
…
−86
11111111
On-Chip ADC Transfer Function Equations
The transfer function equation for the die temperature is
as follows:
The transfer function equation for the measurement of the
voltage between the VLOOP and COM pins is as follows:
Die Temperature = (−1.559 × D) + 312
VLOOP − COM = (2.5/256) × D
where D is the 8-bit digital code returned by the on-chip ADC.
where D is the 8-bit digital code returned by the on-chip ADC.
Rev. F | Page 29 of 36
AD5421
Data Sheet
OFFSET ADJUST REGISTER
The offset adjust register is a read/write register and is addressed as described in Table 11.
Table 20. Offset Adjust Register Bit Map
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit offset adjust data
Table 21. Offset Adjust Register Adjustment Range
Offset Adjust Register Data
Digital Offset Adjustment (LSBs)
65535
65534
…
+32767
+32766
…
32769
+1
32768 (default)
0
32767
−1
…
1
0
…
−32767
−32768
GAIN ADJUST REGISTER
The gain adjust register is a read/write register and is addressed as described in Table 11.
Table 22. Gain Adjust Register Bit Map
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
16-bit gain adjust data
Table 23. Gain Adjust Register Adjustment Range
Gain Adjust Register Data
Digital Gain Adjustment at Full-Scale Output (LSBs)
65535 (default)
0
65534
…
−1
…
32769
32768
32767
…
−32767
−32768
−32769
…
1
0
−65534
−65535
Rev. F | Page 30 of 36
Data Sheet
AD5421
Transfer Function Equations with Offset and Gain Adjust
Values
For the 3.2 mA to 24 mA output range, the loop current can be
expressed as follows:
When the offset adjust and gain adjust register values are taken
into account, the transfer equations can be expressed as follows.
20.8mA
216
× Gain
ILOOP
=
× D
216
For the 4 mA to 20 mA output range, the loop current can be
expressed as follows:
16 mA
216
× Gain
20.8mA
216
+ 3.2mA +
×
(
Offset − 32,768
)
ILOOP
=
× D
216
where:
D is the decimal value of the DAC register.
Gain is the decimal value of the gain adjust register.
Offset is the decimal value of the offset adjust register.
16mA
216
+
4 mA +
×
(
Offset − 32,768
)
Note that the offset adjust register cannot adjust the zero-scale
output value downward.
For the 3.8 mA to 21 mA output range, the loop current can be
expressed as follows:
17.2mA
216
× Gain
ILOOP
=
× D
216
17.2mA
216
+
3.8mA +
×
(
Offset − 32,768
)
Rev. F | Page 31 of 36
AD5421
Data Sheet
APPLICATIONS INFORMATION
Figure 49 shows a typical connection diagram for the AD5421
configured in a HART capable smart transmitter. Such a HART
enabled smart transmitter was developed by Analog Devices as
a reference demo circuit. This circuit, whose block diagram is
shown in Figure 50, was verified and registered as an approved
HART solution by the HART Communication Foundation.
excess of 5 V, a 4.7 V low leakage Zener diode should be placed
between COM and the LOOP− pin, as shown in Figure 49, to
protect the AD5421 from potential damage.
DETERMINING THE EXPECTED TOTAL ERROR
The AD5421 can be set up in a number of different configu-
rations, each of which achieves different levels of accuracy, as
described in Table 1 and Table 2. With the internal voltage
reference and internal RSET enabled, a maximum total error
of 0.157% of full-scale range can be expected for the C grade
device over the temperature range of −40°C to +105°C.
To reduce power dissipation on the chip, a depletion mode
MOSFET (T1), such as a DN2540 or BSP129, can be connected
between the loop voltage and the AD5421, as shown in Figure 49.
If a low loop voltage is used, T1 does not need to be inserted,
and the loop voltage can connect directly to REGIN (see Figure 42).
In Figure 49, all interface signal lines are connected to the micro-
controller. To reduce the number of interface signal lines, the
Other configurations specify an external voltage reference, an
external RSET resistor, or both an external voltage reference and
external RSET resistor. In these configurations, the specifications
assume that the external voltage reference and external RSET
resistor are ideal. Therefore, the errors associated with these
components must be added to the data sheet specifications to
determine the overall performance. The performance depends
on the specifications of these components.
LDAC
signal can be connected to COM, and the SDO and FAULT
lines can be left unconnected. However, this configuration disables
the use of the fault alert features.
Under normal operating conditions, the voltage between COM
and LOOP− does not exceed 1.5 V, and the voltage at LOOP− is
negative with respect to COM. If it is possible that the voltage at
LOOP− may be forced positive with respect to COM, or if the
voltage difference between LOOP− and COM may be forced in
OPTIONAL
EMC FILTER
OPTIONAL
10µF
T1
MOSFET
DN2540
BSP129
4.7µF
0.1µF
200kΩ
IODV
DD
DV
REG
REG
IN
DD
OUT
V
LOOP
RANGE0
RANGE1
DRIVE
19MΩ
1MΩ
R
L
ALARM_CURRENT_DIRECTION
/R
V
LOOP
R
INT EXT
SYNC
SCLK
SDIN
LOOP–
AD5421
V
= 4.7V
Z
SDO
R
EXT1
EXT2
FAULT
LDAC
R1
ADuCM360
R
OPTIONAL
RESISTOR
COM
REFOUT2
C
REFOUT1 REFIN
COM
IN
R1
0.1µF
1µF
470Ω
SETS REGULATOR
VOLTAGE
0.1µF
47nF
168nF
V
CC
AD5700/AD5700-1
TXD
HART_OUT
REF
RXD
RTS
CD
1.2MΩ
1.2MΩ
1µF
300pF
150kΩ
ADC_IP
150pF
AGND DGND
Figure 49. AD5421 Application Diagram for HART Capable Smart Transmitter
Rev. F | Page 32 of 36
Data Sheet
AD5421
3.3V
ADuCM360
ADC 0
AD5421
V
DD
3.3V
REG
IN
+
PRESSURE
SENSOR
SIMULATION
V-REGULATOR
MICRO-
CONTROLLER
V
LOOP
SRAM
FLASH
ADC
DAC
LEXC
CLOCK
TEMPERATURE
SENSOR
SPI
COM
RESET
WATCHDOG
TEMPERATURE
SENSOR
PT100
ADC 1
COM
WATCHDOG
TIMER
50Ω
TEST CONNECTOR
T1: CD
T2: RTS
C
LOOP–
IN
–
T3: COM
T4: TEST
3.3V
V
CC
AD5700
C_HART
HART_OUT
C_SLEW
REF
HART
INPUT
FILTER
HART MODEM
AGND DGND
ADC_IP
Figure 50. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit
Rev. F | Page 33 of 36
AD5421
Data Sheet
To determine the absolute worst-case overall error, the reference
and RSET errors can be directly summed with the specified AD5421
maximum error. For example, when using an external reference
and external RSET resistor, the maximum AD5421 error is 0.048%
of full-scale range. Assuming that the absolute errors for the
voltage reference and RSET resistor are, respectively, 0.04% and
0.05% with temperature coefficients of 3 ppm/°C and 2 ppm/°C,
respectively, the overall worst-case error is as follows:
Excessive junction temperature can occur if the AD5421
experiences elevated voltages across its terminals while
regulating the loop current at a high value. The resulting
junction temperature depends on the ambient temperature.
Table 24 provides the bounds of operation at maximum ambient
temperature and maximum supply voltage. This information is
displayed graphically in Figure 51 and Figure 52. These figures
assume that the exposed paddle is connected to a copper plane
of approximately 6 cm2.
Worst-Case Error =
AD5421 Error + VREF Absolute Error + VREF TC +
4.5
RSET Absolute Error + RSET TC
4.0
Worst-Case Error =
3.5
TSSOP
0.048% + 0.04% + [(3/106) × 100 × 145]% +
0.05% + [(2/106) × 100 × 145]% = 0.21% FSR
3.0
2.5
This is the absolute worst-case value when the AD5421 operates
over the temperature range of −40°C to +105°C. An error of this
value is very unlikely to occur because the temperature coeffi-
cients of the individual components do not exhibit the same
drift polarity, and, therefore, an element of cancelation occurs.
For this reason, the TC values should be added in a root of
squares fashion.
LFCSP
2.0
1.5
1.0
0.5
0
0
20
40
60
80
100
A further improvement can be gained by performing a two-point
calibration at zero scale and full scale, thus reducing the absolute
errors of the voltage reference and RSET resistor to a combined
error of 1 LSB or 0.0015% FSR. After performing this calibration,
the total maximum error becomes
AMBIENT TEMPERATURE (°C)
Figure 51. Maximum Power Dissipation vs. Ambient Temperature
60
TSSOP
50
Total Error =
LFCSP
40
0.048% + 0.0015% + (0.0435%)2 + (0.029%)2 = 0.102%FSR
30
20
10
0
To reduce this error value further, a voltage reference and RSET
resistor with lower TC specifications must be chosen.
THERMAL AND SUPPLY CONSIDERATIONS
The AD5421 is designed to operate at a maximum junction temp-
erature of 125°C. To ensure reliable and specified operation over
the lifetime of the product, it is important that the device not be
operated under conditions that cause the junction temperature
to exceed this value.
40
50
60
70
80
90
100
AMBIENT TEMPERATURE (°C)
Figure 52. Maximum Supply Voltage vs. Ambient Temperature
Table 24. Thermal and Supply Considerations (External MOSFET Not Connected)
Parameter
Description
32-Lead LFCSP
28-Lead TSSOP
Maximum
Power
Dissipation
Maximum permitted power
dissipation when operating at an
ambient temperature of 105°C
TJ MAX −TA
TJ MAX − TA 125 − 105
125 −105
=
= 625mW
=
= 500 mW
θJA
32
θJA
40
Maximum
Ambient
Temperature
Maximum permitted ambient
temperature when operating from a
supply of 52 V while regulating a loop
current of 22.8 mA
TJ MAX − (PD ×θJA )=
125 − ((52 × 0.0228) × 32) = 87°C
TJ MAX − PD ×θJA
=
125 − 52× 0.0228
× 40 = 77°C
Maximum
Supply
Voltage
Maximum permitted supply voltage
when operating at an ambient
temperature of 105°C while regulating
a loop current of 22.8 mA
TJ MAX −TA
TJ MAX − TA
ILOOP × θJA 0.0228 × 32
125 − 105
125 −105
=
= 27 V
=
= 21 V
ILOOP ×θJA 0.0228× 40
Rev. F | Page 34 of 36
Data Sheet
AD5421
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
24
32
1
0.50
BSC
3.65
3.50 SQ
3.45
EXPOSED
PAD
8
9
17
16
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 53. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-11)
Dimensions shown in millimeters
9.80
9.70
9.60
5.55
5.50
5.45
28
1
15
4.50
4.40
4.30
3.05
3.00
2.95
EXPOSED
PAD
(Pins Up)
6.40
SC
B
14
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
1.05
1.00
0.80
0.20
0.09
1.20 MAX
SEATING
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.25
8°
0°
0.75
0.60
0.45
0.15 MAX
0.05 MIN
SECTION OF THIS DATA SHEET.
PLANE
0.65 BSC
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AET
Figure 54. 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-28-2)
Dimensions shown in millimeters
Rev. F | Page 35 of 36
AD5421
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
28-Lead TSSOP_EP
28-Lead TSSOP_EP
28-Lead TSSOP_EP
28-Lead TSSOP_EP
28-Lead TSSOP_EP
28-Lead TSSOP_EP
Evaluation Board
Package Option
AD5421ACPZ-REEL7
AD5421BCPZ-REEL7
AD5421BREZ
AD5421BREZ-REEL
AD5421BREZ-REEL7
AD5421CREZ
AD5421CREZ-RL
AD5421CREZ-RL7
EVAL-AD5421SDZ
CP-32-11
CP-32-11
RE-28-2
RE-28-2
RE-28-2
RE-28-2
RE-28-2
RE-28-2
1 Z = RoHS Compliant Part.
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09128-0-1/13(E)
Rev. F | Page 36 of 36
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