AD5425YRM-REEL7 [ADI]
8-Bit, High Bandwidth Multiplying DAC with Serial Interface; 8位，高带宽，乘法DAC，串行接口
| 型号： | AD5425YRM-REEL7 |
| 厂家： | 
ADI |
| 描述： | 8-Bit, High Bandwidth Multiplying DAC with Serial Interface |
| 文件： | 总20页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, High Bandwidth
Multiplying DAC with Serial Interface
AD5425*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2.5 V to 5.5 V Supply Operation
50 MHz Serial Interface
8-Bit (Byte Load) Serial Interface, 6 MHz Update Rate
10 MHz Multiplying Bandwidth
؎10 V Reference Input
V
V
REF
DD
R
FB
R
I
1
2
OUT
8-BIT
AD5425
R-2R DAC
I
OUT
Low Glitch Energy < 2 nV-s
Extended Temperature Range –40؇C to +125؇C
10-Lead MSOP Package
Guaranteed Monotonic
4-Quadrant Multiplication
LDAC
DAC REGISTER
POWER-ON
RESET
INPUT LATCH
Power On Reset with Brownout Detection
LDAC Function
0.4 A Typical Power Consumption
SYNC
SCLK
SDIN
CONTROL LOGIC AND
INPUT SHIFT REGISTER
APPLICATIONS
GND
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming
GENERAL DESCRIPTION
As a result of processing on a CMOS submicron process, this
DAC offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of 10 MHz.
The AD5425 is a CMOS 8-bit current output digital-to-analog
converter that operates from a 2.5 V to 5.5 V power supply,
making it suited to battery-powered applications and many
other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
This DAC utilizes a double buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, an LDAC pin is provided,
which allows simultaneous update in a multi-DAC configuration.
On power-up, the internal shift register and latches are filled
with 0s and the DAC outputs are at 0 V.
The AD5425 DAC is available in a small 10-lead MSOP package.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
(VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUTx = O V. All specifications TMIN to TMAX, unless
AD5425–SPECIFICATIONS1 otherwise noted. DC performance measured with OP177, AC performance with
AD8038, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
Resolution
8
Bits
Relative Accuracy
0.25
0.5
10
LSB
LSB
mV
ppm FSR/°C
nA
nA
Differential Nonlinearity
Gain Error
Guaranteed monotonic
Gain Error Temperature Coefficient2
Output Leakage Current
5
5
25
Data = 0x0000, TA = 25°C, IOUT
Data = 0x0000, IOUT
REFERENCE INPUT2
Reference Input Range
VREF Input Resistance
10
10
10
V
kΩ
kΩ
8
8
12
12
Input resistance TC = –50 ppm/°C
Input resistance TC = –50 ppm/°C
R
FB Resistance
Input Capacitance
Code Zero Scale
Code Full Scale
3
5
6
8
pF
pF
DIGITAL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
1.7
V
V
A
pF
0.6
2
10
4
DYNAMIC PERFORMANCE2
Reference Multiplying Bandwidth
Output Voltage Settling Time
10
50
MHz
ns
VREF = 3.5 V; DAC loaded all 1s
Measured to 16 mV. RLOAD = 100 Ω, CLOAD =
15 pF DAC latch alternately loaded with 0s and 1s
100
Digital Delay
40
15
2
70
48
75
30
ns
ns
nV-s
dB
dB
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Rise and Fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry VREF = 0 V
DAC latch loaded with all 0s. VREF
10 MHz
= 3.5 V, 1 MHz
Output Capacitance
IOUT
2
22
10
12
25
0.1
25
12
17
30
pF
pF
pF
pF
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with SYNC high and
alternate loading of all 0s and all 1s
IOUT
1
Digital Feedthrough
nV-s
Total Harmonic Distortion
Digital THD Clock = 1 MHz
50 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
Clock = 2 MHz
–81
dB
VREF = 3.5 V pk-pk; all 1s loaded, f = 1 kHz
70
25
dB
nV√Hz
8k Codes
@ 1 kHz
8k Codes, VREF = 3.5 V
50 kHz fOUT
20 kHz fOUT
55
63
dB
dB
SFDR Performance (Narrow Band)
Clock = 2 MHz
50 kHz fOUT
20 kHz fOUT
73
80
dB
dB
Intermodulation Distortion
Clock = 2 MHz
8k codes, VREF = 3.5 V
f1 = 20 kHz, f2 = 25 kHz
79
dB
–2–
REV. 0
AD5425
Parameter
Min
Typ
Max
Unit
Conditions
POWER REQUIREMENTS
Power Supply Range
IDD
2.5
5.5
5
0.6
V
A
A
0.4
Logic inputs = 0 V or VDD
TA = 25°C, Logic inputs = 0 V or VDD
NOTES
1Temperature range is as follows: Y version: –40°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
AD5425
(VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless
otherwise noted.)
TIMING CHARACTERISTICS1, 2
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
50
20
8
8
13
5
3
5
30
0
12
10
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
t9
t10
t11
SCLK falling edge to LDAC rising edge
NOTES
1See Figure 1. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
2All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
t6
t5
DIN
DB0
DB7
t10
t9
1
LDAC
LDAC
t11
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
Figure 1. Timing Diagram
–4–
REV. 0
AD5425
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VREF, RFB to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V
IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Logic Inputs and Output2 . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Industrial (Y Version) . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
10-lead MSOP JA Thermal Impedance . . . . . . . . . . . 206°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2 OvervoltagesatSCLK, SYNC, DIN, andLDAC willbeclampedbyinternaldiodes.
ORDERING GUIDE
Resolution
(Bits)
INL
(LSBs)
Temperature
Range
Package
Description
Package
Option
Model
Branding
AD5425YRM
8
8
8
0.25
0.25
0.25
–40oC to +125oC
–40oC to +125oC
–40oC to +125oC
MSOP
MSOP
MSOP
Evaluation Kit
D1P
D1P
D1P
RM-10
RM-10
RM-10
AD5425YRM-REEL
AD5425YRM-REEL7
EVAL-AD5425EB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5425 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD5425
PIN CONFIGURATION
10
9
I
1
2
1
2
3
4
5
R
FB
OUT
I
V
REF
OUT
AD5425
GND
8
V
DD
(Not to Scale)
SCLK
SDIN
7
LDAC
SYNC
6
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1
2
3
4
I
OUT1
DAC Current Output.
IOUT
2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Digital Ground Pin.
GND
SCLK
Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input.
This device can accommodate clock rates of up to 50 MHz.
5
6
SDIN
Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input.
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on
each falling edge of the following 8 clocks.
7
LDAC
Load DAC Input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively,
if this line is held permanently low, an automatic update mode is selected whereby the DAC is updated
after 8 SCLK falling edges with SYNC low.
8
9
VDD
VREF
RFB
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
10
DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output.
–6–
REV. 0
Typical Performance Characteristics–AD5425
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
1.6
T
V
V
= 25؇C
T
V
V
= 25؇C
A
A
= 10V
= 5V
= 10V
= 5V
REF
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
REF
DD
I
1 V 5V
OUT DD
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
I
1 V 3V
DD
OUT
–40 –20
0
20 40 60 80 100 120
TEMPERATURE ( C)
0
50
100
CODE
150
200
250
250
0
200
50
150
CODE
100
؇
TPC 1. INL vs. Code (8-Bit DAC)
TPC 3. IOUT1 Leakage Current
vs. Temperature
TPC 2. DNL vs. Code (8-Bit DAC)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.5
5
4
T
V
V
= 25؇C
A
= 3V
DD
GAIN ERROR
= 0V
REF
0.3
0.1
3
2
V
= 5V
DD
MAX INL
T
= 25؇C
A
MAX DNL
V
= 3V
= 0V
REF
DD
V
1
0
OFFSET ERROR
–0.1
–0.3
–0.5
–1
–2
–3
–4
–5
V
= 2.5V
DD
MIN DNL
MIN INL
–0.2
V
= 10V
REF
–0.4
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
(V)
0.5
1.0
1.5
–60 –40 –20
0
20 40 60 80 100 120 140
TEMPERATURE (؇C)
V
V
(V)
BIAS
BIAS
TPC 4. Gain Error vs. Temperature
TPC 5. Linearity vs. VBIAS
Voltage Applied to IOUT
TPC 6. Gain and Offset Errors vs.
2
VBIAS Voltage Applied to IOUT
2
10.0
0.5
2.5
2.0
1.5
1.0
0.5
0
T
= 25؇C
A
V
V
= 5V
V
V
= 5V
= 0V
DD
DD
V
= 5V
DD
8.0
6.0
4.0
2.0
0
= 0V
REF
V
= 2.5V
REF
REF
0.3
0.1
GAIN ERROR
MAX DNL
MAX INL
OFFSET ERROR
–0.1
–0.3
–0.5
OFFSET ERROR
MIN INL
MIN DNL
–2.0
–4.0
GAIN ERROR
0
0.5
1.0
V
1.5
(V)
2.0
2.5
–0.5
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
BIAS
V
(V)
V
(V)
BIAS
BIAS
TPC 7. Linearity vs. VBIAS
Voltage Applied to IOUT
TPC 8. Gain and Offset Errors
vs. Voltage Applied to IOUT
TPC 9. Gain and Offset Errors vs.
VBIAS Voltage Applied to IOUT
2
2
2
REV. 0
–7–
AD5425
1.0
0.8
0.6
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
V
V
= 25؇C
T
= 25؇C
A
A
= 5V
DD
= 2.5V
REF
V
IH
MIN INL BIAS
0.4
0.2
MAX INL BIAS
V
= 5V
DD
V
IL
0
–0.2
–0.4
–0.6
–0.8
–1.0
T
= 25؇C
A
MAX DNL BIAS
MIN DNL BIAS
V
= 2.5V
DD
V
= 3V
DD
0
1
2
3
4
5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
0.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
VOLTAGE (V)
V
(V)
BIAS
TPC 10. Linearity vs. VBIAS
Voltage Applied to IOUT
TPC 11. Supply Current vs.
Input Voltage
TPC 12. Threshold Voltages
vs. Supply Voltage
2
0.2
0
6
0
–6
0.060
0.050
0.040
0.030
0.020
0.010
0.000
–0.010
–0.020
T
= 25؇C
ALL ON
DB11
DB10
DB9
A
VDD 5V, 0V REF
NRG = 2.049nVs
T
V
= 25؇C
A
LOADING
ZS TO FS
= 0V
REF
7FFH TO 800H
AD8038 AMP
= 1.8pF
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
C
COMP
AD5443
DB8
DB7
DB6
VDD 3V, 0V REF
NRG = 0.088nVs
800H TO 7FFH
–0.2
–0.4
–0.6
–0.8
DB5
DB4
DB3
DB2
DB1
DB0
VDD 3V, 0V REF
NRG = 1.877nVs
7FFH TO 800H
T
V
V
C
= 25؇C
A
T
V
= 25؇C
= 5V
A
DD
= 5V
DD
= ؎3.5V
REF
V
= ؎3.5V
INPUT
= 1.8pF
VDD 5V, 0V REF
NRG = 0.119nVs,
800H TO 7FFH
REF
= 1.8pF
COMP
ALL OFF
C
AD5445 AMPLIFIER
COMP
AD5445 AMPLIFIER
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0
50
100
150
200
250
300
TIME (ns)
TPC 13. Reference Multiplying
Bandwidth—All 1s Loaded
TPC 15. Reference Multiply-
ing Bandwidth vs. Frequency
and Code
TPC 14. Midscale Transition,
VREF = 3.5 V
–60
–65
–70
–75
–80
–85
–90
3
20
0
T
V
V
= 25؇C
T
V
= 25؇C
A
T
V
= 25؇C
A
A
= 3V
= 5V
DD
= 3V
DD
DD
= 3.5V p-p
AD8038 AMPLIFIER
REF
AMP = AD8038
0
–3
–6
–9
–20
–40
–60
–80
–100
–120
FULL SCALE
ZERO SCALE
V
V
V
V
V
=
=
=
=
=
؎
؎
؎
؎
؎
2V, AD8038 C 1.47pF
C
2V, AD8038 C 1pF
0.15V, AD8038 C 1pF
0.15V, AD8038 C 1.47pF
REF
REF
REF
REF
REF
C
C
C
3.51V, AD8038 C 1.8pF
C
1
10
100
1k
10k 100k
1M
10k
100k
1M
10M
100M
1
10
100
1k
10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 16. Reference Multiply-
ing Bandwidth vs. Frequency
and Compensation Capacitor
TPC 17. THD and Noise vs.
Frequency
TPC 18. Power Supply Rejec-
tion vs. Frequency
–8–
REV. 0
AD5425
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
T
V
V
= 25؇C
T = 25؇C
A
A
T
V
V
= 25؇C
A
= 5V
DD
V = 5V
DD
= 5V
DD
= 3.5V
REF
= 3.5V
V
= 3.5V
REF
REF
AD8038 AMPLIFIER
AD8038 AMPLIFIER
= 1.8pF
C
= 1.8pF
AD8038 AMPLIFIER
= 1.8pF
COMP
C
COMP
8k CODES
C
COMP
8k CODES
8k CODES
0
200k
400k
600k
800k
1M
0
200k
400k
600k
800k
1M
10k 12k 14k 16k 18k 20k 22k 24k 26k 28k 30k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 19. Wideband SFDR,
Clock = 2 MHz, fOUT = 50 kHz
TPC 20. Wideband SFDR,
Clock = 2 MHz, fOUT = 20 kHz
TPC 21. Narrowband SFDR,
Clock = 2 MHz, fOUT = 20 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
V
= 25؇C
T
V
V
= 25؇C
A
A
= 5V
= 5V
DD
DD
= 3.5V
= 3.5V
REF
REF
AD8038
AD8038 AMPLIFIER
= 1.8pF
AMPLIFIER
C
COMP
C
= 1.8pF
COMP
8k CODES
8k CODES
25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75k
10k
15k
20k
25k
30k
35k
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 22. Narrowband SFDR,
Clock = 2 MHz, fOUT = 50 kHz
TPC 23. Narrowband IMD
(؎50%) Clock = 2 MHz,
fOUT1 = 20 kHz, fOUT2 = 25 kHz
REV. 0
–9–
AD5425
TERMINOLOGY
Relative Accuracy
depending upon whether the glitch is measured as a current or
voltage signal.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjusting
for zero and full scale and is normally expressed in LSBs or as a
percentage of full-scale reading.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Differential Nonlinearity
Multiplying Feedthrough Error
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
Gain Error
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower order harmonices are included,
such as second to fifth.
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF – 1 LSB. Gain error of
the DACs is adjustable to 0 with external resistance.
V22 +V32 +V4 +V52
2
Output Leakage Current
(
)
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it
can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
THD = 20log
V
1
Spurious-Free Dynamic Range (SFDR)
It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate,
or fs/2). Narrow band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is digitally generated sine wave.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground. The settling time
specification includes the digital delay from SYNC rising edge
of the full scale output charge.
Digital-to-Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
–10–
REV. 0
AD5425
DAC SECTION
Low Power Serial Interface
The AD5425 is an 8-bit current output DAC consisting of a
standard inverting R-2R ladder configuration. A simplified
diagram is shown in Figure 2. The feedback resistor RFB has a
value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at the same
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
at VREF is always constant and nominally of value R. The DAC
output (IOUT) is code-dependent, producing various resistances
and capacitances. External amplifier choice should take into
account the variation in impedance generated by the DAC on
the amplifiers inverting input node.
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and SDIN input buffers
are powered down on the rising edge of SYNC.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this device can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing as shown in Figure 4.
When an output amplifier is connected in unipolar mode, the
output voltage is given by:
D
R
R
R
VOUT = –VREF
×
V
REF
2n
2R
S1
2R
S2
2R
S3
2R
S8
2R
R
where D is the fractional representation of the digital word loaded
to the DAC, in this case 0 to 255, and n is the number of bits.
R
A
FB
I
1
OUT
I
2
OUT
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
DAC DATA LATCHES
AND DRIVERS
This DAC is designed to operate with either negative or positive
reference voltages. The VDD power pin is used by only the internal
digital logic to drive the DAC switches’ on and off states.
Figure 2. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it to
be configured in several different operating modes, for example,
to provide a unipolar output, bipolar output, or in single-supply
modes of operation in unipolar mode or 4-quadrant multiplication
in bipolar mode. Note that a matching switch is used in series
with the internal RFB feedback resistor. If users attempt to mea-
sure RFB, power must be applied to VDD to achieve continuity.
This DAC is also designed to accommodate ac reference input
signals in the range of –10 V to +10 V.
V
DD
R2
C1
V
R
DD
FB
I
1
OUT
V
A1
REF
V
REF
AD5425
SERIAL INTERFACE
I
2
R1
OUT
V
=
OUT
0 TO –V
The AD5425 has a simple 3-wire interface which is compatible
with SPI/QSPI/MICROWIRE and DSP interface standards. Data
is written to the device in 8 bit words. This 8-bit word consists
of 8 data bits as shown in Figure 3.
REF
SCLK SDIN GND
SYNC
AGND
MICROCONTROLLER
NOTES
DB7 (MSB)
DB0 (LSB)
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DATA BITS
Figure 4. Unipolar Operation
Figure 3. 8-Bit Input Shift Register Contents
With a fixed 10 V reference, the circuit shown in Figure 4 will
give an unipolar 0 V to –10 V output voltage swing. When VIN
is an ac signal, the circuit performs 2-quadrant multiplication.
SYNC is an edge-triggered input that acts as a frame synchroni-
zation signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling to SCLK falling edge setup time, t4.
Table I shows the relationship between digital code and the
expected output voltage for unipolar operation.
After loading eight data bits to the shift register, the SYNC line is
brought high. The contents of the DAC register and the output
will be updated by bringing LDAC low any time after the 8-bit
data transfer is complete as seen in the timing diagram of Figure 1.
LDAC may be tied permanently low if required. For another
serial transfer to take place, the interface must be enabled by
another falling edge of SYNC.
Table I. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
–VREF (255/256)
–VREF (128/256) = –VREF/2
–VREF (1/256)
–VREF (0/256) = 0
REV. 0
–11–
AD5425
R3
10k⍀
R2
V
DD
R5
20k⍀
R
C1
V
FB
DD
R4
R1
10k⍀
I
1
2
OUT
V
؎10V
REF
V
AD5425
A1
REF
I
OUT
A2
V
–V
OUT =
SCLK SDIN GND
SYNC
to +V
REF
REF
AGND
MICROCONTROLLER
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0 V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
Bipolar Operation
value of C1 can produce ringing at the output, while too large a
value can adversely affect the settling time. C1 should be found
empirically but 1 pF–2 pF is generally adequate for compensation.
In some applications, it may be necessary to generate full 4-quadrant
multiplying operation or a bipolar output swing. This can be
easily accomplished by using another external amplifier and some
external resistors as shown in Figure 5. In this circuit, the second
amplifier A2 provides a gain of 2. Biasing the external amplifier
with an offset from the reference voltage results in full 4-quadrant
multiplying operation. The transfer function of this circuit shows
that both negative and positive output voltages are created as the
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
Figure 6 shows a typical circuit for operation with a single 2.5 V
to 5 V supply. In the current mode circuit of Figure 6, IOUT
and hence IOUT1 is biased positive by an amount applied to
2
input data (D) is incremented from code zero (VOUT = –VREF
to midscale (VOUT = 0 V ) to full scale (VOUT = + VREF).
)
V
BIAS. In this configuration, the output voltage is given by
VOUT = D × RFB /RDAC × VBIAS – VIN +V
(
)
(
)
}
{
BIAS
VOUT = VREF × D / 2n−1 –VREF
(
)
As D varies from 0 to 255, the output voltage varies from
Where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
VOUT =VBIAS toVOUT = 2VBIAS –VIN
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
V
DD
C1
Table II shows the relationship between digital code and the
expected output voltage for bipolar operation.
V
R
DD
FB
I
1
OUT
V
V
REF
IN
A1
I
2
V
OUT
OUT
Table II. Bipolar Code Table
GND
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
+VREF (127/128)
0
–VREF (127/128)
–VREF (128/128)
V
BIAS
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
Stability
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be employed. Since every
code change corresponds to a step function, gain peaking may
occur if the op amp has limited GBP and there is excessive para-
sitic capacitance at the inverting node. This parasitic capacitance
introduces a pole into the open-loop response, which can cause
ringing or instability in closed-loop applications.
Figure 6. Single-Supply Current Mode Operation
VBIAS should be a low impedance source capable of sinking and
sourcing all possible variations in current at the IOUT2 terminal
without any problems.
It is important to note that VIN is limited to low voltages because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result their on resistance differs and this
degrades the linearity of the DAC.
An optional compensation capacitor, C1 can be added in parallel
with RFB for stability as shown in Figures 6 and 7. Too small a
–12–
REV. 0
AD5425
Voltage Switching Mode of Operation
ADDING GAIN
Figure 7 shows this DAC operating in the voltage switching
mode. The reference voltage, VIN is applied to the IOUT1 pin,
IOUT2 is connected to AGND and the output voltage is available
at the VREF terminal. In this configuration, a positive reference
voltage results in a positive output voltage making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance), thus an op amp
is necessary to buffer the output voltage. The reference input no
longer sees a constant input impedance, but one that varies with
code. So, the voltage input should be driven from a low imped-
ance source.
In applications where the output voltage is required to be greater
than VIN, gain can be added with an additional external amplifier
or it can also be achieved in a single stage. It is important to
take into consideration the effect of temperature coefficients of
the thin film resistors of the DAC. Simply placing a resistor in
series with the RFB resistor will causing mismatches in the
temperature coefficients resulting in larger gain temperature
coefficient errors. Instead, the circuit of Figure 9 is a recom-
mended method of increasing the gain of the circuit. R1, R2,
and R3 should all have similar temperature coefficients, but
they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains of
greater than 1 are required.
V
DD
R1
R2
V
DD
R
V
FB
DD
V
I
1
A1
IN
V
OUT
OUT
C1
V
REF
R
V
FB
DD
I
2
OUT
R2
I
1
OUT
GND
V
V
V
OUT
A1
IN
REF
I
2
OUT
R
3
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
GND
GAIN = R2 + R3
R2
R
2
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
R1 = R2R3
R2 + R3
Figure 7. Single-Supply Voltage Switching Mode Operation
It is important to note that VIN is limited to low voltage because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC.
Figure 9. Increasing Gain of Current Output DAC
USED AS A DIVIDER OR PROGRAMMABLE GAIN
ELEMENT
Also, VIN must not go negative by more than 0.3 V or an inter-
nal diode will turn on, exceeding the max ratings of the device.
In this type of application, the full range of multiplying capabil-
ity of the DAC is lost.
Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as the
feedback element of an op amp and RFB is used as the input resistor
as shown in Figure 10, then the output voltage is inversely pro-
portional to the digital input fraction D. For D = 1 – 2n the output
voltage is
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting amplifier
because of the resistor tolerance errors. To generate a negative
reference, the reference can be level shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and –2.5 V respectively, as shown in Figure 8.
VOUT = –VIN /D = –VIN / 1– 2–n
(
)
V
DD
V
IN
R
V
DD
FB
I
1
OUT
V
REF
I
2
OUT
V
= 5V
DD
GND
ADR03
V
V
IN
OUT
GND
C1
+5V
R
V
FB
DD
V
A1
OUT
–2.5V
I
1
OUT
V
A2
A1
REF
I
2
V
=
OUT
OUT
0 TO +2.5V
1/2 AD8552
–5V
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
GND
1/2 AD8552
Figure 10. Current Steering DAC Used as a Divider
or Programmable Gain Element
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the ampli-
fier does not saturate and also that the required accuracy is met.
For example, an eight bit DAC driven with the binary code 0x/0
(00010000), i.e., 16 decimal, in the circuit of Figure 10 should
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 8. Positive Voltage Output with Minimum
of Components
REV. 0
–13–
AD5425
cause the output voltage to be 16ϫ VIN. However, if the DAC
has a linearity specification of Ϯ 0.5 LSB, then D can in fact
have the weight anywhere in the range 15.5/256 to 16.5/256 so
that the possible output voltage will be in the range 15.5 VIN to
16.5 VIN—an error of +3% even though the DAC itself has a
maximum error of 0.2%.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the vari-
able gain (due to the code dependent output resistance of the DAC)
of the circuit. A change in this noise gain between two adjacent
digital fractions produces a step change in the output voltage
due to the amplifier’s input offset voltage. This output voltage
change is superimposed on the desired change in output between
the two codes and gives rise to a differential linearity error, which
if large enough, could cause the DAC to be nonmonotonic. In
general, the input offset voltage should be a fraction (~<1/4) of
an LSB to ensure monotonic behavior when stepping through
codes.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an oppo-
site current supplied from the op amp through the DAC. Since
only a fraction D of the current into the VREF terminal is routed
to the IOUT1 terminal, the output voltage has to change as follows:
Output ErrorVoltage Due to DAC Leakage = Leakage × R /D
(
)
where R is the DAC resistance at the VREF terminal. For a DAC
leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of
16 the error voltage is 1.6 mV.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor RFB. Most op amps have input bias currents
low enough to prevent any significant errors.
REFERENCE SELECTION
When selecting a reference for use with the AD5425 series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coeffi-
cient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specifi-
cation to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature should be
less than 78 ppm/°C. A 12-bit system with the same temperature
range to overall specification within 2 LSB requires a maximum
drift of 10 ppm/°C. By choosing a precision reference with low
output temperature coefficient, this error source can be mini-
mized. Table III suggests some of the suitable references available
from Analog Devices that are suitable for use with this range of
current output DACs.
Common-mode rejection of the op amp is important in voltage
switching circuits, since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-bit resolution.
Provided the DAC switches are driven from true wideband low
impedance sources (VIN and AGND), they settle quickly. Con-
sequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, it is important to
minimize capacitance at the VREF node (voltage output node in
this application) of the DAC. This is done by using low inputs
capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. There is a large range of single-supply
amplifiers available from Analog Devices.
Table III. Suitable ADI Precision Voltage References Recommended for Use with AD5425 DACs
Part No.
Output Voltage
Initial Tolerance
Temperature Drift
0.1 Hz to 10 Hz Noise Package
ADR01
ADR02
ADR03
ADR425
10 V
5 V
2.5 V
5 V
0.1%
0.1%
0.2%
0.04%
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
20 V p-p
10 V p-p
10 V p-p
3.4 V p-p
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table IV. Some Precision ADI Op Amps Suitable for Use with AD5425 DACs
Part No.
Max Supply Voltage (V)
VOS(max) (V)
IB(max) (nA)
GBP (MHz)
Slew Rate (V/s)
OP97
OP1177
AD8551
20
18
+6
25
60
5
0.1
2
0.05
0.9
1.3
1.5
0.2
0.7
0.4
Table V. Some High Speed ADI Op Amps Suitable for Use with AD5425 DACs
Max Supply Voltage
(V)
BW @ ACL
(MHz)
Slew Rate
(V/s)
VOS(max)
(V)
IB(max)
(nA)
Part No.
AD8065
AD8021
AD8038
AD9631
12
12
5
145
200
350
320
180
100
425
1300
1500
1000
3000
10000
0.01
1000
0.75
7000
5
–14–
REV. 0
AD5425
MICROPROCESSOR INTERFACING
ITFS = 1, Internal Framing Signal
SLEN = 0111, 8-Bit Data-Word
80C51/80L51 to AD5425 Interface
A serial interface between the DAC and the 8051 is shown in
Figure 13. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, DIN. P3.3 is a
bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data in 8-bit bytes
which is perfect for the AD5425 as it only requires an 8-bit
word. Data on RxD is clocked out of the microcontroller on
the rising edge of TxD and is valid on the falling edge. As
Microprocessor interfacing to this DAC is via a serial bus that
uses standard protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. An LDAC pin is also included. The AD5425 requires
an 8-bit word with the default being data valid on the falling
edge of SCLK, but this is changeable via the control bits in the
data-word.
ADSP-21xx to AD5425 Interface
The ADSP-21xx family of DSPs are easily interfaced to this family
of DACs without extra glue logic. Figure 11 shows an example
of an SPI interface between the DAC and the ADSP-2191.
SCK of the DSP drives the serial data line, DIN. SYNC is
driven from one of the port lines, in this case SPIxSEL.
a
result, no glue logic is required between the DAC and
microcontroller interface. P3.3 is taken high following the
completion of this cycle. The 8051 provides the LSB of its
SBUF register as the first bit in the data stream. The DAC
input register requires its data with the MSB as the first bit
received. The transmit routine should take this into account.
ADSP-2191*
AD5425*
SPIxSEL
SYNC
SDIN
SCLK
MOSI
SCK
8051*
AD5425*
TxD
RxD
P1.1
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. ADSP-2191 SPI to AD5425 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
A serial interface between the DAC and DSP SPORT is shown
in Figure 12. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSPs serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
Figure 13. 80C51/80L51 to AD5425 Interface
MC68HC11 Interface to AD5425 Interface
Figure 14 shows an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master mode
(MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase
bit (CPHA) = 1. The SPI is configured by writing to the SPI
control register (SPCR)—see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface, the
MOSI output drives the serial data line (DIN) of the AD5516. The
SYNC signal is derived from a port line (PC7). When data is being
transmitted to the AD5516, the SYNC line is taken low (PC7).
Data appearing on the MOSI output is valid on the falling edge of
SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes
with only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. PC7 is taken high at the end of
the write.
ADSP-2101/
AD5425*
ADSP-2103/
ADSP-2191*
TFS
DT
SYNC
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. ADSP-2101/ADSP-2103/ADSP-2191 SPORT
to AD5425 Interface
MC68HC11*
AD5425*
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
sync delay and frame sync setup and hold, data delay and data
setup and hold, and SCLK width. The DAC interface expects a
t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns
minimum. Consult the ADSP-21xx User Manual for information
on clock and frame sync frequencies for the SPORT register.
PC7
SCK
SYNC
SCLK
SDIN
MOSI
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. 68HC11/68L11 to AD5425 Interface
The SPORT Control Register should be set up as follows:
TFSW = 1, Alternate Framing
MICROWIRE to AD5425 Interface
Figure 15 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the DAC
input shift register on the rising edge of SK, which corresponds
to the falling edge of the DAC’s SCLK.
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
REV. 0
–15–
AD5425
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
MICROWIRE*
AD5425*
SK
SO
CS
SCLK
SDIN
SYNC
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. MICROWIRE to AD5425 Interface
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
PIC16C6x/7x to AD5425
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual.
In this example, I/O port RA1 is being used to provide a
SYNC signal and enable the serial port of the DAC. This
microcontroller transfers eight bits of data during each serial
transfer operation. Figure 16 shows the connection diagram.
EVALUATION BOARD FOR THE AD5425 DAC
The board consists of an 8-bit AD5425 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
PIC16C6x/7x*
AD5425*
SCK/RC3
SCLK
SDIN
SYNC
SDI/RC4
RA1
OPERATING THE EVALUATION BOARD
Power Supplies
The board requires Ϯ12 V, and +5 V supplies. The +12 V VDD
and VSS are used to power the output amplifier, while the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. PIC16C6x/7x to AD5425 Interface
Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5425 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the DAC is in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at one point only. The star ground point should be estab-
lished as close as possible to the device.
Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
Link2 should be connected to LDAC position.
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and to filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
–16–
REV. 0
AD5425
V
DD1
J3
J4
J5
J6
R1 = 0⍀
+
C1
0.1F
C2
10F
SCLK
SDIN
U1
SCLK
SDIN
4
5
6
7
8
C7 10F
+
C8 0.1F
P1–3
SCLK
SDIN
V
DD
C5
4.7pF
V
SS
10
1
P1–2
P1–4
R
FB
AD8065AR
TP1
SYNC
2
4
V–
V+
V
OUT
I
I
1
2
OUT
SYNC
6
SYNC
2
3
SDO/LDAC
J1
OUT
3
7
U3
SDO/LDAC GND
V
C9 10F
+
REF
LDAC
V
P1–5
REF
V
DD
J2
C10 0.1F
A
B
9
V
LK2
REF
SDO
AD5425/AD5426/
AD5432/AD5443
P1–13
LK1
V
DD
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
2
5
6
+V
V
OUT
IN
U2
ADR01AR
C3
10F
C4
0.1F
C5
0.1F
TRIM
GND
4
V
DD
P2–3
P2–2
C11
C12
+
+
0.1F
10F
C13
C14
AGND
0.1F
10F
P2–1
P2–4
V
V
DD1
SS
C15
C16
+
0.1F
10F
Figure 17. Schematic of the AD5425 Evaluation Board
REV. 0
–17–
AD5425
P1
SCLK
SDIN
J3
J4
J5
C11
U3
SCLK
J1
VOUT
U1
SDIN
SYNC
R1 C6
VREF
C4
C3
C1
C2
LK1
SYNC
U2
SDO/LDAC
J2
VREF
C9
SDO/LDAC
J6
C16
C14
C15
C10
C13
P2
EVAL–AD5425EB
Figure 18. Silkscreen—Component Side View (Top Layer)
C 1 2
C 7
Figure 19. Silkscreen—Component Side View (Bottom Layer)
–18–
REV. 0
AD5425
Overview of AD54xx Devices
tS max Interface Package
Part No.
Resolution
No. DACs INL
Features
AD5403*
8
2
0.25 60 ns
Parallel
CP-40
10 MHz Bandwidth,
10 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5410*
AD5413*
AD5424
AD5425
8
8
8
8
1
2
1
1
0.25 100 ns Serial
0.25 100 ns Serial
RU-16
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
0.25 60 ns
Parallel
RU-16, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
0.25 100 ns Serial
0.25 100 ns Serial
RM-10
Byte Load, 10 MHz Bandwidth,
50 MHz Serial
AD5426
AD5428
8
8
1
2
RM-10
RU-20
10 MHz Bandwidth, 50 MHz Serial
0.25 60 ns
Parallel
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5429
AD5450
AD5404*
8
2
1
2
0.25 100 ns Serial
0.25 100 ns Serial
RU-10
RJ-8
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth, 50 MHz Serial
8
10
0.5
70 ns
Parallel
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5411*
AD5414*
10
10
1
2
0.5
0.5
110 ns Serial
110 ns Serial
110 ns Serial
RU-16
RU-24
RM-10
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5432
AD5433
10
10
1
1
0.5
0.5
10 MHz Bandwidth, 50 MHz Serial
70 ns
Parallel
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5439
AD5440
10
10
2
2
0.5
0.5
110 ns Serial
70 ns Parallel
RU-16
RU-24
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5451
AD5405
10
12
1
2
0.25 110 ns Serial
RJ-8
10 MHz Bandwidth, 50 MHz Serial
1
120 ns Parallel
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5412*
12
12
1
2
1
1
160 ns Serial
160 ns Serial
RU-16
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5415
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5443
AD5444
AD5445
12
12
12
1
1
1
1
160 ns Serial
160 ns Serial
120 ns Parallel
RM-10
RM-10
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth, 50 MHz Serial
0.5
1
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5446
AD5447
14
12
1
2
2
1
180 ns Serial
RM-10
RU-24
10 MHz Bandwidth, 50 MHz Serial
120 ns Parallel
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5449
12
2
1
160 ns Serial
RU-16
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5452
AD5453
12
14
1
1
0.5
2
160 ns Serial
180 ns Serial
RJ-8, RM-8
RJ-8, RM-8
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth, 50 MHz Serial
*Future parts, contact factory for availability
REV. 0
–19–
AD5425
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8؇
0؇
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
–20–
REV. 0
相关型号：
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