AD5432BRM-REEL7 [ADI]
IC IC,D/A CONVERTER,SINGLE,10-BIT,CMOS,TSSOP,10PIN, Digital to Analog Converter;
| 型号： | AD5432BRM-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC IC,D/A CONVERTER,SINGLE,10-BIT,CMOS,TSSOP,10PIN, Digital to Analog Converter 转换器 数模转换器 |
| 文件： | 总10页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
HighBandwidthCMOS8/10/12-Bit
a
SerialInterfaceMultiplyingDACs
AD5426/AD5432/AD5443*
Preliminary Technical Data
FEATURES
+2.5 V to +5.5 V Supply Operation
50MHz Serial Interface
F U NC T IO NAL B LO C K D IAG RAM
10MHz Multiplying Bandw idth
±10V Reference Input
V
V
REF
DD
10-Lead µSOIC Package
Pin Com patible 8, 10 and 12 Bit Current Output DACs
Guaranteed Monotonic
Four Quadrant Multiplication
Pow er On Reset
R
FB
R
AD5426/
AD5432/
AD5443
8/10/12
BIT
R-2R DAC
I
OUT1
I
OUT2
Daisy Chain Mode
Readback Function
5µA typical Pow er Consum ption
DAC REGISTER
INPUT LATCH
Power On
Reset
APPLICATIONS
Portable Battery Pow ered Applications
Waveform Generators
Analog Processing
SYNC
SCLK
SDIN
CONTROL LOGIC &
INPUT SHIFT REGISTER
SDO
Instrum entation Applications
Program m able Am plifiers and Attenuators
Digitally-Controlled Calibration
Program m able Filters and Oscillators
Com posite Video
GND
Ultrasound
Gain, offset and Voltage Trim m ing
G E NE R AL D E S C R IP T IO N
characteristics, with large signal multiplying bandwidths
of 10M H z.
T he AD5426/AD5432/AD5443 are CMOS 8, 10 and
12-bit Current Output digital-to-analog converters
respectively.
T he applied external reference input voltage (VREF
)
determines the full scale output current. An integrated
feedback resistor (RFB) provides temperature tracking and
full scale voltage output when combined with an external
Current to Voltage precision amplifier.
T hese devices operate from a +2.5 V to 5.5 V power sup-
ply, making them suited to battery powered applications
and many other applications.
T hese DACs utilize double buffered 3-wire serial interface
that is compatible with SPIT M, QSPIT M, MICROWIRET M
and most DSP interface standards. In addition, a serial
data out pin (SDO) allows for daisy chaining when
T he AD 5426/AD 5432/AD 5443 D ACs are available in
small 10-lead µSOIC packages.
multiple packages are used. Data readback allows the user
to read the contents of the DAC register via the SDO pin.
On power-up, the internal shift register and latches are
filled with zeros and the DAC outputs are at zero scale.
P R O D U C T H IG H LIG H T S
1. 10M H z M ultiplying Bandwidth
2. 3mm x 5mm 10-lead µSOIC package
As a result of manufacture on a CMOS sub micron
process, they offer excellent four quadrant multiplication
3. Low Voltage, Low Power Current Output DACs.
*US Patent N umber 5,689,257
SPI and QSPI are trademarks of Motorola, Inc.
M ICROWIRE is a trademark of N ational Semiconductor Corporation.
REV. PrI Feb, 2003
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 2003
Fax: 781/ 326-8703
PRELIMINARY TECHNICAL DATA
1
AD5426/AD5432/AD5443–SPECIFICATIONS
(V = 2.5 V to 5.5 V, V = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
DD
REF
OP1177, AC performance with AD9631 unless otherwise noted.)
P ar am eter
Min
Typ
Max
Units
Conditions
ST AT IC PERFORMANCE
AD 5426
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5432
±0.5
±1
Guaranteed Monotonic
Guaranteed Monotonic
Guaranteed Monotonic
Resolution
10
±1
±1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5443
Resolution
12
±2
±1
±2
Bits
LSB
LSB
m V
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error T emp Coefficient2
Output Leakage Current
±5
ppm FSR/°C
±10
±50
nA
nA
V
Data = 0000H, T A = 25°C, IOUT 1
Data = 0000H, IOUT 1
Output Voltage Compliance Range
T BD
REFERENCE INPUT 2
Reference Input Range
VREF Input Resistance
±10
10
V
kΩ
8
12
Input resistance T C = -50ppm/°C
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
1.7
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.8
0.7
1
Input Leakage Current, IIL
Input Capacitance
10
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 1
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 0.5
DYNAMIC PERFORMANCE2
Reference Multiplying BW
10
T BD
MH z
MH z
VREF = 100 mV rms, DAC loaded all 1s
VREF = 6 V rms, DAC loaded all 1s
Output Voltage Settling T ime
AD5426
AD5432
AD5443
Slew Rate
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
30
35
40
100
3
T BD
T BD
T BD
ns
ns
ns
V/µs
nV-s
dB
pF
Measured to ½ LSB. RLOAD = 100Ω, CLOAD = 15pF.
DAC latch alternately loaded with 0s and 1s.
1 LSB change around Major Carry
DAC latch loaded with all 0s. Reference = 10kHz.
DAC Latches Loaded with all 0s
-75
2
4
pF
DAC Latches Loaded with all 1s
Digital Feedthrough
5
nV-s
Feedthrough to DAC output with SYNC high
and Alternate Loading of all 0s and all 1s.
VREF = 6 V rms, All 1s loaded, f = 1kHz
VREF = 5 V, Sinewave generated from digital code.
@ 1kHz
T otal Harmonic Distortion
-85
-85
25
72
T BD
dB
dB
Output Noise Spectral Density
SFDR performance
Intermodulation D istortion
nV/
dB
d B
√H z
POWER REQUIREMENT S
Power Supply Range
IDD
Power Supply Sensitivity2
2.5
5.5
10
0.001
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
NOTES
1T emperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design and characterisation, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrI
PRELIMINARY TECHNICAL DATA
Single Supply Operation (Biased Mode)
AD5426/AD5432/AD5443
(V = 2.5 V to 5.5 V, V = + 2V, IOUT2 = +1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
DD
REF
OP1177, AC performance with AD9631 unless otherwise noted.)
P ar am eter
Min
Typ
Max
Units
Conditions
ST AT IC PERFORMANCE
AD 5426
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5432
±0.5
±1
Guaranteed Monotonic
Guaranteed Monotonic
Guaranteed Monotonic
Resolution
10
±1
±1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5443
Resolution
12
±2
±1
±2
Bits
LSB
LSB
m V
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error T emp Coefficient2
Output Leakage Current
±5
ppm FSR/°C
±10
±50
nA
nA
V
Data = 0000H, TA = 25°C, IOUT 1
Data = 0000H, IOUT 1
Output Voltage Compliance Range
T BD
REFERENCE INPUT 2
Reference Input Range
VREF Input Resistance
tbd
10
V
kΩ
8
12
Input resistance T C = -50ppm/°C
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
1.7
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.8
0.7
1
Input Leakage Current, IIL
Input Capacitance
10
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 1
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 0.5
DYNAMIC PERFORMANCE2
Reference Multiplying BW
10
T BD
MH z
MH z
VREF = 100 mV rms, DAC loaded all 1s
VREF = 1 V, DAC loaded all 1s
Output Voltage Settling T ime
AD5426
AD5432
AD5443
Slew Rate
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
30
35
40
100
3
T BD
T BD
T BD
ns
ns
ns
V/µs
nV-s
dB
pF
Measured to ½ LSB. RLOAD = 100Ω, CLOAD = 15pF.
VREF = 0V,DAC latch alternately loaded with 0s & 1s.
1 LSB change around Major Carry
DAC latch loaded with all 0s. Reference = 10kHz.
DAC Latches Loaded with all 0s
-75
2
4
pF
DAC Latches Loaded with all 1s
Digital Feedthrough
5
nV-s
Feedthrough to DAC output with SYNC high
and Alternate Loading of all 0s and all 1s.
VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz
VREF = 2 V, Sinewave generated from digital code.
@ 1kHz
T otal Harmonic Distortion
-85
-85
25
72
T BD
dB
dB
Output Noise Spectral Density
SFDR performance
Intermodulation D istortion
nV/
dB
d B
√H z
POWER REQUIREMENT S
Power Supply Range
IDD
Power Supply Sensitivity2
2.5
5.5
10
0.001
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
NOTES
1T emperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design and characterisation, not subject to production test.
Specifications subject to change without notice.
REV. PrI
–3–
PRELIMINARY TECHNICAL DATA
1
AD5426/AD5432/AD5443–SPECIFICATIONS
(V = 2.5 V to 5.5 V, V = +5 V, I 2 = O V. All specifications TMIN to TMAX unless
1
DD
REF
OUT
TIMINGCHARACTERISTICS
otherwise noted.)
P ar am eter
Lim it at TMIN, TMAX
Units
Conditions/Com m ents
fSCLK
t1
t2
50
20
8
8
13
5
4.5
5
30
25
M H z max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
M ax Clock frequency
SCLK Cycle time
SCLK H igh T ime
SCLK Low T ime
SYNC falling edge to SCLK active edge setup time
Data Setup T ime
Data H old T ime
SYNC rising edge to SCLK active edge
M inimum SYNC high time
SCLK Active edge to SDO valid
t3
t4
2
t5
t6
t7
t83
t9
NOTES
1See Figures 1 & 2. T emperature range is as follows: B Version: –40°C to +105°C. Guaranteed by design and characterisation, not subject to production test. All input
signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH )/2.
2Falling or Rising edge as determined by control bits of Serial word.
3Daisychain and Readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
t
1
SCLK
t
t
2
3
t
8
t
7
t
4
SYNC
DIN
t
6
t
5
DB15
DB0
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON
RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE WITH SCLK INVERTED
,
.
Figure 1. Stand Alone Mode Tim ing Diagram .
t
1
SCLK
t
t
2
t
3
7
t
8
t
4
SYNC
t
6
t
5
SDIN
SDO
DB15 (N)
DB0 (N) DB15 (N+1)
DB0 (N+1)
DB0(N)
t
9
DB15(N)
A
LTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON
R
ISING
E
DGE OF SCLK AS
ALLING
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON
DGE OF SCLK. TIMING AS PER ABOVE WITH SCLK INVERTED
F
E
,
.
Figure 2. Daisy Chain and Readback Modes Tim ing Diagram
–4–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
2
ABSO LUT E MAXIMUM RAT INGS1,
(T A = +25°C unless otherwise noted)
VDD to GND
VREF, RFB to GND
–0.3 V to +7 V
–12 V to +12 V
–0.3 V to +7 V
±10 mA
I
200uA
OL
TO
OUTPUT
PIN
I
OUT 1, IOUT2 to GND
V
+ V
2
OH (MIN)
OL (MAX)
Input Current to any pin except supplies
C
L
Logic Inputs & Output3
Operating T emperature Range
Industrial (B Version)
-0.3V to VDD +0.3 V
50pF
I
200uA
OH
–40°C to +105°C
–65°C to +150°C
+ 150°C
Storage T emperature Range
Junction T emperature
10 lead µSOIC θJA T hermal Impedance
Lead T emperature, Soldering (10seconds)
IR Reflow, Peak T emperature (<20 seconds)
Figure 3. Load Circuit for SDO Tim ing Specifications
206°C /W
300°C
+ 235°C
NOTES
1Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent
damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periodsmayaffect device reliability. Onlyone absolute maximum ratingmay
be applied at any one time.
2 T ransient currents of up to 100mA will not cause SCR latchup.
3Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
O R D E R ING G U ID E
Model
Tem perature Range
P ackage D escription
Br an din g
P ackage O ption
AD 5426BRM
AD 5432BRM
AD 5443BRM
-40 oC to +105 oC
-40 oC to +105 oC
-40 oC to +105 oC
µSO IC
µSO IC
µSO IC
D 01
D 02
D 03
RM -10
RM -10
RM -10
C AUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrI
–5–
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
P IN F U NC T IO N D E SC R IP T IO N
P in
Mnem onic F u n ction
1
2
3
4
I
I
O U T 1
OUT2
DAC Current Output.
DAC Analog Ground. T his pin should normally be tied to the analog ground of the system.
Ground Pin.
G N D
SC L K
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of
the serial clock input. Alternatively, by means of the serial control bits, the device may be
configured such that data is clocked into the shift register on the rising edge of SCLK.
5
6
SD IN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial
clock input. By default, on power up, data is clocked into the shift register on the falling edge of
SCLK. T he control bits allow the user to change the active edge to rising edge.
SYN C
Active Low Control Input. T his is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is
enabled. Data is loaded to the shift register on the active edge of the following clocks. In
stand alone mode, the serial interface counts clocks and data is latched to the shift register on the
16th active clock edge.
7
8
S D O
Serial Data Output. T his allows a number of parts to be daisychained. By default, data is clocked
into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will
always be clocked out on the alternate edge to loading data to the shift register. Writing the
Readback control word to the shift register makes the DAC register contents available for
readback on the SDO pin, clocked out on the opposite edges to the active clock edge.
Positive power supply input. T hese parts can be operated from a supply of +2.5 V to +5.5 V.
VDD
9
10
VREF
RFB
DAC reference voltage input pin.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external
amplifier output.
P IN C O NF IG U R AT IO N
µS O I C
IOUT1
IOUT2
GND
10
9
RFB
1
2
3
4
5
VREF
VDD
AD5426/
AD5432/
AD5443
8
7
6
SCLK
SDIN
SDO
(Not to Scale)
SYNC
–6–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
T E R M I N O L O G Y
In t er m od u la t ion D ist or t ion
Rela tive Accu r a cy
T he DAC is driven by two combinded sine waves
references of frequencies fa and fb. Distortion products are
produced at sum and difference frequencies of mfa±nfb
where m, n = 0, 1, 2, 3... Intermodulation terms are those
for which m or n is not equal to zero. T he second order
terms include (fa +fb) and (fa - fb) and the third order
terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa -
2fb). IMD is defined as
Relative accuracy or endpoint nonlinearity is a measure of
the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero and full scale and is
normally expressed in LSBs or as a percentage of full
scale reading.
D iffer en t ia l Non lin ea r it y
Differential nonlinearity is the difference between the
measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of
±1 LSB max over the operating temperature range
ensures monotonicity.
IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
C om p lia n ce Volta ge Ra n ge
T he maximum range of (output) terminal voltage for
which the device will provide the specified characteristics.
G a in E r r or
Gain error or full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
For these DACs, ideal maximum output is VREF – 1 LSB.
Gain error of the DACs is adjustable to zero with external
resistance.
G E NE R AL D E S C R IP T IO N
D AC S E C T IO N
T he AD5426, AD5432 and AD5443 are 8, 10 and 12 bit
current output DACs consisting of a standard inverting R-
2R ladder configuration. A simplified diagram for the 8-
Bit AD54246 is shown in Figure 4. T he feedback resistor
RFB has a value of R. T he value of R is typically 10kΩ
(minimum 8kΩ and maximum 12kΩ). If IOUT 1 and IOUT 2
are kept at the same potential, a constant current flows in
each ladder leg, regardless of digital input code.
T herefore, the input resistance presented at VREF is always
constant.
O u tp u t Lea ka ge C u r r en t
Output leakage current is current which flows in the DAC
ladder switches when these are turned off. For the IOUT 1
terminal, it can be measured by loading all 0s to the DAC
and measuring the IOUT 1 current. Minimum current will
flow in the IOUT 2 line when the DAC is loaded with all 1s
O u t p u t C a p a cit a n ce
Capacitance from IOUT 1 or IOUT 2 to AGND.
R
R
R
V
O u tp u t C u r r en t Settlin g T im e
REF
2R
S1
2R
S2
2R
S3
2R
S8
2R
T his is the amount of time it takes for the output to settle
to a specified level for a full scale input change. For these
devices, it is specifed with a 100 Ω resistor to ground.
R
R
A
FB
I
OUT1
I
OUT 2
D igital to Analog Glitch lm pulse
DAC DATA LATCHES
AND DRIVERS
T he amount of charge injected from the digital inputs to
the analog output when the inputs change state. T his is
normally specified as the area of the glitch in either
pA-secs or nV-secs depending upon whether the glitch is
measured as a current or voltage signal.
Figure 4. Sim plified Ladder
Access is provided to the VREF, RFB, IOUT 1 and IOUT 2
terminals of the DAC, making the device extremely
versatile and allowing it to be configured in several
different operating modes, for example, to provide a
unipolar output, bipolar output or in single supply modes
of operation. in unipolar mode or four quadrant
multiplication in bipolar mode.
D igit a l F eed t h r ou gh
When the device is not selected, high frequency logic
activity on the device digital inputs is capacitivelly coupled
through the device to show up as noise on the IOUT pins
and subsequently into the following circuitry. T his noise is
digital feedthrough.
Un ipolar M ode
M u ltip lyin g F eed th r ou gh E r r or
Using a single op amp, these devices can easily be
configured to provide 2 quadrant multiplying operation or
a unipolar output voltage swing as shown in Figure 5.
T his is the error due to capacitive feedthrough from the
DAC reference input to the DAC IOUT 1 terminal, when all
0s are loaded to the DAC.
When an output amplifier is connected in unipolar mode,
the output voltage is given by:
H a r m on ic D ist or t ion
T he DAC is driven by an ac reference. T he ratio of the
rms sum of the harmonics of the DAC output to the
fundamental value is the T HD. Usually only the lower
order harmonices are included, such as second to fifth.
VOUT = -D/2^n x VREF
Where D is the fractional representation of the digital
word loaded to the DAC, and n is the number of bits.
2
2
2
2
T HD = 20log
√
(V2 + V3 + V4 + V5
)
V1
REV. PrI
–7–
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
When VIN is an ac signal, the circuit performs four-
quadrant multiplication.
D = 0 to 256 (8-Bit AD5426)
= 0 to 1024 (10-Bit AD5432)
= 0 to 4096 (12-Bit AD5443)
T able II. shows the relationship between digital code and
the expected output voltage for bipolar operation
(AD 5426, 8-Bit device).
V
DD
R
2
Table II. Bipolar Code Table
C
1
RFB
IOUT1
IOUT2
SCLK SDIN GND
V
DD
D igital Input Analog O utput (V)
V
REF
V
A1
REF AD5426/32/43
R
1
1111 1111
1000 0000
0000 0001
0000 0000
+ VREF (127/128)
0
-VREF (127/128)
-VREF (128/128)
V
= 0 to -V
REF
OUT
SYNC
uController
AGND
NOTES:
1
SE RIAL INT E RF AC E
R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2
C1 PHASE COMPENSATION (1pF - 5pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
T he AD5426/AD5432/AD5443 have an easy to use 3-wire
interface which is compatible with SPI/QSPI/M icroWire
and DSP interface standards. Data is written to the device
in 16 bit words. T his 16-bit word consists of 4 control bits
and either 8, 10 or 12 data bits as shown in Figure 6.T he
AD5443 uses all 12 bits of DAC data. T he AD5432 uses
ten bits and ignores the two LSBs, while the AD5426
uses eight bits and ignores the last four bits. As good
programming practice, these ignored LSB’s should be set
to ‘0’.
Figure 5. Unipolar Operation
With a fixed 10 V reference, the circuit shown above will
give an unipolar 0V to -10V output voltage swing. When
VIN is an ac signal, the circuit performs two-quadrant
multiplication.
T he following table shows the relationship between digital
code and expected output voltage for unipolar operation.
(AD 5426, 8-Bit device).
Low P ower Ser ial Inter face
T o minimize the power consumption of the device, the
interface only powers up fully when the device is being
written to, i.e., on the falling edge of SYNC. T he SCLK
and DIN input buffers are powered down on the rising
edge of SYN C .
Table I. Unipolar Code Table
D igital Input Analog O utput (V)
1111 1111
1000 0000
0000 0001
0000 0000
-VREF (255/256)
-VREF (128/256) = -VREF/2
-VREF (1/256)
D AC C ontr ol Bits C 3 - C 0
Control bits C3 to C0 allow control of various functions
of the DAC as can be seen in T able 3. Default settings of
the DAC on power on are as follows :
-VREF (0/256) = 0
Data clocked into shift register on falling clock edges;
Daisy chain mode is enabled. Device powers on with
zeroscale load to the DAC register and IOUT lines.
T he DAC control bits allow the user to adjust certain
features on power on, for example, Daisy chaining may be
disabled if not in use, active clock edge may be changed to
rising edge and DAC output may be cleared to either zero
B ip ola r O p er a tion
In some applications, it may be necessary to generate full
4-Quadrant multplying operation or a bipolar output
swing. T his can be easily accomplished by using another
external amplifier and some external resistors as shown in
Figure 6.
R3
10kΩ
R2
C1
V
DD
R5
20kΩ
RFB
IOUT1
IOUT2
GND
V
DD
R4
10kΩ
R1
V
AD5426/32/43
A1
REF
± 10V
V
REF
A2
V
= -V
to +V
REF
OUT
REF
SYNC SCLK SDIN
uController
AGND
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
NOTES:
1
OUT
2
3
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 6. Bipolar Operation (4 Quadrant Multiplication)
–8–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
shift register when SYNC is low. If more than 16 clock
pulses are applied, the data ripples out of the shift register
and appears on the SDO line. T his data is clocked out on
the rising edge of SCLK (this is the default, use the
control word to change the active edge) and is valid for
the next device on the falling edge (default). By
or midscale. T he user may also initiate a readback of the
DAC register contents for verification purposes.
TABLE 3. D AC CO NTRO L BITS
C 3 C 2 C 1 C 0 Funtion Im plem ented
connecting this line to the DIN input on the next device
in the chain, a multidevice interface is constructed. 16
clock pulses are required for each device in the system.
T herefore, the total number of clock cycles must equal
16N where N is the total number of devices in the chain.
See the timing diagram in Figure 3.
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
No Operation (Power On Default)
Load and Update
Initiate Readback
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D aisy Chain D isable
Clock Data to shift register On Rising
Ed ge
Clear DAC output to Zero
Clear DAC output to Midscale
Reserved
When the serial transfer to all devices is complete, SYNC
should be taken high. T his prevents any further data being
clocked into the input shift register. A burst clock
containing the exact number of clock cycles may be used
and SYNC taken high some time later. After the rising
edge of SYNC, data is automatically transferred from each
device’s input shift register to the addressed DAC.
When control bits = “0000”, the device is in No
Operation mode. T his may be useful in daisy-chain
applications where the user does not wish to change the
settings of a particular DAC in the chain. Simply write
“0000” to the Control bits for that DAC and the
following data bits will be ignored.
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Reserved
Reserved
SYN C F u n ct ion
SYNC is an edge-triggered input that acts as a frame
synchronization signal and chip enable. Data can only be
transferred into the device while SYNC is low. T o start
the serial data transfer, SYNC should be taken low ob-
serving the minimum SYNC falling to SCLK falling
edge setup time, t4.
Stand alone Mode
After power on, write “1001” to control word to disable
Daisy Chain Mode. T he first falling edge of SYNC resets
a counter that counts the number of serial clocks to ensure
the correct number of bits are shifted in and out of the
serial shift registers. Any further edges on SYNC are
ignored until the correct number of bits are shifted in or
out.
After the falling edge of the 16th SCLK pulse, data will
automatically be transferred from the input shift register to
the DAC. In order for another serial transfer to take place
the counter must be reset by the falling edge of SYNC.
D aisy C h ain Mode
Daisy Chain is the default power on mode. T o disable the
daisy chain function, write “1001” to control word. In
Daisy-Chain Mode the internal gating on SCLK is
disabled. T he SCLK is continuously applied to the input
DB15 (MSB)
DB0 (LSB)
C3
C2
C1
C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DATA BITS
0
0
0
0
CONTROL BITS
Figure 6a. AD5426 8 bit Input Shift Register Contents
DB15 (MSB)
C3 C2
CONTROL BITS
DB0 (LSB)
C1
C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DATA BITS
0
0
Figure 6b. AD5432 10 bit Input Shift Register Contents
DB15 (MSB)
C3 C2
CONTROL BITS
DB0 (LSB)
DB1 DB0
DB3 DB2
C1
C0
DB9 DB8 DB7 DB6 DB5 DB4
DATA BITS
DB11 DB10
Figure 6c. AD5443 12 bit Input Shift Register Contents
REV. PrI
–9–
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443
O ver view of AD 54xx devices
P ar t #
R esolu t ion # D AC s I N L t S
In ter fa ce P a cka ge
F ea tu r es
AD 5 4 2 4 8
AD 5 4 2 5 8
AD 5 4 2 6 8
AD 5 4 2 8 8
AD 5 4 2 9 8
AD 5 4 3 2 1 0
AD 5 4 3 3 1 0
AD 5 4 3 9 1 0
AD 5 4 4 0 1 0
AD 5 4 4 3 1 2
AD 5 4 4 5 1 2
AD 5 4 4 7 1 2
AD 5 4 6 9 1 2
1
1
1
2
2
1
1
2
2
1
1
2
2
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
P arallel
S er ia l
S er ia l
P arallel
S er ia l
S er ia l
P arallel
S er ia l
P arallel
S er ia l
P arallel
P arallel
S er ia l
RU -16, C P -20 10 MH z BW, 10 ns C S Pulse Width
R M - 1 0
R M - 1 0
R U - 2 0
R U - 1 0
R M - 1 0
Byte Load,10 M H z BW, 50 M H z Serial
10 M H z BW, 50 M H z Serial
10 M H z BW, 10 ns C S Pulse Width
10 M H z BW, 50 M H z Serial
± 1
± 1
± 1
± 1
± 2
± 2
± 2
± 2
35n s
35n s
35n s
35n s
40n s
40n s
40n s
40n s
10 M H z BW, 50 M H z Serial
RU -20, C P -20 10 MH z BW, 10 ns C S Pulse Width
R U - 1 6
R U - 2 4
R M - 1 0
10 M H z BW, 50 M H z Serial
10 M H z BW, 10 ns C S Pulse Width
10 M H z BW, 50 M H z Serial
RU -20, C P -20 10 M H z BW, 10 ns CS Pulse Width
R U - 2 4
R U - 1 6
10 M H z BW, 10 ns CS Pulse Width
10 M H z BW, 10 ns CS Pulse Width
O U T LINE D IM E NS IO NS
D imensions shown in inches and (mm).
10 Lead µSO IC
(RM - 10)
0.122 (3.10)
0.114 (2.90)
10
6
5
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
PIN 1
0.0197 (0.50) BSC
0.120 (3.05)
0.112 (2.85)
0.120 (3.05)
0.112 (2.85)
0.037 (0.94)
0.031 (0.78)
0.043 (1.10)
MAX
6؇
0؇
SEATING
PLANE
0.006 (0.15) 0.012 (0.30)
0.002 (0.05) 0.006 (0.15)
0.028 (0.70)
0.016 (0.40)
0.009 (0.23)
0.005 (0.13)
REV. PrI
–10–
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