AD5443YRMZ-REEL7_技术文档

8-/10-/12-Bit High Bandwidth

Multiplying DACs with Serial Interface

Data Sheet

AD5426/AD5432/AD5443

FEATURES

GENERAL DESCRIPTION

2.5 V to 5.5 V supply operation

50 MHz serial interface

10 MHz multiplying bandwidth

2.5 MSPS update rate

INL of 1 LSB for 12-bit DAC

10 V reference input

Low glitch energy < 2 nV-s

Extended temperature range −40°C to +125°C

10-lead MSOP package

Pin-compatible 8-, 10-, and 12-bit current output DACs

Guaranteed monotonic

4-quadrant multiplication

Power-on reset with brownout detection

Daisy-chain mode

The AD5426/AD5432/AD5443¹are CMOS 8-, 10-, and 12-bit

current output digital-to-analog converters (DACs), respectively.

These devices operate from a 2.5 V to 5.5 V power supply,

making them suitable for battery-powered applications and

many other applications.

These DACs use a double buffered, 3-wire serial interface that is

compatible with SPI, QSPI™, MICROWIRE™, and most DSP

interface standards. In addition, a serial data out pin (SDO)

allows for daisy-chaining when multiple packages are used.

Data readback allows the user to read the contents of the DAC

register via the SDO pin. On power-up, the internal shift register

and latches are filled with 0s and the DAC outputs are at zero scale.

As a result of manufacturing on a CMOS submicron process,

the parts offer excellent 4-quadrant multiplication characteristics

with large signal multiplying bandwidths of 10 MHz. The applied

external reference input voltage, V_REF, determines the full-scale

output current. An integrated feedback resistor, R_FB, provides

temperature tracking and full-scale voltage output when combined

with an external current to voltage precision amplifier.

Readback function

0.4 µA typical power consumption

APPLICATIONS

Portable battery-powered applications

Waveform generators

Analog processing

The AD5426/AD5432/AD5443 DACs are available in small,

10-lead MSOP packages.

Instrumentation

Programmable amplifiers and attenuators

Digitally controlled calibration

Programmable filters and oscillators

Composite video

The EV-AD5443/46/53SDZ evaluation board is available for

evaluating DAC performance. For more information, see the

UG-327 evaluation board user guide.

Ultrasound

Gain, offset, and voltage trimming

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

R

AD5426/

AD5432/

AD5443

R

I

FB

1

2

8-/10-/12-BIT

R-2R DAC

OUT

I

OUT

DAC REGISTER

INPUT LATCH

POWER-ON

RESET

SYNC

SCLK

SDIN

CONTROL LOGIC AND

INPUT SHIFT REGISTER

SDO

GND

Figure 1.

¹U.S. Patent No. 5,689,257.

Rev. G

Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5426/AD5432/AD5443

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Circuit Operation....................................................................... 15

Single-Supply Applications ....................................................... 17

Positive Output Voltage............................................................. 17

Adding Gain................................................................................ 18

DACs Used as a Divider or Programmable Gain Element... 18

Reference Selection .................................................................... 18

Amplifier Selection .................................................................... 18

Serial Interface ............................................................................ 20

PCB Layout and Power Supply Decoupling................................ 22

Overview of AD54xx and AD55xx Devices ............................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

REVISION HISTORY

6/13—Rev. F to Rev. G

Change to General Description Section........................................ 1

Changes to Ordering Guide .......................................................... 24

Deleted Evaluation Board for the AD5426/AD5432/AD5443

Series of DACs Section, Operating the Evaluation Board

Section, and Power Supplies Section ........................................... 23

Deleted Figure 59 and Figure 60................................................... 24

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

Deleted Figure 61............................................................................ 25

Deleted Figure 62............................................................................ 26

7/12—Rev. E to Rev. F

No Change to Content, Changed V_DDValues in 7/12 Revision

History Only...................................................................................... 2

7/12—Rev. D to Rev. E

Changed V_DD= 3 V to V_DD= 2.5 V ............................. Throughout

Changes to Table 2............................................................................ 4

Changes to Table 4............................................................................ 7

Change to Daisy-Chain Mode Section ........................................ 20

Change to Ordering Guide............................................................ 24

2/09—Rev. B to Rev. C

Changes to Low Power Serial Interface Section and Daisy-

Chain Mode Section....................................................................... 20

Updated Outline Dimensions....................................................... 28

11/08—Rev. A to Rev. B

4/12—Rev. C to Rev. D

Changes to Ordering Guide.......................................................... 28

Changed V_DD= 2.5 V to V_DD= 3 V ............................. Throughout

Changes to General Description Section ...................................... 1

Deleted Microprocessor Interface Section, ADSP-21xx to

AD5426/AD5432/AD5443 Interface Section, Figure 51,

Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443

Interface Section, Figure 53 and Figure 54; Renumbered

Sequentially ..................................................................................... 21

Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface

Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/

AD5443 Interface Section, Figure 56, MICROWIRE to

AD5426/AD5432/AD5443 Interface Section, Figure 57,

PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22

5/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Specifications.................................................................3

Changes to Figure 42...................................................................... 16

Change to Figure 45 ....................................................................... 17

Change to Figure 46 ....................................................................... 18

Changes to Table 7, Table 8, and Table 9..................................... 19

Additions to Microprocessor Interface Section.......................... 21

2/04—Revision 0: Initial Version

Rev. G | Page 2 of 24

Data Sheet

AD5426/AD5432/AD5443

SPECIFICATIONS

V_DD= 2.5 V to 5.5 V, V_REF= 10 V, I_OUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T_MINto T_MAX, unless

otherwise noted; dc performance measured with OP177; ac performance with AD8038, unless otherwise noted.

Table 1.

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

AD5426

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5432

0.25

0.5

Guaranteed monotonic

Resolution

10

0.5

1

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5443

Resolution

12

1

Bits

LSB

Relative Accuracy

Differential Nonlinearity

Gain Error

−1/+2 LSB

10

Guaranteed monotonic

mV

Gain Error Temperature Coefficient¹

Output Leakage Current

5

ppm FSR/°C

nA

10

20

Data = 0x0000, T_A= 25°C, I_OUT1

Data = 0x0000, T = −40°C to 125°C, I_OUT

1

REFERENCE INPUT¹

Reference Input Range

V_REFInput Resistance

R_FBResistance

10

V

kΩ

8

12

Input resistance TC = −50 ppm/°C

Input Capacitance

Code Zero Scale

Code Full Scale

3

5

6

8

pF

DIGITAL INPUT/OUTPUT¹

Input High Voltage, V_IH

Input Low Voltage, V_IL

Output High Voltage, V_OH

1.7

V

µA

pF

0.6

V_DD− 1

V_DD− 0.5

V_DD= 4.5 V to 5 V, I_SOURCE= 200 µA

V_DD= 2.5 V to 3.6 V, I_SOURCE= 200 µA

V_DD= 4.5 V to 5 V, I_SINK= 200 µA

V_DD= 2.5 V to 3.6 V, I_SINK= 200 µA

Output Low Voltage, V_OL

0.4

1

Input Leakage Current, I_IL

Input Capacitance

4

10

DYNAMIC PERFORMANCE¹

Reference Multiplying Bandwidth

Output Voltage Settling Time

10

MHz

V_REF= 3.5 V; DAC loaded all 1s

V_REF= 10 V; R_LOAD= 100 Ω, DAC latch alternately

loaded with 0s and 1s

Measured to 16 mV of FS

Measured to 4 mV of FS

Measured to 1 mV of FS

Digital Delay

10% to 90% Rise/Fall Time

Digital-to-Analog Glitch Impulse

Multiplying Feedthrough Error

50

55

90

40

15

2

100

110

160

75

ns

nV-s

Interface delay time

30

Rise and fall time, V_REF= 10 V, R_LOAD= 100 Ω

1 LSB change around major carry, V_REF= 0 V

DAC latch loaded with all 0s, V_REF= 3.5

1 MHz

70

48

dB

10 MHz

Rev. G | Page 3 of 24

AD5426/AD5432/AD5443

Data Sheet

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

Output Capacitance

I_OUT

1

12

10

22

10

0.1

17

12

25

12

pF

All 0s loaded

All 1s loaded

All 0s loaded

All 1s loaded

I_OUT

2

Digital Feedthrough

nV-s

SYNC

high and

Feedthrough to DAC output with

alternate loading of all 0s and all 1s

Analog THD

81

dB

V_REF= 3.5 V p-p, all 1s loaded, f = 1 kHz

Digital THD

Clock = 1 MHz, V_REF= 3.5 V, C_COMP= 1.8 pF

50 kHz f_OUT

20 kHz f_OUT

Output Noise Spectral Density

SFDR Performance (Wide Band)

50 kHz f_OUT

73

74

25

dB

nV/√Hz

@ 1 kHz

Clock = 1 MHz, V_REF= 3.5 V

75

76

dB

20 kHz f_OUT

SFDR Performance (Narrow Band)

50 kHz f_OUT

20 kHz f_OUT

Intermodulation Distortion

POWER REQUIREMENTS

Power Supply Range

I_DD

Clock = 1 MHz, V_REF= 3.5 V

87

78

dB

Clock = 1 MHz, f₁= 20 kHz, f₂= 25 kHz, V_REF= 3.5 V

2.5

5.5

0.6

5

V

µA

%/%

T_A= 25°C, logic inputs = 0 V or V_DD

T = −40°C to +125°C , logic inputs = 0 V or V_DD

∆V_DD= 5%

0.4

Power Supply Sensitivity¹

0.001

¹Guaranteed by design and characterization, not subject to production testing.

Rev. G | Page 4 of 24

Data Sheet

AD5426/AD5432/AD5443

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2. V_DD= 2.5 V to 5.5 V,

_REF= 10 V, I_OUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T_MINto T_MAX, unless otherwise noted.

V

Table 2.

Parameter

2.5 V to 5.5 V

4.5 V to 5.5 V

Unit

Test Conditions/Comments

Max clock frequency

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK active edge setup time

Data setup time

Data hold time

SYNC rising edge to SCLK active edge

Minimum SYNC high time

SCLK active edge to SDO valid

f_SCLK

t₁

t₂

50

20

8

13

5

50

20

8

13

5

MHz max

ns min

ns typ

ns max

t₃

t₄

1

t₅

t₆

t₇

t₈

3

5

3

5

30

80

120

30

45

65

2, 3

t₉

¹Falling or rising edge as determined by control bits of serial word.

²Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4.

³SDO operates with a VDD of 3.0 V to 5.5 V.

t₁

SCLK

t₂

t₃

t₈

t₄

t₇

SYNC

DIN

t₆

t₅

DB15

DB0

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF

SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.

Figure 2. Standalone Mode Timing Diagram

t₁

SCLK

SYNC

t₂

t₃

t₇

t₄

t₈

t6

t₆

t₅

DB15

(N + 1)

DB0

(N + 1)

SDIN

SDO

DB15 (N)

DB0 (N)

t₉

DB15(N)

DB0(N)

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

Rev. G | Page 5 of 24

AD5426/AD5432/AD5443

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up.

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DDto GND

V_REF, R_FBto GND

I_OUT1, I_OUT2 to GND

Logic Inputs and Output¹

Operating Temperature Range

Extended Industrial (Y Version)

Storage Temperature Range

Junction Temperature

−0.3 V to +7 V

−12 V to +12 V

−0.3 V to V_DD+ 0.3 V

200µA

I

OL

−40°C to +125°C

−65°C to +150°C

150°C

V

+ V

2

OH (MIN)

OL (MAX)

TO OUTPUT PIN

C

L

20pF

10-lead MSOP θ_JAThermal Impedance

Lead Temperature, Soldering (10 sec)

IR Reflow, Peak Temperature (<20 sec)

206°C/W

300°C

235°C

200µA

I

OH

Figure 4. Load Circuit for SDO Timing Specifications

1

SYNC

, and DIN are clamped by internal diodes.

Overvoltages at SCLK,

ESD CAUTION

Rev. G | Page 6 of 24

Data Sheet

AD5426/AD5432/AD5443

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

I

1

2

1

2

3

4

5

10

9

R

FB

OUT

AD5426/

AD5432/

AD5443

TOP VIEW

(Not to Scale)

V

REF

DD

GND

8

SCLK

SDIN

7

SDO

6

SYNC

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

I_OUT

GND

SCLK

1

2

DAC Current Output.

DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

Digital Ground Pin.

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into

the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz.

5

6

7

SDIN

SYNC

SDO

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By

default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the

user to change the active edge to rising edge.

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial

interface counts clocks, and data is latched to the shift register on the 16th active clock edge.

Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes

the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active

clock edge. SDO operates with a V_DDof 3.0 V to 5.5 V.

8

9

10

V_DD

V_REF

R_FB

Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.

DAC Reference Voltage Input.

DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.

Rev. G | Page 7 of 24

AD5426/AD5432/AD5443

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

0.05

0

T

= 25°C

T = 25°C

A

V

= 10V

V

= 10V

REF

= 5V

REF

= 5V

DD

0.15

0.10

0.05

0

V

DD

–0.05

–0.10

–0.15

–0.20

–0.05

–0.10

–0.15

–0.20

0

50

100

150

200

250

0

50

100

150

200

250

CODE

Figure 6. INL vs. Code (8-Bit DAC)

Figure 9. DNL vs. Code (8-Bit DAC)

0.5

0.4

0.5

0.4

T

V

= 25°C

T

V

= 25°C

= 10V

A

= 10V

REF

= 5V

REF

= 5V

DD

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

200

400

600

800

10000

200

400

600

800

1000

CODE

Figure 7. INL vs. Code (10-Bit DAC)

Figure 10. DNL vs. Code (10-Bit DAC)

1.0

0.8

1.0

0.8

T

V

= 25°C

T

V

= 25°C

A

= 10V

REF

= 5V

REF

= 5V

DD

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

500

1000 1500 2000 2500 3000 3500 4000

CODE

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 8. INL vs. Code (12-Bit DAC)

Figure 11. DNL vs. Code (12-Bit DAC)

Rev. G | Page 8 of 24

Data Sheet

AD5426/AD5432/AD5443

0.6

0.5

0.4

0.3

0.2

2.0

1.5

MAX INL

1.0

T

V

= 25°C

A

= 0V

REF

= 3V

0.5

DD

AD5443

T

= 25°C

= 5V

A

0

MAX DNL

MIN INL

V

DD

AD5443

0.1

0

–0.5

–1.0

–1.5

–2.0

–0.1

–0.2

–0.3

MIN INL

MIN DNL

2

3

4

5

6

7

8

9

10

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

REFERENCE VOLTAGE

V

(V)

BIAS

Figure 12. INL vs. Reference Voltage

Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

4

3

T

= 25°C

= 5V

T

V

= 25°C

A

MAX DNL

V

= 2.5V

DD

AD5443

REF

= 3V

DD

AD5443

2

MAX INL

1

0

–1

–2

–3

–4

–5

MIN DNL

MIN INL

MIN DNL

2

3

4

5

6

7

8

9

10

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

REFERENCE VOLTAGE

V

(V)

BIAS

Figure 13. DNL vs. Reference Voltage

Figure 16. Linearity vs. VBIAS Voltage Applied to IOUT2

5

4

0.5

0.4

T

V

= 25°C

= 0V

V

= 10V

A

REF

= 3V AND 5V

DD

3

0.3

V

= 5V

DD

2

0.2

1

0.1

GAIN ERROR

0

V

= 3V

DD

OFFSET ERROR

–1

–2

–3

–4

–5

–0.1

–0.2

–0.3

–0.4

–0.5

–60 –40 –20

0

20

40

60

80

100 120 140

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

TEMPERATURE (°C)

V

(V)

BIAS

Figure 14. Gain Error vs. Temperature

Figure 17. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2

Rev. G | Page 9 of 24

AD5426/AD5432/AD5443

Data Sheet

0.5

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T

V

= 25°C

T = 25°C

A

= 2.5V

REF

= 3V AND 5V

0.4

0.3

DD

GAIN ERROR

0.2

V

= 5V

DD

0.1

OFFSET ERROR

0

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 3V

2

DD

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0

1

3

4

5

V

(V)

INPUT VOLTAGE (V)

BIAS

Figure 18. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2

SYNC

Figure 21. Supply Current vs. Logic Input Voltage,

(SCLK), DATA = 0

3

1.6

1.4

T

V

= 25°C

A

= 0V

REF

= 5V

MAX INL

DD

2

1

AD5443

1.2

I

1 V 5V

OUT DD

1.0

0.8

0.6

0.4

0.2

0

MAX DNL

0

–1

–2

–3

MIN INL

I

1 V 3V

DD

OUT

MIN DNL

0.5

1.0

1.5

2.0

2.5

–40

–20

0

20

40

60

80

100

120

V

(V)

TEMPERATURE (°C)

BIAS

Figure 22. IOUT1 Leakage Current vs. Temperature

Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

4

3

T

V

= 25°C

A

= 2.5V

REF

= 5V

DD

AD5443

2

V

= 5V

DD

MAX DNL

1

ALL 0s

ALL 1s

0

MAX INL

MIN DNL

–1

–2

–3

–4

–5

V

= 3V

DD

ALL 1s

ALL 0s

MIN INL

–60 –40 –20

0

20

40

60

80

100 120 140

0.5

1.0

1.5

2.0

TEMPERATURE (°C)

V

(V)

BIAS

Figure 23. Supply Current vs. Temperature

Figure 20. Linearity vs. VBIAS Voltage Applied to IOUT2

Rev. G | Page 10 of 24

Data Sheet

AD5426/AD5432/AD5443

3.5

3

0

T

= 25°C

A

V

= ±0.15V, AD8038 C 1pF

C

REF

AD5443

LOADING 010101010101

3.0

2.5

2.0

1.5

1

V

= ±2V, AD8038 C 1pF

REF

C

V

= ±3.51V, AD8038 C 1.8pF

C

REF

V

= ±2V, AD8038 C 1.47pF

C

REF

–3

–6

–9

V

= ±0.15V, AD8038 C 1.47pF

C

REF

V

= 5V

CC

V

= 3V

CC

0.5

0

T

V

= 25°C

A

= 5V

DD

AD8038 AMPLIFIER

1

10

100

1k

10k

100k

1M

10M

100M

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 24. Supply Current vs. Update Rate

Figure 27. Reference Multiplying Bandwidth vs. Frequency and

Compensation Capacitor

6

0

–6

0.060

0.050

0.040

0.030

0.020

0.010

0

T

V

= 25°C

= 0V

LOADING

ZS TO FS

V

5V, 0V REF

ALL ON

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

A

DD

NRG = 2.049nVs

0x7FF TO 0x800

REF

AD8038 AMPLIFIER

–12

–18

–24

–30

–36

–42

–48

–54

–60

–66

–72

–78

–84

–90

–96

–102

C

= 1.8pF

COMP

AD5443

V

3V, 0V REF

DD

NRG = 0.088nVs

0x800 TO 0x7FF

V

3V, 0V REF

NRG = 1.877nVs

0x7FF TO 0x800

DD

DB2

DB1

DB0

T

V

= 25°C

A

= 5V

DD

V

5V, 0V REF

DD

V

= ±3.5V

= 1.8pF

–0.010

–0.020

REF

NRG = 0.119nVs,

0x800 TO 0x7FF

ALL OFF

C

COMP

AD8038 AMPLIFIER

1

10

100

1k

10k

100k

1M 10M 100M

0

50

100

150

200

250

300

FREQUENCY (Hz)

TIME (ns)

Figure 25. Reference Multiplying Bandwidth vs. Frequency and Code

Figure 28. Midscale Transition VREF = 0 V

0.2

0

–1.70

–1.71

–1.72

–1.73

–1.74

–1.75

–1.76

T

V

= 25°C

= 3.5V

V

5V, 3.5V REF

A

DD

NRG = 1.184nVs

0x7FF TO 0x800

REF

AD8038 AMPLIFIER

= 1.8pF

C

COMP

AD5443

V

3V, 3.5V REF

DD

–0.2

–0.4

NRG = 1.433nVs

0x7FF TO 0x800

V

3V, 3.5V REF

DD

NRG = 0.647nVs

0x800 TO 0x7FF

T

V

= 25°C

= 5V

A

–0.6

–0.8

DD

= ±3.5V

REF

V

5V, 3.5V REF, NRG = 0.364nVs,

C

= 1.8pF

DD

0x800 TO 0x7FF

COMP

AD8038 AMPLIFIER

1

10 100

1k

10k

100k

1M

10M

100M

0

50

100

150

200

250

300

FREQUENCY (Hz)

TIME (ns)

Figure 26. Reference Multiplying Bandwidth—All 1s Loaded

Figure 29. Midscale Transition VREF = 3.5 V

Rev. G | Page 11 of 24

AD5426/AD5432/AD5443

Data Sheet

20

100

80

60

40

20

0

T

V

= 25°C

= 3V

A

DD

AMPLIFIER = AD8038

MCLK = 200kHz

0

–20

MCLK = 500kHz

MCLK = 1MHz

–40

–60

FULL SCALE

–80

ZERO SCALE

T

= 25°C

A

–100

–120

V

= 3.5V

REF

AD8038 AMP

AD5443

1

10

100

1k

10k

100k

1M

10M

0

10

20

30

40

50

FREQUENCY (Hz)

f_OUT(kHz)

Figure 30. Power Supply Rejection vs. Frequency

Figure 33. Wideband SFDR vs. fOUT Frequency (AD5443)

–60

–65

–70

–75

–80

–85

–90

80

60

40

20

0

T

V

= 25°C

A

MCLK = 500kHz

= 3V

DD

= 3.5V p-p

REF

MCLK = 1MHz

MCLK = 200kHz

T

V

= 25°C

A

= 3.5V

REF

AD8038 AMP

AD5426

1

10

100

1k

10k

100k

1M

0

10

20

30

40

50

FREQUENCY (Hz)

f_OUT(kHz)

Figure 34. Wideband SFDR vs. fOUT Frequency (AD5426)

Figure 31. THD and Noise vs. Frequency

0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

T

V

= 25°C

A

T

= 25°C

A

= 3.5V

REF

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AD8038 AMPLIFIER

AD5443

V

IH

V

IL

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (Hz)

2.5

3.0

3.5

4.0

VOLTAGE (V)

4.5

5.0

5.5

Figure 35. Wideband SFDR fOUT = 50 kHz, Update = 1 MHz

Figure 32. Threshold Voltages vs. Supply Voltage

Rev. G | Page 12 of 24

Data Sheet

AD5426/AD5432/AD5443

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

T

V

= 25°C

T = 25°C

A

= 3.5V

V

= 3.5V

REF

AD8038 AMPLIFIER

AD5443

AD8038 AMPLIFIER

AD5443

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (Hz)

10

12

14

16

18

20

22

24

26

28

30

FREQUENCY (Hz)

Figure 36. Wideband SFDR fOUT = 20 kHz, Update = 1 MHz

Figure 38. Narrowband ( 50%) SFDR fOUT = 20 kHz, Update = 1 MHz

0

T

V

= 25°C

A

T

V

= 25°C

A

= 3.5V

REF

= 3.5V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

REF

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AD8038 AMPLIFIER

AD5443

AD8038 AMPLIFIER

AD5443

25

30

35

40

45

50

55

60

65

70

75

10

15

20

25

30

35

FREQUENCY (Hz)

Figure 37. Narrowband ( 50%) SFDR fOUT = 50 kHz, Update = 1 MHz

Figure 39. Narrowband ( 50%) IMD fOUT = 20 kHz, 25 kHz, Update = 1 MHz

Rev. G | Page 13 of 24

AD5426/AD5432/AD5443

Data Sheet

TERMINOLOGY

Relative Accuracy

Digital Feedthrough

Relative accuracy or endpoint nonlinearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for 0 and full scale and is normally expressed in LSBs

or as a percentage of full-scale reading.

When the device is not selected, high frequency logic activity

on the device digital inputs may be capacitively coupled to show

up as noise on the I_OUTpins and subsequently into the following

circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

Differential Nonlinearity

This is the error due to capacitive feedthrough from the DAC

reference input to the DAC I_OUT1 terminal, when all 0s are

loaded to the DAC.

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of −1 LSB maximum

over the operating temperature range ensures monotonicity.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum

of the harmonics of the DAC output to the fundamental value is

the THD. Usually only the lower order harmonics are included,

such as second to fifth.

Gain Error

Gain error or full-scale error is a measure of the output error

between an ideal DAC and the actual device output. For these

DACs, ideal maximum output is V_REF− 1 LSB. Gain error of the

DACs is adjustable to 0 with external resistance.

2

(

V₂+ V₃+ V₄+ V₅

V₁

Digital Intermodulation Distortion

)

THD = 20 log

Output Leakage Current

Output leakage current is current that flows in the DAC ladder

switches when these are turned off. For the I_OUT1 terminal, it

can be measured by loading all 0s to the DAC and measuring

the I_OUT1 current. Minimum current flows in the I_OUT2 line

when the DAC is loaded with all 1s.

Second-order intermodulation distortion (IMD) measurements

are the relative magnitude of the fa and fb tones generated

digitally by the DAC and the second-order products at 2fa − fb

and 2fb − fa.

Output Capacitance

Spurious-Free Dynamic Range (SFDR)

Capacitance from I_OUT1 or I_OUT2 to AGND.

SFDR is the usable dynamic range of a DAC before spurious

noise interferes or distorts the fundamental signal. It is the mea-

sure of the difference in amplitude between the fundamental

and the largest harmonically or nonharmonically related spur

from dc to full Nyquist bandwidth (half the DAC sampling rate,

or f_S/2). Narrow band SFDR is a measure of SFDR over an

arbitrary window size, in this case 50% of the fundamental.

Digital SFDR is a measure of the usable dynamic range of the

DAC when the signal is a digitally generated sine wave.

Output Current Settling Time

This is the amount of time it takes for the output to settle to a

specified level for a full-scale input change. For these devices, it

is specified with a 100 Ω resistor to ground.

The settling time specification includes the digital delay from

rising edge to the full-scale output charge.

SYNC

Digital-to-Analog Glitch Impulse

The amount of charge injected from the digital inputs to the

analog output when the inputs change state. This is normally

specified as the area of the glitch in either pA-s or nV-s

depending upon whether the glitch is measured as a current

or voltage signal.

Rev. G | Page 14 of 24

Data Sheet

AD5426/AD5432/AD5443

THEORY OF OPERATION

The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit

current output DACs consisting of a standard inverting R-2R

ladder configuration. A simplified diagram for the 8-bit AD5426 is

shown in Figure 40. The matching feedback resistor, R_FB, has a

value of R. The value of R is typically 10 kΩ (minimum 8 kΩ

and maximum 12 kΩ). If I_OUT1 and I_OUT2 are kept at the same

potential, a constant current flows in each ladder leg, regardless

of digital input code. Therefore, the input resistance presented

at V_REFis always constant and nominally of value R. The DAC

output (I_OUT) is code-dependent, producing various resistances

and capacitances. External amplifier choice should take into

account the variation in impedance generated by the DAC on

the amplifiers inverting input node.

Note that the output voltage polarity is opposite to the V_REF

polarity for dc reference voltages.

These DACs are designed to operate with either negative or

positive reference voltages. The V_DDpower pin is used by only the

internal digital logic to drive the DAC switches’ on and off states.

These DACs are also designed to accommodate ac reference

input signals in the range of −10 V to +10 V.

With a fixed 10 V reference, the circuit shown in Figure 41 gives

a unipolar 0 V to −10 V output voltage swing. When V_INis an ac

signal, the circuit performs 2-quadrant multiplication. Table 5

shows the relationship between digital code and expected output

voltage for unipolar operation (AD5426, 8-bit device).

R

V

REF

Table 5. Unipolar Code Table

2R

S1

2R

S2

2R

S3

2R

S8

2R

Digital Input

1111 1111

1000 0000

0000 0001

0000 0000

Analog Output (V)

R

−V_REF(255/256)

−V_REF(128/256) = −V_REF/2

−V_REF(1/256)

R

I

A

1

FB

OUT

I

2

DAC DATA LATCHES

AND DRIVERS

−V_REF(0/256) = 0

Figure 40. Simplified Ladder

V

R2

DD

Access is provided to the V_REF, R_FB, I_OUT1, and I_OUT2 terminals of

the DAC, making the device extremely versatile and allowing it

to be configured in several different operating modes. For example,

it can be configured to provide a unipolar output, 4-quadrant

multiplication in bipolar or single-supply modes of operation.

Note that a matching switch is used in series with the internal

R_FBfeedback resistor. If users attempt to measure R_FB, power

must be applied to V_DDto achieve continuity.

C1

V

R

DD

FB

AD5426/

AD5432/

AD5443

I

1

2

OUT

A1

V

REF

V

= 0

R1

OUT

TO –V

REF

SYNC SCLK SDIN GND

MICROCONTROLLER

AGND

NOTES

CIRCUIT OPERATION

Unipolar Mode

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Using a single op amp, these devices can easily be configured to

provide 2-quadrant multiplying operation or a unipolar output

voltage swing, as shown in Figure 41.

Figure 41. Unipolar Operation

When an output amplifier is connected in unipolar mode, the

output voltage is given by

D

V_OUT V_REF

2ⁿ

where D is the fractional representation of the digital word

loaded to the DAC, and n is the number of bits.

D = 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

= 0 to 4095 (12-bit AD5443)

Rev. G | Page 15 of 24

AD5426/AD5432/AD5443

Data Sheet

Bipolar Operation

Table 6. Bipolar Code Table

Digital Input

1111 1111

1000 0000

0000 0001

0000 0000

Analog Output (V)

In some applications, it may be necessary to generate full

4-quadrant multiplying operation or a bipolar output swing.

This can easily be accomplished by using another external

amplifier and some external resistors, as shown in Figure 42.

In this circuit, the second amplifier, A2, provides a gain of 2.

Biasing the external amplifier with an offset from the reference

voltage results in full 4-quadrant multiplying operation. The

transfer function of this circuit shows that both negative and

positive output voltages are created as the input data, D, which

is incremented from code zero (V_OUT= −V_REF) to midscale

(V_OUT= 0 V) to full scale (V_OUT= +V_REF).

+V_REF(127/128)

0

−V_REF(127/128)

−V_REF(128/128)

Stability

In the I-to-V configuration, the I_OUTof the DAC and the inverting

node of the op amp must be connected as close as possible and

proper PCB layout techniques must be employed. Since every

code change corresponds to a step function, gain peaking may

occur if the op amp has limited gain bandwidth product (GBP)

and there is excessive parasitic capacitance at the inverting node.

This parasitic capacitance introduces a pole into the open-loop

response that can cause ringing or instability in closed-loop

applications.

D











V_OUT= V

×

−V

REF



REF

2^{n − 1}

where D is the fractional representation of the digital word

loaded to the DAC and n is the resolution of the DAC.

An optional compensation capacitor, C1, can be added in parallel

with R_FBfor stability, as shown in Figure 41 and Figure 42. Too

small a value of C1 can produce ringing at the output, while

too large a value can adversely affect the settling time. C1 should

be found empirically, but 1 pF to 2 pF is generally adequate for

compensation.

D = 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

= 0 to 4095 (12-bit AD5443)

When V_INis an ac signal, the circuit performs 4-quadrant

multiplication.

Table 6 shows the relationship between digital code and the

expected output voltage for bipolar operation (AD5426,

8-bit device).

R3

20kΩ

R5

20kΩ

V

R2

DD

C1

V

R

FB

DD

R4

10kΩ

AD5426/

^REFAD5432/

AD5443

I

1

OUT

A1

V

REF

±10V

I

2

OUT

R1

A2

V

= –V

REF

SYNC SCLK SDIN GND

OUT

TO +V

REF

MICROCONTROLLER

AGND

NOTES

1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR

= 0V WITH CODE 10000000 LOADED TO DAC.

V

OUT

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH

SPEED AMPLIFIER.

Figure 42. Bipolar Operation

Rev. G | Page 16 of 24

Data Sheet

AD5426/AD5432/AD5443

V

DD

R1

R2

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

R

V

FB

DD

These DACs are specified and tested to guarantee operation

in single-supply applications. In the current mode circuit of

Figure 43, I_OUT2 and hence I_OUT1 is biased positive by an amount

A1

V

OUT

V

I

1

V

IN

OUT

REF

GND

applied to V_BIAS

.

V

DD

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

C1

R

DD

FB

I

1

2

OUT

A1

V

REF

OUT

IN

Figure 44. Single-Supply Voltage Switching Mode Operation

I

OUT

GND

It is important to note that V_INis limited to low voltages because

the switches in the DAC ladder no longer have the same source

drain drive voltage. As a result, their on resistance differs, which

degrades the linearity of the DAC.

A2

V

BIAS

Also, V_INmust not go negative by more than 0.3 V or an

internal diode turns on, exceeding the maximum ratings of the

device. In this type of application, the full range of multiplying

capability of the DAC is lost.

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE

REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 43. Single-Supply Current Mode Operation

POSITIVE OUTPUT VOLTAGE

In this configuration, the output voltage is given by

_OUT= {D × (R_FB/R_DAC) × (V_BIAS− V_IN)} + V_BIAS

Note that the output voltage polarity is opposite to the V_REF

polarity for dc reference voltages. To achieve a positive voltage

output, an applied negative reference to the input of the DAC

is preferred over the output inversion through an inverting

amplifier because of the resistor’s tolerance errors. To generate

a negative reference, the reference can be level shifted by an

op amp such that the V_OUTand GND pins of the reference

become the virtual ground and −2.5 V, respectively, as shown

in Figure 45.

V

As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095

(AD5443), the output voltage varies from

V

_OUT= V_BIASto V_OUT= 2 V_BIAS− V_IN

V_BIASshould be a low impedance source capable of sinking and

sourcing all possible variations in current at the I_OUT2 terminal

without any problems.

V

= 5V

DD

ADR03

It is important to note that V_INis limited to low voltages because

the switches in the DAC ladder no longer have the same source

drain drive voltage. As a result, their on resistance differs, which

degrades the linearity of the DAC. See Figure 15 to Figure 20.

V

IN

OUT

GND

C1

+5V

V

DD

R

FB

Voltage Switching Mode of Operation

I

1

2

OUT

A1

V

REF

V

= 0V

I

–2.5V

Figure 44 shows these DACs operating in the voltage switching

mode. The reference voltage, V_IN, is applied to the I_OUT1 pin,

OUT

TO +2.5V

OUT

GND

–5V

I

_OUT2 is connected to AGND, and the output voltage is available

at the V_REFterminal. In this configuration, a positive reference

voltage results in a positive output voltage, making single-

supply operation possible. The output from the DAC is voltage

at a constant impedance (the DAC ladder resistance), thus an

op amp is necessary to buffer the output voltage. The reference

input no longer sees a constant input impedance, but one that

varies with code. Therefore, the voltage input should be driven

from a low impedance source.

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS

A HIGH SPEED AMPLIFIER.

Figure 45. Positive Voltage Output with Minimum of Components

Rev. G | Page 17 of 24

AD5426/AD5432/AD5443

Data Sheet

DAC leakage current is also a potential error source in divider

circuits. The leakage current must be counterbalanced by an

opposite current supplied from the op amp through the DAC.

Since only a fraction D of the current into the VREF terminal is

routed to the IOUT1 terminal, the output voltage has to change

as follows:

ADDING GAIN

In applications where the output voltage is required to be greater

than V_IN, gain can be added with an additional external amplifier or

it can be achieved in a single stage. It is important to consider the

effect of temperature coefficients of the thin film resistors of the

DAC. Simply placing a resistor in series with the R_FBresistor causes

mismatches in the temperature coefficients, resulting in larger

gain temperature coefficient errors. Instead, the circuit shown

in Figure 46 is a recommended method of increasing the gain of

the circuit. R1, R2, and R3 should all have similar temperature

coefficients, but they need not match the temperature coefficients

of the DAC. This approach is recommended in circuits where

gains of greater than 1 are required.

Output Error Voltage due to DAC Leakage = (Leakage × R)/D

where R is the DAC resistance at the V_REFterminal. For a DAC

leakage current of 10 nA, R = 10 kΩ, and a gain (that is, 1/D) of 16,

the error voltage is 1.6 mV.

V

DD

V

IN

R

V

FB

DD

V

DD

I

1

OUT

V

REF

2

OUT

C1

GND

V

R

DD

FB

I

1

2

OUT

R1

A1

V

REF

OUT

IN

I

OUT

R3

R2

GND

V

OUT

GAIN = R2 + R3

R2

R1 = R2R3

R2 + R3

ADDITIONAL PINS OMITTED FOR CLARITY.

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 47. Current Steering DAC as a Divider or Programmable Gain Element

REFERENCE SELECTION

Figure 46. Increasing Gain of Current Output DAC

When selecting a reference for use with the AD5426 series of

current output DACs, pay attention to the references output

voltage temperature coefficient specification. This parameter not

only affects the full-scale error, but can also affect the linearity (INL

and DNL) performance. The reference temperature coefficient

should be consistent with the system accuracy specifications. For

example, an 8-bit system required to hold its overall specification to

within 1 LSB over the temperature range 0°C to 50°C dictates

that the maximum system drift with temperature should be less

than 78 ppm/°C. A 12-bit system with the same temperature

range to overall specification within 2 LSBs requires a maximum

drift of 10 ppm/°C. By choosing a precision reference with low

output temperature coefficient this error source can be minimized.

Table 7 suggests some references available from Analog Devices

that are suitable for use with this range of current output DACs.

DACS USED AS A DIVIDER OR PROGRAMMABLE

GAIN ELEMENT

Current-steering DACs are very flexible and lend themselves to

many different applications. If this type of DAC is connected as

the feedback element of an op amp and R_FBis used as the input

resistor as shown in Figure 47, then the output voltage is inversely

proportional to the digital input fraction, D.

For D = 1 − 2⁻ⁿthe output voltage is

V

_OUT= −V_IN/D = −V_IN/(1 − 2^−N

)

As D is reduced, the output voltage increases. For small values

of D, it is important to ensure that the amplifier does not saturate

and also that the required accuracy is met. For example, an 8-bit

DAC driven with the binary code 0x10 (00010000), that is, 16

decimal, in the circuit of Figure 47 should cause the output

voltage to be 16 × V_IN. However, if the DAC has a linearity

specification of 0.5 LSB, then D can in fact have the weight

anywhere in the range 15.5/256 to 16.5/256 so that the possible

output voltage will be in the range 15.5 V_INto 16.5 V_IN—an error of

+3% even though the DAC itself has a maximum error of 0.2%.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an

amplifier with low input bias currents and low input offset

voltage. The input offset voltage of an op amp is multiplied by

the variable gain (due to the code-dependent output resistance

of the DAC) of the circuit. A change in this noise gain between

two adjacent digital fractions produces a step change in the

output voltage due to the amplifier’s input offset voltage. This

output voltage change is superimposed on the desired change in

output between the two codes and gives rise to a differential

linearity error, which, if large enough, could cause the DAC to

be nonmonotonic. In general, the input offset voltage should be

Rev. G | Page 18 of 24

Data Sheet

AD5426/AD5432/AD5443

a fraction (~ <1/4) of an LSB to ensure monotonic behavior

when stepping through codes.

Provided the DAC switches are driven from true wideband low

impedance sources (V_INand AGND), they settle quickly.

Consequently, the slew rate and settling time of a voltage switching

DAC circuit is determined largely by the output op amp.

The input bias current of an op amp also generates an offset at

the voltage output as a result of the bias current flowing in the

feedback resistor, R_FB. Most op amps have input bias currents low

enough to prevent any significant errors in 12-bit applications.

To obtain minimum settling time in this configuration, it is

important to minimize capacitance at the V_REFof the DAC. This

is done by using low input capacitance buffer amplifiers and

careful board design. Most single-supply circuits include ground as

part of the analog signal range, which in turn requires an amplifier

that can handle rail-to-rail signals,. There is a large range of

single-supply amplifiers available from Analog Devices.

Common-mode rejection of the op amp is important in voltage

switching circuits since it produces a code-dependent error at

the voltage output of the circuit. Most op amps have adequate

common-mode rejection at an 8-, 10-, or 12-bit resolution.

Table 7. Suitable ADI Precision References

Part No.

ADR01

ADR02

ADR03

ADR06

ADR431

ADR435

ADR391

ADR395

Output Voltage (V)

Initial Tolerance (%) Temp Drift (ppm/°C) I_SS(mA)

Output Noise µV p-p Package

10

5

0.05

0.06

0.10

0.04

0.16

0.10

3

9

3

9

3

9

3

9

3

9

1

0.8

0.12

20

10

6

SOIC-8

TSOT-23, SC70

SOIC-8

TSOT-23, SC70

SOIC-8

5

2.5

3

2.5

5

6

TSOT-23, SC70

SOIC-8

TSOT-23, SC70

SOIC-8

10

3.5

8

SOIC-8

2.5

5

TSOT-23

8

TSOT-23

Table 8. Suitable ADI Precision Op Amps

0.1 Hz to 10 Hz

Noise (µV p-p) Supply Current (µA) Package

Part No.

OP97

OP1177

AD8551

AD8603

AD8628

Supply Voltage (V)

2 to 20

2.5 to 15

2.7 to 5

1.8 to 6

2.7 to 6

V_OS(Max) (µV)

I_B(Max) (nA)

25

60

5

50

5

0.1

2

0.05

0.001

0.1

0.5

0.4

1

2.3

0.5

600

500

975

50

SOIC-8

MSOP, SOIC-8

TSOT

850

TSOT, SOIC-8

Table 9. Suitable ADI High Speed Op Amps

Part No.

AD8065

AD8021

AD8038

AD9631

Supply Voltage (V)

BW @ A_CL(MHz)

Slew Rate (V/µs)

V_OS(Max) (µV) I_B(Max) (nA)

Package

5 to 24

2.5 to 12

3 to 12

145

490

350

320

180

100

425

1,300

1,500

1,000

3,000

10,000

6,000

10,500

750

SOIC-8, SOT-23, MSOP

SOIC-8, MSOP

SOIC-8, SC70-5

SOIC-8

2 to 6

7,000

Rev. G | Page 19 of 24

AD5426/AD5432/AD5443

Data Sheet

DB15 (MSB)

DB0 (LSB)

SERIAL INTERFACE

C3

C2

C1

C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DATA BITS

X

The AD5426/AD5432/AD5443 have an easy to use 3-wire inter-

face that is compatible with SPI/QSPI/MICROWIRE and DSP

interface standards. Data is written to the device in 16 bit words.

This 16-bit word consists of 4 control bits and either 8 , 10 , or 12

data bits as shown in Figure 48, Figure 49, and Figure 50. The

AD5443 uses all 12 bits of DAC data. The AD5432 uses 10 bits

and ignores the 2 LSBs, while the AD5426 uses 8 bits and ignores

the last 4 bits.

CONTROL BITS

Figure 48. AD5426 8-Bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C3

C2

C1

C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DATA BITS

X

CONTROL BITS

Figure 49. AD5432 10-Bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C3

C2

C1

C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DATA BITS

Low Power Serial Interface

CONTROL BITS

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, that is,

Figure 50. AD5443 12-Bit Input Shift Register Contents

SYNC

on the falling edge of

. The SCLK and DIN input buffers

SYNC SYNC

Function

SYNC

are powered down on the rising edge of

. The

of

SYNC

is an edge-triggered input that acts as a frame synchro-

the AD5426/AD5432/AD5443 needs to be synchronous with

the microprocessor control. Unfinished data frames are latched

into the part and will affect the output.

nization signal and chip enable. Data can be transferred into the

device only while is low. To start the serial data transfer,

SYNC

should be taken low observing the minimum

SYNC

DAC Control Bits C3 to C0

falling to SCLK falling edge setup time, t₄.

Control Bits C3 to C0 allow control of various functions of

the DAC, as seen in Table 10. Default settings of the DAC on

power-on are as follows: Data is clocked into the shift register

on falling clock edges and daisy-chain mode is enabled.

Device powers on with zero-scale load to the DAC register

and I_OUTlines.

Daisy-Chain Mode

Daisy-chain is the default power-on mode. Note that the SDO

line operates with a V_DDof 3.0 V to 5.5 V. To disable the daisy

chain function, write 1001 to the control word. In daisy-chain

mode, the internal gating on SCLK is disabled. The SCLK is

continuously applied to the input shift register when

is

SYNC

The DAC control bits allow the user to adjust certain features

on power-on, for example, daisy-chaining may be disabled if

not in use, active clock edge may be changed to rising edge, and

DAC output may be cleared to either zero scale or midscale.

The user may also initiate a readback of the DAC register

contents for verification purposes.

low. If more than 16 clock pulses are applied, the data ripples

out of the shift register and appears on the SDO line. This data

is clocked out on the rising edge of SCLK (this is the default, use

the control word to change the active edge) and is valid for the

next device on the falling edge (default). By connecting this line

to the D_INinput on the next device in the chain, a multidevice

interface is constructed. Sixteen clock pulses are required for

each device in the system. Therefore, the total number of clock

cycles must equal 16 N where N is the total number of devices

in the chain. See the timing diagram in Figure 4.

Table 10. DAC Control Bits

C3 C2 C1 C0 Function Implemented

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No operation (power-on default)

Load and update

Initiate readback

Reserved

Daisy-chain disable

Clock data to shift register on rising edge

Clear DAC output to zero scale

Clear DAC output to midscale

Reserved

When the serial transfer to all devices is complete,

should be taken high. This prevents any further data being

clocked into the input shift register. A burst clock containing

the exact number of clock cycles may be used and

high some time later. After the rising edge of

SYNC

taken

SYNC

, data is

SYNC

automatically transferred from each device’s input shift register

to the addressed DAC.

When control bits = 0000, the device is in no operation mode.

This may be useful in daisy-chain applications where the user

does not want to change the settings of a particular DAC in the

chain. Simply write 0000 to the control bits for that DAC and

the following data bits will be ignored. To re-enable the daisy-

chain mode, if disabled, a power recycle is required.

Reserved

Rev. G | Page 20 of 24

Data Sheet

AD5426/AD5432/AD5443

Standalone Mode

After the falling edge of the 16th SCLK pulse, data is auto-

matically transferred from the input shift register to the DAC.

For another serial transfer to take place, the counter must be

After power-on, write 1001 to the control word to disable daisy-

chain mode. The first falling edge of

counts the number of serial clocks, ensuring the correct number

of bits are shifted in and out of the serial shift registers. A rising

resets a counter that

SYNC

reset by the falling edge of

.

SYNC

edge on

during a write causes the write cycle to be aborted.

SYNC

Rev. G | Page 21 of 24

AD5426/AD5432/AD5443

Data Sheet

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration of

the power supply and ground return layout helps to ensure the

rated performance. The printed circuit board on which the

AD5426/AD5432/AD5443 is mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the DAC is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close to the device as possible.

Fast switching signals such as clocks should be shielded with

digital ground to avoid radiating noise to other parts of the

board and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micro-

strip technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of the

board is dedicated to ground plane while signal traces are placed

on the solder side.

The DAC should have ample supply bypassing of 10 µF in parallel

with 0.1 µF on the supply located as close to the package as

possible, ideally right up against the device. The 0.1 µF capacitor

should have low effective series resistance (ESR) and effective

series inductance (ESI), like the common ceramic types that

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching. Low

ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should

also be applied at the supplies to minimize transient disturbance

and filter out low frequency ripple.

It is good practice to employ compact, minimum lead length

PCB layout design. Leads to the input should be as short as

possible to minimize IR drops and stray inductance.

The PCB metal traces between V_REFand R_FBshould also be

matched to minimize gain error. To maximize on high frequency

performance, the I-to-V amplifier should be located as close to

the device as possible.

Rev. G | Page 22 of 24

Data Sheet

AD5426/AD5432/AD5443

OVERVIEW OF AD54xx AND AD55xx DEVICES

Table 11.

Part No.

AD5424

AD5426

AD5428

AD5429

AD5450

AD5432

AD5433

AD5439

AD5440

AD5451

AD5443

AD5444

AD5415

AD5405

AD5445

AD5447

AD5449

AD5452

AD5446

AD5453

AD5553

AD5556

AD5555

AD5557

AD5543

AD5546

AD5545

AD5547

Resolution

No. DACs

INL (LSB)

Interface

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Serial

Parallel

Package

RU-16, CP-20

RM-10

RU-20

Features

8

1

2

1

2

1

2

1

2

1

2

0.25

0.5

0.25

1

10 MHz BW, 17 ns CS pulse width

10 MHz BW, 50 MHz serial

10 MHz BW, 17 ns CS pulse width

10 MHz BW, 50 MHz serial

10 MHz BW, 17 ns CS pulse width

10 MHz BW, 50 MHz serial

10 MHz BW, 17 ns CS pulse width

10 MHz BW, 50 MHz serial

50 MHz serial interface

8

RU-10

RJ-8

RM-10

RU-20, CP-20

RU-16

10

12

14

16

RU-24

RJ-8

RM-10

RM-8

RU-24

CP-40

0.5

1

10 MHz BW, 50 MHz serial

10 MHz BW, 17 ns CS pulse width

10 MHz BW, 50 MHz serial

1

RU-20, CP-20

RU-24

1

0.5

1

2

1

RU-16

RJ-8, RM-8

RM-8

UJ-8, RM-8

RM-8

RU-28

10 MHz BW, 50 MHz serial

4 MHz BW, 50 MHz serial clock

4 MHz BW, 20 ns WR pulse width

4 MHz BW, 50 MHz serial clock

4 MHz BW, 20 ns WR pulse width

4 MHz BW, 50 MHz serial clock

4 MHz BW, 20 ns WR pulse width

4 MHz BW, 50 MHz serial clock

4 MHz BW, 20 ns WR pulse width

1

RM-8

RU-38

2

RM-8

RU-28

2

RU-16

RU-38

Rev. G | Page 23 of 24

AD5426/AD5432/AD5443

OUTLINE DIMENSIONS

Data Sheet

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 51. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Resolution (Bit) INL (LSB) Temperature Range

Package Description Package Option Branding

AD5426YRM

8

0.25

0.5

1

−40°C to +125°C

10-Lead MSOP

Evaluation Board

RM-10

D1Q

D6W

D1R

D1R#

D1S

D1S#

AD5426YRM-REEL

AD5426YRM-REEL7

AD5426YRMZ

AD5426YRMZ-REEL

AD5426YRMZ-REEL7

AD5432YRM

10

12

AD5432YRMZ

AD5432YRMZ-REEL

AD5432YRMZ-REEL7

AD5443YRM

AD5443YRM-REEL

AD5443YRM-REEL7

AD5443YRMZ

AD5443YRMZ-REEL

AD5443YRMZ-REEL7

EV-AD5443/46/53SDZ

1

¹Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

registered trademarks are the property of their respective owners.

D03162-0-6/13(G)

Rev. G | Page 24 of 24


型号：	AD5443YRMZ-REEL7
厂家：	ADI
描述：	8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface 8位/ 10位/ 12位，高带宽乘法数模转换器，串行接口转换器数模转换器光电二极管
文件：	总24页 (文件大小：754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5443YRMZ-REEL7 [ADI]

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