AD5445BCP [ADI]
IC PARALLEL, WORD INPUT LOADING, 0.04 us SETTLING TIME, 12-BIT DAC, QCC20, 4 X 4 MM, CSP-20, Digital to Analog Converter;
| 型号： | AD5445BCP |
| 厂家： | 
ADI |
| 描述： | IC PARALLEL, WORD INPUT LOADING, 0.04 us SETTLING TIME, 12-BIT DAC, QCC20, 4 X 4 MM, CSP-20, Digital to Analog Converter 输入元件 |
| 文件： | 总12页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
HighBandwidthCMOS8-/10-/12-Bit
a
ParallelInterfaceMultiplyingDACs
AD5424/AD5433/AD5445*
Preliminary Technical Data
FEATURES
F U NC T IO NAL B LO C K D IAG RAM
+2.5 V to +5.5 V Supply Operation
Fast Parallel Interface (10ns WR cycle)
10MHz Multiplying Bandw idth
±10V Reference Input
V
V
REF
DD
20-Lead TSSOP and Chip Scale (4 x4m m ) Packages
8, 10 and 12 Bit Current Output DACs
Pin com patible 8, 10 & 12 Bit DACs in Chip Scale
Guaranteed Monotonic
R
FB
AD5424/
AD5433/
AD5445
R
8/10/12
BIT
R-2R DAC
I
OUT1
I
OUT2
Four Quadrant Multiplication
Pow er On Reset
Readback Function
Power On
Reset
DAC REGISTER
INPUT LATCH
5µA typical Pow er Consum ption
CS
R/W
APPLICATIONS
Portable Battery Pow ered Applications
Waveform Generators
Analog Processing
Instrum entation Applications
Program m able Am plifiers and Attenuators
Digitally-Controlled Calibration
Program m able Filters and Oscillators
Com posite Video
DB7/DB9/DB11
DB0
GND
DATA
INPUTS
Ultrasound
Gain, offset and Voltage Trim m ing
T he applied external reference input voltage (VREF
)
G E NE R AL D E S C R IP T IO N
determines the full scale output current. An integrated
feedback resistor (RFB) provides temperature tracking and
full scale voltage output when combined with an external
I-toV precision amplifier.
T he AD5424/AD5433/AD5445 are CMOS 8, 10 and
12-bit current output digital-to-analog converters (DACs)
respectively.
T hese devices operate from a +2.5 V to 5.5 V power sup-
ply, making them suited to battery powered applications
and many other applications.
T he AD5424 is available in small 20 lead CSP and 16
lead T SSOP packages, while the AD5433/AD5445 DACs
are available in small 20-lead CSP and T SSOP packages.
T hese DACs utilize Data readback allowing the user to
read the contents of the DAC register via the DB pins. On
power-up, the internal register and latches are filled with
zeros and the DAC outputs are at zero scale.
P R O D U C T H IG H LIG H T S
1. 10M H z M ultiplying Bandwidth
As a result of manufacture on a CMOS sub micron
process, they offer excellent four quadrant multiplication
characteristics, with large signal multiplying bandwidths
of up to 10MHz.
2. 4mm x 4mm Chip Scale Packages and small
T SSOP packages.
3. Low Voltage, Low Power Current Output DACs.
*US Patent N umber 5,689,257
REV. PrI Feb 2003
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 2003
Fax: 781/ 326-8703
PRELIMINARY TECHNICAL DATA
1
AD5424/AD5433/AD5445–SPECIFICATIONS
(V = 2.5 V to 5.5 V, V = +10 V, IOUT2 = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with
DD
REF
OP1177, AC performance with AD9631 unless otherwise noted.)
P ar am eter
M in
T yp
Max
Units
C onditions
ST AT IC PERFORMANCE
AD 5424
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5433
±0.5
±1
Guaranteed Monotonic
Guaranteed Monotonic
Guaranteed Monotonic
Resolution
10
±1
±1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5445
Resolution
12
±2
±1
±2
Bits
LSB
LSB
m V
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error T emp Coefficient2
Output Leakage Current
±5
ppm FSR/°C
±10
±50
nA
nA
V
Data = 0000H, TA = 25°C, IOUT 1
Data = 0000H, IOUT 1
Output Voltage Compliance Range
T BD
REFERENCE INPUT 2
Reference Input Range
VREF Input Resistance
±10
10
V
kΩ
8
12
Input resistance T C = -50ppm/°C
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
1.7
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.8
0.7
1
Input Leakage Current, IIL
Input Capacitance
10
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 1
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 0.5
DYNAMIC PERFORMANCE2
Reference Multiplying BW
10
T BD
MH z
MH z
VREF = 100 mV rms, DAC loaded all 1s
VREF = 6 V rms, DAC loaded all 1s
Output Voltage Settling T ime
AD5424
30
35
40
100
3
T BD
T BD
T BD
ns
ns
ns
V/µs
nV-s
dB
Measured to ½ LSB. RLOAD = 100Ω, CLOAD =
15pF. DAC latch alternately loaded with
0s and 1s.
AD5433
AD5445
Slew Rate
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
1 LSB change around Major Carry
DAC latch loaded with all 0s. Reference =
10kH z.
-75
Output Capacitance
2
4
pF
pF
nV-s
DAC Latches Loaded with all 0s
DAC Latches Loaded with all 1s
Feedthrough to DAC output with CS high
and Alternate Loading of all 0s and all 1s.
VREF = 6 V rms, All 1s loaded, f = 1kHz
Digital Feedthrough
5
T otal Harmonic Distortion
-85
-85
25
72
T BD
dB
dB
nV/
dB
d B
VREF = 5 V, Sinewave generated from digital code.
@ 1kHz
Output Noise Spectral Density
SFDR performance
Intermodulation D istortion
√H z
POWER REQUIREMENT S
Power Supply Range
IDD
Power Supply Sensitivity2
2.5
5.5
10
0.001
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
NOTES
1T emperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrI
PRELIMINARY TECHNICAL DATA
Single Supply Operation (Biased Mode)
AD5424/AD5433/AD5445
(V = 2.5 V to 5.5 V, V = +2 V, IOUT2 = 1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177,
DD
REF
AC performance with AD9631 unless otherwise noted.)
P ar am eter
M in
T yp
Max
Units
C onditions
ST AT IC PERFORMANCE
AD 5424
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5433
±0.5
±1
Guaranteed Monotonic
Guaranteed Monotonic
Guaranteed Monotonic
Resolution
10
±1
±1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD 5445
Resolution
12
±2
±1
±2
Bits
LSB
LSB
m V
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error T emp Coefficient2
Output Leakage Current
±5
ppm FSR/°C
±10
±50
nA
nA
V
Data = 0000H, T A = 25°C, IOUT 1
Data = 0000H, IOUT 1
Output Voltage Compliance Range
T BD
REFERENCE INPUT 2
Reference Input Range
VREF Input Resistance
tbd
10
V
kΩ
8
12
Input resistance T C = -50ppm/°C
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
1.7
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.8
0.7
1
Input Leakage Current, IIL
Input Capacitance
10
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 1
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD - 0.5
DYNAMIC PERFORMANCE2
Reference Multiplying BW
10
T BD
MH z
MH z
VREF = 100 mV rms, DAC loaded all 1s
VREF = 1 V rms, DAC loaded all 1s
Output Voltage Settling T ime
AD5424
30
35
40
100
3
T BD
T BD
T BD
ns
ns
ns
V/µs
nV-s
dB
Measured to ½ LSB. RLOAD = 100Ω, CLOAD =
15pF. DAC latch alternately loaded with
0s and 1s.
AD5433
AD5445
Slew Rate
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
1 LSB change around Major Carry
DAC latch loaded with all 0s. Reference =
10kH z.
-75
Output Capacitance
2
4
pF
pF
nV-s
DAC Latches Loaded with all 0s
DAC Latches Loaded with all 1s
Feedthrough to DAC output with CS high
and Alternate Loading of all 0s and all 1s.
Digital Feedthrough
5
T otal Harmonic Distortion
-85
-85
25
72
T BD
dB
dB
nV/
dB
d B
VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz
VREF = 2 V, Sinewave generated from digital code.
@ 1kHz
Output Noise Spectral Density
SFDR performance
Intermodulation D istortion
√H z
POWER REQUIREMENT S
Power Supply Range
IDD
Power Supply Sensitivity2
2.5
5.5
10
0.001
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
NOTES
1T emperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–3–
REV. PrI
PRELIMINARY TECHNICAL DATA
1
AD5424/AD5433/AD5445–SPECIFICATIONS
1,2
(V = 2.5 V to 5.5 V, V = +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless
DD
REF
TIMINGCHARACTERISTICS
otherwise noted.)
P ar am eter
Lim it at TMIN, TMAX
Units
Conditions/Com m ents
t1
t2
t3
t4
t5
t6
t7
t8
0
0
10
6
0
5
7
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
R/W to CS Setup T ime
R/W to CS Hold T ime
CS Low T ime (Write Cycle)
Data Setup T ime
Data H old T ime
R/W high to CS low
CS Min H igh T ime
Data Acess T ime
25
5
ns max
ns typ
t9
Bus Relinquish T ime
10
ns max
NOTES
1See Figure 1. T emperature range is as follows: B Version: –40°C to +105°C. Guaranteed by design and characterisation, not subject to production test.
2All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH )/2. Digital Output timing measured with Load circuit in
Figure 2.
Specifications subject to change without notice.
t6
t2
t2
t1
R/W
t7
t3
t4
DATA VALID
CS
t8
t9
t5
DATA
DATA VALID
Figure 1. Tim ing Diagram .
I
200uA
OL
TO
OUTPUT
PIN
V
+ V
2
OH (MIN)
OL (MAX)
C
50pF
L
I
200uA
OH
Figure 2. Load Circuit for Data Output Tim ing Specifications
–4–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
AB SO LUT E M AXIM UM RAT ING S1
(T A = +25°C unless otherwise noted)
VD D to GN D
VREF, RFB to GND
–0.3 V to +7 V
–12 V to +12 V
I
OUT 1, IOUT 2 to GND
–0.3 V to +7 V
-0.3V to VDD +0.3 V
Logic Inputs & Output2
Operating T emperature Range
Industrial (B Version)
–40°C to +105°C
–65°C to +150°C
+ 150°C
Storage T emperature Range
Junction T emperature
16 lead T SSOP θJA T hermal Impedance
20 lead T SSOP θJA T hermal Impedance
20 lead CSP θJA T hermal Impedance
Lead T emperature, Soldering (10seconds)
IR Reflow, Peak T emperature (< 20 seconds)
150°C /W
143°C /W
135°C /W
300°C
+ 235°C
NOTES
1Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent
damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periodsmayaffect device reliability. Onlyone absolute maximum ratingmay
be applied at any one time.
2Overvoltagesat DBx, CS and W/R, willbe clamped byinternaldiodes. Current should
be limited to the maximum ratings given.
O R D E R ING G U ID E
P ackage D escription
Model
Tem perature Range
P ackage O ption
AD 5424BRU
AD 5424BC P
AD 5433BRU
AD 5433BC P
AD 5445BRU
AD 5445BC P
-40 oC to +105 oC
-40 oC to +105 oC
-40 oC to +105 oC
-40 oC to +105 oC
-40 oC to +105 oC
-40 oC to +105 oC
T SSOP (T hin Shrink Small Outline Package)
CSP (Chip Scale Package)
T SSOP (T hin Shrink Small Outline Package)
CSP (Chip Scale Package)
T SSOP (T hin Shrink Small Outline Package)
CSP (Chip Scale Package)
RU -16
C P-20
RU -20
C P-20
RU -20
C P-20
C AUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrI
–5–
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
AD 5424 P IN F UNC T IO N D E SC RIP T IO N
P in
Mnem onic Function
TSSO P
C S P
1
2
19
20
I
I
OUT1
OUT2
DAC Current Output.
DAC Analog Ground. T his pin should normally be tied to the analog ground of the
system.
3
1
G N D
Ground Pin.
4-11
2-9
10-13
14
D B7-D B0 Parallel Data Bits 7 through 0.
N C
No internal connection
12
13
14
C S
Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data to
the input latch or to read data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When
high, used in conjunction with CS to readback contents of DAC Register.
Positive power supply input. T hese parts can be operated from a supply of +2.5 V to
+5.5 V.
15
16
R /W
VDD
15
16
17
18
VREF
RFB
DAC reference voltage input terminal.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to
external amplifier output.
P IN C O NF IG U R AT IO NS
TSSO P & CSP
IOUT1
IOUT2
GND
1
2
3
4
5
6
7
8
RFB
16
15
VREF
VDD
14
13
GND
DB7
DB6
DB5
DB4
1
2
3
4
5
AD5424
DB7
R/W
15 R/W
14 CS
13 NC
12 NC
11 NC
PIN 1
INDICATOR
DB6
DB5
CS
(Not to Scale) 12
11
AD5424
TOP VIEW
DB0(LSB)
DB4
DB3
10
9
DB1
DB2
–6–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
AD 5433 P IN F UNC T IO N D E SC RIP T IO N
P in
Mnem onic Function
TSSO P
C S P
1
2
19
20
IOUT
IOUT
1
2
DAC Current Output.
DAC Analog Ground. T his pin should normally be tied to the analog ground of the
system.
3
1
G N D
Ground Pin.
4-13
14, 15
16
2-11
D B9-D B0 Parallel Data Bits 7 through 0.
12, 13 N C
Not internally connected.
14
15
16
C S
Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data to
the input latch or to read data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When high,
used in conjunction with CS to readback contents of DAC Register.
Positive power supply input. T hese parts can be operated from a supply of +2.5 V to
+5.5 V.
17
18
R /W
VDD
19
20
17
18
VREF
RFB
DAC reference voltage input terminal.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to
external amplifier output.
P IN C O NF IG U R AT IO NS
TSSO P & CSP
IOUT1
1
2
3
4
5
6
7
RFB
20
19
IOUT2
GND
DB9
VREF
VDD
18
17
GND
DB9
DB8
DB7
DB6
1
2
3
4
5
15 R/W
14 CS
13 NC
12 NC
11 DB0
PIN 1
INDICATOR
AD5433
R/W
AD5433
TOP VIEW
CS
NC
(Not to Scale) 16
15
DB8
DB7
DB6
DB5
14
13
12
11
NC
8
9
DB0(LSB)
DB1
DB4
DB3
10
DB2
REV. PrI
–7–
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
AD 5445 P IN F UNC T IO N D E SC RIP T IO N
P in
Mnem onic
Function
TSSO P
C S P
1
2
19
20
I
I
OUT1
OUT2
DAC Current Output.
DAC Analog Ground. T his pin should normally be tied to the analog ground of the
system.
3
1
G N D
Ground Pin.
4-15
16
2-13
14
D B11-D B0
C S
Parallel Data Bits 7 through 0.
Chip Select Input. Active Low. Used in conjunction with R/W to load parallel data
to the input latch or to read data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When
high, used in conjunction with CS to readback contents of DAC Register.
Positive power supply input. T hese parts can be operated from a supply of +2.5 V to
+5.5 V.
17
18
15
16
R /W
VDD
19
20
17
18
VREF
RFB
DAC reference voltage input terminal.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to
external amplifier output.
P IN C O NF IG U R AT IO NS
TSSO P & CSP
IOUT1
1
RFB
20
19
IOUT2
GND
VREF
VDD
2
3
4
5
6
7
8
9
18
17
GND
DB11
DB10
DB9
1
2
3
4
5
AD5445
15 R/W
14 CS
13 DB0
12 DB1
11 DB2
PIN 1
R/W
DB11
INDICATOR
CS
DB10
DB9
(Not to Scale) 16
15
AD5445
TOP VIEW
DB0(LSB)
DB8
DB8
DB7
14
13
12
11
DB1
DB2
DB3
DB4
DB6
DB5 10
–8–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
T E R M I N O L O G Y
In t er m od u la t ion D ist or t ion
Rela tive Accu r a cy
T he DAC is driven by two combinded sine waves
references of frequencies fa and fb. Distortion products are
produced at sum and difference frequencies of mfa±nfb
where m, n = 0, 1, 2, 3... Intermodulation terms are those
for which m or n is not equal to zero. T he second order
terms include (fa +fb) and (fa - fb) and the third order
terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa -
2fb). IMD is defined as
Relative accuracy or endpoint nonlinearity is a measure of
the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero and full scale and is
normally expressed in LSBs or as a percentage of full scale
reading.
D iffer en t ia l Non lin ea r it y
Differential nonlinearity is the difference between the
measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of
±1 LSB max over the operating temperature range ensures
monotonicity.
IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
C om p lia n ce Volta ge Ra n ge
T he maximum range of (output) terminal voltage for
which the device will provide the specified characteristics.
G a in E r r or
Gain error or full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
For these DACs, ideal maximum output is VREF – 1 LSB.
Gain error of the DACs is adjustable to zero with external
resistance.
G E NE R AL D E S C R IP T IO N
D AC Section
T he AD5424, AD5433 and AD5445 are 8, 10 and 12 bit
current output DACs consisting of a standard inverting R-
2R ladder configuration. A simplified diagram for the 8-
Bit AD5424 is shown in Figure 3. T he feedback resistor
RFB has a value of R. T he value of R is typically 10kΩ
(minimum 8kΩ and maximum 12kΩ). If IOUT 1 and IOUT 2
are kept at the same potential, a constant current flows in
each ladder leg, regardless of digital input code.
T herefore, the input resistance presented at VREF is always
constant.
O u tp u t Lea ka ge C u r r en t
Output leakage current is current which flows in the DAC
ladder switches when these are turned off. For the IOUT 1
terminal, it can be measured by loading all 0s to the DAC
and measuring the IOUT 1 current. Minimum current will
flow in the IOUT 2 line when the DAC is loaded with all 1s
O u t p u t C a p a cit a n ce
Capacitance from IOUT 1 or IOUT 2 to AGND.
O u tp u t C u r r en t Settlin g T im e
T his is the amount of time it takes for the output to settle
to a specified level for a full scale input change. For these
devices, it is specifed with a 100 Ω resistor to ground.
R
R
R
V
REF
2R
S1
2R
S2
2R
S3
2R
S8
2R
D igital to Analog Glitch lm pulse
R
R
A
FB
T he amount of charge injected from the digital inputs to
the analog output when the inputs change state. T his is
normally specified as the area of the glitch in either
pA-secs or nV-secs depending upon whether the glitch is
measured as a current or voltage signal.
I
OUT1
I
OUT 2
DAC DATA LATCHES
AND DRIVERS
Figure 3. Sim plified Ladder
D igit a l F eed t h r ou gh
Access is provided to the VREF, RFB, IOUT 1 and IOUT 2
terminals of the DAC, making the device extremely
versatile and allowing it to be configured in several
different operating modes, for example, to provide a
unipolar output, bipolar output or in single supply modes
of operation. in unipolar mode or four quadrant
multiplication in bipolar mode.
When the device is not selected, high frequency logic
activity on the device digital inputs is capacitivelly coupled
through the device to show up as noise on the IOUT pins
and subsequently into the following circuitry. T his noise is
digital feedthrough.
M u ltip lyin g F eed th r ou gh E r r or
T his is the error due to capacitive feedthrough from the
DAC reference input to the DAC IOUT 1 terminal, when all
o0s are loaded to the DAC.
Un ipolar M ode
Using a single op amp, these devices can easily be
configured to provide 2 quadrant multiplying operation or
a unipolar output voltage swing as shown in Figure 4.
H a r m on ic D ist or t ion
T he DAC is driven by an ac reference. T he ratio of the
rms sum of the harmonics of the DAC output to the
fundamental value is the T HD. Usually only the lower
order harmonices are included, such as second to fifth.
When an output amplifier is connected in unipolar mode,
the output voltage is given by:
VOUT = -D/2^n x VREF
2
2
2
2
T HD = 20log
√
(V2 + V3 + V4 + V5
)
Where D is the fractional representation of the digital
word loaded to the DAC and n is the resolution of the
D AC .
V1
REV. PrI
–9–
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
B ip ola r O p er a tion
D = 0 to 256 (8-Bit AD5424)
= 0 to 1024 (10-Bit AD5433)
= 0 to 4096 (12-Bit AD5445)
In some applications, it may be necessary to generate full
4-Quadrant multplying operation or a bipolar output
swing. T his can be easily accomplished by using another
external amplifier and some external resistors as shown in
Figure 5.
V
DD
R
2
When VIN is an ac signal, the circuit performs four-
quadrant multiplication.
C
1
RFB
IOUT1
IOUT2
GND
V
DD
V
REF
V
REF
T able II. shows the relationship between digital code and
the expected output voltage for bipolar operation
(AD 5426, 8-Bit device).
AD5424/33/45
R
1
V
= 0V to -V
REF
OUT
CS
R/W
Table II. Bipolar Code Table
AGND
DATA
INPUTS
NOTES:
1
D igital Input Analog O utput (V)
R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
1111 1111
1000 0000
0000 0001
0000 0000
+ VREF (127/128)
0
-VREF (127/128)
-VREF (128/128)
Figure 4. Unipolar Operation
With a fixed 10 V reference, the circuit shown above will
give an unipolar 0V to -10V output voltage swing. When
VIN is an ac signal, the circuit performs two-quadrant
multiplication.
T he following table shows the relationship between digital
code and expected output voltage for unipolar operation.
(AD 5424, 8-Bit device).
Table I. Unipolar Code Table
D igital Input Analog O utput (V)
1111 1111
1000 0000
0000 0001
0000 0000
-VREF (255/256)
-VREF (128/256) = -VREF/2
-VREF (1/256)
-VREF (0/256) = 0
R3
10kΩ
R2
C1
V
DD
R5
20kΩ
RFB
V
DD
R4
10kΩ
R1
IOUT1
IOUT2
V
A1
REF
± 10V
V
AD5424/33/45
REF
A2
V
= -V
to +V
REF
OUT
REF
GND
CS
R/W
AGND
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
NOTES:
1
DATA
INPUTS
OUT
2
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 5. Bipolar Operation (4 Quadrant Multiplication)
–10–
REV. PrI
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
O ver view of AD 54xx devices
P ar t #
R esolu t ion # D AC s I N L t S
In ter fa ce P a cka ge
F ea tu r es
AD 5 4 2 4 8
AD 5 4 2 5 8
AD 5 4 2 6 8
AD 5 4 2 8 8
AD 5 4 2 9 8
AD 5 4 3 2 1 0
AD 5 4 3 3 1 0
AD 5 4 3 9 1 0
AD 5 4 4 0 1 0
AD 5 4 4 3 1 2
AD 5 4 4 5 1 2
AD 5 4 4 7 1 2
AD 5 4 6 9 1 2
1
1
1
2
2
1
1
2
2
1
1
2
2
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
± 0.5 30n s
P arallel
S er ia l
S er ia l
P arallel
S er ia l
S er ia l
P arallel
S er ia l
P arallel
S er ia l
P arallel
P arallel
S er ia l
RU -16, C P -20 10 MH z BW, 10 ns C S Pulse Width
R M - 1 0
R M - 1 0
R U - 2 0
R U - 1 0
R M - 1 0
Byte Load,10 M H z BW, 50 M H z Serial
10 M H z BW, 50 M H z Serial
10 M H z BW, 10 ns C S Pulse Width
10 M H z BW, 50 M H z Serial
± 1
± 1
± 1
± 1
± 2
± 2
± 2
± 2
35n s
35n s
35n s
35n s
40n s
40n s
40n s
40n s
10 M H z BW, 50 M H z Serial
RU -20, C P -20 10 MH z BW, 10 ns C S Pulse Width
R U - 1 6
R U - 2 4
R M - 1 0
10 M H z BW, 50 M H z Serial
10 M H z BW, 10 ns C S Pulse Width
10 M H z BW, 50 M H z Serial
RU -20, C P -20 10 M H z BW, 10 ns CS Pulse Width
R U - 2 4
R U - 1 6
10 M H z BW, 10 ns CS Pulse Width
10 M H z BW, 10 ns CS Pulse Width
REV. PrI
–11–
PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445
O U T LINE D IM E NS IO NS
D imensions shown in inches and (mm).
20 Lead CSP
(C P - 20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.010 (0.25)
MIN
0.157 (4.0)
BSC SQ
BOTTOM
VIEW
0.017 (0.42)
0.009 (0.24)
16
15
20
1
PIN 1
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
0.080 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
INDICATOR
0.148 (3.75)
BSC SQ
TOP
VIEW
11
10
5
6
0.028 (0.70) MAX
0.026 (0.65) NOM
12o MAX
0.080 (2.00)
REF
0.035 (0.90) MAX
0.033 (0.85) NOM
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
20 Lead TSSO P
(RU- 20)
16 Lead TSSO P
(RU- 16)
0.201 (5.10)
0.193 (4.90)
0.260 (6.60)
0.252 (6.40)
16
9
20
11
10
1
8
1
PIN
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.0433
(1.10)
MAX
8o
0o
0.028 (0.70)
0.020 (0.50)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0079 (0.20)
0.0035 (0.090)
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. PrI
–12–
相关型号：
AD5445BRU
IC PARALLEL, WORD INPUT LOADING, 0.04 us SETTLING TIME, 12-BIT DAC, PDSO20, TSSOP-20, Digital to Analog Converter
ADI
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