AD5530BRU-REEL [ADI]
Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters; 串行输入，电压输出12位/ 14位数字 - 模拟转换器
| 型号： | AD5530BRU-REEL |
| 厂家： | 
ADI |
| 描述： | Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters |
| 文件： | 总20页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Serial Input, Voltage Output
12-/14-Bit Digital-to-Analog Converters
AD5530/AD5531
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
DD
SS
Pin-compatible 12-, 14-bit digital-to-analog converters
Serial input, voltage output
Maximum output voltage range of 10 V
Data readback
3-wire serial interface
Clear function to a user-defined voltage
Power-down function
AD5530/AD5531
REFIN
12-/14-BIT
DAC
R
R
V
OUT
R
R
REFAGND
LDAC
RBEN
DUTGND
CLR
DAC REGISTER
Serial data output for daisy-chaining
16-lead TSSOP
POWER-DOWN
CONTROL LOGIC
PD
SDIN
SHIFT REGISTER
SCLK SYNC
APPLICATIONS
GND
SDO
Industrial automation
Figure 1.
Automatic test equipment
Process control
General-purpose instrumentation
GENERAL DESCRIPTION
The AD5530/AD5531 are single 12- and 14-bit (respectively)
serial input, voltage output digital-to-analog converters (DAC).
The DAC output is buffered by a gain of two amplifier and
LDAC
referenced to the potential at DUTGND.
update the output of the DAC asynchronously. A power-down
PD
can be used to
They utilize a versatile 3-wire interface that is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data
is presented to the part in a 16-bit serial word format. Serial
data is available on the SDO pin for daisy-chaining purposes.
Data readback allows the user to read the contents of the DAC
register via the SDO pin.
pin ( ) allows the DAC to be put into a low power state, and
CLR
a
pin allows the output to be cleared to a user-defined
voltage, the potential at DUTGND.
The AD5530/AD5531 are available in 16-lead TSSOP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD5530/AD5531
TABLE OF CONTENTS
Features .............................................................................................. 1
PD
Function................................................................................ 13
Readback Function .................................................................... 13
CLR
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 5
Standalone Timing Characteristics............................................ 5
Daisy-Chaining and Readback Timing Characteristics.......... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
DAC Architecture....................................................................... 13
Serial Interface ............................................................................ 13
Function.............................................................................. 13
Output Voltage............................................................................ 14
Bipolar Configuration................................................................ 14
Microprocessor Interfacing........................................................... 15
AD5530/AD5531 to ADSP-21xx.............................................. 15
AD5530/AD5531 to 8051 Interface......................................... 15
AD5530/AD5531 to MC68HC11 Interface............................ 15
Applications Information.............................................................. 17
Optocoupler Interface................................................................ 17
Serial Interface to Multiple AD5530s or AD5531s................ 17
Daisy-Chaining Interface with Multiple AD5530s or
AD5531s ...................................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
1/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 28...................................................................... 17
3/06—Rev. 0 to Rev. A
Change to Table 3 ............................................................................. 5
Change to Figure 4 ........................................................................... 8
Change to Output Voltage Section............................................... 14
Change to Ordering Guide............................................................ 18
5/02—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD5530/AD5531
SPECIFICATIONS
VDD = 15 V 10%; VSS = −15 V 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
AD5530
AD5531
Unit
Test Conditions/Comments
ACCURACY
Resolution
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±±
±±
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Guaranteed monotonic over temperature
Typically within ±1 LSB
Typically within ±1 LSB
Gain Temperature Coefficient2
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
0 to 5
100
±1
0 to 5
100
±1
V min to V max
MΩ typ
μA max
Max output range ±10 V
Per input, typically ±20 nA
DUTGND INPUT2
DC Input Impedance
Max Input Current
Input Range
60
±0.3
−4 to +4
60
±0.3
−4 to +4
kΩ typ
mA typ
V min to V max
Max output range ±10 V
O/P CHARACTERISTICS2
Output Voltage Swing
Short-Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
DIGITAL I/O
±10
15
5
1200
0.5
±10
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
To 0 V
To 0 V
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL, Output Low Voltage
POWER REQUIREMENTS
VDD/VSS
2.4
0.±
±10
10
2.4
0.±
±10
10
V min
V max
μA max
pF max
V max
Total for all pins
3 pF typical
ISINK = 1 mA
0.4
0.4
+15/−15
+15/−15
V nom
±10ꢀ for specified performance
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
IDD
ISS
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
μA max
Outputs unloaded
Outputs unloaded
Typically 50 μA
IDD in Power-Down
1 Temperature range for B Version: −40°C to +±5°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 3 of 20
AD5530/AD5531
VDD = 12 V 10%; VSS = −12 V 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
AD5530
AD5531
Unit
Test Conditions/Comments
ACCURACY
Resolution
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±±
±±
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Guaranteed monotonic over temperature
Typically within ±1 LSB
Typically within ±1 LSB
Gain Temperature Coefficient2
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
0 to 4.096
100
±1
0 to 4.096
100
±1
V min to V max
MΩ typ
μA max
Max output range ±±.192 V
Per input, typically ±20 nA
DUTGND INPUT2
DC Input Impedance
Max Input Current
Input Range
60
±0.3
−3 to +3
60
±0.3
−3 to +3
kΩ typ
mA typ
V min to V max
Max output range ±±.192 V
O/P CHARACTERISTICS2
Output Voltage Swing
Short-Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
DIGITAL I/O
±±.192
15
5
1200
0.5
±±.192
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
To 0 V
To 0 V
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL, Output Low Voltage
POWER REQUIREMENTS
VDD/VSS
2.4
0.±
±10
10
2.4
0.±
±10
10
V min
V max
μA max
pF max
V max
Total for all pins
3 pF typical
ISINK = 1 mA
0.4
0.4
+12/−12
+12/−12
V nom
±10ꢀ for specified performance
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
IDD
ISS
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
μA max
Outputs unloaded
Outputs unloaded
Typically 50 μA
IDD in Power-Down
1 Temperature range for B Version: −40°C to +±5°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 20
AD5530/AD5531
AC PERFORMANCE CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter
B Version Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
20
μs typ
Full-scale change to ±ꢁ LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
Slew Rate
Digital-to-Analog Glitch Impulse
1.3
120
V/μs typ
nV-s typ
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
0.5
100
nV-s typ
nV/√Hz typ
Effect of input bus activity on DAC output under test.
All 1s loaded to DAC.
STANDALONE TIMING CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 4.
Parameter1, 2
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
7
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
Data setup time
Data hold time
SYNC high to LDAC low
LDAC pulse width
140
60
60
50
40
50
40
15
5
t5
t6
t7
t±
t9
t10
t11
t12
50
5
LDAC high to SYNC low
50
CLR
pulse width
1 Guaranteed by design, not subject to production test.
2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10ꢀ to
90ꢀ of VDD) and timed from a voltage level of (VIL + VIH)/2.
t1
t3
SCLK
t2
t4
t5
SYNC
SDIN
t6
t7
t8
MSB
LSB
DB0
DB15
DB14
DB11
t9
t11
1
LDAC
t10
t12
CLR
1
LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
Figure 2. Timing Diagram for Standalone Mode
Rev. B | Page 5 of 20
AD5530/AD5531
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 5.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
2
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
SCLK frequency
SCLK cycle time
SCLK low time
SCLK high time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Min SYNC high time
500
200
200
50
t5
40
t6
50
t7
t±
40
15
50
Data setup time
Data hold time
CLR pulse width
t12
t13
t14
t15
t16
t17
130
50
50
SCLK falling edge to SDO valid
SCLK falling edge to SDO invalid
RBEN to SCLK falling edge setup time
RBEN hold time
50
100
RBEN falling edge to SDO valid
1 Guaranteed by design, not subject to production test.
2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10ꢀ to
90ꢀ of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 SDO; RPULLUP = 5 kΩ, CL = 15 pF
t1
t3
SCLK
t2
t4
t5
SYNC
SDIN
t6
t7
t8
MSB
LSB
DB15
DB14
DB11
DB0
t13
t14
DB11
MSB
LSB
DB0
SDO
(DAISY-
CHAINING)
DB15
t15
t16
RBEN
t13
t17
t14
SDO
(READBACK)
0
0
RB13
RB0
LSB
MSB
Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode
Rev. B | Page 6 of 20
AD5530/AD5531
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD to GND
−0.3 V to +17 V
VSS to GND
+0.3 V to −17 V
Digital Inputs to GND
SDO to GND
−0.3 V to VDD + 0.3 V
−0.3 V to +6.5 V
REFIN to REFAGND
−0.3 V to +17 V
REFIN to GND
REFAGND to GND
DUTGND to GND
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
ESD CAUTION
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature (TJ MAX
Package Power Dissipation
Thermal Impedance θJA
TSSOP (RU-16)
−40°C to +±5°C
−65°C to +150°C
150°C
)
(TJ MAX – TA)/θJA
150.4°C/W
300°C
235°C
Lead Temperature (Soldering 10 sec)
IR Reflow, Peak Temperature (<20 sec)
Rev. B | Page 7 of 20
AD5530/AD5531
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFAGND
REFIN
LDAC
SDIN
1
2
3
4
5
6
7
8
16
15
V
V
DD
OUT
14 DUTGND
13
AD5530/
AD5531
TOP VIEW
(Not to Scale)
V
SS
SYNC
RBEN
SCLK
SDO
12 NC
11 GND
10 PD
9
CLR
NC = NO CONNECT
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
REFAGND
REFIN
Description
1
2
3
For bipolar ±10 V output range, this pin should be tied to 0 V.
This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output.
Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC
register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC.
LDAC
4
5
6
SDIN
SYNC
RBEN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK.
Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK.
Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data
from the DAC register is shifted out on the SDO pin on each rising edge of SCLK.
7
±
SCLK
SDO
Clock Input. Data is clocked into the input register on the falling edge of SCLK.
Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be
used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it
should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left
high impedance.
9
CLR
Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to DUTGND. The contents of the registers
are untouched.
10
11
12
13
14
15
16
PD
This allows the DAC to be put into a power-down state.
GND
NC
VSS
DUTGND
VOUT
VDD
Ground Reference.
Do not connect anything to this pin.
Negative Analog Supply Voltage. −12 V ± 10ꢀ or −15 V ± 10ꢀ, for specified performance.
VOUT is referenced to the voltage applied to this pin.
DAC Output.
Positive Analog Supply Voltage. 12 V ± 10ꢀ or 15 V ± 10ꢀ, for specified performance.
Rev. B | Page ± of 20
AD5530/AD5531
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.00
0.75
0.50
0.25
0
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
DD
0.8
0.6
SS
SS
REFIN = +5V
REFAGND = 0V
REFIN = +5V
REFAGND = 0V
T
= 25°C
T = 25°C
A
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.25
–0.50
–0.75
–1.00
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
Figure 5. AD5530 Typical INL Plot
Figure 8. AD5531 Typical DNL Plot
0.5
0.4
2.0
1.5
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
DD
SS
SS
REFIN = +5V
REFIN = +5V
REFAGND = 0V
REFAGND = 0V
0.3
T
= 25°C
A
1.0
0.2
0.5
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 6. AD5530 Typical DNL Plot
Figure 9. AD5531 Typical INL Error vs. Temperature
1.0
0.8
V
V
= +15V
= –15V
2.0
1.5
DD
V
V
= +15V
= –15V
DD
SS
REFIN = +5V
REFAGND = 0V
SS
REFIN = +5V
REFAGND = 0V
0.6
T
= 25°C
1.0
A
0.4
0.2
0.5
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–40
–20
0
20
40
60
80
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
TEMPERATURE (°C)
Figure 10. AD5531 Typical DNL Error vs. Temperature
Figure 7. AD5531 Typical INL Plot
Rev. B | Page 9 of 20
AD5530/AD5531
3
0.03
0.02
0.01
0
V
V
= +15V
= –15V
DD
SS
REFIN = 0V
2
T
= 25°C
A
–40°C
POSITIVE INL
NEGATIVE INL
1
+25°C
+85°C
0
–1
–2
–3
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
10
11
12
13
14
15
16
17
REFIN VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11. AD5531 Typical INL Error vs. Reference Voltage
Figure 14. IDD in Power-Down vs. Supply
0
12
8
V
V
= +15V
= –15V
DD
SS
REFIN = +5V
REFAGND = 0V
–0.5
–1.0
–1.5
–2.0
–2.5
4
0
–4
–8
–12
V
V
= +15V
= –15V
DD
SS
REFIN = +5V
REFAGND = 0V
T
= 25°C
A
–40
–20
0
20
40
60
80
0
5
10
15
20
25
TEMPERATURE (°C)
TIME (µs)
Figure 12. Typical Full-Scale and Offset Error vs. Temperature
Figure 15. Settling Time
1.50
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
1.45
+85°C
1.40
+25°C
1.35
–40°C
1.30
V
V
= +15V
= –15V
DD
SS
1.25
1.20
REFIN = +5V
REFAGND = 0V
T
= 25°C
A
10
11
12
13
14
/V (V)
15
16
17
V
DD SS
TIME (750ns/DIV)
Figure 13. IDD vs. VDD/VSS
Figure 16. Typical Digital-to-Analog Glitch Impulse
Rev. B | Page 10 of 20
AD5530/AD5531
V
V
= +15V
= –15V
DD
V
OUT
SS
REFIN = +5V
REFAGND = 0V
T
= 25°C
A
PD
2V/DIV
2V/DIV
Figure 17. Typical Power-Down Time
Rev. B | Page 11 of 20
AD5530/AD5531
TERMINOLOGY
Gain Error
Relative Accuracy
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from ideal.
Relative accuracy or endpoint linearity is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Zero-Scale Error
Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.
Full-Scale Error
Digital Feedthrough
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF − 1 LSB.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.
Rev. B | Page 12 of 20
AD5530/AD5531
THEORY OF OPERATION
DAC ARCHITECTURE
REFIN
12-/14-BIT DAC
14
OUTPUT
The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode
DAC, and the AD5531 consists of a 14-bit R-2R section. Using a
5 V reference connected to the REFIN pin and REFAGND tied
to 0 V, a bipolar 10 V voltage output results. The DAC coding
is straight binary.
LDAC
SYNC
DAC REGISTER
14
SYNC REGISTER
14
SERIAL INTERFACE
Serial data on the SDIN input is loaded to the input register
SYNC
LDAC
under the control of SCLK,
, and
. A write
16-BIT SHIFT
REGISTER
SDIN
SDO
operation transfers a 16-bit word to the AD5530/AD5531.
Figure 2 and Figure 3 show the timing diagrams. Figure 18 and
Figure 19 show the contents of the input shift register. Twelve or
14 bits of the serial word are data bits; the rest are don’t cares.
Figure 20. Simplified Serial Interface
Data written to the part via SDIN is available on the SDO pin 16
clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
DB15 (MSB)
DB0 (LSB)
X
X
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
X X
PD FUNCTION
Figure 18. AD5530 Input Shift Register Contents
PD
The
pin allows the user to place the device into power-down
DB15 (MSB)
DB0 (LSB)
mode. While in this mode, power consumption is at a minimum;
the device draws only 50 μA of current. The
not affect the contents of the DAC register.
X
X
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
PD
function does
Figure 19. AD5531 Input Shift Register Contents
READBACK FUNCTION
SYNC
The serial word is framed by the signal,
. After a high-to-
, data is latched into the input shift
register on the falling edges of SCLK. There are two ways the
LDAC
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
SYNC
low transition on
RBEN
RBEN
and SDO (serial data out). When
the next falling edge of SCLK, the contents of the DAC register
RBEN
is taken low, on
DAC register and output can be updated. The
signal is
; depending on its status,
either a synchronous or asynchronous update is selected. If
SYNC
examined on the falling edge of
are transferred to the shift register.
can be used to frame
the readback data by leaving it low for 16 clock cycles, or it can
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word are 0s.
LDAC
is low, then the DAC register and output are updated on
SYNC
LDAC
is
the low-to-high transition of
. Alternatively, if
high upon sampling, the DAC register is not loaded with the
SYNC
new data on a rising edge of
register and the output voltage are updated by bringing
LDAC
. The contents of the DAC
LDAC
low any time after the 16-bit data transfer is complete.
can be tied permanently low if required. A simplified diagram
of the input loading circuitry is illustrated in Figure 20.
CLR FUNCTION
CLR
The falling edge of
potential as DUTGND. The contents of the registers remain
LDAC
causes VOUT to be reset to the same
unchanged, so the user can reload the previous data with
CLR LDAC
is tied low, the
after
output is loaded with the contents of the DAC register auto-
CLR
is asserted high. Alternatively, if
matically after
is brought high.
Rev. B | Page 13 of 20
AD5530/AD5531
+15V
OUTPUT VOLTAGE
The DAC transfer function is as follows:
2
AD586
4
V
OUT
6
5
V
OUT
(–10V TO +10V)
V
D
REFIN
OUT
9
V
OUT = 2 × [2 × ((REFIN − REFAGND) ×
) + 2 ×
2N
AD5530/
AD55311
R1
10kΩ
REFAGND − REFIN] − DUTGND
where:
C1
1µF
DUTGND
REFAGND GND
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
V
SS
SIGNAL
GND
SIGNAL
GND
BIPOLAR CONFIGURATION
–15V
Figure 21 shows the AD5530/AD5531 in a bipolar circuit
configuration. REFIN is driven by the AD586, 5 V reference,
and the REFAGND and DUTGND pins are tied to GND. This
results in a bipolar output voltage ranging from −10 V to +10 V.
Resistor R1 is provided (if required) for gain adjust. Figure 22
shows the transfer function of the DAC when REFAGND is tied
to 0 V.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Bipolar 10 V Operation
2 REFIN
0V
–2 REFIN
DAC INPUT CODE 000 001
(3)FFF
Figure 22. Output Voltage vs. DAC Input Codes (Hex)
Rev. B | Page 14 of 20
AD5530/AD5531
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5530/AD5531
requires a 16-bit data-word with data valid on the falling edge
of SCLK.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly because the DAC expects MSB first.
1
AD5530/
AD55311
80C51/80L51
P3.4
P3.3
RxD
TxD
LDAC
SYNC
SDIN
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in or asynchronously
SCLK
LDAC
under the control of
The contents of the DAC register can be read using the
RBEN
.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 24. AD5530/AD5531 to 8051 Interface
readback function.
is used to frame the readback data,
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
which is clocked out on SDO. Figure 23, Figure 24, and Figure 25
show these DACs interfacing with a simple 4-wire interface.
The serial interface of the AD5530/AD5531 can be operated
from a minimum of three wires.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. As the DAC expects
a 16-bit word, P3.3 must be left low after the first 8 bits are
transferred. After the second byte has been transferred, the P3.3
AD5530/AD5531 TO ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 23. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control register
should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
LDAC
line is taken high. The DAC can be updated using
P3.4 of the 8051.
via
AD5530/AD5531 TO MC68HC11 INTERFACE
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
Figure 25 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK of
the MC68HC11 drives the SCLK of the DAC, and the MOSI
SYNC
output drives the serial data lines, SDIN.
one of the port lines, in this case PC7.
is driven from
LDAC
output is updated using the
pin via the DSP. Alternatively,
input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
LDAC
the
1
AD5530/
AD55311
MC68HC11
AD5530/
AD55311
ADSP-2101/
PC6
LDAC
SYNC
SDIN
1
ADSP-2103
PC7
MOSI
SCK
FO
TFS
LDAC
SYNC
SDIN
SCLK
DT
SCLK
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 25. AD5530/AD5531 to MC68HC11 Interface
1
ADDITIONAL PINS OMITTED FOR CLARITY.
The MC68HC11 is configured for master mode, MSTR = 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of SCK.
Eight falling clock edges occur in the transmit cycle, so to load the
required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC input shift register.
Figure 23. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 TO 8051 INTERFACE
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 24. TxD of the 8051 drives SCLK of the
AD5530/AD5531, while RxD drives the serial data line, SDIN.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive
and
, respectively.
SYNC
LDAC
Rev. B | Page 15 of 20
AD5530/AD5531
LDAC
data back from the DAC register, the SDO line can be
RBEN
another port output controlling and framing the readback
data transfer.
is controlled by the PC6 port output. The DAC can be
connected to MISO of the MC68HC11, with
tied to
LDAC
updated after each 2-byte transfer by bringing
example does not show other serial lines for the DAC. If
were used, it could be controlled by port output PC5. To read
low. This
CLR
Rev. B | Page 16 of 20
AD5530/AD5531
APPLICATIONS INFORMATION
SERIAL INTERFACE TO MULTIPLE AD5530s OR
AD5531s
OPTOCOUPLER INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD5530/
AD5531 makes it ideal for opto-isolated interfaces because the
number of interface lines is kept to a minimum. Figure 26
shows a 4-channel isolated interface to the AD5530/AD5531.
To reduce the number of opto-isolators, if simultaneous
SYNC
Figure 27 shows how the
AD5530/AD5531s. All devices receive the same serial clock and
SYNC
pin is used to address multiple
serial data, but only one device receives the
signal at any
one time. The DAC addressed is determined by the decoder.
There is some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.
LDAC
updating is not required, then the
permanently low.
pin can be tied
AD5530/AD55311
SCLK
SYNC
V
CC
SDIN
SDIN
V
OUT
SCLK
V
µCONTROLLER
CONTROL OUT
CC
TO LDAC
TO SYNC
TO SCLK
TO SDIN
AD5530/AD55311
ENABLE
EN
SYNC
1
DECODER
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
SDIN
V
OUT
CODED
ADDRESS
DGND
SCLK
1
AD5530/AD55311
ADDITIONAL PINS
OMITTED FOR CLARITY.
SYNC
SDIN
V
OUT
SCLK
OPTOCOUPLER
AD5530/AD55311
Figure 26. Opto-Isolated Interface
SYNC
SDIN
V
OUT
SCLK
Figure 27. Addressing Multiple AD5530/AD5531s
DAISY-CHAINING INTERFACE WITH MULTIPLE AD5530s OR AD5531s
A number of these DAC parts can be daisy-chained together using the SDO pin. Figure 28 illustrates such a configuration.
V
DD
R
R
R
AD5530/AD55311
AD5530/AD55311
AD5530/AD55311
SCLK
SDIN
SCLK
SCLK
SCLK
SDIN
SDO
SDIN
SDO
SDIN
SDO
SYNC
SYNC
SYNC
SYNC
TO OTHER
SERIAL DEVICES
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 28. Daisy-Chaining Multiple AD5530/AD5531s
Rev. B | Page 17 of 20
AD5530/AD5531
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 29. 16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5530BRU
Temperature Range
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
Resolution INL (LSBs) DNL (LSBs) Package Description
Package Option
RU-16
RU-16
RU-16
RU-16
12
12
12
12
12
12
14
14
14
14
14
14
±1
±1
±1
±1
±1
±1
±2
±2
±2
±2
±2
±2
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
±1
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
AD5530BRU-REEL
AD5530BRU-REEL7
AD5530BRUZ1
AD5530BRUZ-REEL1
AD5530BRUZ-REEL71
AD5531BRU
AD5531BRU-REEL
AD5531BRU-REEL7
AD5531BRUZ1
AD5531BRUZ-REEL1
AD5531BRUZ-REEL71
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
1 Z = Pb-free part.
Rev. B | Page 1± of 20
AD5530/AD5531
NOTES
Rev. B | Page 19 of 20
AD5530/AD5531
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00938-0-1/07(B)
Rev. B | Page 20 of 20
相关型号：
AD5530BRUZ-REEL
SERIAL INPUT LOADING, 20us SETTLING TIME, 12-BIT DAC, PDSO16, LEAD FREE, MO-153AB, TSSOP-16
ADI
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