AD5541AACPZ-REEL7_技术文档

2.7 V to 5.5 V, Serial-Input,

Voltage Output, Unbuffered 16-Bit DAC

AD5541A

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

16-bit resolution

V

DD

11.8 nV/√Hz noise spectral density

1 μs settling time

AD5541A

V

16-BIT DAC

REF

OUT

1.1 nV-sec glitch energy

0.05 ppm/°C temperature drift

5 kV HBM ESD classification

0.375 mW power consumption at 3 V

2.7 V to 5.5 V single-supply operation

Hardware CS and LDAC functions

50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface

Power-on reset clears DAC output to zero scale

Available in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead

MSOP

AGND

V

LOGIC

CS

16-BIT DAC LATCH

CONTROL

LOGIC

DIN

SERIAL INPUT REGISTER

SCLK

LDAC

DGND

Figure 1. AD5541A

APPLICATIONS

V

DD

Automatic test equipment

Precision source-measure instruments

Data acquisition systems

AD5541A-1

V

16-BIT DAC

REF

OUT

Medical instrumentation

Aerospace instrumentation

Communications infrastructure equipment

Industrial control

16-BIT DAC LATCH

CS

DIN

CONTROL

LOGIC

SERIAL INPUT REGISITER

SCLK

CLR

GND

Figure 2. AD5541A-1

The AD5541A uses a versatile 3-wire interface that is compatible

with 50 MHz LPI, QLPI™, MICROWIRE™, and DLP interface

standards.

GENERAL DESCRIPTION

The AD5541A is a single, 16-bit, serial input, unbuffered voltage

output digital-to-analog converter (DAC) that operates from a

single 2.7 V to 5.5 V supply.

Table 1. Related Devices

The DAC output range extends from 0 V to V_REFand is guaranteed

monotonic, providing 1 ꢀLB INꢀ accuracy at 16 bits without

adjustment over the full specified temperature range of −40°C

to +125°C. The AD5541A is available in a 3 mm × 3 mm, 10-lead

ꢀFCLP and 10-lead MLOP. The AD5541A-1 is available in a

3 mm × 3 mm, 8-lead ꢀFCLP.

Part No.

Description

AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs

AD5541/AD5542 2.7 V to 5.5 V 16-bit voltage output DACs

AD5781/AD5791 18-/20-bit voltage output DACs

AD5024/AD5064 4.5 V to 5.5 V, 12-/16-bit quad channel DACs

AD5061

Single, 16-bit nanoDAC, 4 ꢀSꢁ ꢂNꢀ, SOT-23

16-bit, bipolar, voltage output DAC

AD5542A

Offering unbuffered outputs, the AD5541A achieves a 1 μs set-

tling time with low power consumption and low offset errors.

Providing low noise performance of 11.8 nV/√Hz and low

glitch, the AD5541A is suitable for deployment across multiple

end systems.

PRODUCT HIGHLIGHTS

1. 16-bit performance without adjustment.

2. 2.7 V to 5.5 V single operation.

3. ꢀow 11.8 nV/√Hz noise spectral density.

4. ꢀow 0.05 ppm/°C temperature drift.

5. 3 mm × 3 mm ꢀFCLP and MLOP packaging.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5541A* PRODUCT PAGE QUICK LINKS

Last Content Update: 09/27/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE DESIGNS

• CN0169

• CN0181

• CN0348

EVALUATION KITS

• AD5541A Evaluation Board

REFERENCE MATERIALS

DOCUMENTATION

Solutions Bulletins & Brochures

Data Sheet

• Digital to Analog Converters ICs Solutions Bulletin

• AD5541A: 2.7 V to 5.5 V, Serial-Input, Voltage- Output,

Unbuffered 16-Bit DAC

• Digital-to-Analog Converter ICs Solutions Bulletin, Volume

10, Issue 1

User Guides

DESIGN RESOURCES

• AD5541A Material Declaration

• PCN-PDN Information

• UG-1046: Evaluation Board for the AD5541A and the

AD5542A, 16-Bit, Accurate, High Precision DAC in LFCSP

with 1 μs Settling Time and 5 kV ESD Ratings

• Quality And Reliability

• Symbols and Footprints

SOFTWARE AND SYSTEMS REQUIREMENTS

• AD5446 IIO DAC Linux Driver

• AD5541A - No-OS Driver for Microchip Microcontroller

Platforms

DISCUSSIONS

View all AD5541A EngineerZone Discussions.

• AD5541A - No-OS Driver for Renesas Microcontroller

Platforms

SAMPLE AND BUY

• AD5791 IIO DAC Linux Driver

Visit the product page to see pricing options.

• AD5541A FMC-SDP Interposer & Evaluation Board / Xilinx

KC705 Reference Design

TECHNICAL SUPPORT

• AD5541A Pmod Xilinx FPGA Reference Design

Submit a technical question or find your regional support

number.

• BeMicro FPGA Project for AD5541A with Nios driver

TOOLS AND SIMULATIONS

• AD5541A IBIS Model

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

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AD5541A

TABLE OF CONTENTS

Features .............................................................................................. 1

Lerial Interface............................................................................ 14

Unipolar Output Operation...................................................... 15

Output Amplifier Lelection....................................................... 15

Force Lense Amplifier Lelection............................................... 16

Reference and Ground............................................................... 16

Power-On Reset.......................................................................... 16

Power Lupply and Reference Bypassing.................................. 16

Applications Information.............................................................. 17

Microprocessor Interfacing....................................................... 17

AD5541A to ADLP-BF531 Interface ....................................... 17

AD5541A to LPORT Interface.................................................. 17

ꢀayout Guidelines....................................................................... 17

Galvanically Isolated Interface ................................................. 17

Decoding Multiple DACs.......................................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Lpecifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ELD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

Digital-to-Analog Lection ......................................................... 14

REVISION HISTORY

3/11—Rev. 0 to Rev. A

Added Figure 5 and Figure 6............................................................8

Added Table 7; Renumbered Lequentially .....................................8

Changes to Figure 15...................................................................... 10

Changed V_REFto V_REF– 1 ꢀLB in Unipolar Output Operation

Lection.............................................................................................. 15

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 18

Added 10-ꢀead ꢀFCLP and 8-ꢀead ꢀFCLP.....................Universal

Changes to Features, General Description, and Product

Highlights Lections and Table 1 ..................................................... 1

Added Figure 2; Renumbered Lequentially .................................. 1

Changes to ꢀogic Inputs Parameter, Table 1................................. 3

Changes to Figure 3.......................................................................... 5

Changes to Table 5............................................................................ 6

Changes to Table 6............................................................................ 7

7/10—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5541A

SPECIFICATIONS

V_DD= 2.7 V to 5.5 V, 2.5 V ≤ V_REF≤ V_DD, AGND = DGND = 0 V, −40°C < T_A< +125°C,¹unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Condition

STATꢂC PERFORMANCE

Resolution

Relative Accuracy (ꢂNꢀ)

16

ꢁits

ꢀSꢁ

0.5

1.0

2.0

1.0

ꢁ grade

A grade

Guaranteed monotonic

Differential Nonlinearity (DNꢀ)

Gain Error

0.5

2

3

4

ꢀSꢁ

T_A= 25°C

−40°C < T_A< +85°C

−40°C < T_A< +125°C

Gain Error Temperature Coefficient

Zero-Code Error

0.1

0.3

ppm/°C

ꢀSꢁ

0.7

1.5

3

T_A= 25°C

−40°C < T_A< +85°C

−40°C < T_A< +125°C

ꢀSꢁ

Zero-Code Temperature Coefficient

DC Power Supply Rejection Ratio

OUTPUT CHARACTERꢂSTꢂCS²

Output Voltage Range

0.05

ppm/°C

ꢀSꢁ

1

ΔV_DD10ꢃ

0

V_REF− 1 ꢀSꢁ

V

Unipolar operation

DAC Output ꢂmpedance

6.25

kΩ

Tolerance typically 20ꢃ

DAC REFERENCE ꢂNPUT³

Reference ꢂnput Range

Reference ꢂnput Resistance

Reference ꢂnput Capacitance

2.0

9

V_DD

V

kΩ

pF

Unipolar operation

Code 0x0000

Code 0xFFFF

26

ꢀOGꢂC ꢂNPUTS

ꢂnput Current

ꢂnput ꢀow Voltage, V_ꢂNꢀ

1

0.4

0.8

μA

V

V_ꢀOGꢂC= 1.8 V to 5.5 V

V_ꢀOGꢂC= 2.7 V to 5.5 V

V_ꢀOGꢂC= 4.5 V to 5.5 V

V_ꢀOGꢂC= 2.7 V to 3.6 V

V_ꢀOGꢂC= 1.8 V to 2.7 V

ꢂnput High Voltage, V_ꢂNH

2.4

1.8

1.3

V

pF

V

ꢂnput Capacitance²

Hysteresis Voltage²

10

0.15

125

POWER REQUꢂREMENTS

V_DD

ꢂ_DD

V_ꢀOGꢂC

2.7

1.8

5.5

150

5.5

V

ꢄA

V

All digital inputs at 0 V, V_ꢀOGꢂC, or V_DD

V_ꢂH= V_ꢀOGꢂCor V_DDand V_ꢂꢀ= GND

ꢂ_ꢀOGꢂC

15

0.625

24

0.825

ꢄA

mW

All digital inputs at 0 V, V_ꢀOGꢂC, or V_DD

Power Dissipation

¹For 2.7 V ≤ V_ꢀOGꢂC≤ 5.5 V: −40°C < T_A< +125°C. For 1.8 V ≤ V_ꢀOGꢂC≤ 2.7 V: −40°C < T_A< +105°C.

²Guaranteed by design, but not subject to production test.

³Reference input resistance is code-dependent, minimum at 0x8555.

Rev. A | Page 3 of 20

AD5541A

AC CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, 2.5 V ≤ V_REF≤ V_DD, AGND = DGND = 0 V, −40°C < T_A< +125°C, unless otherwise noted.

Table 3.

Parameter

Min

Typ

1

17

1.1

2.2

1

0.2

92

80

74

Max

Unit

μs

Test Condition

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch ꢂmpulse

Reference −3 dꢁ ꢁandwidth

Reference Feedthrough

Digital Feedthrough

Signal-to-Noise Ratio

Spurious Free Dynamic Range

Total Harmonic Distortion

To ½ ꢀSꢁ of full scale, C_ꢀ= 10 pF

C_ꢀ= 10 pF, measured from 0ꢃ to 63ꢃ

1 ꢀSꢁ change around major carry

All 1s loaded

V/μs

nV-sec

MHz

mV p-p

nV-sec

dꢁ

All 0s loaded, V_REF= 1 V p-p at 100 kHz

dꢁ

Digitally generated sine wave at 1 kHz

DAC code = 0xFFFF, frequency 10 kHz,

V_REF= 2.5 V 1 V p-p

Output Noise Spectral Density

Output Noise

11.8

0.134

nV/√Hz

μV p-p

DAC code = 0x0000, frequency = 1 kHz

0.1 Hz to 10 Hz

Rev. A | Page 4 of 20

AD5541A

TIMING CHARACTERISTICS

V_DD= 5 V, 2.5 V ≤ V_REF≤ V_DD, V_INH= 90% of V_ꢀOGIC, V_INꢀ= 10% of V_ꢀOGIC, AGND = DGND = 0 V, −40°C < T_A< +105°C, unless otherwise

noted.

Table 4.

Limit at

1.8 ≤ V_LOGIC≤ 2.7 V

Limit at

2.7 V ≤ V_LOGIC≤ 5.5 V

Parameter^1,2

Unit

Description

f_SCꢀK

t₁

t₂

t₃

t₄

14

70

35

5

50

20

10

5

MHz max

ns min

SCꢀK cycle frequency

SCꢀK cycle time

SCꢀK high time

SCꢀK low time

CS low to SCꢀK high setup

CS high to SCꢀK high setup

SCꢀK high to CS low hold time

SCꢀK high to CS high hold time

Data setup time

Data hold time (V_ꢂNH= 90ꢃ of V_DD, V_ꢂNꢀ= 10ꢃ of V_DD)

Data hold time (V_ꢂNH= 3 V, V_ꢂNꢀ= 0 V)

ꢀDAC pulse width

t₅

5

t₆

5

t₇

10

35

5

t₈

t₉

t₁₀

t₁₁

t₁₂

10

4

5

20

10

15

5

20

10

15

CS high to ꢀDAC low setup

CS high time between active periods

¹Guaranteed by design and characterization. Not production tested.

²All input signals are specified with t_R= t_F= 1 ns/V and timed from a voltage level of (V_ꢂNꢀ+ V_ꢂNH)/2.

t₁

SCLK

t₂

t₃

t₆

t₅

t₇

t₄

CS

t₁₂

t₈

t₉

DIN

DB15

t₁₁

t₁₀

LDAC

Figure 3. Timing Diagram

Rev. A | Page 5 of 20

AD5541A

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Ltresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

V_DDto AGND

V_ꢀOGꢂCto DGND

−0.3 V to +6 V

Digital ꢂnput Voltage to DGND

−0.3 V to V_DD/V_ꢀOGꢂC

0.3 V

+

V_OUTto AGND

AGND to DGND

−0.3 V to V_DD+ 0.3 V

−0.3 V to +0.3 V

10 mA

ESD CAUTION

ꢂnput Current to Any Pin Except Supplies

Operating Temperature Range

ꢂndustrial (A, ꢁ Versions)

Storage Temperature Range

Maximum Junction Temperature (T_Jmax)

Package Power Dissipation

Thermal ꢂmpedance, θ_JA

ꢀFCSP (CP-10-9)

−40°C to +125°C

−65°C to +150°C

150°C

(T_Jmax − T_A)/θ_JA

50°C/W

62°C/W

135°C/W

ꢀFCSP (CP-8-11)

MSOP (RM-10)

ꢀead Temperature, Soldering

Peak Temperature¹

ESD²

260°C

5 kV

¹As per JEDEC Standard 20.

²Human body model (HꢁM) classification.

Rev. A | Page 6 of 20

AD5541A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

10

9

V

LOGIC

DD

V

DGND

LDAC

DIN

OUT

AD5541A

TOP VIEW

(Not to Scale)

AGND

8

REF

CS

7

6

SCLK

Figure 4. AD5541A 10-Lead MSOP Pin Configuration

Table 6. AD5541A Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

V_DD

V_OUT

AGND

REF

Analog Supply Voltage.

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry.

Voltage Reference ꢂnput for the DAC. Connect to an external 2.5 V reference. The reference can range from

2 V to V_DD.

CS

5

6

ꢀogic ꢂnput Signal. The chip select signal is used to frame the serial data input.

SCꢀK

Clock ꢂnput. Data is clocked into the serial input register on the rising edge of SCꢀK. The duty cycle must be

between 40ꢃ and 60ꢃ.

7

8

9

DꢂN

Serial Data ꢂnput. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge

of SCꢀK.

ꢀDAC ꢂnput. When this input is taken low, the DAC register is simultaneously updated with the contents of the

serial register data.

Digital Ground. Ground reference for digital circuitry.

ꢀogic Power Supply.

ꢀDAC

DGND

V_ꢀOGꢂC

10

Rev. A | Page 7 of 20

AD5541A

V

1

2

3

4

5

10 V

DD

LOGIC

REF

CS

1

2

3

4

8

7

6

5

GND

V

9

8

7

6

DGND

LDAC

DIN

OUT

AD5541A

TOP VIEW

(Not to Scale)

V

AD5541A-1

TOP VIEW

(Not to Scale)

DD

AGND

V

SCLK

DIN

REF

CS

OUT

SCLK

CLR

NOTES

1. FOR INCREASED RELIABILITY OF THE SOLDER

JOINTS AND MAXIMUM THERMAL CAPABILITY,

IT IS RECOMMENDED THAT THE PAD BE SOLDERED

TO THE SUBSTRATE, GND.

1. FOR INCREASED RELIABILITY OF THE SOLDER

JOINTS AND MAXIMUM THERMAL CAPABILITY,

IT IS RECOMMENDED THAT THE PAD BE SOLDERED

TO THE SUBSTRATE, GND.

Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration

Figure 6. AD5541A 10-Lead LFCSP Pin Configuration

Table 7. AD5541A-1 and AD5541A Pin Function Descriptions

Pin No.

Mnemonic

Description

8-Lead LFCSP 10-Lead LFCSP

1

4

REF

Voltage Reference ꢂnput for the DAC. Connect to an external 2.5 V reference. The

reference can range from 2 V to V_DD.

2

3

5

6

CS

ꢀogic ꢂnput Signal. The chip select signal is used to frame the serial data input.

SCꢀK

Clock ꢂnput. Data is clocked into the serial input register on the rising edge of SCꢀK.

Duty cycle must be between 40ꢃ and 60ꢃ.

4

5

7

DꢂN

CꢀR

Serial Data ꢂnput. This device accepts 16-bit words. Data is clocked into the serial input

register on the rising edge of SCꢀK.

Asynchronous Clear ꢂnput. The CꢀR input is falling edge sensitive. When CꢀR is low, all

ꢀDAC pulses are ignored. When CꢀR is activated, the serial input register and the DAC

register are cleared to zero scale.

N/A¹

6

2

9

1

N/A¹

3

10

8

V_OUT

DGND

V_DD

GND

AGND

V_ꢀOGꢂC

ꢀDAC

Analog Output Voltage from the DAC.

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage.

Ground Reference Point for ꢁoth Analog and Digital Circuitry.

Ground Reference Point for Analog Circuitry.

ꢀogic Power Supply.

N/A¹

7

8

N/A¹

ꢀDAC ꢂnput. When this input is taken low, the DAC register is simultaneously updated

with the contents of the serial input register.

EPAD

Exposed Pad. For increased reliability of the solder joints and maximum thermal

capability, it is recommended that the pad be soldered to the substrate, GND.

¹N/A means not applicable.

Rev. A | Page 8 of 20

AD5541A

TYPICAL PERFORMANCE CHARACTERISTICS

0.50

V

= 5V

V

= 5V

DD

= 2.5V

REF

0.25

0

0.25

0

–0.25

–0.50

–0.25

–0.50

–0.75

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE

Figure 7. Integral Nonlinearity vs. Code

Figure 10. Differential Nonlinearity vs. Code

0.25

0.75

V

= 5V

V

= 5V

DD

V

= 2.5V

V

= 2.5V

REF

0

–0.25

–0.50

–0.75

0.50

0.25

0

–0.25

–1.00

–0.50

–60 –40 –20

0

20

40

60

80

100 120 140

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE (°C)

Figure 8. Integral Nonlinearity vs. Temperature

Figure 11. Differential Nonlinearity vs. Temperature

0.50

0.75

V

T

= 5V

V

= 2.5V

DD

= 25°C

REF

= 25°C

T

A

0.25

0

0.50

0.25

0

DNL

–0.25

–0.50

INL

–0.25

INL

–0.75

–0.50

2

3

4

5

6

7

0

1

2

3

4

5

6

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

Figure 9. Linearity Error vs. Supply Voltage

Figure 12. Linearity Error vs. Reference Voltage

Rev. A | Page 9 of 20

AD5541A

3

1.5

1.0

V

= 5V

DD

V

T

= 5V

DD

= 2.5V

REF

= 2.5V

REF

T

= 25°C

A

= 25°C

A

2

1

0.5

0

–0.5

–1.0

–1.5

–1

–2

–3

–100

–50

0

50

100

150

–55

–5

45

95

TEMPERATURE (°C)

Figure 13. Gain Error vs. Temperature

Figure 16. Zero-Code Error vs. Temperature

200

150

100

50

160

T

= 25°C

A

V

= 5V

DD

= 2.5V

REF

140

120

100

80

T

= 25°C

A

REFERENCE VOLTAGE

V

= 5V

DD

SUPPLY VOLTAGE

= 2.5V

V

REF

60

40

20

0

–55

0

1

2

3

VOLTAGE (V)

4

5

6

–5

45

95

TEMPERATURE (°C)

Figure 14. Supply Current vs. Temperature

Figure 17. Supply Current vs. Reference Voltage or Supply Voltage

200

180

160

140

120

100

80

V

= 5V

DD

= 2.5V

REF

T

= 25°C

A

150

100

50

60

40

20

0

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

DIGITAL INPUT VOLTAGE (V)

0

10,000 20,000 30,000 40,000 50,000 60,000 70,000

CODE (Decimal)

Figure 15. Supply Current vs. Digital Input Voltage

Figure 18. Reference Current vs. Code

Rev. A | Page 10 of 20

AD5541A

V

T

= 2.5V

V

T

= 2.5V

REF

= 5V

REF

= 5V

DD

= 25°C

DD

= 25°C

A

100 •

90

•

• • • •

100

90

V

(1V/DIV)

OUT

DIN (5V/DIV)

V

(50mV/DIV)

OUT

V

(50mV/DIV)

GAIN = –216

1LSB = 8.2mV

OUT

10

•

• • • •

0%

0.5µs/DIV

2µs/DIV

Figure 19. Digital Feedthrough

Figure 22. Small Signal Settling Time

1.236

5

4

3

2

+125°C

+25°C

–55°C

CS

0

1.234

1.232

1.230

1.228

1.226

1.224

–5

–10

–15

–20

–25

–30

V

OUT

1

0

90

100

110

120

–0.5

0

0.5

1.0

1.5

2.0

I

SUPPLY (µA)

DD

TIME (ns)

Figure 20. Digital-to-Analog Glitch Impulse

Figure 23. Analog Supply Current Histogram

6

5

4

3

2

+125°C

+25°C

–55°C

V

= 2.5V

REF

= 5V

2µs/DIV

DD

T

= 25°C

A

•

CS (5V/DIV)

100 •

90

•

• • • •

10pF

50pF

100pF

200pF

10

1

0

•

• • • •

0%

V

(0.5V/DIV)

OUT

15

16

17

18

19

I

AT RAILS (µA)

LOGIC

Figure 21. Large Signal Settling Time

Figure 24. Digital Supply Current Histogram

Rev. A | Page 11 of 20

AD5541A

40

20

10

0

5

0

–20

–40

–60

–80

–5

0

–100

20

40

60

80

100

120

0

10,000 20,000 30,000 40,000 50,000 60,000 70,000

FREQUENCY (Hz)

Figure 25. 0.1 Hz to 10 Hz Output Noise

Figure 28. Total Harmonic Distortion

40

35

30

25

20

15

10

0

–10

–20

–30

–40

10

5

–50

–60

0

600

700

800

900

1000

1100

1200

1300

1400

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 26. Noise Spectral Density vs. Frequency,1 kHz

Figure 29. Multiplying Bandwidth

14

12

10

8

6

4

2

0

9600

9700

9800

9900 10,000 10,100 10,200 10,300 10,400

FREQUENCY (Hz)

Figure 27. Noise Spectral Density vs. Frequency, 10 kHz

Rev. A | Page 12 of 20

AD5541A

TERMINOLOGY

Digital-to-Analog Glitch Impulse

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or INꢀ is a measure of the

maximum deviation, in ꢀLBs, from a straight line passing

through the endpoints of the DAC transfer function. A typical

INꢀ vs. code plot is shown in Figure 7.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by

1 ꢀLB at the major carry transition. A digital-to-analog glitch

impulse plot is shown in Figure 20.

Differential Nonlinearity (DNL)

DNꢀ is the difference between the measured change and the

ideal 1 ꢀLB change between any two adjacent codes. A specified

differential nonlinearity of 1 ꢀLB maximum ensures mono-

tonicity. A typical DNꢀ vs. code plot is shown in Figure 10.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but it is measured when the DAC output is not updated.

Gain Error

CL

is held high while the LCꢀK and DIN signals are toggled. It

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range.

It is the deviation in slope of the DAC transfer characteristic

from ideal.

is specified in nV-sec and is measured with a full-scale code

change on the data bus, that is, from all 0s to all 1s and vice

versa. A typical digital feedthrough plot is shown in Figure 19.

Power Supply Rejection Ratio (PSRR)

Gain Error Temperature Coefficient

PLRR indicates how the output of the DAC is affected by changes

in the power supply voltage. The power supply rejection ratio is

expressed in terms of percent change in output per percent

change in V_DDfor full-scale output of the DAC. V_DDis varied by

10%.

Gain error temperature coefficient is a measure of the change

in gain error with changes in temperature. It is expressed in

ppm/°C.

Zero-Code Error

Zero-code error is a measure of the output error when zero

code is loaded to the DAC register.

Reference Feedthrough

Reference feedthrough is a measure of the feedthrough from the

Zero-Code Temperature Coefficient

This is a measure of the change in zero-code error with a

change in temperature. It is expressed in mV/°C.

V_REFinput to the DAC output when the DAC is loaded with all

0s. A 100 kHz, 1 V p-p is applied to V_REF. Reference feedthrough

is expressed in mV p-p.

Rev. A | Page 13 of 20

AD5541A

THEORY OF OPERATION

The AD5541A is a single, 16-bit, serial input, voltage output

DAC. It operates from a single supply ranging from 2.7 V to 5 V

and consumes typically 125 μA with a supply of 5 V. Data is written

to these devices in a 16-bit word format, via a 3- or 4-wire serial

interface. To ensure a known power-up state, this part is designed

with a power-on reset function. The output is reset to 0 V.

SERIAL INTERFACE

The AD5541A is controlled by a versatile 3- or 4-wire serial

interface that operates at clock rates of up to 50 MHz and is

compatible with LPI, QLPI, MICROWIRE, and DLP interface

standards. The timing diagram is shown in Figure 3. The

AD5541A has a separate serial input register from the 16-bit

DAC register that allows preloading of a new data value into the

serial input register without disturbing the present DAC output

voltage.

DIGITAL-TO-ANALOG SECTION

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 30. The DAC

architecture of the AD5541A is segmented. The four MLBs of

the 16-bit data-word are decoded to drive 15 switches, E1 to

E15. Each switch connects one of 15 matched resistors to either

AGND or V_REF. The remaining 12 bits of the data-word drive

the L0 to L11 switches of a 12-bit voltage mode R-2R ladder

network.

CL

Input data is framed by the chip select input, . After a high-

CL

to-low transition on , data is shifted synchronously and

latched into the serial input register on the rising edge of the

serial clock, LCꢀK. After 16 data bits have been loaded into the

CL

serial input register, a low-to-high transition on

contents of the shift register to the DAC register if

ꢀDAC

transfers the

ꢀDAC

is held

is high at this point, a low-to-high transition on

transfers the contents into the serial input register only.

R

low. If

CL

V

OUT

2R

S0

2R . . . . .

S1 . . . . .

2R

E1

2R . . . . .

E2 . . . . .

2R

E15

After a new value is fully loaded in the serial input register, it

can be asynchronously transferred to the DAC register by

S11

ꢀDAC

strobing the

pin. Data is loaded MLB first in 16-bit

CL

V

REF

words. Data can be loaded to the part only while

is low.

FOUR MSBs DECODED

INTO 15 EQUAL SEGMENTS

12-BIT R-2R LADDER

Figure 30. DAC Architecture

With this type of DAC configuration, the output impedance is

independent of code, whereas the input impedance seen by the

reference is heavily code dependent. The output voltage is

dependent on the reference voltage, as shown in the following

equation:

V_REF× D

V_OUT

where:

=

2^N

D is the decimal data-word loaded to the DAC register.

N is the resolution of the DAC.

For a reference of 2.5 V, the equation simplifies to the following:

2.5 × D

V_OUT

=

65,536

This gives a V_OUTof 1.25 V with midscale loaded and 2.5 V with

full scale loaded to the DAC.

The ꢀLB size is V_REF/65,536.

Rev. A | Page 14 of 20

AD5541A

UNIPOLAR OUTPUT OPERATION

OUTPUT AMPLIFIER SELECTION

This DAC is capable of driving unbuffered loads of 60 kΩ.

Unbuffered operation results in low supply current, typically

300 ꢁA, and a low offset error. The AD5541A provides a

unipolar output swing ranging from 0 V to V_REF− 1 ꢀLB.

Figure 31 shows a typical unipolar output voltage circuit. The

code table for this mode of operation is shown in Table 8. The

example includes the ADR421 2.5 V reference and the AD8628

low offset and zero-drift reference buffer.

For bipolar mode, a precision amplifier should be used and

supplied from a dual power supply. This provides the V_REF

output. In a single-supply application, selection of a suitable

op amp may be more difficult because the output swing of the

amplifier does not usually include the negative rail, in this case,

AGND. This can result in some degradation of the specified

performance unless the application does not use codes near zero.

The selected op amp must have a very low offset voltage (the

DAC ꢀLB is 38 ꢁV with a 2.5 V reference) to eliminate the need

for output offset trims. Input bias current should also be very

low because the bias current, multiplied by the DAC output

impedance (approximately 6 kꢂ), adds to the zero-code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code independent, but to minimize gain errors,

the input impedance of the output amplifier should be as high

as possible. The amplifier should also have a 3 dB bandwidth of

1 MHz or greater. The amplifier adds another time constant to

the system, thus increasing the settling time of the output. A

higher 3 dB amplifier bandwidth results in a shorter effective

settling time of the combined DAC and amplifier.

Table 8. Unipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

V_REF× (65,535/65,536)

V_REF× (32,768/65,536) = ½ V_REF

V_REF× (1/65,536)

0 V

1111 1111 1111 1111

1000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0000

Assuming a perfect reference, the unipolar worst-case output

voltage can be calculated from the following equation:

D

V_{OUT −UNI}

=

×

(

V_REF+ V_GE+ V_ZSE+ INL

)

2¹⁶

where:

_OUT−UNIis the unipolar mode worst-case output.

D is the code loaded to DAC.

V

_REFis the reference voltage applied to the part.

_GEis the gain error in volts.

_ZSEis the zero-scale error in volts.

INL is the integral nonlinearity in volts.

5V

1µF

0.1µF

2

AD8628

5V

10µF

V

IN

V

6

OUT

0.1µF

ADR421

0.1µF

4

SERIAL

INTERFACE

V

REF

DD

AD820/

CS

OP196

UNIPOLAR

OUTPUT

DIN

AD5541A

V

OUT

SCLK

EXTERNAL

OP AMP

DGND

AGND

Figure 31. Unipolar Output

Rev. A | Page 15 of 20

AD5541A

FORCE SENSE AMPLIFIER SELECTION

POWER-ON RESET

Use single-supply, low noise amplifiers. A low output impedance at

high frequencies is preferred because the amplifiers must be

able to handle dynamic currents of up to 20 mA.

The AD5541A has a power-on reset function to ensure that the

output is at a known state on power-up. On power-up, the DAC

register contains all 0s until the data is loaded from the serial

register. However, the serial register is not cleared on power-up;

therefore, its contents are undefined. When loading data initially

to the DAC, 16 bits or more should be loaded to prevent erroneous

data appearing on the output. If more than 16 bits are loaded,

the last 16 are kept, and if less than 16 bits are loaded, bits remain

from the previous word. If the AD5541A must be interfaced

with data shorter than 16 bits, pad the data with 0s at the ꢀLBs.

REFERENCE AND GROUND

Because the input impedance is code dependent, drive the refer-

ence pin from a low impedance source. The AD5541A operates

with a voltage reference ranging from 2 V to V_DD. References

below 2 V result in reduced accuracy. The full-scale output

voltage of the DAC is determined by the reference. Table 8

outlines the analog output voltage or particular digital codes.

POWER SUPPLY AND REFERENCE BYPASSING

If the application does not require separate force and sense

lines, tie the lines close to the package to minimize voltage

drops between the package leads and the internal die.

For accurate high resolution performance, it is recommended

that the reference and supply pins be bypassed with a 10 ꢁF

tantalum capacitor in parallel with a 0.1 ꢁF ceramic capacitor.

Rev. A | Page 16 of 20

AD5541A

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

LAYOUT GUIDELINES

Microprocessor interfacing to the AD5541A is via a serial bus

that uses standard protocol that is compatible with DLP proces-

sors and microcontrollers. The communications channel requires

a 3- or 4-wire interface consisting of a clock signal, a data signal,

and a synchronization signal. The AD5541A requires a 16-bit

data-word with data valid on the rising edge of LCꢀK.

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps to

ensure the rated performance. Design the printed circuit board

(PCB) on which the AD5541A is mounted so that the analog

and digital sections are separated and confined to certain areas

of the board. If the AD5541A is in a system where multiple

devices require an analog ground-to-digital ground connection,

make the connection at one point only. Establish the star

ground point as close as possible to the device.

AD5541A TO ADSP-BF531 INTERFACE

The LPI interface of the AD5541A is designed to be easily

connected to industry-standard DLPs and microcontrollers.

Figure 32 shows how the AD5541A can be connected to the

Analog Devices, Inc., Blackfin® DLP. The Blackfin has an

integrated LPI port that can be connected directly to the LPI

pins of the AD5541A.

The AD5541A should have ample supply bypassing of 10 ꢁF

in parallel with 0.1 ꢁF on each supply located as close to the

package as possible, ideally right up against the device. The

10 ꢁF capacitors are the tantalum bead type. The 0.1 ꢁF capaci-

tor should have low effective series resistance (ELR) and low

effective series inductance (ELI), such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

AD5541A

SPISELx

SCK

CS

SCLK

DIN

MOSI

ADSP-BF531

GALVANICALLY ISOLATED INTERFACE

PF9

LDAC

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that may occur. iCoupler®

products from Analog Devices provide voltage isolation in excess

of 2.5 kV. The serial loading structure of the AD5541A makes

the part ideal for isolated interfaces because the number of

interface lines is kept to a minimum. Figure 34 shows a 4-channel

isolated interface to the AD5541A using an ADuM1400. For

further information, visit http://www.analog.com/icouplers.

Figure 32. AD5541A to ADSP-BF531 Interface

AD5541A TO SPORT INTERFACE

The Analog Devices ADLP-BF527 has one LPORT serial port.

Figure 33 shows how one LPORT interface can be used to

control the AD5541A.

AD5541A

SPORT_TFS

SPORT_TSCK

SPORT_DTO

CS

SCLK

DIN

ADuM1400¹

CONTROLLER

V

IA

IB

IC

ID

OA

OB

OC

OD

TO

SERIAL

ENCODE

DECODE

SCLK

CLOCK IN

ADSP-BF527

GPIO0

LDAC

TO

DIN

SERIAL

DATA OUT

Figure 33. AD5541A to SPORT Interface

TO

CS

SYNC OUT

LOAD DAC

OUT

TO

LDAC

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 34. Isolated Interface

Rev. A | Page 17 of 20

AD5541A

DECODING MULTIPLE DACS

AD5541A

SCLK

DIN

CS

CL

The

number of DACs. All devices receive the same serial clock and

CL

pin of the AD5541A can be used to select one of a

V

OUT

DIN

V

DD

SCLK

serial data, but only one device receives the

signal at any one

time. The DAC addressed is determined by the decoder. There is

some digital feedthrough from the digital input lines. Using a

burst clock minimizes the effects of digital feedthrough on the

analog signal channels. Figure 35 shows a typical circuit.

ENABLE

AD5541A

EN

CS

CODED

ADDRESS

DECODER

DGND

DIN

SCLK

AD5541A

CS

DIN

SCLK

AD5541A

CS

DIN

SCLK

Figure 35. Addressing Multiple DACs

Rev. A | Page 18 of 20

AD5541A

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 36. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

3.10

3.00 SQ

0.50 BSC

2.90

6

10

PIN 1 INDEX

EXPOSED

PAD

1.74

1.64

1.49

AREA

0.50

0.40

0.30

5

1

PIN 1

INDICATOR

TOP VIEW

BOTTOM VIEW

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 37. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Rev. A | Page 19 of 20

AD5541A

2.44

2.34

2.24

3.10

3.00 SQ

2.90

0.50 BSC

8

5

PIN 1 INDEX

AREA

EXPOSED

PAD

1.70

1.60

1.50

0.50

0.40

0.30

4

1

PIN 1

INDICATOR

(R 0.15)

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-229-WEED

Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-11)

Dimensions shown in millimeters

ORDERING GUIDE

Power-On

Package

Option

Branding

Code

Model¹

INL

1 ꢀSꢁ

DNL

1 ꢀSꢁ

Reset to Code Temperature Range Package Description

AD5541AꢁRMZ

AD5541AꢁRMZ-REEꢀ7

AD5541AARMZ

AD5541AARMZ-REEꢀ7

AD5541AACPZ-REEꢀ7

AD5541AꢁCPZ-REEꢀ7

AD5541AꢁCPZ-500Rꢀ7

AD5541AꢁCPZ-1-Rꢀ7

EVAꢀ-AD5541ASDZ

Zero Scale

−40°C to +125°C

10-ꢀead MSOP

10-lead ꢀFCSP_WD

8-lead ꢀFCSP_WD

AD5541A Evaluation ꢁoard

RM-10

CP-10-9

CP-8-11

DEQ

DER

DEQ

DFG

1 ꢀSꢁ

2 ꢀSꢁ

1 ꢀSꢁ

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08516-0-3/11(A)

Rev. A | Page 20 of 20


型号：	AD5541AACPZ-REEL7
厂家：	ADI
描述：	2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDAC in 8-lead 3 mm x 3 mm LFCSP 光电二极管转换器
文件：	总21页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5541AACPZ-REEL7 [ADI]

相关型号：

AD5541AARMZ

AD5541AARMZ-REEL7

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AD5541ABCPZ-1

AD5541ABCPZ-1-RL7

AD5541ABCPZ-1-RL7

AD5541ABCPZ-500RL7

AD5541ABCPZ-REEL7

AD5541ABCPZ-REEL7

AD5541ABRMZ

AD5541ABRMZ

AD5541ABRMZ-REEL7