AD5543CRZ-REEL7 [ADI]
IC SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 16-BIT DAC, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8, Digital to Analog Converter;
| 型号： | AD5543CRZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 16-BIT DAC, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Current Output/
Serial Input, 16-/14-Bit DAC
AD5543/AD5553
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
16-bit resolution AD5543
14-bit resolution AD5553
1 ꢀSB DNꢀ
AD5543/AD5553
R
FB
V
DD
1 ꢀSB INꢀ
ꢀow noise: 12 nV/√Hz
ꢀow power: IDD = 10 μA
0.5 μs settling time
4Q multiplying reference input
2 mA full-scale current 20ꢁ, with VREF = 10 V
Built-in RFB facilitates voltage conversion
3-wire interface
I
V
DAC
OUT
REF
CS
16 OR 14
CONTROL
LOGIC
DAC
REGISTER
16 OR 14
CLK
SDI
GND
16-BIT/14-BIT SHIFT
REGISTER
Ultracompact MSOP-8 and SOIC-8 packages
APPꢀICATIONS
Figure 1.
Automatic test equipment
Instrumentation
1.0
0.8
Digitally controlled calibration
Industrial control PꢀCs
0.6
0.4
GENERAꢀ DESCRIPTION
0.2
The AD5543/AD5553 are precision 16-/14-bit, low power,
current output, small form factor digital-to-analog converters
(DAC). They are designed to operate from a single 5 V supply
with a 10 V multiplying reference.
0
–0.2
–0.4
–0.6
–0.8
–1.0
The applied external reference, VREF, determines the full-scale
output current. An internal feedback resistor (RFB) facilitates the
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.
CODE
A serial-data interface offers high speed, 3-wire microcontroller-
compatible inputs using serial data in (SDI), clock (CLK), and
Figure 2. Integral Nonlinearity
REF LEVEL /DIV
0.000dB 12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
CS
chip select ( ).
0xFFFF
0x8000
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
The AD5543/AD5553 are packaged in ultracompact (3 mm ×
4.7 mm) MSOP-8 and SOIC-8 packages.
0x0000
10
100
1k
10k
100k
1M
10M
START 10.000Hz
STOP 50 000 000.000Hz
Figure 3. Reference Multiplying Bandwidth
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
AD5543/AD5553
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 10
Serial Data Interface....................................................................... 11
ESD Protection Circuits ............................................................ 11
PCB Layout and Power Supply Bypassing .............................. 11
Applications Information.............................................................. 12
Stability ........................................................................................ 12
Positive Voltage Output............................................................. 12
Bipolar Output............................................................................ 12
Programmable Current Source ................................................ 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Circuit Operation ........................................................................... 10
REVISION HISTORY
7/09—Rev. A to Rev. B
Updated Format..................................................................Universal
Change to Features Section ............................................................. 1
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 15
2/03—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 3
12/02—Rev. 0: Initial Version
Rev. B | Page 2 of 16
AD5543/AD5553
SPECIFICATIONS
VDD = 5 V 10%, VSS = 0 V, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
N
Condition
5 V 10ꢁ
Unit
STATIC PERFORMANCE1
Resolution
1 LSB = VREF/216 = 153 μV when VREF = 10 V (AD5543)
1 LSB = VREF/214 = 610 μV when VREF = 10 V (AD5553)
Grade: AD5553C
16
14
1
Bits
Bits
Relative Accuracy
INL
LSB max
LSB max
LSB max
LSB max
nA max
nA max
mV typ/max
ppm/°C typ
Grade: AD5543C
Grade: AD5543B
Monotonic
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = TA max
Data = 0xFFFF
1
2
1
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
10
20
1/ 4
1
Full-Scale Gain Error
Full-Scale Tempco2
REFERENCE INPUT
VREF Range
Input Resistance
Input Capacitance2
ANALOG OUTPUT
Output Current
GFSE
TCVFS
VREF
RREF
CREF
−15/+15
V min/max
kΩ typ3
pF typ
5
5
IOUT
Data = 0xFFFF for AD5543
Data = 0x3FFF for AD5553
Code dependent
2
mA typ
pF typ
Output Capacitance2
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
INTERFACE TIMING 2, 4
Clock Input Frequency
Clock Width High
COUT
200
VIL
VIH
IIL
0.8
2.4
10
V max
V min
μA max
pF max
CIL
10
fCLK
tCH
tCL
tCSS
tCSH
tDS
50
10
10
0
MHz
ns min
ns min
ns min
ns min
ns min
ns min
Clock Width Low
CS to Clock Setup
Clock to CS Hold
10
5
10
Data Setup
Data Hold
tDH
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
VDD RANGE
IDD
PDISS
PSS
4.5/5.5
10
0.055
0.006
V min/max
μA max
mW max
ꢀ/ꢀ max
Logic inputs = 0 V
Logic inputs = 0 V
ΔVDD = 5ꢀ
Power Supply Sensitivity
Rev. B | Page 3 of 16
AD5543/AD5553
Parameter
AC CHARACTERISTICS4
Symbol
Condition
5 V 10ꢁ
Unit
Output Voltage Settling Time tS
To 0.1ꢀ of full scale,
0.5
μs typ
Data = 0x0000 to 0xFFFF to 0x0000 for AD5543
Data = 0x0000 to 0x3FFF to 0x0000 for AD5553
VREF = 5 V p-p, data = 0xFFFF
VREF = 0 V, data = 0x7FFF to 0x8000 for AD5543
Data = 0x0000, VREF = 100 mV rms, same channel
CS = 1, and fCLK = 1 MHz
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
BW
Q
VOUT/VREF
Q
THD
eN
4
7
−65
7
−85
12
MHz typ
nV-sec
dB
nV-sec
dB typ
nV/√Hz
VREF = 5 V p-p, data = 0xFFFF, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is
tied to the amplifier output. The +IN op amp is grounded, and the DAC IOUT is tied to the −IN op amp. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and are not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier.
4 All input control signals are specified with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V) and timed from a voltage level of 1.5 V.
Rev. B | Page 4 of 16
AD5543/AD5553
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance, θJA
8-Lead Surface Mount (MSOP-8)
8-Lead Surface Mount (SOIC-8)
Maximum Junction Temperature (TJ Max
Operating Temperature Range
Model B and Model C
−0.3 V to +8 V
−18 V to +18 V
−0.3 V to +8 V
−0.3 V to VDD + 0.3 V
50 mA
(TJ Max − TA )/θJA
ESD CAUTION
150°C/W
100°C/W
150°C
)
−40°C to +85°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature
RN-8, RM-8 (Vapor Phase, 60 sec)
RN-8, RM-8 (Infrared, 15 sec)
215°C
220°C
Rev. B | Page 5 of 16
AD5543/AD5553
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
SDI
1
2
3
4
8
7
6
5
CS
AD5543/
AD5553
V
DD
R
GND
FB
TOP VIEW
(Not to Scale)
V
I
OUT
REF
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
2
3
4
5
6
7
8
CLK
SDI
RFB
VREF
IOUT
GND
VDD
Clock Input. Positive-edge triggered, clocks data into shift register.
Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
Internal Matching Feedback Resistor. Connects to an external op amp for voltage output.
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
DAC Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output.
Analog and Digital Ground.
Positive Power Supply Input. Specified range of operation at 5 V 10ꢀ.
Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge. See Table 4 for
operation.
CS
Rev. B | Page 6 of 16
AD5543/AD5553
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
0
2048
4096
6144
CODE (Decimal)
8192 10,240 12,288 14,336 16,384
Figure 5. AD5543 Integral Nonlinearity Error
Figure 8. AD5553 Differential Nonlinearity Error
1.5
1.0
0.8
V
A
= 2.5V
REF
= 25°C
T
1.0
0.5
0
0.6
0.4
0.2
INL
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
GE
2
4
6
8
10
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
SUPPLY VOLTAGE V (V)
DD
Figure 6. AD5543 Differential Nonlinearity Error
Figure 9. Linearity Error vs. VDD
5
4
3
2
1
0
1.0
0.8
V
A
= 5V
DD
= 25°C
T
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IH
4.0
4.5
5.0
0
2048
4096
6144
CODE (Decimal)
8192 10,240 12,288 14,336 16,384
LOGIC INPUTVOLTAGEV (V)
Figure 7. AD5553 Integral Nonlinearity Error
Figure 10. Supply Current vs. Logic Input Voltage
Rev. B | Page 7 of 16
AD5543/AD5553
3.0
2.5
2.0
1.5
1.0
0.5
0
A2
–5V
DLY
67.72µs
0x5555
0x8000
0xFFFF
0x0000
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
5V
2V
136ns
Figure 11. AD5543 Supply Current vs. Clock Frequency
Figure 14. Settling Time
90
80
70
60
50
40
30
20
10
0
V
V
= 5V ± 10%
= 10V
DD
REF
CS (5V/DIV)
V
V
= 5V
DD
= 10V
REF
CODES 0x8000 ↔ 0x7FFF
V
(50mV/DIV)
OUT
0
0.5
1.0
1.5
2.0
2.5
TIME (µs)
3.0
3.5
4.0
4.5
5.0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 15. Midscale Transition and Digital Feedthrough
Figure 12. Power Supply Rejection Ratio vs. Frequency
REF LEVEL /DIV
0.000dB 12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
0xFFFF
0x8000
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
0x0000
10
100
1k
10k
100k
1M
10M
START 10.000Hz
STOP 50 000 000.000Hz
Figure 13. Reference Multiplying Bandwidth
Rev. B | Page 8 of 16
AD5543/AD5553
SDI
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
CLK
tDS
tDH
tCH
tCL
tCSS
tCSH
CS
Figure 16. AD5543 Timing Diagram
SDI
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
CLK
tDS
tDH
tCH
tCL
tCSS
tCSH
CS
Figure 17. AD5553 Timing Diagram
Table 4. Control-Logic Truth Table
CS
CꢀK
Serial Shift Register Function
DAC Register
Latched
X
H
No effect
↑+1
X1
X1
L
Shift register data advanced one bit
No effect
Shift register data transferred to DAC register
Latched
H
↑+1
Latched
New data loaded from serial register
1 ↑+ = positive logic transition; X = don't care.
Table 5. AD5543 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB
ꢀSB
B1
D1
B15
D15
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B0
D0
Table 6. AD5553 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB1
ꢀSB
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
1
CS
A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when returns to
logic high.
Rev. B | Page 9 of 16
AD5543/AD5553
CIRCUIT OPERATION
V
DD
The AD5543/AD5553 contain 16-/14-bit, current output,
digital-to-analog converters (DAC), serial input registers, and
DAC registers. Both converters use a 3-wire serial data interface.
U1
V
V
R
FB
DD
U2
I
V
OUT
REF
REF
DAC SECTION
V
V+
O
AD8628
GND
The DAC architecture uses a current steering R-2R ladder
design. Figure 18 shows the typical equivalent DAC structure.
The DAC contains a matching feedback resistor for use with an
external op amp (see Figure 19). With RFB and IOUT terminals
connected to the op amp output and inverting node, respectively,
a precision voltage output is achieved as
V–
AD5543/AD5553
–5V
Figure 19. Voltage Output Configuration
These DACs are also designed to accommodate ac reference
input signals. The AD5543 accommodates input reference
voltages in the range of −12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input resistance value of
5 kΩ 30%. The DAC output (IOUT) is code-dependent, producing
various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the AD5543 on the inverting input node of the amplifier. The
feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. To maintain good analog
performance, power supply bypassing of 0.01 μF to 0.1 μF
ceramic or chip capacitors, in parallel with a 1 μF tantalum
capacitor, is recommended. Due to degradation of power supply
rejection ratio (PSRR) in frequency, users must avoid using
switching power supplies.
V
V
OUT = −VREF × D/65,536 (AD5543)
OUT = −VREF × D/16,384 (AD5553)
(1)
(2)
Note that the output voltage polarity is the opposite of the VREF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal logic to drive the on and off states of the DAC
switches.
V
DD
R
R
R
R
V
FB
REF
2R
2R
2R
R
5kΩ
S1
S2
I
OUT
GND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED.
DD
Figure 18. Equivalent R-2R DAC Circuit
Note that a matching switch is used in series with the internal
5 kΩ feedback resistor. If users attempt to measure RFB, power
must be applied to VDD to achieve continuity.
Rev. B | Page 10 of 16
AD5543/AD5553
V
DD
SERIAL DATA INTERFACE
DIGITAL
INPUTS
CS
The AD5543/AD5553 use a 3-wire ( , SDI, CLK) serial data
5kΩ
interface. New serial data is clocked into the serial input register
in a 16-bit data-word format for the AD5543. The MSB is loaded
first. Table 5 defines the 16 data-word bits. Data is placed on the
SDI pin and clocked into the register on the positive clock edge
of CLK, subject to the data setup-and-hold time requirements
that are specified in the interface timing specifications. Only the
last 16 bits clocked into the serial register are interrogated when
DGND
Figure 20. Equivalent ESD Protection Circuits
PCB ꢀAYOUT AND POWER SUPPꢀY BYPASSING
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
CS
the
pin is strobed to transfer the serial register data to the
DAC register. Because most microcontrollers output serial data
in 8-bit bytes, two data bytes can be written to the AD5543/
It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low-ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
CS
AD5553. After loading the serial register, the rising edge of
transfers the serial register data to the DAC register; during this
strobe, the CLK should not be toggled. For the AD5553, with
16-bit clock cycles, the two LSBs are ignored.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (GND) and VDD as shown in
Figure 20.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
Rev. B | Page 11 of 16
AD5543/AD5553
APPLICATIONS INFORMATION
amplifier with a 2.5 V offset from the reference voltage results
in a full four-quadrant multiplying circuit. The transfer
equation of this circuit shows that both negative and positive
output voltages are created as the input data (D) is incremented
from code zero (VOUT = −2.5 V) to midscale (VOUT = 0 V) to
full-scale (VOUT = +2.5 V).
STABIꢀITY
V
DD
U1
C1
R
V
FB
DD
I
V
V
OUT
REF
REF
V
O
AD8628
GND
VOUT = (D/32,768 − 1) × VREF (AD5543)
OUT = (D/16,384 − 1) × VREF (AD5553)
(3)
(4)
V
AD5543/AD5553
U2
Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention
For the AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible to each other, and proper PCB layout technique must
be employed. Since every code change corresponds to a step
function, gain peaking may occur if the op amp has limited
GBP and, there is excessive parasitic capacitance at the inverting
node.
R1
R2
10kΩ ± 0.01% 10kΩ ± 0.01%
C2
U4
+5V
V+
+5V
U1
5kΩ ± 0.01%
V
O
R3
ADR03
1/2AD8620
V–
C1
OUT
V
R
FB
DD
I
V
V
V
An optional compensation capacitor, C1, can be added for
stability as shown in Figure 21. C1 should be found empirically,
but 20 pF is generally adequate for the compensation.
+5V
IN
REF
GND
OUT
GND
U3
–5V
1/2AD8620
–2.5V < V < +2.5V
O
AD5553 ONLY
U2
POSITIVE VOꢀTAGE OUTPUT
Figure 23. Four-Quadrant Multiplying Application Circuit
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the tolerance
errors of the resistors. To generate a negative reference, the
reference can be level-shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
−2.5 V, respectively (see Figure 22).
PROGRAMMABꢀE CURRENT SOURCE
Figure 24 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirectional
current flow and high voltage compliance. This circuit can be
used in 4 mA to 20 mA current transmitters with up to 500 Ω of
load. In Figure 24, it can be shown that if the resistor network is
matched, the load current is
+5V
ADR03
V
V
R2 + R3 /R1
IN
OUT
U4
+5V
IL
=
×VREF × D
(5)
U1
V
GND
U3
–2.5V
C1
OUT
R3
V
R
FB
DD
V+
I
1/2AD8620
V–
REF
R3 in theory can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that AD8510 can deliver 20 mA in both directions
and the voltage compliance approaches 15 V, which is limited
mainly by the supply voltages of U3. However, users must pay
attention to the compensation. Without C1, it can be shown
that the output impedance becomes
V
O
1/2AD8628
GND
–5V
AD5543/AD5553
U2
0V < V < +2.5V
O
Figure 22. Positive Voltage Output Configuration
BIPOꢀAR OUTPUT
The AD5543/AD5553 are inherently two-quadrant multiplying
D/A converters. That is, they can easily be set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference input voltage.
R1' R3
R2' + R3'
If the resistors are perfectly matched, ZO is infinite, which is
R1 + R2
ZO
=
(6)
R1
(
)
− R1' R2 + R3
(
)
desirable, and behaves as an ideal current source. On the other
hand, if they are not matched, ZO can be either positive or
negative. Negative can cause oscillation. As a result, C1 is needed to
prevent the oscillation. For critical applications, C1 could be
found empirically but typically falls in the range of a few
picofarads (pF).
In some applications, it may be necessary to generate the full
four-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished by using an additional U4 external
amplifier configured as a summing amplifier (see Figure 23). In
this circuit, the second U4 amplifier provides a gain of 2 that
increases the output span magnitude to 5 V. Biasing the external
Rev. B | Page 12 of 16
AD5543/AD5553
V
DD
DD
U1
R
V
FB
I
V
V
REF
OUT
REF
R1'
150kΩ
R2'
15kΩ
AD8628
GND
C1
10pF
AD5543/AD5553
U2
V
DD
U3
R3'
50Ω
V+
AD8510
V–
R3
50Ω
V
SS
V
L
R1
150kΩ
R2
15kΩ
I
LOAD
L
Figure 24. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities
Rev. B | Page 13 of 16
AD5543/AD5553
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 25. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 14 of 16
AD5543/AD5553
ORDERING GUIDE
INL
(LSB)
RES
(LSB)
Package
Description
Package
Option
Model1
AD5543CRZ2
AD5543CRZ-REEL7
AD5543CRMZ2
AD5543CRMZ-REEL72
AD5543BR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Branding
1
1
1
1
2
2
2
2
2
2
1
1
1
1
16
16
16
16
16
16
16
16
16
16
14
14
14
14
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
R-8
R-8
RM-8
RM-8
R-8
DEV
DEV
AD5543BRZ2
AD5543BRM
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
DXB
DXB
AD5543BRM –REEL7
AD5543BRMZ2
AD5543BRMZ-REEL7
AD5553CRM
AD5553CRM –REEL7
AD5553CRMZ2
AD5553CRMZ –REEL72
DXB#
DXB#
DUC
DUC
DUC#
DUC#
1 The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil.
2 Z = RoHS Compliant Part, # denotes RoHS Compliant product may be top or bottom marked.
Rev. B | Page 15 of 16
AD5543/AD5553
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02917-0-8/09(B)
Rev. B | Page 16 of 16
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