AD5546CRUZ-REEL7 [ADI]
Current-Output Parallel-Input, 16-Bit Digital-to-Analog Converter;
| 型号： | AD5546CRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Current-Output Parallel-Input, 16-Bit Digital-to-Analog Converter 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Current Output, Parallel Input, 16-/14-Bit
Multiplying DACs with Four-Quadrant Resistors
Data Sheet
AD5546/AD5556
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
R1
R
REF R
COM
OFS
16-bit resolution
14-bit resolution
2- or 4-quadrant multiplying DAC
1 ꢀSB DNꢀ
R
R
R1
R2
OFS
FB
R
I
FB
DAC
16/14
AD5546/
AD5556
OUT
V
DD
1 ꢀSB INꢀ
Operating supply voltage: 2.7 V to 5.5 V
ꢀow noise: 12 nV/√Hz
ꢀow power: IDD = 10 μA
WR
CONTROL
LOGIC
DAC
REGISTER
LDAC
GND
DB0 TO DB15
0.5 μs settling time
POR
Built-in RFB facilitates current-to-voltage conversion
Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,
or 10 V outputs
2 mA full-scale current 20ꢁ, with VREF = 10 V
Automotive operating temperature: –40°C to +125°C
Compact TSSOP-28 package
MSB RS
Figure 1. AD5546/AD5556 Simplified Block Diagram
GENERAꢀ DESCRIPTION
The AD5546/AD5556 are precision 16-/14-bit, multiplying, low
power, current output, parallel input digital-to-analog converters
(DACs). They operate from a single 2.7 V to 5.5 V supply with
10 V multiplying references for four-quadrant outputs. Built-
in four-quadrant resistors facilitate the resistance matching and
temperature tracking that minimize the number of components
needed for multiquadrant applications. The feedback resistor
(RFB) simplifies the I-V conversion with an external buffer. The
AD5546/AD5556 are packaged in compact TSSOP-28 packages
with operating temperatures from –40°C to +125°C.
APPꢀICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Digital waveform generation
The EVAL-AD5546SDZ is available for evaluating DAC perfor-
mance. For more information, see the UG-309 evaluation board
user guide.
+
U2A
OP2177
–
+10V
–10V
C7
R1A
R1
R
VREFA
R
R
FBA
COMA
OFSA
+15V
C4
1µF
C6
R2
R
R
FB
OFS
+5V
V
DD
C5
C1
1µF
C2
I
0.1µF
OUT
16-/14-BIT
DATA
0.1µF
–
V+
U1
U2B
AD5546/AD5556
VOUT
OP2177
GND
V–
+
16-/14-BIT
C8
1µF
DATA
WR LDAC RS MSB
WR
LDAC
RS
C9
0.1µF
–15V
MSB
Figure 2. 16-/14-Bit, Four-Quadrant Multiplying DAC with a Minimum of External Components
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004-2011 Analog Devices, Inc. All rights reserved.
AD5546/AD5556
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Section ............................................................................ 11
ESD Protection Circuits ............................................................ 11
Amplifier Selection .................................................................... 11
Reference Selection .................................................................... 11
Applications Information .............................................................. 12
Unipolar Mode ........................................................................... 12
Bipolar Mode .............................................................................. 13
AC Reference Signal Attenuator............................................... 14
System Calibration ..................................................................... 14
Reference Selection .................................................................... 15
Amplifier Selection .................................................................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Diagram ........................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Operation ........................................................................... 10
Digital-to-Analog (DAC) Converter Section ......................... 10
REVISION HISTORY
11/11—Rev. C to Rev. D
Changes to General Description Section ...................................... 1
Changes to Ordering Guide .......................................................... 18
1/11—Rev. B to Rev. C
Changes to Figure 2.......................................................................... 1
Changes to Figure 21...................................................................... 13
4/10—Rev. A to Rev. B
Changes to Table 1............................................................................ 4
Moved Timing Diagram Section and Figure 5 to
Specifications Section....................................................................... 4
Moved Table 5 Through Table 7 to Digital Section Section ....... 7
Replaced Figure 15 and Figure 16 .................................................. 9
Deleted Figure 17 and Figure 18..................................................... 9
Added Reference Selection Section, Amplifier Selection Section,
and Table 11 Through Table 13 .................................................... 15
9/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Static Performance, Relative Accuracy,
Grade: AD5546C Parameter, Table 1............................................. 3
Changes to Ordering Guide .......................................................... 16
1/04—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
AD5546/AD5556
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, IOUT = virtual GND, GND = 0 V, VREF = –10 V to 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
N
AD5546, 1 LSB = VREF/216 = 153 µV at
16
14
Bits
Bits
V
REF = 10 V
AD5556, 1 LSB = VREF/214 = 610 µV at
REF = 10 V
V
Relative Accuracy
INL
Grade: AD5556C
Grade: AD5546B
Grade: AD5546C
Monotonic
Data = zero scale, TA = 25°C
Data = zero scale, TA = TA maximum
Data = full scale
Data = full scale
Data = full scale
1
2
1
LSB
LSB
LSB
LSB
nA
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
1
10
20
4
4
2.5
nA
Full-Scale Gain Error
Bipolar Mode Gain Error
Bipolar Mode Zero-Scale
Error
GFSE
GE
GZSE
1
1
1
mV
mV
mV
Full-Scale Tempco2
REFERENCE INPUT
VREF Range
REF Input Resistance
R1 and R2 Resistance
R1-to-R2 Mismatch
Feedback and Offset
Resistance
Input Capacitance2
TCVFS
1
ppm/°C
VREF
REF
R1 and R2
∆(R1 to R2)
RFB, ROFS
–18
4
4
+18
6
6
1.5
12
V
5
5
0.5
10
kΩ
kΩ
Ω
8
kΩ
CREF
5
pF
ANALOG OUTPUT
Output Current
IOUT
COUT
Data = full scale
Code dependent
2
200
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
VIL
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
0.8
0.4
V
V
V
V
Logic Input High Voltage
VIH
2.4
2.1
Input Leakage Current
Input Capacitance2
IIL
CIL
10
10
µA
pF
INTERFACE TIMING2, 3
Data to WR Setup Time
tDS
tDH
tWR
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
20
35
0
ns
ns
ns
ns
ns
Data to WR Hold Time
WR Pulse Width
0
20
VDD = 3 V
VDD = 5 V
VDD = 3 V
35
20
35
ns
ns
ns
LDAC Pulse Width
tLDAC
Rev. D | Page 3 of 20
AD5546/AD5556
Data Sheet
Parameter
Symbol
Conditions
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Min
20
35
0
Typ
Max
Unit
ns
RS Pulse Width
tRS
ns
ns
WR to LDAC Delay Time
tLWD
0
ns
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
AC CHARACTERISTICS4
VDD RANGE
IDD
PDISS
PSS
2.7
5.5
10
0.055
0.003
V
μA
mW
ꢀ/ꢀ
Logic inputs = 0 V
Logic inputs = 0 V
∆VDD = 5ꢀ
Output Voltage Settling
Time
tS
To 0.1ꢀ of full scale, data cycles from zero
scale to full scale to zero scale
0.5
μs
Reference Multiplying BW
DAC Glitch Impulse
Multiplying Feedthrough
Error
BW
Q
VOUT/VREF
VREF = 100 mV rms, data = full scale, C6 =5.6 pF5
VREF = 0 V, midscale minus 1 to midscale
VREF = 100 mV rms, f = 10 kHz
6.8
−3
79
MHz
nV-s
dB
Digital Feedthrough
QD
WR = 1, LDAC toggles at 1 MHz
VREF = 5 V p-p, data = full-scale, f = 1 kHz
f = 1 kHz, BW = 1 Hz
7
nV-s
Total Harmonic Distortion
Output Noise Density
THD
eN
–103
12
dB
nV/rt Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system, using an external precision OP97 I-V converter amplifier. The AD554x RFB terminal is
tied to the amplifier output. The op amp +IN is grounded, and the DAC IOUT is tied to the op amp –IN. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and are not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-V converter amplifier except for THD where an AD8065 was used.
5 C6 is the C6 capacitor shown in Figure 20.
TIMING DIAGRAM
tWR
WR
DATA
tDH
tDS
tLWD
LDAC
tLDAC
tRS
RS
Figure 3. AD5546/AD5556 Timing Diagram
Rev. D | Page 4 of 20
Data Sheet
AD5546/AD5556
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
–0.3 V, +8 V
–18 V, 18 V
–0.3 V, +8 V
–0.3 V, VDD + 0.3 V
50 mA
RFB, ROFS, R1, RCOM, and REF to GND
Logic Inputs to GND
V (IOUT) to GND
Input Current to Any Pin Except Supplies
Thermal Resistance (θJA)
128°C
ESD CAUTION
Maximum Junction Temperature (TJ MAX
Operating Temperature Range
Storage Temperature Range
Lead Temperature:
)
150°C
–40°C to +125°C
–65°C to +150°C
Vapor Phase, 60 s
215°C
Infrared, 15 s
220°C
Package Power Dissipation
(TJ MAX – TA)/θJA
Rev. D | Page 5 of 20
AD5546/AD5556
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D7
D6
D5
D4
D3
D2
D1
D0
1
28
V
D5
D4
D3
D2
D1
D0
NC
NC
1
2
28 V
DD
DD
2
27 D8
27 D6
3
26 D9
3
26 D7
4
25 D10
24 D11
23 D12
22 D13
21 D14
20 D15
19 GND
18 RS
4
25 D8
5
5
24 D9
6
6
23 D10
22 D11
21 D12
20 D13
19 GND
18 RS
AD5546
AD5556
7
7
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
8
8
R
9
R
9
OFS
OFS
R
10
R
10
FB
FB
R1 11
12
R1 11
12
R
17 MSB
16 WR
15 LDAC
R
17 MSB
16 WR
15 LDAC
COM
REF 13
14
COM
REF 13
14
I
I
OUT
OUT
NC = NO CONNECT
Figure 4. AD5546 Pin Configuration
Figure 5. AD5556 Pin Configuration
Table 3. AD5546 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 8
9
D7 to D0
ROFS
Digital Input Data Bits[D7: D0]. The signal level must be ≤ VDD + 0.3 V.
Bipolar Offset Resistor. Accepts up to 18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
10
11
12
RFB
R1
RCOM
Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
13
REF
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14
15
16
IOUT
LDAC
WR
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17
18
19
MSB
RS
Power-On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
Reset in Active Low. Resets to zero scale if MSB = 0, and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
GND
Analog and Digital Grounds.
20 to 21 D15 to D14 Digital Input Data Bits[D15:D14]. The signal level must be ≤ VDD + 0.3 V.
22 to 27 D13 to D8
28 VDD
Digital Input Data Bits[D13:D8]. The signal level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
Table 4. AD5556 Pin Function Descriptions
Pin No. Mnemonic Description
1 to 6
7 to 8
9
D5 to D0
NC
ROFS
Digital Input Data Bits[D5:D0]. The signal level must be ≤ VDD+0.3 V.
No Connection. The user should not connect anything other than dummy pads on these terminals.
Bipolar Offset Resistor. Accepts up to 18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1
and the external reference.
10
11
12
RFB
R1
RCOM
Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion.
Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS.
Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of
the reference amplifier. In two-quadrant mode, shorts to the REF pin.
Rev. D | Page 6 of 20
Data Sheet
AD5546/AD5556
Pin No. Mnemonic Description
13
REF
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14
15
16
IOUT
LDAC
WR
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
Digital Input Load DAC Control. The signal level must be ≤ VDD + 0.3 V.
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17
18
19
MSB
RS
Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
GND
Analog and Digital Grounds.
20 to 27 D13 to D6
28 VDD
Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
Rev. D | Page 7 of 20
AD5546/AD5556
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
0
0248 4096
6144
8192 10,240 12,288 14,336 16,384
CODE (Decimal)
Figure 9. AD5556 Differential Nonlinearity Error
Figure 6. AD5546 Integral Nonlinearity Error
1.5
1.0
1.0
0.8
V
T
= 2.5V
REF
= 25°C
A
0.6
0.4
0.5
0.2
INL
0
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
GE
2
4
6
8
10
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE (Decimal)
SUPPLY VOLTAGE V (V)
DD
Figure 7. AD5546 Differential Nonlinearity Error
Figure 10. Linearity Error vs. VDD
1.0
0.8
5
4
3
2
V
= 5V
DD
T
= 25°C
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IH
4.0
4.5
5.0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE (Decimal)
LOGIC INPUT VOLTAGE V (V)
Figure 11. Supply Current vs. Logic Input Voltage
Figure 8. AD5556 Integral Nonlinearity Error
Rev. D | Page 8 of 20
Data Sheet
AD5546/AD5556
3.0
2.5
2.0
1.5
1.0
0.5
0
–3.80
–3.85
–3.90
–3.95
–4.00
–4.05
–4.10
–4.15
–4.20
0x5555
0x8000
0xFFFF
0x0000
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
–200
–100
0
100
200
300
400
TIME (ns)
Figure 12. AD5546 Supply Current vs. Clock Frequency
Figure 15. AD5546 Midscale Transition
2
90
80
70
60
50
40
30
20
10
0
V
V
= 5V ± 10%
0
–2
DD
= 10V
REF
–4
–6
–8
–10
–12
–14
–16
–18
10
100
1k
10k
100k
1M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Power Supply Rejection Ratio vs. Frequency
Figure 16. AD5546 Unipolar Reference Multiplying Bandwidth
LDAC
1
2
V
OUT
CH1 5.00V CH2 2.00V M 200ns
A CH1 2.70V
B CH1 –6.20V
400.00ns
Figure 14. Settling Time from Full Scale to Zero Scale
Rev. D | Page 9 of 20
AD5546/AD5556
Data Sheet
CIRCUIT OPERATION
variation of the AD5546/AD5556 output impedance. The
DIGITAL-TO-ANALOG (DAC) CONVERTER SECTION
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended to bypass the power supply
with a 0.01 μF to 0.1 μF ceramic or chip capacitor in parallel
with a 1 μF tantalum capacitor. Also, to minimize gain error,
PCB metal traces between VREF and RFB should match.
The AD5546/AD5556 are 16-/14-bit multiplying, current out-
put, and parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply and provide both unipolar 0 V to –VREF, or
0 V to +VREF, and bipolar VREF output ranges from a –18 V to
+18 V reference. In addition to the precision conversion RFB
commonly found in current output DACs, there are three addi-
tional precision resistors for four-quadrant bipolar applications.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 20 pF capacitor is
generally adequate for the compensation.
The AD5546/AD5556 consist of two groups of precision R-2R
ladders, which make up the 12/10 LSBs, respectively. Further-
more, the four MSBs are decoded into 15 segments of resistor
value 2R. Figure 17 shows the architecture of the 16-bit AD5546.
Each of the 16 segments in the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor, RFB, and four-quadrant resistor, ROFS, have values of 10
kΩ. Each four-quadrant resistor, R1 and R2, equals 5 kΩ. In
four-quadrant operation, R1, R2, and an external op amp work
together to invert the reference voltage and apply it to the REF
input. With ROFS and RFB connected as shown in Figure 2, the
The VDD power is used primarily by the internal logic and to
drive the DAC switches. Note that the output precision
degrades if the operating voltage falls below the specified
voltage. The user should also avoid using switching regulators
because device power supply rejection degrades at higher
frequencies.
output can swing from –VREF to +VREF
.
The reference voltage inputs exhibit a constant input resistance
of 5 kΩ 20ꢀ. The DAC output, IOUT, impedance is code depen-
dent. External amplifier choice should take into account the
REF
2R
2R
2R
2R
80kΩ
R2
5kΩ
80kΩ 80kΩ 80kΩ
R
COM
R1
5kΩ
4 MSB
15 SEGMENTS
R1
R
R
R
R
R
R
R
R
40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ
2R 2R 2R 2R 2R 2R 2R 2R 2R
80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ
8-BIT R–2R
R
OFS
FB
RA
RB
R
R
R
R
R
2R
2R
2R
2R
2R
80kΩ 80kΩ 80kΩ 80kΩ 80kΩ
10kΩ 10kΩ
4-BIT R–2R
I
OUT
GND
16
8
4
ADDRESS DECODER
LDAC
LDAC
WR
DAC REGISTER
RS
RS
RS
INPUT REGISTER
WR
D15 D14
D0
Figure 17. 16-Bit AD5546 Equivalent R-2R DAC Circuit with Digital Section
Rev. D | Page 10 of 20
Data Sheet
AD5546/AD5556
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
WR
controller bus when the
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie
RS
pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
WR
low and LDAC high. The asynchronous
pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
MSB
LSB
Bit Position
Data Word
B15
D15
B14
B13
B12
D12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D14 D13
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 6. AD5556 Parallel Input Data Format
MSB
LSB
B0
Bit Position
Data Word
B13
D13
B12
D12
B11
D11
B10
D10
B9
B8
D8
B7
D7
B6
B5
D5
B4
D4
B3
B2
D2
B1
D1
D9
D6
D3
D0
Table 7. Control Inputs
LDAC Register Operation
RS WR
0
1
1
1
1
X1
0
1
0
X1
0
1
1
Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
Load input register with data bits.
Load DAC register with the contents of the input register.
Input and DAC registers are transparent.
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
No register operation.
1
1
0
1 X = don’t care.
are good candidates for the I-V conversion.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD, as shown in Figure 18. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
REFERENCE SELECTION
The initial accuracy and the rated output of the voltage refer-
ence determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
V
DD
DIGITAL
INPUTS
5kΩ
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V ref-
erence with a TC of 5 ppm/oC means that the output changes by
25 µV per degree Celsius. As a result, the reference that operates
at 55oC contributes an additional 750 µV full-scale error.
DGND
Figure 18. Equivalent ESD Protection Circuits
AMPLIFIER SELECTION
Similarly, the same 5 V reference with a 50 ppm long-term
drift means that the output may change by 250 µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
Rev. D | Page 11 of 20
AD5546/AD5556
Data Sheet
APPLICATIONS INFORMATION
UNIPOLAR MODE
Two-Quadrant Multiplying Mode, VOUT = 0 V to +VREF
The AD5546/AD5556 are designed to operate with either
positive or negative reference voltages. As a result, positive
output can be achieved with an additional op amp, (see
Figure 20), and the output becomes
Two-Quadrant Multiplying Mode, VOUT = 0 V to –VREF
The AD5546/AD5556 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op
amp to convert the unipolar mode of output voltage to
AD5546
AD5546
V
OUT = +VREF × D/65,536
(3)
(4)
V
OUT = –VREF × D/65,536
(1)
(2)
AD5556
AD5556
VOUT = +VREF × D/16,384
VOUT = –VREF × D/16,384
Table 9 shows the positive output vs. code for the AD5546.
where D is the decimal equivalent of the input code.
The output voltage polarity is opposite to the VREF polarity in
Table 9. AD5546 Unipolar Mode Positive Output vs. Code
this case (see Figure 19). Table 8 shows the negative output vs.
code for the AD5546.
D in Binary
VOUT (V)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+VREF(65,535/65,536)
+VREF/2
+VREF(1/65,536)
0
Table 8. AD5546 Unipolar Mode Negative Output vs. Code
D in Binary
VOUT (V)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
–VREF(65,535/65,536)
–VREF/2
–VREF(1/65,536)
0
+5V
2
V
IN
U3
C1
1µF
C2
0.1µF
ADR03
5
TRIM
V
OUT
GND
4
R1
R
REF
R
R
R
COM
OFS
FB
C6
2.2pF
R1
R2
R
OFS
FB
V
DD
C3
0.1µF
I
OUT
16-/14-BIT
DATA
–
V+
U2
AD8628
V–
U1
AD5546/AD5556
VOUT
–2.5V TO 0V
GND
+
C4
0.1µF
16-/14-BIT
DATA
WR LDAC RS MSB
C5
1µF
WR
LDAC
RS
–5V
MSB
Figure 19. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to –VREF
Rev. D | Page 12 of 20
Data Sheet
AD5546/AD5556
+
U2A
OP2177
–
+10V
–10V
C7
R1A
R1
R
VREFA
R
R
FBA
COMA
R2
OFSA
+15V
C4
1µF
C6
R
R
FB
OFS
+5V
V
DD
C5
C1
1µF
C2
I
0.1µF
OUT
16-/14-BIT
DATA
0.1µF
–
V+
U1
U2B
AD5546/AD5556
VOUT
OP2177
GND
V–
+
16-/14-BIT
C8
1µF
DATA
WR LDAC RS MSB
WR
LDAC
RS
C9
0.1µF
–15V
MSB
Figure 20. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to +VREF
5V
2
+
V
IN
U2A
U3
OP2177
ADR03
TRIM
–
5
6
C1
–VREF
REF
+VREF
V
OUT
GND
R1
R
R
R
R
COM
OFS
FB
4
R1
R2
R
OFS
FB
C2
5V
V
DD
I
OUT
16-/14-BIT
DATA
–
U1
U2B
OP2177
AD5546/AD5556
VOUT
16-/14-BIT
DATA
GND
+
–VREF TO +VREF
WR LDAC RS MSB
WR
LDAC
RS
MSB
Figure 21. Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
10 V reference, the circuit yields a precision, bipolar –10 V to
+10 V output.
BIPOLAR MODE
Four-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
AD5546
The AD5546/AD5556 contain on-chip all the four-quadrant
resistors necessary for the precision bipolar multiplying
operation. Such a feature minimizes the number of exponent
components to only a voltage reference, dual op amp, and
compensation capacitor (see Figure 21). For example, with a
VOUT = (D/32768 − 1) × VREF
(5)
(6)
AD5556
VOUT = (D/16384 − 1) × VREF
Table 10 shows some of the results for the 16-bit AD5546.
Rev. D | Page 13 of 20
AD5546/AD5556
Data Sheet
ac reference signals for signal attenuation, channel equalization,
and waveform generation applications. The maximum signal
range can be up to ±±1 ꢀ ꢁsee Figure 22).
Table 10. AD5546 Output vs. Code
D in Binary
VOUT
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF(32,767/32,768)
+VREF(1/32,768)
0
–VREF(1/32,768)
–VREF
SYSTEM CALIBRATION
The initial accuracy of the system can be adjusted by trimming
the voltage reference ADR0x with a digital potentiometer ꢁsee
Figure 23). The AD5±70 provides an OTP ꢁone time program-
mable), 1-bit adjustment that is ideal and reliable for such cali-
bration. The Analog Devices, Inc., OTP digital potentiometer
comes with programmable software that simplifies the factory
calibration process.
AC REFERENCE SIGNAL ATTENUATOR
Besides handling digital waveforms decoded from parallel input
data, the AD5546/AD5556 handle equally well low frequency
+
U2A
OP2177
–
+10V
–10V
C7
R1A
R1
RCOMA
VREFA
ROFSA RFBA
+15V
C4
1F
C6
R2
ROFS
RFB
+5V
VDD
C5
C1
1F
C2
IOUT
0.1F
0.1F
–
16/14-BIT
V+
U1
U2B
AD5546/AD5556
VOUT
OP2177
GND
V–
+
16/14 DATA
C8
1F
WR LDAC RS MSB
WR
LDAC
RS
C9
0.1F
–15V
MSB
Figure 22. Signal Attenuator with AC Reference
+5V
2
+
V+
U2A
V
IN
U3
U4
C1
1µF
C2
0.1µF
AD5170
R3
470kΩ
AD8628
ADR03
V–
C8
5
6
–
10kΩ
TRIM
0.1µF
B
V
OUT
R7
1kΩ
GND
C9
1µF
4
–2.5V
R
–5V
C7
+2.5V
R1A
R
VREFA
R
FBA
COMA
OFSA
+5V
C4
1µF
C6
R1
R2
R
R
FB
OFS
V
DD
C5
C3
0.1µF
I
0.1µF
OUT
16-/14-BIT
DATA
–
V+
U1
AD5546/AD5556
U2B
VOUT
0V TO +2.5V
AD8628
GND
V–
+
16-/14-BIT
DATA
WR LDAC RS MSB
WR
LDAC
RS
MSB
Figure 23. Full Span Calibration
Rev. D | Page 14 of 20
Data Sheet
AD5546/AD5556
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 11 lists some of the references
available from Analog Devices that are suitable for use with this
range of current output DACs.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources, they settle quickly. Consequently, the
slew rate and settling time of a voltage-switching DAC circuit is
determined largely by the output op amp. To obtain minimum
settling time in this configuration, minimize capacitance at the
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which, if large enough, can cause the DAC to be
nonmonotonic.
V
REF node (the voltage output node in this application) of the
DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 12 and Table 13.
Table 11. Suitable Analog Devices Precision References
Maximum Temperature
Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C)
ISS (mA) Output Noise (µV p-p) Package(s)
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR420 2.048
ADR421 2.50
ADR423 3.00
ADR425 5.00
ADR431 2.500
ADR435 5.000
ADR391 2.5
ADR395 5.0
10
10
0.05
0.05
0.06
0.06
0.1
0.1
0.1
0.1
0.05
0.04
0.04
0.04
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
3
3
3
3
9
9
1
1
1
1
1
1
1
1
0.5
0.5
0.5
0.5
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
TSOT-5
5.0
5.0
2.5
2.5
3.0
3.0
6
10
10
1.75
1.75
2
3.4
3.5
8
5
8
TSOT-5
Rev. D | Page 15 of 20
AD5546/AD5556
Data Sheet
Table 12. Suitable Analog Devices Precision Op Amps
V
OS Maximum IB Maximum 0.1 Hz to 10 Hz
Part No.
OP97
Supply Voltage (V) (µV)
(nA)
Noise (µV p-p)
Supply Current (µA)
Package(s)
2 to 20
2.5 to 15
5 to 18
5 to 15
5 to 15
1.8 to 5
1.8 to 5
2.7 to 5
2.7 to 5
2.7 to 5
25
60
75
75
125
50
50
65
65
65
0.1
2
2
12
0.5
0.4
0.1
0.077
0.1
2.3
2.3
2.3
2.4
2.4
600
500
2300
3000
2000
40
SOIC-8 , PDIP-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
SOIC-8, SOT-23-5
TSOT-5
OP1177
AD8675
AD8671
ADA4004-1
AD8603
AD8607
AD8605
AD8615
AD8616
90
0.001
0.001
0.001
0.001
0.001
40
MSOP-8, SOIC-8
WLCSP-5, SOT-23-5
TSOT-23-5
1000
2000
2000
MSOP-8, SOIC-8
Table 13. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8066
AD8021
AD8038
Supply Voltage (V) BW @ ACL (MHz)
Slew Rate (V/µs)
VOS (Max) (µV)
IB (Max) (nA)
0.006
0.006
10,500
750
100
500
500
350
Package(s)
5 to 24
5 to 24
5 to 24
3 to 12
145
145
490
350
600
325
325
320
320
320
180
180
120
425
310
1000
850
650
650
1300
1500
1500
1000
3000
35
5000
5000
6000
6000
10,000
SOIC-8, SOT-23-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, SC70-5
LFCSP-8, SOIC-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOIC-8, PDIP-8
ADA4899-1 5 to 12
AD8057
AD8058
AD8061
AD8062
AD9631
3 to 12
3 to 12
2.7 to 8
2.7 to 8
350
7000
3 to
6
Rev. D | Page 16 of 20
Data Sheet
AD5546/AD5556
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 24. 28-Lead Thin Shrink Small Outline Package [TSSOP]
RU-28
Dimensions shown in millimeters
ORDERING GUIDE
RES
DNL
(LSB)
INL
(LSB)
Temperature
Range (°C)
Model1
(Bit)
16
16
16
16
16
16
14
14
14
Package Description Package Option Ordering Quantity
AD5546BRU
AD5546BRU-REEL7
AD5546BRUZ
AD5546BRUZ-REEL7
AD5546CRUZ
AD5546CRUZ-REEL7
AD5556CRU
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
−40 to +125
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
50
1,000
50
1,000
50
1,000
50
AD5556CRU-REEL7
AD5556CRUZ
1,000
50
EVAL-AD5546SDZ
1 Z = RoHS Compliant Part.
Rev. D | Page 17 of 20
AD5546/AD5556
NOTES
Data Sheet
Rev. D | Page 18 of 20
Data Sheet
NOTES
AD5546/AD5556
Rev. D | Page 19 of 20
AD5546/AD5556
NOTES
Data Sheet
©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03810-0-11/11(D)
Rev. D | Page 20 of 20
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