AD5623RSRMZ-EP-5R7 [ADI]
Dual 12-Bit nanoDAC® with 5 ppm/°C On-Chip Reference;
| 型号： | AD5623RSRMZ-EP-5R7 |
| 厂家： | 
ADI |
| 描述： | Dual 12-Bit nanoDAC® with 5 ppm/°C On-Chip Reference 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-Bit nanoDAC with
1ꢀ ꢁꢁpm/C ꢂO-Chiꢁ ꢃReRꢄROnR
EOhaOnRd Pꢄodunt
AD5623ꢃ-EP
The AD5623R-EP has an on-chip 2.5 V reference giving a
maximum full-scale output of 5 V. The on-chip reference is off
at power-up, allowing the use of an external reference.
FEATURES
Low power, smallest pin-compatible, dual nanoDAC: 12 bits
User-selectable external or internal reference
External reference default
On-chip 2.5 V, 10 ppmꢀ/C reference
10-lead MSOP
4.5 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
The AD5623R-EP incorporates a power-on reset circuit that
ensures that the output of the DACs powers up to 0 V and
remains there until a valid write takes place. The AD5623R-EP
contains a power-down feature that reduces the current
consumption of the device to 0.48 μA at 5 V and provides
software-selectable output loads while in power-down mode.
Per channel power-down
Serial interface up to 50 MHz
The low power consumption of this device in normal operation
makes it ideally suited to portable, battery-operated equipment.
LDAC
CLR
functions
Hardware
and
The AD5623R-EP uses a versatile, 3-wire serial interface that
operates at clock rates of up to 50 MHz, and is compatible with
standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables rail-
to-rail output swing to be achieved. Additional application and
technical information can be found in the AD5623R data sheet.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC)
Extended temperature range: −55°C to +105/C
Controlled manufacturing baseline
One assemblyꢀtest site
One fabrication site
Enhanced product change notification
Qualification data available on request
PRODUCT HIGHLIGHTS
1. Dual 12-Bit DAC.
2. On-Chip 2.5 V, 10 ppm/°C Reference.
3. Available in 10-Lead MSOP.
APPLICATIONS
4. Low Power. Typically consumes 1.25 mW at 5 V. 4.5 μs
maximum settling time.
Process control
Data acquisition systems
Table 1. Related Device
GENERAL DESCRIPTION
Part No.
Description
The AD5623R-EP, a member of the nanoDAC® family, is a low
power, dual 12-bit buffered voltage output digital-to-analog
converter (DAC) that operates from a single 4.5 V to 5.5 V
supply and is guaranteed monotonic by design.
AD5623R
2.7 V to 5.5 V, dual 12-bit nanoDAC, with external
reference
FUNCTIONAL BLOCK DIAGRAM
V
V
/V
DD
REFIN REFOUT
2.5V
REFERENCE
LDAC
INPUT
DAC
STRING
DAC A
V
V
A
B
SCLK
SYNC
DIN
BUFFER
BUFFER
OUT
REGISTER
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
OUT
AD5623R-EP
POWER-ON
RESET
POWER-DOWN
LOGIC
LDAC CLR
GND
Figure 1.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5623R-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Applications Information .............................................................. 13
Using a Reference as a Power Supply....................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 4
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Added Enhanced Product Features Section.................................. 1
Change to Table 5 ............................................................................. 6
Changes to Using a Reference as a Power Supply Section and
Figure 33 .......................................................................................... 13
Deleted Terminology Section ....................................................... 13
Deleted Theory of Operation Section, Digital-to-Analog
Architecture Section, Figure 33; Renumbered Sequentially,
Resistor String Section, Output Amplifier Section, Figure 34,
Internal Reference Section, External Reference Section, and
Serial Interface Section .................................................................. 15
Deleted Input Shift Register Section, Table 7; Renumbered
SYNC
Sequentially, Table 8,
Interrupt Section, Power-On Reset
Section, Software Reset Section, Table 9, Figure 35, and
Figure 36 .......................................................................................... 16
Deleted Power-Down Modes Section, Table 10 to Table 13, and
Figure 37 .......................................................................................... 17
LDAC
Asynchronous
LDAC
Deleted
Function Section, Synchronous
LDAC
Section,
Section, Table 14 to Table 16, and Internal
Reference Setup Section................................................................. 18
Deleted Microprocessor Interfacing Section, AD5623R-EP to
Blackfin® ADSP-BF53x Interface Section, Figure 38, AD5623R-EP
to M68HC11/MC68L11 Interface Section, Figure 39, AD5623R-EP
to 80C51 Interface Section, Figure 40, AD5623R-EP to
MICOWIRE Interface Section, and Figure 41............................ 19
Deleted Power Supply Bypassing and Grounding Section ....... 20
4/14—Revision 0: Initial Version
Rev. A | Page 2 of 16
Enhanced Product
SPECIFICATIONS
AD5623R-EP
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN/VREFOUT = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
STATIC PERFORMANCE2
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
12
Bits
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Scale Error
Offset Error
Full-Scale Error
1
1.5
1
+12
12
1
LSB
LSB
mV
mV
% of FSR
% of FSR
µV/°C
ppm
dB
Guaranteed monotonic by design
All 0s loaded to DAC register
+2
1
−0.1
All 1s loaded to DAC register
Gain Error
1.5
Zero-Scale Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk
2
2.5
−100
Of FSR/°C
DAC code = midscale; VDD = 5 V 10%
External Reference
10
10
5
µV
µV/mA
µV
Due to full-scale output change; RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Internal Reference
25
20
10
µV
µV/mA
µV
Due to full-scale output change; RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
170
26
200
VDD
µA
V
kΩ
VREFIN/VREFOUT = VDD = 5.5 V
0.75
2.495
2.505
V
At ambient
Reference Temperature Coefficient3
Output Impedance
LOGIC INPUTS3
10
7.5
ppm/°C
kΩ
Input Current
Input Low Voltage (VINL
2
0.8
µA
V
All digital inputs
VDD = 5 V
)
Input High Voltage (VINH
)
2
V
VDD = 5 V
Pin Capacitance
3
pF
pF
DIN, SCLK, and SYNC
LDAC and CLR
19
POWER REQUIREMENTS
VDD
IDD (Normal Mode)4
4.5
5.5
V
VINH = VDD and VINL = GND
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
Internal Reference Off
Internal Reference On
IDD (All Power-Down Modes)5
0.25
0.8
0.48
0.45
1
1
mA
mA
µA
VDD = 4.5 V to 5.5 V, VINH = VDD and VINL = GND
1 Temperature range = −55°C to +105°C, typical at +25°C.
2 Linearity calculated using a reduced code range: Code 32 to Code 4064. Output unloaded.
3 Guaranteed by design and characterization, but not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 Both DACs powered down.
Rev. A | Page 3 of 16
AD5623R-EP
Enhanced Product
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN/VREFOUT = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Min
Typ
Max
Unit
Test Conditions/Comments
SLEW RATE
1.8
V/µs
FEEDTHROUGH
Digital Feedthrough
Reference Feedthrough
CROSSTALK
0.1
−90
nV-sec
dB
VREFIN/VREFOUT = 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk
Analog Crosstalk
0.1
1
4
1
4
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
External reference
Internal reference
External reference
Internal reference
DAC-to-DAC Crosstalk
MULTIPLYING BANDWIDTH
340
−80
VREFIN/VREFOUT = 2 V 0.1 V p-p
VREFIN/VREFOUT = 2 V 0.1 V p-p, frequency = 10 kHz
TOTAL HARMONIC DISTORTION
OUTPUT CHARACTERISTICS
Digital-to-Analog Glitch Impulse
Output Voltage Settling Time
Output Noise Spectral Density
dB
10
3
120
100
15
nV-sec
µs
nV/√Hz
nV/√Hz
μV p-p
1 LSB change around major carry
¼ to ¾ scale settling to 0.5 LSB
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
4.5
Output Noise
1 Guaranteed by design and characterization, but not production tested.
2 Temperature range = −55°C to +105°C, typical at +25°C.
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2.
DD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
Parameter1
Limit at TMIN, TMAX
Unit
Description
2
t1
t2
t3
20
9
9
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
t4
13
5
5
t5
t6
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
t7
0
t8
15
13
0
t9
t10
t11
t12
t13
t14
t15
10
15
5
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
0
300
1 Guaranteed by design and characterization, but not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
Rev. A | Page 4 of 16
Enhanced Product
AD5623R-EP
Timing Diagram
t10
t1
t9
SCLK
SYNC
DIN
t2
t8
t7
t3
t4
t6
t5
DB23
DB0
t14
t11
1
LDAC
t12
2
LDAC
t13
CLR
t15
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 5 of 16
AD5623R-EP
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 5.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VOUTx to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
ESD CAUTION
−55°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
142°C/W
43.7°C/W
260 (+0/−5)°C
Rev. A | Page 6 of 16
Enhanced Product
AD5623R-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
9
V
V
A
B
V
V
/V
OUT
REFIN REFOUT
OUT
DD
AD5623R-EP
TOP VIEW
8
GND
DIN
(Not to Scale)
7
LDAC
CLR
SCLK
SYNC
6
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VOUT
VOUT
GND
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground. Reference point for all circuitry on the device.
Load DAC. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
LDAC
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The device exits clear code mode on the 24th falling edge of the next write to the device. If CLR is activated during
a write sequence, the write is aborted.
6
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
7
SCLK
DIN
VDD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. This device can be operated from 4.5 V to 5.5 V. Decouple the supply with a 10 μF capacitor in
parallel with a 0.1 μF capacitor to GND.
8
9
10
VREFIN/VREFOUT Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
Rev. A | Page 7 of 16
AD5623R-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.20
0.15
0.10
0.05
V
V
= 5V
/V
= 25°C
V
T
= V
/V
= 5V
DD
DD
REFIN REFOUT
= 2.5V
= 25°C
REFIN REFOUT
0.8
A
T
A
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
CODE
CODE
Figure 4. INL, External Reference
Figure 7. DNL, at 5 V VDD
0.20
0.15
0.10
0.05
0
8
6
V
= V
= 25°C
/V
= 5V
DD
REFIN REFOUT
T
A
MAX INL
V
= V
/V
= 5V
DD
REFIN REFOUT
4
2
MAX DNL
MIN DNL
0
–0.05
–0.10
–0.15
–0.20
–2
–4
–6
–8
MIN INL
100
–40
–20
0
20
40
60
80
120
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
TEMPERATURE (°C)
CODE
Figure 5. DNL, External Reference
Figure 8. INL Error and DNL Error vs. Temperature
10
1.0
V
V
= 5V
/V
= 25°C
DD
= 2.5V
8
6
MAX INL
REFIN REFOUT
0.8
0.6
0.4
0.2
T
A
V
T
= 5V
= 25°C
DD
4
A
2
MAX DNL
MIN DNL
0
0
–0.2
–0.4
–0.6
–2
–4
–6
MIN INL
4.25
–8
–0.8
–1.0
–10
0.75
1.25
1.75
2.25
2.75
3.25
(V)
3.75
4.75
0
0.5k
1.0k
1.5k
2.0k
CODE
2.5k
3.0k
3.5k
4.0k
V
REF
Figure 6. INL, at 5 V VDD
Figure 9. INL Error and DNL Error vs. VREF
Rev. A | Page 8 of 16
Enhanced Product
AD5623R-EP
8
6
1.5
1.0
MAX INL
ZERO-SCALE ERROR
T
= 25°C
A
4
2
0.5
0
MAX DNL
MIN DNL
0
–0.5
–1.0
–1.5
–2.0
–2.5
–2
–4
–6
–8
OFFSET ERROR
MIN INL
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD
Figure 10. INL Error and DNL Error vs. VDD
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
1.0
0
–0.02
–0.04
–0.06
–0.08
T
= 25°C
V
= 5V
A
DD
0.5
0
ZERO-SCALE ERROR
GAIN ERROR
–0.5
–1.0
–1.5
–0.10
–0.12
–0.14
–0.16
FULL-SCALE ERROR
–2.0
–2.5
OFFSET ERROR
–0.18
–0.20
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD
Figure 11. Gain Error and Full-Scale Error vs. Temperature
Figure 14. Zero-Scale Error and Offset Error vs. VDD
1.0
V
= 5.5V
DD
T
= 25°C
A
8
6
4
2
0
0.5
0
GAIN ERROR
FULL-SCALE ERROR
–0.5
–1.0
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
0.230
0.235
0.240
0.245
0.250
0.255
V
I
(mA)
DD
DD
Figure 12. Gain Error and Full-Scale Error vs. VDD
Figure 15. IDD Histogram with External Reference
Rev. A | Page 9 of 16
AD5623R-EP
Enhanced Product
0.30
5
T
= 25°C
A
V
= 5.5V
DD
T
= 25°C
A
0.25
0.20
0.15
0.10
4
3
2
1
0
V
= V
/V
= 5V
DD
REFIN REFOUT
0.05
0
–40
–20
0
20
40
60
80
100
0.78
0.80
0.82
(mA)
0.84
TEMPERATURE (°C)
I
DD
Figure 19. Supply Current vs. Temperature
Figure 16. IDD Histogram with Internal Reference
0.5
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.4
0.3
0.2
V
= V
/V
= 5V
DD
REFIN REFOUT
T
= 25°C
A
0.1
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
0
–0.1
–0.2
–0.3
V
V
= 5V
/V
DD
= 2.5V
V
= 909mV/DIV
REFIN REFOUT
OUT
1
–0.4
–0.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
TIME BASE = 4µs/DIV
CURRENT (mA)
Figure 20. Full-Scale Settling Time, 5 V
Figure 17. Headroom at Rails vs. Source and Sink Current
6
5
4
3
2
1
V
= V
= 25°C
/V = 5V
DD
REFIN REFOUT
V
V
T
= 5V
DD
T
A
/V
= 2.5V
FULL SCALE
REFIN REFOUT
= 25C
A
3/4 SCALE
MIDSCALE
1/4 SCALE
V
DD
1
2
MAX(CH2)*
420.0mV
0
ZERO SCALE
V
OUT
–1
–30
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
–20
–10
0
10
20
30
CURRENT (mA)
Figure 21. Power-On Reset to 0 V
Figure 18. 5 V VDD Source and Sink Capability
Rev. A | Page 10 of 16
Enhanced Product
AD5623R-EP
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
SYNC
1
SCLK
3
V
V
V
= 5V
/V
= 25°C
OUT
DD
REFIN REFOUT
V
= 5V
DD
= 2.5V
T
A
2
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
Figure 25. Analog Crosstalk, Internal Reference
Figure 22. Exiting Power-Down to Midscale
2.538
V
= V
/V
= 5V
DD
REFIN REFOUT
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
T
= 25°C
A
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
V
= V
= 25°C
/V
= 5V
DD
REFIN REFOUT
T
A
DAC LOADED WITH MIDSCALE
MIDSCALE (0x8000 TO 0x7FFF)
1
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 23. Digital-to-Analog Glitch Impulse (Negative)
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
= V
= 25°C
/V
= 5V
DD
REFIN REFOUT
V
V
= 5V
/V
= 25°C
T
DD
REFIN REFOUT
A
= 2.5V
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
T
A
DAC LOADED WITH MIDSCALE
1
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
5s/DIV
Figure 24. Analog Crosstalk, External Reference
Figure 27. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Rev. A | Page 11 of 16
AD5623R-EP
Enhanced Product
800
5
0
V
= 5V
= 25°C
DD
T
= 25°C
A
T
A
MIDSCALE LOADED
700
600
500
400
300
200
–5
–10
–15
–20
–25
–30
–35
–40
V
V
= 5V
/V
DD
REFIN REFOUT
= 2.5V
100
0
100
1k
10k
FREQUENCY (Hz)
1M
10M
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 28. Noise Spectral Density, Internal Reference
Figure 31. Multiplying Bandwidth
–20
–30
–40
V
= 5V
= 25°C
DD
T
A
DAC LOADED WITH FULL SCALE
V
CLR
3
/V
= 2V ± 0.3V p-p
REFIN REFOUT
V
A
–50
–60
–70
OUT
–80
V
B
OUT
4
2
–90
–100
2k
4k
6k
8k
10k
CH2 1.0V
CH4 1.0V
M200ns A CH3
1.10V
CH3 5.0V
FREQUENCY (Hz)
Figure 29. Total Harmonic Distortion
CLR
Pulse Activation Time
Figure 32.
16
14
12
10
8
V
/V
= 25°C
= V
REFIN REFOUT DD
T
A
V
= 5V
DD
6
4
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 30. Settling Time vs. Capacitive Load
Rev. A | Page 12 of 16
Enhanced Product
AD5623R-EP
APPLICATIONS INFORMATION
The load regulation of the ADR293-EP is typically 30 ppm/mA,
which results in a 45 ppm (225 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.184 LSB error.
12V
USING A REFERENCE AS A POWER SUPPLY
Because the supply current required by the AD5623R-EP is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the device (see Figure 33). This
is especially useful if the power supply is quite noisy or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5623R-EP. If the ADR293-EP is used, it must
supply ~500 μA of current to the AD5623R-EP, with no load on
the output of the DAC. When the DAC output is loaded, the
ADR293-EP also needs to supply the current to the load. The
total current required (with a 5 kΩ load on the DAC output) is
5V
ADR293-EP
V
DD
SYNC
SCLK
DIN
V
= 0V TO 5V
3-WIRE
SERIAL
INTERFACE
OUT
AD5623R-EP
Figure 33. ADR293-EP as Power Supply to the AD5623R-EP
500 μA + (5 V/5 kΩ) = 1.5 mA
Rev. A | Page 13 of 16
AD5623R-EP
Enhanced Product
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 34. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Internal
Reference
Package
Option
Model1
Temperature Range
−55°C to +105°C
Accuracy
Package Description
Branding
AD5623RSRMZ-EP-5R7
1.5 ꢀSꢁ ꢂIꢀ
2.5 V
10-ꢀead MSOP
RM-10
DI9
1 Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Enhanced Product
NOTES
AD5623R-EP
Rev. A | Page 15 of 16
AD5623R-EP
NOTES
Enhanced Product
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12105-0-9/15(A)
Rev. A | Page 16 of 16
相关型号：
AD5624RBCPZ-3250R7
IC SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, DSO10, 3 X 3 MM, LEAD FREE, LFCSP-10, Digital to Analog Converter
ADI
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