AD5625BCPZ-R2
更新时间：2024-11-08 12:35:56
品牌：ADI
描述：Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface
概述
数据手册
替代型号AD5625BCPZ-R2 概述
Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface 四， 12位/ 14位/ 16位nanoDACs 5 PPM / °时C片参考， I2C接口 DA转换器
AD5625BCPZ-R2 数据手册
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PDF下载Quad, 12-/14-/16-Bit nanoDACs with
5 ppm/°C On-Chip Reference, I2C Interface
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
V
/V
DD
GND
REFIN REFOUT
Low power, smallest pin-compatible, quad nanoDACs
AD5625R/AD5645R/AD5665R
AD5625R/AD5645R/AD5665R
1.25V/2.5V REF
12-/14-/16-bit nanoDACs
BUFFER
BUFFER
BUFFER
BUFFER
On-chip, 2.5 V, 5 ppm/°C reference in TSSOP
On-chip, 2.5 V, 10 ppm/°C reference in LFCSP
On-chip, 1.25 V, 10 ppm/°C reference in LFCSP
AD5625/AD5665
12-/16-bit nanoDACs
External reference only
INPUT
DAC
STRING
DAC A
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
ADDR1
ADDR2
SCL
REGISTER
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
3 mm × 3 mm, 10-lead LFCSP; 14-lead TSSOP; and 1.665 mm
× 2.245 mm, 12-ball WLCSP
SDA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
2.7 V to 5.5 V power supply
POWER-ON RESET
POWER-DOWN LOGIC
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
LDAC CLR
POR
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
Figure 1. AD5625R/AD5645R/AD5665R
V
V
REFIN
DD
GND
AD5625/AD5665
APPLICATIONS
BUFFER
BUFFER
BUFFER
BUFFER
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
INPUT
DAC
STRING
DAC A
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
ADDR1
ADDR2
SCL
REGISTER
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
GENERAL DESCRIPTION
SDA
The AD5625R/AD5645R/AD5665R and AD5625/AD5665
members of the nanoDAC® family are low power, quad, 12-/
14-/16-bit, buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V supply,
are guaranteed monotonic by design, and have an I2C-compatible
serial interface.
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
POWER-ON RESET
POWER-DOWN LOGIC
LDAC CLR
POR
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
Figure 2. AD5625/AD5665
The AD5625R/AD5645R/AD5665R have an on-chip reference. The
LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V, 10 ppm/°C
reference, giving a full-scale output range of 2.5 V or 5 V; the
TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C refer-
ence, giving a full-scale output range of 5 V. The WLCSP package
has a 1.25 V reference. The on-chip reference is off at power-up,
allowing the use of an external reference. The internal reference is
enabled via a software write. The AD5625/AD5665 require an
external reference voltage to set the output range of the DAC.
The AD56x5R/AD56x5 use a 2-wire I2C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No.
Description
AD5025/AD5045/AD5065
Dual 12-/14-/16-bit DACs
AD5624R/AD5644R/AD5664R,
AD5624/AD5664
Quad SPI 12-/14-/16-bit DACs,
with/without internal reference
Dual I2C 12-/14-/16-bit DACs,
with/without internal reference
AD5627R/AD5647R/AD5667R,
AD5627/AD5667
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR = GND) or midscale
(POR = VDD) and remains there until a valid write occurs. The
on-chip precision output amplifier enables rail-to-rail output swing.
AD5666
Quad SPI 16-bit DAC with internal
reference
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2007-2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
External Reference ..................................................................... 24
Serial Interface............................................................................ 24
Write Operation.......................................................................... 24
Read Operation........................................................................... 24
High Speed Mode....................................................................... 26
Input Shift Register .................................................................... 26
Multiple Byte Operation............................................................ 26
Broadcast Mode.......................................................................... 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Specifications—AD5665R/AD5645R/AD5625R ..................... 3
Specifications—AD5665/AD5625 ............................................. 5
AC Characteristics........................................................................ 7
I2C Timing Specifications............................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 23
Digital-to-Analog Converter (DAC) ....................................... 23
Resistor String............................................................................. 23
Output Amplifier........................................................................ 23
Internal Reference ...................................................................... 23
LDAC
Function .......................................................................... 28
Power-Down Modes .................................................................. 30
Power-On Reset and Software Reset ....................................... 31
Internal Reference Setup (R Versions) .................................... 31
Applications Information.............................................................. 32
Using a Reference as a Power Supply for the
AD56x5R/AD56x5..................................................................... 32
Bipolar Operation Using the AD56x5R/AD56x5 .................. 32
Power Supply Bypassing and Grounding................................ 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 35
REVISION HISTORY
3/13—Rev. B to Rev. C
12/09—Rev. A to Rev. B
Added 12-Ball WLCSP ......................................................Universal
Change to Features and General Description Sections ............... 1
Changes to Reference Output (1.25 V), Reference TC
Changes to Features Section, General Description Section,
and Table 1..........................................................................................1
Changes to Table 2.............................................................................3
Changes to Internal Reference Section........................................ 22
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide.......................................................... 33
Parameter, Table 2............................................................................. 4
Added θJA Thermal Impedance, WLCSP Parameter, Table 6 ... 10
Added Figure 8; Renumbered Sequentially ................................ 12
Added Table 8; Renumbered Sequentially .................................. 12
Changes to Internal Reference Section........................................ 23
Changes to Serial Interface Section and Table 9 Title................ 24
Changes to Figure 58 and Figure 60 Captions............................ 25
Updated Outline Dimensions....................................................... 33
Changes to Ordering Guide .......................................................... 35
6/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections ..............1
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................5
Changes to Digital-to-Analog Converter (DAC) Section, Added
Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22
Changes to Ordering Guide.......................................................... 33
3/07—Revision 0: Initial Version
Rev. C | Page 2 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
SPECIFICATIONS
SPECIFICATIONS—AD5665R/AD5645R/AD5625R
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade
Min Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE2
Max
Min
Max
Unit
Test Conditions/Comments1
AD5665R
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5645R
±±
±16
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5625R
±2
±4
±0.5
Resolution
12
Bits
LSB
±0.25 LSB
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
±1
±4
±1
10
±10
±0.5
±1.25
±0.5
±1
Guaranteed monotonic by design
All 0s loaded to DAC register
2
±1
2
±1
10
mV
mV
±10
±0.5
±1
−0.1
±0.1
±2
±2.5
−100
−0.1
±0.1
±2
±2.5
−100
% FSR
% FSR
µV/°C
ppm
dB
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk (External
Reference)
15
15
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
10
±
10
±
µV/mA
µV
Due to load current change
Due to powering down (per channel)
DC Crosstalk (Internal
Reference)
25
25
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20
10
20
10
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
VDD
2 ×
0
VDD
2 ×
V
Internal reference disabled
Internal reference enabled
VREF
VREF
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode;
VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
210
26
260
VDD
210
26
260
VDD
µA
V
kΩ
VREF = VDD = 5.5 V
0.75
0.75
Rev. C | Page 3 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
A Grade
Min Typ
B Grade
Typ
Parameter
Max
Min
Max
Unit
Test Conditions/Comments1
REFERENCE OUTPUT (1.25 V)
Output Voltage
1.247
1.253
1.247
1.253
V
At ambient
TSSOP and LFCSP packages
WLCSP package
Reference TC3
1ꢀ
7.5
1ꢀ
15
7.5
ppm/°C
ppm/°C
kΩ
Output Impedance
REFERENCE OUTPUT (2.5 V)
Output Voltage
Reference TC3
Output Impedance
VDD = 4.5 V to 5.5 V
At ambient
2.495
2.5ꢀ5
2.495
2.5ꢀ5
1ꢀ
V
1ꢀ
7.5
5
7.5
ppm/°C
kΩ
LOGIC INPUTS (ADDRx, CLR,
LDAC, POR)3
IIN, Input Current
1
1
μA
V
V
pF
V
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
ꢀ.15 × VDD
ꢀ.15 × VDD
ꢀ.85 × VDD
2
ꢀ.1 × VDD
ꢀ.85 × VDD
2
ꢀ.1 × VDD
1
1
μA
V
V
pF
V
V
ꢀ.3 × VDD
ꢀ.3 × VDD
ꢀ.7 × VDD
2
ꢀ.1 × VDD
ꢀ.ꢀ5 × VDD
ꢀ.7 × VDD
2
ꢀ.1 × VDD
ꢀ.ꢀ5 × VDD
High speed mode
Fast mode
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage
ꢀ.4
ꢀ.6
1
ꢀ.4
ꢀ.6
1
V
V
μA
ISINK = 3 mA
ISINK = 6 mA
Floating-State Leakage
Current
Floating-State Output
Capacitance
2
2
pF
V
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)5
VDD = 2.7 V to 5.5 V
VDD = 3.6 V to 5.5 V
VIH = VDD, VIL = GND, full-scale loaded
Internal reference off
Internal reference off
Internal reference on
Internal reference on
1.ꢀ
ꢀ.9
1.9
1.4
1.16
1.ꢀ5
2.14
1.59
1.ꢀ
1.16
1.ꢀ5
2.14
1.59
mA
mA
mA
mA
ꢀ.9
1.9
1.4
ꢀ.48
ꢀ.48
1
1
ꢀ.48
ꢀ.48
1
1
μA
μA
VIH = VDD, VIL = GND (LFCSP)
VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of A and B grades is −4ꢀ°C to +1ꢀ5°C.
2 Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,ꢀ24), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4ꢀ64). Output
unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
Rev. C | Page 4 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
SPECIFICATIONS—AD5665/AD5625
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments1
STATIC PERFORMANCE2
AD5665
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5625
±±
±16
±1
Guaranteed monotonic by design
Resolution
12
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
±0.5
±1
±0.25
10
LSB
LSB
mV
Guaranteed monotonic by design
All 0s loaded to DAC register
2
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
±1
±10
±0.5
±1
mV
−0.1
±0.1
±2
±2.5
−100
15
% FSR
% FSR
µV/°C
ppm
dB
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
µV
10
±
µV/mA
µV
Due to load current change
Due to powering down (per channel)
DC Crosstalk (Internal Reference)
25
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20
10
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
210
26
260
VDD
µA
V
kΩ
VREF = VDD = 5.5 V
Reference Input Range
Reference Input Impedance
LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
0.75
±1
0.15 × VDD
µA
V
V
pF
V
0.±5 × VDD
0.1 × VDD
2
2
±1
0.3 × VDD
µA
V
V
pF
V
V
0.7 × VDD
VHYST, Input Hysteresis
0.1 × VDD
0.05 × VDD
High speed mode
Fast mode
Rev. C | Page 5 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
B Grade
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments1
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage
0.4
0.6
±1
V
V
µA
pF
ISINK = 3 mA
ISINK = 6 mA
Floating-State Leakage Current
Floating-State Output Capacitance
POWER REQUIREMENTS
VDD
2
2.7
5.5
V
IDD (Normal Mode)4
VIH = VDD, VIL = GND, full-scale loaded
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)5
1.0
0.9
1.16
1.05
mA
mA
VDD = 2.7 V to 5.5 V
VDD = 3.6 V to 5.5 V
0.4±
0.4±
1
1
µA
µA
VIH = VDD, VIL = GND (LFCSP)
VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of B grade is −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
Rev. C | Page 6 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1,2
Min
Typ
Max
Unit
Test Conditions/Comments3
Output Voltage Settling Time
AD5625R/AD5625
AD5645R
AD5665R/AD5665
Slew Rate
3
3.5
4
4.5
5
7
µs
µs
µs
V/µs
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±2 LSB
1.±
Digital-to-Analog Glitch Impulse
1 LSB change around major carry
15
5
0.1
−90
0.1
1
4
1
4
340
−±0
120
100
15
nV-s
nV-s
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
LFCSP
TSSOP
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Analog Crosstalk
External reference
Internal reference
External reference
Internal reference
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREF = 2 V ± 0.1 V p-p
dB
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
µV p-p
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
Rev. C | Page 7 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 5.
Parameter Test Conditions2
Min
Max
100
400
3.4
Unit
kHz
kHz
MHz
MHz
μs
μs
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
μs
Description
3
fSCL
Standard mode
Serial clock frequency
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
1.7
t1
4
tHIGH, SCL high time
tLOW, SCL low time
Fast mode
0.6
60
120
4.7
1.3
160
320
250
100
10
0
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
t2
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
t3
t4
tSU;DAT, data setup time
tHD;DAT, data hold time
3.45
0.9
Fast mode
0
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
0
0
4.7
0.6
160
4
70
150
ns
ns
μs
μs
ns
μs
t5
t6
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
Fast mode
High speed mode
Standard mode
0.6
160
4.7
μs
ns
μs
t7
t±
tBUF, bus-free time between a stop and a start
condition
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
1.3
4
0.6
160
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
t9
1000
300
±0
160
300
300
±0
160
1000
300
40
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
t10
t11
t11A
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
±0
1000
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
300
±0
160
ns
ns
ns
10
20
Rev. C | Page ± of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Parameter Test Conditions2
Min
Max
300
300
40
Unit
ns
ns
ns
ns
Description
t12
Standard mode
tFCL, fall time of SCL signal
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
10
10
10
300
±0
t13
ns
LDAC pulse width low
Fast mode
ns
ns
ns
High speed mode
Standard mode
t14
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
Fast mode
300
30
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
t15
CLR pulse width low
4
tSP
50
10
Pulse width of spike suppressed
High speed mode
0
1 See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
t11
t12
t6
t2
t6
SCL
SDA
t1
t3
t5
t10
t8
t4
t9
t7
P
S
S
P
t14
t13
LDAC*
CLR
t15
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure 3. 2-Wire Serial Interface Timing Diagram
Rev. C | Page 9 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VOUT to GND
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C
ESD CAUTION
Storage Temperature Range
Junction Temperature (TJ maximum)
Power Dissipation
−65°C to +150°C
150°C
(TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD (4-Layer Board)
TSSOP
61°C/W
150.4°C/W
75°C/W
WLCSP
Reflow Soldering Peak Temperature,
RoHS Compliant
260°C ± 5°C
Rev. C | Page 10 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
LDAC
SCL
SDA
GND
1
2
3
4
5
10
9
V
V
A
B
V
V
/V
OUT
REFIN REFOUT
ADDR1
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
OUT
DD
V
DD
8
GND
SDA
V
V
A
V
B
D
OUT
OUT
OUT
7
V
V
C
SCL
OUT
C
V
OUT
CLR
ADDR2
6
D
ADDR
OUT
POR
REFIN REFOUT
8
V
/V
EXPOSED PAD TIED TO GND.
Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version
Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version
1
2
3
4
5
6
7
14
13
12
11
10
9
LDAC
SCL
SDA
GND
1
2
3
4
5
10
9
V
V
A
B
V
V
OUT
REFIN
ADDR1
AD5625/
AD5665
TOP VIEW
(Not to Scale)
OUT
DD
AD5625/
AD5665
TOP VIEW
(Not to Scale)
V
DD
8
GND
SDA
V
V
A
C
V
V
B
D
OUT
OUT
OUT
OUT
7
V
V
C
SCL
OUT
OUT
6
D
ADDR
POR
CLR
ADDR2
EXPOSED PAD TIED TO GND.
8
V
REFIN
Figure 7. Pin Configuration (10-Lead LFCSP)
Figure 5. Pin Configuration (14-Lead TSSOP)
Table 7. Pin Function Descriptions
Pin Number
14-Lead 10-Lead Mnemonic Description
1
N/A
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
2
3
N/A
9
ADDR1
VDD
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 10).
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
5
6
1
4
N/A
VOUT
VOUT
POR
A
C
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to VDD
powers up the part to midscale.
7
10
VREFIN/VREFOUT The AD56x5R have a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference
input pin. The default for this pin is as a reference input. (The internal reference and reference output
are only available on R suffix versions.) The AD56x5 has a reference input pin only.
±
9
N/A
N/A
ADDR2
CLR
Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 10).
Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses
are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the
output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last
byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is
activated during high speed mode, the part exits high speed mode.
10
11
12
13
5
2
3
±
VOUT
VOUT
GND
SDA
D
B
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an
external pull-up resistor.
14
7
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input register.
N/A
6
ADDR
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 9).
EPAD
For the 10-lead LFCSP, the exposed pad must be tied to GND.
Rev. C | Page 11 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
BALL A1
INDICATOR
1
2
3
V
/
REFIN
V
V
A
REFOUT
GND OUT
A
B
VDD
V
V
B
C
D
GND
OUT
OUT
OUT
SDA GND
C
D
SCL ADDR V
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 8. Pin Configuration (12-Ball WLCSP)
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
A1
VREFIN/VREFOUT The AD5665R has a common pin for reference input and reference output. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin. The default
for this pin is as a reference input.
A2, B2, C2 GND
Ground Reference Point for All Circuitry on the Part.
A3
B1
VOUT
VDD
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Power Supply Input. The AD5665R can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
B3
C1
VOUT
SDA
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input
register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up
resistor.
C3
D1
VOUT
SCL
C
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input
register.
D2
D3
ADDR
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 9).
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
VOUTD
Rev. C | Page 12 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
V
T
= V = 5V
REF
DD
= 25°C
V
T
= V = 5V
REF
DD
= 25°C
A
0.8
0.6
0.4
0.2
8
A
6
4
2
0
–2
–4
0
–0.2
–0.4
–0.6
–6
–8
–0.8
–1.0
–10
0
10k
20k
30k
CODE
40k
50k
60k
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 12. DNL, AD5665, External Reference
Figure 9. INL, AD5665, External Reference
0.5
4
V
= V = 5V
REF
DD
= 25°C
V
= V = 5V
REF
DD
T = 25°C
A
T
A
0.4
0.3
0.2
0.1
3
2
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
2500
5000
7500
CODE
10000
12500
15000
0
2500
5000
7500
CODE
10000
12500
15000
Figure 10. INL, AD5645R, External Reference
Figure 13. DNL, AD5645R, External Reference
1.0
0.8
0.20
0.15
0.10
0.05
0
V
T
= V
REF
= 5V
V
T
= V = 5V
REF
DD
= 25°C
DD
= 25°C
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
500
1000 1500 2000
2500 3000 3500 4000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
CODE
Figure 11. INL, AD5625, External Reference
Figure 14. DNL, AD5625, External Reference
Rev. C | Page 13 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
1.0
0.8
0.6
0.4
0.2
10
V
V
T
= 5V
V
V
= 5V
DD
REFOUT
= 25°C
DD
= 2.5V
8
6
4
2
= 2.5V
REFOUT
TA = 25°C
A
0
0
–0.2
–2
–0.4
–0.6
–4
–6
–0.8
–1.0
–8
–10
CODE
CODE
Figure 15. INL, AD5665R, 2.5 V Internal Reference
Figure 18. DNL, AD5665R, 2.5 V Internal Reference
4
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REFOUT
REFOUT
3
2
TA = 25°C
TA = 25°C
1
0
0
–0.1
–1
–2
–0.2
–0.3
–3
–4
–0.4
–0.5
CODE
CODE
Figure 19. DNL, AD5645R, 2.5 V Internal Reference
Figure 16. INL, AD5645R, 2.5 V Internal Reference
1.0
0.20
0.15
0.10
0.05
V
V
T
= 5V
V
V
= 5V
DD
REFOUT
= 25°C
DD
= 2.5V
0.8
0.6
0.4
0.2
= 2.5V
REFOUT
TA = 25°C
A
0
–0.2
–0.4
–0.6
0
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
Figure 20. DNL, AD5625R, 2.5 V Internal Reference
Figure 17. INL, AD5625R, 2.5 V Internal Reference
Rev. C | Page 14 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
10
1.0
V
V
= 3V
V
V
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
8
6
= 1.25V
0.8
0.6
= 1.25V
T
T
A
A
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 21. INL, AD5665R,1.25 V Internal Reference
Figure 24. DNL, AD5665R,1.25 V Internal Reference
4
3
0.5
0.4
V
V
= 3V
V
V
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
= 1.25V
= 1.25V
T
T
A
A
0.3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–1
–2
–3
–4
–0.4
–0.5
CODE
CODE
Figure 22. INL, AD5645R, 1.25 V Internal Reference
Figure 25. DNL, AD5645R,1.25 V Internal Reference
1.0
0.8
0.20
0.15
0.10
0.05
0
V
V
= 3V
V
V
= 3V
DD
REFOUT
= 25°C
DD
REFOUT
= 25°C
= 1.25V
= 1.25V
T
T
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
Figure 23. INL, AD5625R,1.25 V Internal Reference
Figure 26. DNL, AD5625R, 1.25 V Internal Reference
Rev. C | Page 15 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
8
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
DD
6
MAX INL
V
= V = 5V
REF
DD
GAIN ERROR
4
2
MAX DNL
MIN DNL
0
–0.10
–0.12
–2
–4
–6
–8
–0.14
–0.16
FULL-SCALE ERROR
MIN INL
80
–0.18
–0.20
–40
–20
0
20
40
60
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. INL Error and DNL Error vs. Temperature
Figure 30. Gain Error and Full-Scale Error vs. Temperature
10
8
1.5
MAX INL
1.0
ZERO-SCALE ERROR
6
0.5
0
V
= 5V
DD
= 25°C
4
T
A
2
MAX DNL
MIN DNL
–0.5
0
–2
–4
–6
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
MIN INL
4.25
–8
–10
0.75 1.25
–40
–20
0
20
40
60
80
100
1.75
2.25
2.75
3.25
(V)
3.75
4.75
TEMPERATURE (°C)
V
REF
Figure 28. INL Error and DNL Error vs. VREF
Figure 31. Zero-Scale Error and Offset Error vs. Temperature
8
6
1.0
0.5
MAX INL
T
= 25°C
A
4
2
GAIN ERROR
0
MAX DNL
MIN DNL
FULL-SCALE ERROR
–0.5
0
–2
–4
–6
–8
–1.0
MIN INL
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
Figure 32. Gain Error and Full-Scale Error vs. Supply
Figure 29. INL Error and DNL Error vs. Supply
Rev. C | Page 16 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1.0
2.0
T
A
= 25°C
= 5.5V
T
= 25°C
A
V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DD
0.5
0
ZERO-SCALE ERROR
V
= 2.5V
= 5V
REFOUT
–0.5
–1.0
–1.5
V
REFIN
–2.0
–2.5
OFFSET ERROR
512
10512
20512
30512
CODE
40512
50512
60512
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
DD
Figure 33. Zero-Scale Error and Offset Error vs. Supply
Figure 36. Supply Current vs. DAC Code
30
25
20
15
10
5
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 3.6V
= 5.5V
DD
DD
T
= 25°C
A
0
3.7
4.2
(V)
4.7
5.2
2.7
3.2
V
DD
I
(mA)
DD
Figure 37. Supply Current vs. Supply
Figure 34. IDD Histogram with External Reference
1.2
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5
V
V
= 3.6V
= 5.5V
DD
DD
V
= V
REF
= 5V
= 3V
DD
V
= V
REF
DD
V
= 1.25V
V
= 2.5V
REFOUT
REFOUT
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
I
(mA)
DD
Figure 35. IDD Histogram with Internal Reference
Figure 38. Supply Current vs. Temperature
Rev. C | Page 17 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
0.5
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.4
0.3
0.2
V
= V = 5V
REF
DD
= 25°C
T
A
V
V
= 3V
DD
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
0.1
= 1.25V
REFOUT
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
0
–0.1
–0.2
–0.3
V
= 909mV/DIV
OUT
V
V
= 5V
DD
1
= 2.5V
–2
REFOUT
–0.4
–0.5
TIME BASE = 4µs/DIV
–10
–8
–6
–4
0
2
4
6
8
10
CURRENT (mA)
Figure 42. Full-Scale Settling Time, 5 V
Figure 39. Headroom at Rails vs. Source and Sink
6
5
4
3
2
1
V
T
= V = 5V
REF
V
V
= 5V
DD
= 25°C
DD
REFOUT
= 25°C
FULL SCALE
= 2.5V
A
T
A
3/4 SCALE
MIDSCALE
1/4 SCALE
V
DD
1
2
MAX(C2)
420.0mV
0
ZERO SCALE
V
OUT
CH2 500mV
–1
–30
CH1 2.0V
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
–20
–10
0
10
20
30
CURRENT (mA)
Figure 40. AD56x5R with 2.5 V Reference, Source and Sink Capability
Figure 43. Power-On Reset to 0 V
4
SYNC
SLCK
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
1
3
3
2
1
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
V
OUT
V
= 5V
DD
0
ZERO SCALE
2
–1
–30
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
–20
–10
0
10
20
30
CURRENT (mA)
Figure 44. Exiting Power-Down to Midscale
Figure 41. AD56x5R with 1.25 V Reference, Source and Sink Capability
Rev. C | Page 1± of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
V
T
= V = 5V
REF
V
T
= V = 5V
REF
DD
= 25°C
DD
= 25°C
A
A
DAC LOADED WITH MIDSCALE
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
1
4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 45. Digital-to-Analog Glitch Impulse (Negative)
Figure 48. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
V
= 5V
V
= V
REF
= 5V
DD
REFOUT
= 25°C
DD
= 25°C
= 2.5V
T
A
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
DAC LOADED WITH MIDSCALE
1
0
50
100 150 200 250 300 350 400 450 512
SAMPLE NUMBER
5s/DIV
Figure 49. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
Figure 46. Analog Crosstalk, External Reference
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
V
V
= 3V
DD
REFOUT
= 25°C
= 1.25V
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
DD
REFOUT
= 25°C
= 2.5V
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 47. Analog Crosstalk, Internal Reference
Figure 50. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference
Rev. C | Page 19 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
800
16
14
12
10
8
T
= 25°C
V
= V
DD
A
REF
= 25°C
MIDSCALE LOADED
T
A
700
600
500
400
300
200
V
= 3V
DD
V
=
5V
DD
V
V
= 5V
DD
REFOUT
= 2.5V
6
4
100
0
V
V
= 3V
DD
REFOUT
= 1.25V
1k
100
10k
FREQUENCY (Hz)
100k
1M
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 51. Noise Spectral Density, Internal Reference
Figure 53. Settling Time vs. Capacitive Load
–20
–30
–40
5
0
V
T
= 5V
V
T
= 5V
DD
A
DD
= 25°C
= 25°C
A
DAC LOADED WITH FULL SCALE
V
= 2V ± 0.3V p-p
REF
–5
–10
–15
–20
–25
–30
–35
–40
–50
–60
–70
–80
–90
–100
2k
4k
6k
8k
10k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 52. Total Harmonic Distortion
Figure 54. Multiplying Bandwidth
Rev. C | Page 20 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC
transfer function.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change, and it is measured from the rising edge
of the stop condition.
Differential Nonlinearity (DNL)
Digital-to-Analog Glitch Impulse
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic
by design.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 45).
Zero-Code Error
Zero-code error is a measurement of the output error when zero
scale (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5665R because the output of the DAC cannot go below 0 V
due to a combination of the offset errors in the DAC and the out-
put amplifier. Zero-code error is expressed in millivolts (mV).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Full-Scale Error
Reference Feedthrough
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of full-scale range (FSR).
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in decibels (dB).
Output Noise Spectral Density
Gain Error
Output noise spectral density is a measurement of the internally
generated random noise, which is characterized as a spectral
density (nanovolts per square root of hertz frequency (nV/√Hz)).
It is measured by loading the DAC to midscale and measuring
noise at the output. It is measured in nanovolts per square root
of hertz frequency (nV/√Hz). A plot of noise spectral density is
shown in Figure 51.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percentage of full-scale range (FSR).
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in
zero-code error with a change in temperature. It is expressed in
microvolts per degrees Celsius (µV/°C).
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in microvolts (μV).
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in parts
per million (ppm) of full-scale range per degrees Celsius
(FSR/°C).
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in microvolts per
milliampere (μV/mA).
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5665R
with Code 512 loaded in the DAC register. It can be negative or
positive.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nanovolts per
second (nV-s).
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
V
OUT to the change in VDD for full-scale output of the DAC. It is
measured in decibels (dB). VREF is held at 2 V, and VDD is varied
by 10%.
Rev. C | Page 21 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
Analog Crosstalk
Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) and then executing
a software LDAC and monitoring the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nanovolts per second (nV-s).
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in
decibels (dB).
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
LDAC
to all 1s and vice versa) with
low while monitoring the
output of the victim channel that is at midscale. The energy of
the glitch is expressed in nanovolts per second (nV-s).
Rev. C | Page 22 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
RESISTOR STRING
The resistor string is shown in Figure 57. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
The AD56x5R/AD56x5 DACs are fabricated on a CMOS
process. The AD56x5 does not have an internal reference, and
the DAC architecture is shown in Figure 55. The AD56x5R does
have an internal reference and can be configured for use with
either an internal or external reference (see Figure 55 and
Figure 56).
OUTPUT AMPLIFIER
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
The output buffer amplifier can generate rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. It can drive a
load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier are shown in Figure 39
and Figure 40. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale
settling time of 7 μs.
D
VOUT VREFIN
2N
V
/V
REFIN REFOUT
REF
BUFFER
OUTPUT
AMPLIFIER
GAIN = ×2
R
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
R
OUT
REF (–)
TO OUTPUT
R
AMPLIFIER
GND
Figure 55. Internal Configuration When Using an External Reference
R
R
The ideal output voltage when using the internal reference is
given by
D
VOUT 2VREFOUT
2N
Figure 57. Resistor String
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register, as follows:
INTERNAL REFERENCE
The AD5625R/AD5645R/AD5665R feature an on-chip reference.
Versions without the R suffix require an external reference. The
on-chip reference is off at power-up and is enabled via a write to a
control register. See the Internal Reference Setup section for details.
0 to 4095 for AD5625R/AD5625 (12-bit).
0 to 16,383 for AD5645R (14-bit).
0 to 65,535 for AD5665R/AD5665 (16-bit).
N is the DAC resolution.
Versions packaged in a 10-lead LFCSP have a 1.25 V reference
or a 2.5 V reference, giving a full-scale output of 2.5 V or 5 V,
depending on the model selected (see the Ordering Guide). The
WLCSP package has an internal reference of 1.25 V. These parts
can be operated with a VDD supply of 2.7 V to 5.5 V. Versions
packaged in a 14-lead TSSOP have a 2.5 V reference, giving a
full-scale output of 5 V. Parts are functional with a VDD supply
of 2.7 V to 5.5 V, but with a VDD supply of less than 5 V, the
output is clamped to VDD. See the Ordering Guide for a full list
of models. The internal reference associated with each part is
available at the VREFOUT pin (available on R suffix versions only).
V
/V
REFIN REFOUT
1.25V INTERNAL
1
OUTPUT
AMPLIFIER
GAIN = ×2
REFERENCE
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
1
CAN BE OVERDRIVEN
BY V .
/V
REFIN REFOUT
GND
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is recom-
mended that a 100 nF capacitor be placed between the reference
output and GND for reference stability.
Figure 56. Internal Configuration When Using the Internal Reference
Rev. C | Page 23 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
EXTERNAL REFERENCE
The 2-wire serial bus protocol operates as follows:
The VREFIN pin on the AD56x5R allows the use of an external
reference if the application requires it. The default condition of
the on-chip reference is off at power-up. All devices can be
operated from a single 2.7 V to 5.5 V supply.
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master brings the SDA line low before
the 10th clock pulse, and then high during the 10th clock
pulse to establish a stop condition.
SERIAL INTERFACE
The AD56x5R/AD56x5 have 2-wire I2C-compatible serial inter-
faces. The AD56x5R/AD56x5 can be connected to an I2C bus as
a slave device, under the control of a master device. See Figure 3
for a timing diagram of a typical write sequence.
The AD56x5R/AD56x5 support standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) data transfer modes.
High speed operation is only available on selected models. See
the Ordering Guide for a full list of models. Support is not
provided for 10-bit addressing and general call addressing.
The AD56x5R/AD56x5 each has a 7-bit slave address. The
10-lead and 12-ball versions of the part have a slave address
whose five MSBs are 00011, and the two LSBs are set by the
state of the ADDR address pin, which determines the state of
the A0 and A1 address bits. The 14-lead versions of the part
have a slave address whose three MSBs are 001, and the four
LSBs are set by the ADDR1 and ADDR2 address pins, which
determine the state of the A0 and A1 and A2 and A3 address
bits, respectively.
WRITE OPERATION
When writing to the AD56x5R/AD56x5, the user must begin
The facility to make hardwired changes to the ADDR pin allows
the user to incorporate up to three of these devices on one bus,
as outlined in Table 9.
W
with a start command followed by an address byte (R/ = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5665 requires two bytes of
data for the DAC and a command byte that controls various
DAC functions. Three bytes of data must, therefore, be written
to the DAC, the command byte followed by the most significant
data byte and the least significant data byte, as shown in Figure 58
and Figure 59. After these data bytes are acknowledged by the
AD56x5R/AD56x5, a stop condition follows.
Table 9. ADDR Pin Settings (10-Lead and 12-Ball Packages)
ADDR Pin Connection
A1
A0
VDD
0
0
NC
1
0
GND
1
1
The facility to make hardwired changes to the ADDR1 and the
ADDR2 pins allows the user to incorporate up to nine of these
devices on one bus, as outlined in Table 10.
READ OPERATION
When reading data back from the AD56x5R/AD56x5, the
user begins with a start command followed by an address byte
Table 10. ADDR1, ADDR2 Pin Settings (14-Lead Package)
W
(R/ = 1), after which the DAC acknowledges that it is prepared
ADDR2 Pin
Connection
ADDR1 Pin
Connection
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master
as shown in Figure 60 and Figure 61. A stop condition follows.
A3
0
A2
0
A1
0
A0
0
VDD
VDD
VDD
NC
0
0
1
0
VDD
NC
GND
VDD
0
1
0
0
1
0
1
0
NC
NC
1
0
1
0
NC
GND
VDD
NC
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
GND
GND
GND
GND
Rev. C | Page 24 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
1
9
1
9
SCL
0
0
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
AD56x5
ACK. BY
AD56x5
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
(CONTINUED)
STOP BY
MASTER
ACK. BY
AD56x5
ACK. BY
AD56x5
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 58. I2C Write Operation (10-Lead and 12-Ball Packages)
1
9
1
9
SCL
SDA
0
1
A3
A2
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
AD56x5
ACK. BY
AD56x5
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
(CONTINUED)
STOP BY
MASTER
ACK. BY
AD56x5
ACK. BY
AD56x5
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 59. I2C Write Operation (14-Lead Package)
1
9
1
9
SCL
SDA
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
AD56x5
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
STOP BY
MASTER
ACK. BY
MASTER
NO ACK.
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 60. I2C Read Operation (10-Lead and 12-Ball Packages)
Rev. C | Page 25 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
1
9
1
9
SCL
0
0
1
A3
A2
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
AD56x5
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
STOP BY
MASTER
ACK. BY
MASTER
NO ACK.
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 61. I2C Read Operation (14-Lead Package)
FAST MODE
HIGH-SPEED MODE
1
9
1
9
SCL
SDA
0
0
0
0
1
X
X
X
0
0
1
A3
A2
A1
A0
R/W
NO ACK.
SR
START BY
MASTER
ACK. BY
AD56x5
HS-MODE
MASTER CODE
SERIAL BUS
ADDRESS BYTE
Figure 62. Placing the AD56x5RBRUZ-2/AD56x5RBRUZ-2REEL7 in High Speed Mode
HIGH SPEED MODE
INPUT SHIFT REGISTER
Some models offer high speed serial communication with a
clock frequency of 3.4 MHz. See the Ordering Guide for a full
list of models.
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock
input, SCL. The timing diagram for this operation is shown in
Figure 3. The eight MSBs make up the command byte. DB23
is reserved and should always be set to 0 when writing to the
device. DB22 (S) is used to select multiple byte operation.
The next three bits are the command bits (C2, C1, and C0)
that control the mode of operation of the device. See Table 11
for details. The last three bits of the first byte are the address bits
(A2, A1, and A0). See Table 12 for details. The rest of the bits
are the 16-/14-/12-bit data-word. The data-word comprises the
16-/14-/12-bit input code followed by two or four don’t care bits
for the AD5645R and the AD5625R/AD5625, respectively (see
Figure 65 through Figure 67).
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to
begin. No device connected to the bus is permitted to acknowl-
edge the high speed master code; therefore, the code is followed
by a no acknowledge. Next, the master must issue a repeated
start followed by the device address. The selected device then
acknowledges its address. All devices continue to operate in
high speed mode until the master issues a stop condition. When
the stop condition is issued, the devices return to standard/fast
CLR
mode. The part also returns to standard/fast mode when
activated while the part is in high speed mode.
is
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD56x5R/AD56x5.
A 2-byte operation is useful for applications that require fast
DAC updating and do not need to change the command byte.
The S bit (DB22) in the command register can be set to 1 for
2-byte mode of operation (see Figure 64). For standard 3-byte
and 4-byte operation, the S bit (DB22) in the command byte
should be set to 0 (see Figure 63).
Rev. C | Page 26 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
BLOCK 1
BLOCK 2
BLOCK n
S = 0
S = 0
S = 0
SLAVE
ADDRESS
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT
BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT
STOP
BYTE
DATA BYTE
DATA BYTE
Figure 63. Multiple Block Write with Command Byte in Each Block (S = 0)
BLOCK 1
BLOCK 2
BLOCK n
S = 1
S = 1
S = 1
SLAVE
ADDRESS
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT
BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE
MOST SIGNIFICANT LEAST SIGNIFICANT
STOP
DATA BYTE
DATA BYTE
Figure 64. Multiple Block Write with Initial Command Byte Only (S = 1)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 65. AD5665R/AD5665 Input Shift Register (16-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 66. AD5645R Input Shift Register (14-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R
S
C2
C1
C0
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 67. AD5625R/AD5625 Input Shift Register (12-Bit DAC)
Rev. C | Page 27 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
BROADCAST MODE
LDAC FUNCTION
Broadcast addressing is supported on the AD56x5R/AD56x5
in write mode only. Broadcast addressing can be used to synchro-
nously update or power down multiple AD56x5R/AD56x5
devices. When the broadcast address is used, the AD56x5R/
AD56x5 respond regardless of the states of the address pins.
The AD56x5R/AD56x5 broadcast address is 00010000.
The AD56x5R/AD56x5 DACs have double-buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register, and the digital code is transferred to the relevant
input register upon completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor strings.
LDAC
Access to the DAC registers is controlled by the
pin.
pin is high, the DAC registers are latched
and the input registers can change state without affecting the
LDAC
Table 11. Command Definition
C2 C1 C0 Command
LDAC
When the
0
0
0
0
0
1
0
1
0
Write to input Register n
Update DAC Register n
Write to input Register n, update all
(software LDAC)
contents of the DAC registers. When
is brought low,
however, the DAC registers become transparent and the contents of
the input registers are transferred to them. The double-buffered
interface is useful if the user requires simultaneous updating of
all DAC outputs. The user can write to one of the input registers
low when writing to
the other DAC input register, all outputs update simultaneously.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Write to and update DAC Channel n
Power up/power down
Reset
LDAC
individually and then, by bringing
LDAC register setup
Internal reference setup (on/off )
These parts each contain an extra feature whereby a DAC register
is not updated unless its input register has been updated since
LDAC
LDAC
the last time
was brought low. Normally, when
is
Table 12. DAC Address Command
brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD56x5R/AD56x5, the DAC
register updates only if the input register has changed since the
last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
A2
A1
A0
ADDRESS (n)
0
0
0
DAC A
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
The outputs of all DACs can be simultaneously updated, using
1
1
1
All DACs
LDAC
the hardware
pin.
.
Rev. C | Page 2± of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
LDAC
Synchronous
LDAC
Table 13.
Register Mode of Operation on the 10-Lead
LDAC
The DAC registers are updated after new data is read in.
can be permanently low or pulsed.
LFCSP (Load DAC Register)
LDAC Bits
(DB3 to DB0)
LDAC Mode of Operation
LDAC
Asynchronous
The outputs are not updated at the same time that the input
LDAC
0
Normal operation (default), DAC register
update is controlled by the write command.
registers are written to. When
registers are updated with the contents of the input register.
LDAC
goes low, the DAC
1
The DAC registers are updated after new data
is read in.
The
the hardware
parts that do not have the hardware
This register allows the user to select which combination of
LDAC
register gives the user full flexibility and control over
LDAC LDAC
pin (and software
LDAC
on the 10-lead
pin—see Table 13).
LDAC
Table 14.
Register Mode of Operation on the 14-Lead
TSSOP (Load DAC Register)
LDAC Bits
(DB3 to DB0)
channels to simultaneously update when the hardware
LDAC
LDAC Pin
LDAC Operation
pin is executed. Setting the
channel means that the update of this channel is controlled by
LDAC
bit register to 0 for a DAC
0
1/0
Determined by the LDAC pin.
1
x = don’t
care
The DAC registers are updated
after new data is read in.
the
updates; that is, the DAC register is updated after new data is
LDAC
pin. If this bit is set to 1, this channel synchronously
read in, regardless of the state of the
pin. The device
pin as being pulled low. See Table 14
register mode of operation. This flexibility is
LDAC
effectively sees the
LDAC
for the
useful in applications when the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
LDAC
Writing to the DAC using Command 110 loads the 4-bit
register [DB3:DB0]. The default for each channel is 0; that is,
LDAC
the
the DAC register is updated, regardless of the state of the
pin. See Figure 68 for the contents of the input shift register
pin works normally. Setting the bits to 1 means that
LDAC
LDAC
during the
register setup command.
R
0
S
C2
1
C1
1
C0
0
A2
A2
A1
A1
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
DAC D DAC C DAC B DAC A
DAC ADDRESS
(DON’T CARE)
DAC SELECT
(0 = LDAC PIN ENABLED)
COMMAND
DON’T CARE
DON’T CARE
LDAC
Figure 68.
Setup Command
Rev. C | Page 29 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
Table 15. Modes of Operation for the AD56x5R/AD56x5
POWER-DOWN MODES
DB5
DB4
Operating Mode
Normal operation
Power-down modes
Command 100 is reserved for the power-up/power-down
function. The power-up/power-down modes are programmed
by setting Bit DB5 and Bit DB4. This defines the output state of
the DAC amplifier, as shown in Table 15. Bit DB3 to Bit DB0
determine to which DAC or DACs the power-up/power-down
command is applied. Setting one of these bits to 1 applies the
power-up/power-down state defined by DB5 and DB4 to the
corresponding DAC. If a bit is 0, the state of the DAC is
unchanged. Figure 70 shows the contents of the input shift
register for the power-up/power-down command.
0
0
0
1
1
1
0
1
1 kΩ pull-down resistor to GND
100 kΩ pull-down resistor to GND
Three-state, high impedance
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 1 mA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kΩ or 100 kΩ resistor or be left
open-circuited (three-state) as shown in Figure 67.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 69. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 4 μs for VDD = 5 V or VDD = 3 V.
Note that the 14-lead TSSOP models offer the power-down
function when the part is operated with a VDD of 3.6 V to 5.5 V.
The 10-lead LFCSP models offer the power-down function
when the part is powered with a VDD of 2.7 V to 5.5 V.
R
0
S
X
C2
1
C1
0
C0
0
A2
A2
A1
A1
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A0
X
X
X
X
X
X
X
X
X
X
PD1 PD0 DAC D DAC C DAC B DAC A
DAC SELECT
POWER-
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
DOWN MODE
(1 = DAC SELECTED)
Figure 70. Power-Up/Power-Down Command
Rev. C | Page 30 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
POWER-ON RESET AND SOFTWARE RESET
Table 16. Software Reset Modes for the AD56x5R/AD56x5
The AD56x5R/AD56x5 contain a power-on reset circuit that
controls the output voltage during power-up. The 10-lead
version of the device powers up to 0 V. The 14-lead version has
a power-on reset (POR) pin that allows the output voltage to
be selected. By connecting the POR pin to GND, the AD56x5R/
AD56x5 output powers up to 0 V; by connecting the POR pin to
VDD, the AD56x5R/AD56x5 output powers up to midscale. The
output remains powered up at this level until a valid write sequence
is made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.
DB0
Registers Reset to Zero
0
DAC register
Input shift register
DAC register
Input shift register
LDAC register
1 (Power-On Reset)
Power-down register
Internal reference setup register
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register. Table 17 shows how the
state of the bit corresponds to the mode of operation.
Any events on
or during power-on reset are ignored.
LDAC CLR
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting bit
DB0 in the input shift register.
Table 17. Reference Setup Command
DB0
Action
0
1
Internal reference off (default)
Internal reference on
Table 16 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Figure 71
shows the contents of the input shift register during the
software reset mode of operation.
X
0
S
X
C2
1
C1
0
C0
1
A2
X
A1
X
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RST
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
Figure 71. Reset Command
R
0
S
X
C2
1
C1
1
C0
1
A2
X
A1
X
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
DON’T CARE
DON’T CARE
Figure 72. Reference Setup Command
Rev. C | Page 31 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD56x5R/AD56x5
R2 = 10kΩ
+5V
R1 = 10kΩ
Because the supply current required by the AD56x5R/AD56x5 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see Figure 73). This is
especially useful if the power supply is noisy or if the system
supply voltages are at some value other than 5 V or 3 V, for
example, 15 V. The voltage reference outputs a steady supply
voltage for the AD56x5R/AD56x5. If the low dropout REF195 is
used, it must supply 450 µA of current to the AD56x5R/AD56x5
with no load on the output of the DAC. When the DAC output
is loaded, the REF195 also must supply the current to the load.
The total current required (with a 5 kΩ load on the DAC
output) is
V
±5V
O
AD820/
OP295
V
V
+5V
10µF
DD
OUT
0.1µF
AD5625R/
AD5645R/
AD5665R/
AD5625/
AD5665
–5V
GND SCL SDA
2-WIRE
SERIAL
INTERFACE
Figure 74. Bipolar Operation with the AD56x5R/AD56x5
1 mA + (5 V/5 kΩ) = 2 mA
POWER SUPPLY BYPASSING AND GROUNDING
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 4 ppm (20 µV) error for the 2 mA current drawn
from it. This corresponds to a 0.263 LSB error.
15V
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD56x5R/AD56x5
should have separate analog and digital sections, each having its
own area of the board. If the AD56x5R/AD56x5 are in a system
where other devices require an AGND-to-DGND connection,
the connection should be made at one point only. This ground
point should be as close as possible to the AD56x5R/AD56x5.
5V
REF195
V
DD
SCL
SDA
AD5625R/
AD5645R/
AD5665R/
AD5625/
AD5665
GND
V
= 0V TO 5V
OUT
2-WIRE
SERIAL
INTERFACE
The power supply to the AD56x5R/AD56x5 should be bypassed
with 10 µF and 0.1 µF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 µF capaci-
tor ideally right up against the device. The 10 µF capacitor is
the tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and low effective
series inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
Figure 73. REF195 as Power Supply to the AD56x5R/AD56x5
BIPOLAR OPERATION USING THE
AD56x5R/AD56x5
The AD56x5R/AD56x5 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit shown in Figure 74. The circuit gives an output voltage
range of 5 V. R ail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
The output voltage for any input code can be calculated as follows:
D
65,536
R1+ R2
R1
R2
R1
V = V
×
×
−V
×
DD
O
DD
where D represents the input code in decimal (0 to 65,535).
If VDD = 5 V, R1 = R2 = 10 kΩ,
10× D
65,536
V =
− 5 V
O
This is an output voltage range of 5 V, wit h 0x0000 corre-
sponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.
Rev. C | Page 32 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 75. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. C | Page 33 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Data Sheet
1.705
1.665
1.625
BOTTOM VIEW
(BALL SIDE UP)
3
2
1
A
BALL A1
IDENTIFIER
2.285
2.245
2.205
1.50
REF
B
C
D
0.50
BSC
TOP VIEW
(BALL SIDE DOWN)
1.00
REF
0.380
0.650
0.595
0.540
0.355
0.330
END VIEW
COPLANARITY
0.05
SEATING
PLANE
0.270
0.240
0.210
0.340
0.320
0.300
Figure 77. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-9)
Dimensions shown in millimeters
Rev. C | Page 34 of 36
Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
ORDERING GUIDE
Temperature
Range
On-Chip
Maximum
Package
Description
Package
Option
Model1
Accuracy
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
Reference I2C Speed
Branding
D±V
D±V
AD5625BCPZ-R2
AD5625BCPZ-REEL7
AD5625BRUZ
AD5625BRUZ-REEL7
AD5625RBCPZ-R2
AD5625RBCPZ-REEL7
AD5625RACPZ-REEL7
AD5625RACPZ-1RL7
AD5625RBRUZ-1
AD5625RBRUZ-1REEL7
AD5625RBRUZ-2
AD5625RBRUZ-2REEL7
AD5645RBCPZ-R2
AD5645RBCPZ-REEL7
AD5645RBRUZ
AD5645RBRUZ-REEL7
AD5665BCPZ-R2
AD5665BCPZ-REEL7
AD5665BRUZ
AD5665BRUZ-REEL7
AD5665RBCBZ-1-RL7
AD5665RBCPZ-R2
AD5665RBCPZ-REEL7
AD5665RBRUZ-1
AD5665RBRUZ-1REEL7
AD5665RBRUZ-2
AD5665RBRUZ-2REEL7
EVAL-AD5665REBZ1
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
None
None
None
None
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
14-Lead TSSOP
14-Lead TSSOP
RU-14
RU-14
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
D±S
D±S
DEU
DFW
RU-14
RU-14
RU-14
RU-14
1.25 V
1.25 V
2.5 V
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
14-Lead TSSOP
14-Lead TSSOP
D±9
D±9
RU-14
RU-14
2.5 V
±16 LSB INL None
±16 LSB INL None
±16 LSB INL None
±16 LSB INL None
±16 LSB INL 1.25 V
±16 LSB INL 1.25 V
±16 LSB INL 1.25 V
±16 LSB INL 2.5 V
±16 LSB INL 2.5 V
±16 LSB INL 2.5 V
±16 LSB INL 2.5 V
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
14-Lead TSSOP
14-Lead TSSOP
12-Ball WLCSP
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
D6U
D6U
RU-14
RU-14
CB-12-9
DA2
DA2
RU-14
RU-14
RU-14
RU-14
TSSOP Evaluation
Board
EVAL-AD5665REBZ2
1 Z = RoHS Compliant Part.
LFCSP Evaluation
Board
Rev. C | Page 35 of 36
AD5625R/AD5645R/AD5665R, AD5625/AD5665
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007-2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06341-0-3/13(C)
Rev. C | Page 36 of 36
AD5625BCPZ-R2 CAD模型
引脚图
封装焊盘图
AD5625BCPZ-R2 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| AD5625BCPZ-REEL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On | 完全替代 |
|
| AD5625BRUZ | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On | 类似代替 |
|
| AD5625RBCPZ-R2 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C | 类似代替 |
|
AD5625BCPZ-R2 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AD5625BCPZ-REEL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
|
| AD5625BRUZ | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
|
| AD5625BRUZ-REEL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
|
| AD5625R | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
|
| AD5625RACPZ-1RL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface | 获取价格 |
|
| AD5625RACPZ-REEL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface | 获取价格 |
|
| AD5625RBCPZ-250RL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
|
| AD5625RBCPZ-R2 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface | 获取价格 |
|
| AD5625RBCPZ-REEL7 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
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| AD5625RBRUZ-1 | ADI | Quad, 12-/14-/16-Bit nanoDACs with 5ppm/∑C On-chip Ref, I2C Interface | 获取价格 |
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