AD5648BRUZ-1 [ADI]
Octal, 12-14-16 Bit Dac with 10ppm/∑C Max On-Chip Reference in 14-Lead TSSOP; 八， 16年12月14日bit数模转换器，具有10ppm的/ ΣC最大片的14引脚TSSOP参考
| 型号： | AD5648BRUZ-1 |
| 厂家： | 
ADI |
| 描述： | Octal, 12-14-16 Bit Dac with 10ppm/∑C Max On-Chip Reference in 14-Lead TSSOP |
| 文件： | 总24页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 12-14-16 Bit Dac with 10ppm/°C Max
On-Chip Reference in 14-Lead TSSOP
Preliminary Technical Data
AD5628/AD5648/AD5668
Digital Gain and Offset Adjustment
FEATURES
Programmable Voltage and Current Sources
Low Power Smallest Pin compatible Octal DACs
AD5668: 16 Bits
Programmable Attenuators
V
V
REF
DD
AD5648: 14 Bits
AD5628: 12 Bits
AD5628/AD5648/AD5668
1.25/2.5V
Ref
12-Bit Accuracy Guaranteed
14/16-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/°C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero/Midscale
Three Power-Down Functions
Hardware /LDAC and /CLR functions
Rail-to-Rail Operation
I
NPUT
REGISTER
DAC
STRING
DAC A
BUFFER
REGISTER
LDAC
V
A
B
OUT
I
NPUT
REGISTER
STRING
DAC B
DAC
REGISTER
BUFFER
BUFFER
BUFFER
V
OUT
I
NPUT
REGISTER
DAC
REGISTER
STRING
DAC C
V
OUT
C
SCLK
SYNC
DIN
I
NPUT
REGISTER
STRING
DAC D
D
AC
REGISTER
V
OUT
D
INTERFACE
LOGIC
I
NPUT
REGIS-
TER
D
AC
REGISTER
STRING
DAC E
V
OUT
E
BUFFER
I
NPUT
REGISTER
D
AC
REGISTER
STRING
DAC F
V
OUT
F
BUFFER
BUFFER
BUFFER
I
NPUT
REGISTER
STRING
DAC G
D
AC
REGISTER
V
V
G
H
OUT
OUT
I
NPUT
REGISTER
D
AC
REGISTER
STRING
DAC
H
Temperature Range -40°C to +125°C
POWER-DOWN
LOGIC
POWER-ON
RESET
APPLICATIONS
ProcessControl
GND
LDAC*
CLR*
*RU-16 PACKAGE ONLY
Data Acquisition Systems
Portable Battery Powered Instruments
Figure 1. Functional Block Diagram
The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .
GENERAL DESCRIPTION
The AD5628/48/68 family of devices are low power, octal, 12-
14-16-bit buffered voltage-out DACs. All devices operate from
a single +2.7V to +5.5V, and are guaranteed monotonic by
design.
The AD5628/48/68 utilizes a versatile three-wire serial
interface that operates at clock rates up to 50 MHz and is
compatible with standard SPI™, QSPI™, MICROWIRE™ and
DSP interface standards. Its on-chip precision output amplifier
allows rail-to-rail output swing to be achieved.
The AD5628/48/68 have an on-chip reference with an internal
gain of two. The AD56x8-1 has a 1.25V 10ppm/°C max
reference and the AD56x8-2,-3 have a 2.5V 10ppm/°C max
reference. The on-board reference is off at power-up allowing
the use of an external reference. The internal reference is
turned on by writing to the DAC. The part incorporates a
power-on-reset circuit that ensures that the DAC output
powers up to zero volts (AD56x8-1,-2/) or midscale (AD5668-
3) and remains there until a valid write takes place. The part
contains a power-down feature that reduces the current
consumption of the device to 200nA at 5V and provides
software selectable output loads while in power-down mode for
any or all DACs channels.
PRODUCT HIGHLIGHTS
1. Octal 12/14/16-Bit DAC; 12-Bit Accuracy Guaranteed.
2. On-chip 1.25/2.5V, 10ppm/°C max Reference.
3. Available in 14/16-lead TSSOP package.
4. Power-On-Reset to Zero volts or Midscale.
5. Power-down capability. When powered down, the
DAC typically consumes 50nA at 3V and 200nA at 5V.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
AD5628/AD5648/AD5668
TABLE OF CONTENTS
Features.......................................................................................... 1
AD5628/AD5648/AD5668–Typical Performance
Characteristics ................................................................................ 13
General Description................................................................... 16
Serial Interface............................................................................ 16
Microprocessor Interfacing............................................................
Applications .....................................................................................
Outline Dimensions....................................................................... 23
Ordering Guide ...............................................................................
Applications................................................................................... 1
General Description..................................................................... 1
Product Highlights....................................................................... 1
AD5628/AD5648/AD5668–Specifications ................................... 3
Timing Characteristics..................................................................... 9
Pin Configuration and Function Descriptions........................... 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Terminology................................................................................ 11
REVISION HISTORY
Revision 0: Initial Version
Rev.PrA | Page 2 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
AD5628/AD5648/AD5668–SPECIFICATIONS
(VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications TMIN to TMAX unless otherwise
noted)
Table 1.
A Grade
Typ
B Grade
Typ
B Version 1,2
Conditions/Comments
Parameter
STATIC PERFORMANCE3,4
Min
Max
Min
Max
Unit
AD5628
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
LSB
±±.5
±2
±6
±1
±±.5
±2
±1
±1
See Figure 4
Guaranteed Monotonic by Design. See
Figure 5.
AD5648
Resolution
Relative Accuracy
Differential Nonlinearity
14
16
14
16
Bits
LSB
LSB
±8
±1
±4
±1
See Figure 4
Guaranteed Monotonic by Design. See
Figure 5.
AD5668
Resolution
Relative Accuracy
Differential Nonlinearity
Bits
LSB
LSB
±32
±1
±16
±1
See Figure 4
Guaranteed Monotonic by Design. See
Figure 5.
Load Regulation
Zero Code Error
2
2
LSB/mA
mV
VDD=Vref=5V, Midscale Iout=±mA to
15mA sourcing/sinking
All Zeroes Loaded to DAC Register. See
Figure 8.
+1
+9
+1
+9
Zero Code Error Drift3
Full-Scale Error
±2±
-±.15
±2±
-±.15
µV/°C
% of FSR
-1.25
±1.5
-1.25
±1.5
All Ones Loaded to DAC Register. See
Figure 8.
Gain Error
Gain Temperature
Coefficient
% of FSR
ppm
±5
±5
of FSR/°C
Offset Error
±1
±9
±1
±9
mV
Offset Temperature
Coefficient
1.7
1.7
µV/°C
DC Power Supply Rejection
–80
–80
dB
VDD 10ꢀ
Ratio6
DC Crosstalk6 (Ext Ref)
DC Crosstalk6 (Int Ref)
R
L
= 2 k. to GND or VDD
µV
10
4.5
10
20
4.5
20
10
4.5
10
20
4.5
20
µV/mA
µV
Due to Load current change
Due to Powering Down (per channel)
µV
RL = 2 k. to GND or VDD
µV/mA
µV
Due to Load current change
Due to Powering Down (per channel)
1 Temperature ranges are as follows: B Version: -4±°C to +125°C, typical at 25°C.
2 Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
3DC specifications tested with the outputs unloaded unless stated otherwise.
4Linearity is tested using a reduced code range: AD5628 (Code 48 to Code 4±47), AD5648 (Code / to Code /), and AD5668 (Code 485 to 64714).
6Guaranteed by design and characterization; not production tested.
8Interface inactive. All DACs active. DAC outputs unloaded.
9All eight DACs powered down.
Specifications subject to change without notice.
Rev. PrA| Page 3 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
A Grade
B Grade
Typ
B Version 1,2
Conditions/Comments
Parameter
Min
Typ
Max
Min
Max
Unit
OUTPUT
CHARACTERISTICS6
Output Voltage Range
Capacitive Load Stability
±
VDD
±
VDD
V
2
2
pF
pF
Ω
mA
µs
RL=∞
RL=2 kΩ
1±
±.5
3±
4
1±
±.5
3±
4
DC Output Impedance
Short Circuit Current
Power-Up Time
VDD=+5V
Coming out of Power-Down Mode.
VDD=+5V
REFERENCE INPUTS3
Reference Input voltage
Reference Current
VDD
VDD
V
µ A
1ꢀ for specified performance
VREF = VDD = +5.5V (per DAC channel)
35
45
35
45
Reference Input Range
Reference Input Impedance
0
VDD
0
VDD
14.6
14.6
Per DAC channel
kΩ
REFERENCE OUTPUT
Output Voltage
2.495
2.5
2.5±5
±1±
2.495
2.5
2.5±5
±1±
V
AD5628/AD5648/AD5668x-
2/3
Reference TC
ppm/°C
Reference Output
Impedance
2
2
kΩ
LOGIC INPUTS3
Input Current
±1
±.8
±1
±.8
µA
V
V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)8
VDD=4.5 V to +5.5 V
VDD=+5 V
VDD=+5 V
2
2
3
2
3
2
pF
4.5
5.5
4
4.5
5.5
4
V
All Digital Inputs at ± or VDD
DAC Active and Excluding Load Current
VIH=VDD and VIL=GND
mA
IDD (All Power-Down
Modes)9
VDD=4.5 V to +5.5 V
POWER EFFICIENCY
IOUT/IDD
±.2
89
1
±.2
89
1
µA
%
VIH=VDD and VIL=GND
ILOAD=2 mA, VDD=+5 V
Rev.PrA | Page 4 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
AC CHARACTERISTICS1 (VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all
specifications TMIN to TMAX unless otherwise noted)
B Version 1
Conditions/Comments
Parameter2
Min
Typ
Max
Unit
Output Voltage Settling Time
AD5628
6
7
8
8
9
1±
µs
µs
µs
¼ to ¾ scale settling to ±2LSB
¼ to ¾ scale settling to ±2LSB
¼ to ¾ scale settling to ±2LSB
AD5648
AD5668
Settling Time for 1LSB Step
Slew Rate
Digital-to-Analog Glitch Impulse
Channel –to-Channel Isolation
Digital Feedthrough
Digital Crosstalk
1.5
5
1±±
±.1
±.5
1
V/µs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
kHz
1 LSB Change Around Major Carry. See Figure 21.
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
3
2±±
-8±
12±
1±±
15
VREF = 2V ± ±.1 V p-p.
dB
VREF = 2V ± ±.1 V p-p. Frequency = 1±kHz
DAC code=84±±H, 1kHz
DAC code=84±±H, 1±kHz
±.1Hz to 1±Hz;
nV/√Hz
nV/√Hz
µVp-p
Output Noise
NOTES
1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.
Specifications subject to change without notice.
Rev. PrA| Page 5 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
AD5628/AD5648/AD5668–SPECIFICATIONS
(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD ; all specifications TMIN to TMAX unless otherwise
noted)
Table 2.
A Grade
Typ
B Grade
Typ
B Version 1,1
Conditions/Comments
Parameter
STATIC PERFORMANCE3,4
Min
Max
Min
Max
Unit
AD5628
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
LSB
±±.5
±2
±6
±1
±±.5
±2
±1
±1
See Figure 4
Guaranteed Monotonic by Design.
See Figure 5.
AD5648
Resolution
Relative Accuracy
Differential Nonlinearity
14
16
14
16
Bits
LSB
LSB
±8
±1
±4
±1
See Figure 4
Guaranteed Monotonic by Design.
See Figure 5.
AD5668
Resolution
Relative Accuracy
Differential Nonlinearity
Bits
LSB
LSB
±32
±1
±16
±1
See Figure 4
Guaranteed Monotonic by Design.
See Figure 5.
Load Regulation
4
4
LSB/mA
VDD=Vref=3V, Midscale
Iout=±mA to 7.5mA
sourcing/sinking
Zero Code Error
+1
+9
+1
+9
mV
All Zeroes Loaded to DAC Register.
See Figure 8.
Zero Code Error Drift1
Full-Scale Error
±2±
-±.15
±2±
-±.15
µV/°C
-1.25
±±.7
-1.25
±±.7
% of FSR All Ones Loaded to DAC Register.
See Figure 8.
% of FSR
Gain Error
Gain Temperature
Coefficient
±5
±5
ppm
of FSR/°C
Offset Error
±1
±9
±1
±9
mV
Offset Temperature
Coefficient
1.7
1.7
µV/°C
DC Power Supply Rejection
–80
–80
dB
VDD 10ꢀ
Ratio6
DC Crosstalk6 (Ext Ref)
DC Crosstalk6 (Int Ref)
R
L
= 2 k. to GND or VDD
µV
10
4.5
10
10
4.5
10
µV/mA
µV
Due to Load current change
Due to Powering Down (per
channel)
RL = 2 k. to GND or VDD
µV
20
4.5
20
20
4.5
20
µV/mA
µV
Due to Load current change
Due to Powering Down (per
channel)
OUTPUT
CHARACTERISTICS6
Output Voltage Range
Capacitive Load Stability
±
VDD
±
VDD
V
pF
2
2
RL=∞
Rev.PrA | Page 6 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
1±
1±
±.5
3±
5
pF
Ω
mA
µs
RL=2 kΩ
DC Output Impedance
Short Circuit Current
Power-Up Time
±.5
3±
5
VDD=+3V
Coming Out of Power-Down Mode.
VDD=+3V
REFERENCE INPUTS3
Reference Input voltage
Reference Current
VDD
VDD
V
µ A
1ꢀ for specified performance
VREF = VDD = +3.6V (per DAC
channel)
20
20
20
20
Reference Input Range
0
VDD
0
VDD
Reference Input Impedance
14.6
14.6
Per DAC channel
kΩ
REFERENCE OUTPUT
Output Voltage
1.248
1.25
1.252
±1±
1.248
1.25
1.252
±1±
V
AD5628/AD5648/AD5668x-
1
Reference TC
ppm/°C
Reference Output
Impedance
2
2
kΩ
LOGIC INPUTS3
Input Current
±1
±.8
±1
±.8
µA
V
V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
VDD=+3 V
VDD=+3 V
2
2
3
2
3
2
pF
2.7
3.6
4
2.7
3.6
4
V
All Digital Inputs at ± or VDD
DAC Active and Excluding Load
Current
IDD (Normal Mode)8
VDD=2.7 V to +3.6 V
mA
VIH=VDD and VIL=GND
IDD (All Power-Down
Modes)9
VDD=2.7 V to +3.6 V
POWER EFFICIENCY
IOUT/IDD
±.2
89
1
±.2
89
1
µA
%
VIH=VDD and VIL=GND
ILOAD=2 mA, VDD=+5 V
AC CHARACTERISTICS1
(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications TMIN to TMAX unless otherwise
noted)
B Version 1
Conditions/Comments
Parameter2
Min
Typ
Max
Unit
Output Voltage Settling Time
AD5628
6
7
8
8
9
1±
µs
µs
µs
¼ to ¾ scale settling to ±2LSB
¼ to ¾ scale settling to ±2LSB
¼ to ¾ scale settling to ±2LSB
AD5648
AD5668
Settling Time for 1LSB Step
Slew Rate
Digital-to-Analog Glitch Impulse
Channel –to-Channel Isolation
Digital Feedthrough
1.5
1±
1±±
±.5
V/µs
nV-s
dB
1 LSB Change Around Major Carry. See Figure 21.
nV-s
Rev. PrA| Page 7 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Digital Crosstalk
±.5
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
3
nV-s
kHz
dB
nV/√Hz
nV/√Hz
µVp-p
2±±
-8±
12±
1±±
15
VREF = 2V ± ±.1 V p-p.
VREF = 2V ± ±.1 V p-p. Frequency = 1±kHz
DAC code=84±±H, 1kHz
DAC code=84±±H, 1±kHz
±.1Hz to 1±Hz;
Output Noise
NOTES
1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.
Specifications subject to change without notice.
Rev.PrA | Page 8 of 24
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5628/AD5648/AD5668
All input signals are specified with tr = tf = 1 ns/V (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 2.
(VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 3.6 V
VDD= 3.6 V to 5.5 V
Unit
Conditions/Comments
1
t1
2±
2±
ns min
SCLK Cycle Time
t2
t3
t4
t5
t6
t7
t8
t9
t1±
11
9
9
9
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK High Time
SCLK Low Time
SYNC
13
4
4
13
4
4
to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SYNC
±
±
SCLK Falling Edge to
SYNC
Rising Edge
25
13
±
2±
13
±
Minimum
SYNC
High Time
Rising Edge to SCLK Fall Ignore
SYNC
SCLK Falling Edge to
Fall Ignore
LDAC Pulsewidth Low
t11
t12
t13
t14
t15
2±
2±
2±
±
2±
2±
2±
±
ns min
ns min
ns min
ns min
ns min
SCLK Falling Edge to LDAC Rising Edge
/CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
/CLR Pulse Activation Time (AD538±?)
tbd
tbd
t
10
t
1
t
9
SCLK
t
2
t
8
t
t
7
3
t
4
SYNC
t
6
t
5
DIN
DB31
DB0
t11
t14
LDAC1
t12
LDAC2
CLR
t13
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE.
2. SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
1 3Maximum SCLK frequency is 5± MHz at VDD = +2.7 V to +5.5 V
Rev. PrA| Page 9 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
14 SCLK
1
2
16 SCLK
LDAC
SYNC
AD5628
15
VDD
2
13
AD5628
AD5648
AD5668
DIN
SYNC
VDD
DIN
AD5648
AD5668
V
V
A
12 GND
14 GND
3
4
5
6
7
3
4
5
6
7
8
OUT
V
V
A
V
V
B
11
10
9
13
12
11
10
9
C
V
V
B
D
OUT
OUT
OUT
OUT
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
D
F
V
E
C
OUT
OUT
OUT
OUT
V
G
V
F
V
V
V
V
E
OUT
V
OUT
OUT
OUT
H
8
V
H
REF
G
OUT
OUT
OUT
V
CLR
REF
Figure 3. 14-Lead TSSOP (RU-14)
Figure 4. 16-Lead TSSOP (RU-16)
Table 2. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
2
/LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
/SYNC
Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following 32 clocks. If SYNC is taken high before the 32nd
falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
device.
3
4
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
VOUTA
VOUTB
VOUTC
VOUTD
VREF
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Reference Input/Output Pin
13
5
12
8
Active Low Control Input that Loads Software selectable code – Zero, midscale, fullscale - to All Input and
DAC Registers. Therefore, the outputs also go to selected code. Default clears the output to 0V.
9
/CLR
6
VOUTE
VOUTF
VOUTG
VOUTH
GND
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
11
7
10
14
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 50 MHz.
Rev.PrA | Page 1± of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
ABSOLUTE MAXIMUM RATINGS
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ Max)
TSSOP Package
-±.3 V to VDD + ±.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-4±°C to +1±5°C
-65°C to +15±°C
+15±°C
Power Dissipation
(TJ Max-TA)/θJA
15±.4°C/W
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (6± sec)
(TA = +25°C unless otherwise noted)
+215°C
+22±°C
Parameter
Rating
Infrared (15 sec)
VDD to GND
Digital Input Voltage to GND
-±.3 V to +7 V
-±.3 V to VDD + ±.3 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
(0000Hex) is loaded to the DAC register. Ideally the output should
be 0 V. The zero-code error is always positive in the AD56x8
because the output of the DAC cannot go below 0 V. It is due to a
combination of the offset errors in the DAC and output amplifier.
Zero-code error is expressed in mV. A plot of zero-code error vs.
temperature can be seen in Figure 6.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL) is a
measure of the maximum deviation, in LSBs, from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 2.
Gain Error
Differential Nonlinearity
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal expressed as
a percent of the full-scale range.
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen in
Figure 3.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a change in
temperature. It is expressed in µV/°C.
Gain Error Drift
Offset Error
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear
region of the transfer function. Offset error is measured on
the AD5668 with Code ??? loaded into the DAC register.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFFF Hex) is loaded to the DAC register. Ideally the output
should be VDD – 1 LSB. Full-scale error is expressed in percent of
full-scale range. A plot of full-scale error vs. temperature can be
seen in Figure 6.
This is a measure of the offset error of the DAC and the output
amplifier (see Figures 2 and 3). It can be negative or positive, and is
expressed in mV.
Zero-Code Error
Total Unadjusted Error
Zero-code error is a measure of the output error when zero code
Total Unadjusted Error (TUE) is a measure of the output error
Rev. PrA| Page 11 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
taking the various offset and gain errors into account. A typical
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to (SYNC held
high). It is specified in nV-s and is measured with a fullscale
change on the digital input pins, i.e., from all 0s to all 1s and vice
versa.
TUE vs. code plot can be seen in Figure 4.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs and
is measured when the digital input code is changed by 1 LSB at the
major carry transition (7FFF Hex to 8000 Hex). See Figure 19.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s and
vice versa) in the input register of another DAC. It is measured in
standalone mode and is expressed in nV-s.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT
to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied 10ꢀ.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC due
to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change (all
0s to all 1s and vice versa) while keeping LDAC high. Then pulse
LDAC low and monitor the output of the DAC whose digital code
was not changed. The area of the glitch is expressed in nV-s.
DC Crosstalk
This is the dc change in the output level of one DAC in response to
a change in the output of another DAC. It is measured with a full-
scale output change on one DAC while monitoring another DAC
kept at midscale. It is expressed in µV.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC due
to a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code change
(all 0s to all 1s and vice versa) with LDAC low and monitoring the
output of another DAC. The energy of the glitch is expressed in
nV-s.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
Multiplying Bandwidth
This is the ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of another DAC. It is
measured in dB.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on the
output. The multiplying bandwidth is the frequency at which the
output amplitude falls to 3 dB below the input.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB at
the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).
Total Harmonic Distortion
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference for
the DAC, and the THD is a measure of the harmonics present on
the DAC output. It is measured in dB.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
Rev.PrA | Page 12 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
AD5628/AD5648/AD5668–TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical INL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 5. Typical DNL Plot
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. Typical Total Unadjusted Error Plot
Figure 9. IDD Histogram with VDD=3V and VDD=5V
Rev. PrA| Page 13 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Figure 13. Supply Current vs. Temperature
Figure 10. Source and Sink Current Capability with VDD=3V
Figure 14. Supply Current vs. Supply Voltage
Figure 11. Source and Sink Current Capability with VDD=5 V
Figure 12. Supply Current vs. Code
Figure 15. Power-Down Current vs. Supply Voltage
Rev.PrA | Page 14 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Figure 19. Power-On Reset to 0V
Figure 16. Supply Current vs. Logic Input Voltage
Figure 20. Exiting Power-Down (800 Hex Loaded)
Figure 17. Full-Scale Settling Time
Figure 21. Digital-to-Analog Glitch Impulse
Figure 18. Half-Scale Settling Time
Rev. PrA| Page 15 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
GENERAL DESCRIPTION
D/A Section
The AD5628/AD5648/AD5668 DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. The parts include an
internal 1.25/2.5V, 10ppm/°C reference with an internal gain of
two. Figure 22 shows a block diagram of the DAC architecture.
V
DD
REF (+)
RESISTOR
STRING
V
DAC REGISTER
OUT
REF ()
OUTPUT
AMPLIFIER
(Gain=2)
GND
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
D
⎛
⎜
⎞
⎟
VOUT = Vref (ext)×
Figure 23. Resistor String
2^ N
⎝
⎠
Resistor String
D
⎛
⎜
⎞
⎟
VOUT = 2∗Vref (int)×
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
2^ N
⎝
⎠
where D = decimal equivalent of the binary code that is loaded
to the DAC register;
0 - 4095 for AD5628 (12 bit)
0 - 16383 for AD5648 (14 bit)
0 - 65535 for AD5668 (16 bit)
Output Amplifier
N = the DAC resolution
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
VDD. It is capable of driving a load of 2 kΩ in parallel with 1000
pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 10 and Figure 11. The slew rate
is 1.5 V/µs with a half-scale settling time of 8 µs with the output
unloaded.
SERIAL INTERFACE
The AD5628/AD5648/AD5668 has a three-wire serial interface
SYNC
(
, SCLK and DIN), which is compatible with SPI, QSPI
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed
Rev.PrA | Page 16 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Input Shift Register
(i.e., a change in DAC register contents and/or a change in the
SYNC
mode of operation). At this stage, the
line may be kept
The input shift register is 32 bits wide (see Figure 24). The first
four bits are “don’t cares.” The next four bits are the Command
bits C3-C0, (see Table 1) followed by the 4-bit DAC address
A3-A0, (see Table 2) and finally the 16/14/12-bit data word.
The data word comprises the 16- 14- 12- bit input code
followed by 4, 6 or 8 don’t care bits, the AD5668, AD5648 and
AD5628 respectively. See figure 24, 25, 26. These data bits are
transferred to the DAC register on the 32nd falling edge of
SCLK.
low or be brought high. In either case, it must be brought high
for a minimum of 50 ns before the next write sequence so that a
SYNC
falling edge of
can initiate the next write sequence. Since
buffer draws more current when VIN = 2V than it
SYNC
SYNC
the
does when VIN = 0.8 V,
should be idled low between
write sequences for even lower power operation of the part. As
is mentioned above, however, it must be brought high again just
before the next write sequence.
DB0 (LSB)
X
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
ADDRESS BITS
Figure 24 AD5668. Input Register Contents
DB0 (LSB)
X
X
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
COMMAND BITS
ADDRESS BITS
Figure 25. AD5648. Input Register Contents
DB0 (LSB)
X
X
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
COMMAND BITS
ADDRESS BITS
Figure 26. AD5628 Input Register Contents
Rev. PrA| Page 17 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Command
ADDRESS (n)
C3
0
C2
0
C1
0
C0
0
A3
0
A2
0
A1
0
A0
0
Write to Input Register n
Update DAC Register n
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
0
0
0
1
0
0
0
1
0
0
1
0
Write to Input Register n,
Update All
0
0
1
0
0
0
1
1
0
0
0
1
1
0
1
0
Write to and Update DAC
channel n
0
1
0
0
0
1
0
1
Power Down DAC
(Power-up)
0
1
1
0
0
0
1
1
0
1
1
0
Load Clear Code Register
0
1
1
1
Load LDAC Register
(LDAC overwrite)
1
1
1
1
0
1
1
*
1
0
0
*
1
0
0
*
1
0
1
*
Reset (Power-on-Reset)
REF Setup Register
Reserved
Reserved
1
1
1
1
Reserved
Table 1. Command Definition
Table2. Address Command
SYNC
Interrupt
In a normal write sequence, the
rising edge of SYNC . However, if
SYNC
line is kept low for 32 falling edges of SCLK and the DAC is updated on the 32nd falling edge and
SYNC
is brought high before the 32nd falling edge this acts as an interrupt to the write sequence. The
shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating
mode occurs—see Figure 27.
SCLK
SYNC
DB31
DB0
DB0
DB31
DIN
VALID WRITE SEQUENCE, OUTPUT UPDATES
ND
INVALID WRITE SEQUENCE:
ND
ON THE 32
FALLING EDGE
SYNC HIGH BEFORE 32
FALLING EDGE
Figure 27. SYNC Interrupt Facility
Rev.PrA | Page 18 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Reference Setup –External to Internal
The on-board reference is turned off at power-up by default. This allows the use of an external reference. The AD5628/48/68 have an on-
chip reference with an internal gain of two. The AD56x8-1 has a 1.25V 10ppm/°C max reference and the AD56x8-2,-3 have a 2.5V
10ppm/°C max reference. The on-board reference can be turned on/off through a software executable REF Setup function, see Table 3.
Command 1000 is reserved for this REF Setup function, see Table 1. The reference mode is software-programmable by setting a bit
(DB0) in the REF Setup register.
Table 4 shows how the state of the bits corresponds to the mode of operation of the device.
REF Setup Register
(DB0)
Action
0
1
Ref Off (Default)
Ref On
Table 3. Reference Set-up Register
MSB
LSB
DB31 –
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB1-
DB19
DB0
x
1
0
0
0
x
x
x
x
x
1/0
Don’t
Cares
COMMAND BITS (C3-C0)
ADDRESS BITS (A3 – A0)
Don’t
Cares
REF Setup
Register
Table 4 32-Bit Input Shift Register Contents for Reference Setup Function
Power-On-Reset
The AD5628/AD5648/AD5668 family contains a power-on-reset circuit that controls the output voltage during power-up. The
AD5628/AD5648/AD5668x-1/2 DAC output powers up to zero volts and the AD5668-3 DAC output powers up to midscale. The output
remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable Reset function that will reset the DAC to the Power-on -Reset code. Command 0111 is reserved for
this Reset function, see Table 1.
Power-Down Modes
The AD5628/AD5648/AD5668 contains four separate modes of operation. Command 0100 is reserved for the Power-Down function,
see Table 1. These modes are software-programmable by setting two bits (DB9 and DB8) in the control register.
Table 5 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs, (DacH to DacA) may be
powered down to the selected mode by setting the corresponding 8 bits (DB7 to DB0) to a “1”. See Table 6 for contents of the Input
Shift Register during power down/up operation.
When both bits are set to 0, the part works normally with its normal power consumption of 250 µA at 5 V. However, for the three power-
Rev. PrA| Page 19 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also
internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output
impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected
internally to GND through a 1 kΩ resistor, a 100 kΩ resistor or it is left open-circuited (Tri-State). The output stage is illustrated in
figure 24.
The bias generator of selected DAC(s), the output amplifier, the resistor string and other associated linear circuitry are all shut down
when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit
power-down is typically (2.5 µs for VDD = 5 V and 5 µs for VDD = 3 V). See Figure 20 for a plot.
Any combination of DACs can be powered up by setting PD1 and PD0 to “0” (normal operation). Output powers-up to value in input
register (/LDAC Low) or to value in DAC register before Power-Down (/LDAC High).
DB9
DB8
Operating Mode
Normal Operation
Power Down Modes
1 kΩ to GND
1±± kΩ to GND
Tri State
±
±
±
1
1
1
±
1
Table 5. Modes of Operation for the AD5628/AD5648/AD5668
MSB
LSB
DB31 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10— DB9 DB8 DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
–
DB19
DB28
x
±
1
±
±
x
x
x
x
x
PD1 PD±
DacH DacG DacF DacE DacD DacC DacB DacA
Don’t
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 – A0)
Don’t cares
Don’t
Cares
Power
Down Mode
Power Down/Up Channel Selection – Set Bit to a “1” to select
Table 6. 32-Bit Input Shift Register Contents for Power Down/Up Function
Rev.PrA | Page 2± of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Clear Code Register
The AD5628/AD5648/AD5668 gives the option of clearing any one or all DAC channels to 0, midscale or fullscale code. Command 0101
is reserved for the Clear Code function. See Table1. These clear code values are software-programmable by setting two bits (DB1 and
DB0) in the control register.
Table shows how the state of the bits corresponds to the clear code values of the device. Upon execution of the hardware /CLR pin
(active LOW), the DAC output is cleared to the clear code register value (default setting is zero). See Table 8 for contents of the Input
Shift Register during the Clear Code Register operation. The part will exit Clear code mode on the 32nd falling edge of the next write to
the part.
Clear Code Register
CR1
±
CR0
±
Clears to code
±±±±h
±
1
8±±±h
1
±
FFFFh
1
1
No operation
Table 7. Clear Code Register
MSB
LSB
DB0
1/±
DB31 –
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2-
DB19
DB1
X
±
1
±
1
1/±
1/±
1/±
1/±
x
1/±
Don’t
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 – A0)
Don’t
Cares
Clear Code
Register (CR1-
CR±)
Table 8. 32-Bit Input Shift Register Contents Clear Code Function
LDAC Function
The outputs of all DACs may be updated simultaneously using the hardware /LDAC pin.
Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 32nd SCLK pulse. LDAC can be
permanently low or pulsed as in Figure 1.
Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the
DAC registers are updated with the contents of the input register.
The outputs of all DACs may be updated simultaneously using the /LDAC function, with the added functionality of selecting through
software any number of DAC channels to synchronize.
Writing to the DAC using command 0110, the hardware /LDAC pin can be overwritten by setting the bits of the 8-bit /LDAC register
(DB7-DB0) . SeeTable 9 for the /LDAC mode of operation. The default for each channel is “0” ie /LDAC pin works normally. Setting the
bits to a “1” means the DAC channel will be updated regardless of the state of the /LDAC pin. This gives the added benefit of allowing
any combination of channels to be synchronously updated. See Table 10 for contents of the Input Shift Register during the /LDAC
overwrite mode of operation.
Rev. PrA| Page 21 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
Load DAC OVERWRITE
/LDACBITS (DB7-
DB0)
/LDAC PIN
1/±
/LDAC Operation
±
Determined by
/LDAC pin
1
x – Don’t Care
DAC channels will
update, overwriting
the /LDAC pin
Table 9. LDAC Overwrite Definition
MSB
LSB
DB31 DB27
–
DB28
DB8 – DB7
DB19
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB2
6
DB2
5
DB2
4
DB2
3
DB2
2
DB2
1
DB2
0
x
±
1
1
±
x
x
x
x
x
DacH
DacG
DacF
DacE
DacD
DacC
DacB
DacA
Don’t
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 – A0)
Don’t cares
Don’t
Cares
Setting /LDAC bit to “1” overwrites /LDAC pin
Table 10. 32-Bit Input Shift Register Contents for /LDAC Overwrite Function
Effective Series Inductance (ESI), e.g., common ceramic types
of capacitors. This 0.1 µF capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.
Power Supply Bypassing and Grounding
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
AD5628/AD5648/AD5668 should have separate analog and
digital sections, each having its own area of the board. If the
AD5628/AD5648/AD5668 is in a system where other devices
require an AGND to DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should be physically as close as possible to the device with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor has low Effective Series Resistance (ESR) and
Rev.PrA | Page 22 of 24
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5628/AD5648/AD5668
0.201 (5.10)
0.193 (4.90)
14
8
7
1
PIN 1
0.006 (0.15)
0.0433
(1.10)
MAX
0.002 (0.05)
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
Figure 28. 14-Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
0.201 (5.10)
0.193 (4.90)
16
9
1
8
PIN
1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
Figure 29. 16-Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Bit
Power-On-Reset
Internal Reference
Package
Option1
AD5628BRUZ-1
AD5628BRUZ-2
AD5628ARUZ-2
AD5648BRUZ-1
AD5648BRUZ-2
AD5648ARUZ-2
AD5668BRUZ-1
12
12
12
14
14
14
16
Zero
Zero
Zero
Zero
Zero
Zero
Zero
1.25V
2.5V
RU-14
RU-16
RU-16
RU-14
RU-16
RU-16
RU-14
2.5V
1.25V
2.5V
2.5V
1.25V
Rev. PrA| Page 23 of 24
Preliminary Technical Data
AD5628/AD5648/AD5668
AD5668BRUZ-2
AD5668BRUZ-3
AD5668ARUZ-2
AD5668ARUZ-3
16
16
16
16
Zero
Midscale
Zero
2.5V
2.5V
2.5V
2.5V
RU-16
RU-16
RU-16
RU-16
Midscale
1 Thin Shrink Small Outline Package (TSSOP)
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective companies.
Printed in the U.S.A.
PR05302-0-12/04(PrA)
Rev.PrA | Page 24 of 24
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