AD5660ARJ-2 [ADI]
3 V/5 V, 16-Bit nanoDACTM D/A with 10 ppm/°C Max On-Chip Reference in SOT-23; 3 V / 5 V ， 16位nanoDACTM D / A和10 ppm的/ A ° C（最大值）片内基准采用SOT -23
| 型号： | AD5660ARJ-2 |
| 厂家： | 
ADI |
| 描述： | 3 V/5 V, 16-Bit nanoDACTM D/A with 10 ppm/°C Max On-Chip Reference in SOT-23 |
| 文件： | 总20页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V/5 V, 16-Bit nanoDACTM D/A with
10 ppm/°C Max On-Chip Reference in SOT-23
AD5660
Preliminary Technical Data
FEATURES
Low power single 16-bit nanoDAC
12-bit accuracy guaranteed
On-chip 1.25/2.5 V, 10 ppm/°c reference
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on-reset to zero/midscale
Three power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Processcontrol
Data acquisition systems
Figure 1.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
standards. Its on-chip precision output amplifier allows rail-to-
rail output swing to be achieved.
GENERAL DESCRIPTION
The AD5660 parts are a member of the nanoDAC family of
devices. They are low power, single, 16-bit buffered voltage-out
DACs, guaranteed monotonic by design.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 µW in
power-down mode.
The AD5660x-1 operate from a 3 V single supply featuring an
internal reference of 1.25 V and an internal gain of 2. The
AD5660x-2/3 operate from a 5 V single supply featuring an
internal reference of 2.5 V and an internal gain of 2. Each
reference has a 10 ppm/°C max temperature coefficient. The
reference associated with each part is available at the REFOUT
pin.
The AD5660 is designed with new technology and is the next
generation to the AD53xx family.
PRODUCT HIGHLIGHTS
1. 16-Bit DAC; 12-Bit Accuracy Guaranteed.
2. On-chip 1.25/2.5 V, 10 ppm/°C max Reference.
3. Available in 8-lead SOT-23 and 8-lead MSOP package.
4. Power-On Reset to 0 V or Midscale.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (AD5660x-1/2) or midscale
(AD5660x-3) and remains there until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 200 nA at 5 V and provides
software selectable output loads while in power-down mode.
5. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200n A at 5 V.
6. 10 µS Settling Time.
RELATED DEVICES
Part No.
Description
The AD5660 uses a versatile three-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
AD5620/AD5640
3 V/5 V 12-/14-bit DAC with internal ref in
SOT-23
2.7V to 5.5 V, 16-bit DAC in SOT-23,
external reference
AD5662
Rev. Pr J
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5660
Preliminary Technical Data
TABLE OF CONTENTS
Serial Interface............................................................................ 14
AD5660X-2/3–Specifications ......................................................... 3
AD5660x-1–Specifications.............................................................. 5
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
D/A Section................................................................................. 14
Resistor String............................................................................. 14
Output Amplifier........................................................................ 14
SYNC
Interrupt .......................................................................... 15
Power-On Reset.......................................................................... 15
Power-Down Modes .................................................................. 15
Microprocessor Interfacing....................................................... 15
Applications..................................................................................... 17
Using REF19x as a Power Supply for AD5660 ....................... 17
Bipolar Operation Using the AD5660 ..................................... 17
Using AD5660 with an Opto-Isolated Interface..................... 17
Power Supply Bypassing and Grounding................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
Revision PrJ: Preliminary
Rev. PrJ Page 2 of 20
Preliminary Technical Data
AD5660
AD5660X-2/3–SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version 1
Parameter
STATIC PERFORMANCE2
A Grade B Grade C Grade Unit
Conditions/Comments
Resolution
16
32
1
16
16
1
16
16
1
Bits min
LSB max
LSB max
mV typ
Relative Accuracy
Differential Nonlinearity
Zero Code Error
See Figure 4
Guaranteed Monotonic by Design. See Figure 5.
All Zeroes Loaded to DAC
+5
+5
+5
+20
−0.15
−1.25
1.25
20
+20
−0.15
−1.25
1.25
20
+20
−0.15
−1.25
1.25
20
mV max
% of FSR typ
% of FSR max Register. See Figure 8
% of FSR max
µV/°C typ
ppm typ
Register. See Figure 8.
All Ones Loaded to DAC
Full-Scale Error
Gain Error
Zero Code Error Drift3
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS3
Output Voltage Range
5
5
5
f FSR/°C
0
0
V min
VDD
8
10
12
1
470
1000
100
VDD
8
10
12
1
470
1000
100
VDD
8
10
12
1
470
1000
100
V max
µs typ
µs max
µs typ
V/µs typ
pF typ
Output Voltage Settling Time
To 0.003% FSR 0200H to FD00H
RL = 2 kΩ; 0 pF <CL < 200 pF See Figure 18.
RL = 2 kΩ; CL = 500 pF
Slew Rate
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
DAC code = 8400H, 10 kHz
pF typ
Output Noise
Output Drift
nV/√Hz typ
ppm/°C typ
nV-s typ
nV-s typ
Ω typ
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power-Up Time
10
0.5
1
50
10
10
0.5
1
50
10
10
0.5
1
50
10
1 LSB Change Around Major Carry. See Figure 21.
mA typ
ms typ
VDD = 5 V
Coming Out of Power-Down Mode. VDD = 5 V
REFERENCE OUTPUT
Output Voltage
AD5660x-2/3
2.495
2.505
25
2.495
2.505
25
2.495
2.505
10
V min
V max
ppm/°C max
Reference TC
LOGIC INPUTS3
Input Current
1
0.8
2
1
0.8
2
1
0.8
2
µA max
V max
V min
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
VDD = 5 V
VDD = 5 V
3
3
3
pF max
Rev. PrJ | Page 3 of 20
AD5660
Preliminary Technical Data
B Version 1
Conditions/Comments
Parameter
A Grade B Grade C Grade Unit
POWER REQUIREMENTS
VDD
4.5
5.5
4.5
5.5
4.5
5.5
V min
V max
All Digital Inputs at 0 V or VDD
DAC Active and Excluding
Load Current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD = 4.5 V to +5.5 V
VDD = 4.5 V to +5.5 V
IDD (All Power-Down Modes)
VDD = 4.5 V to +5.5 V
VDD = 4.5 V to +5.5 V
POWER EFFICIENCY
IOUT/IDD
0.5
1
0.5
1
0.5
1
mA typ
mA max
0.2
1
0.2
1
0.2
1
µA typ
µA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
89
89
89
%
ILOAD = 2 mA, VDD = 5 V
1 Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
3 Guaranteed by design and characterization, not production tested.
Rev. PrJ Page 4 of 20
Preliminary Technical Data
AD5660
AD5660X-1–SPECIFICATIONS
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version 4
Parameter
STATIC PERFORMANCE5
A Grade B Grade C Grade Unit
Conditions/Comments
Resolution
16
32
1
16
16
1
16
16
1
Bits min
LSB max
LSB max
mV typ
Relative Accuracy
Differential Nonlinearity
Zero Code Error
See Figure 4
Guaranteed Monotonic by Design. See Figure 5.
All Zeroes Loaded to DAC
+5
+5
+5
+20
−0.15
−1.25
1.25
20
+20
−0.15
−1.25
1.25
20
+20
−0.15
−1.25
1.25
20
mV max
% of FSR typ
% of FSR max Register. See Figure 8.
% of FSR max
µV/°C typ
ppm typ
Register. See Figure 8.
All Ones Loaded to DAC
Full-Scale Error
Gain Error
Zero Code Error Drift6
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS3
Output Voltage Range
5
5
5
of FSR/°C
0
0
V min
VDD
8
10
12
1
470
1000
100
VDD
8
10
12
1
470
1000
100
tbd
10
0.5
1
VDD
8
10
12
1
470
1000
100
V max
µs typ
µs max
µs typ
V/µs typ
pF typ
Output Voltage Settling Time
To 0.003% FSR 0200H to FD00H
RL = 2 kΩ; 0 pF<CL<200 pF See Figure 18.
RL = 2 kΩ; CL = 500 pF
Slew Rate
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
DAC code = 8400H, 10 kHz
pF typ
Output Noise
Output Drift
nV/√Hz typ
ppm/°C typ
nV-s typ
nV-s typ
Ω typ
Digital-to-Analog Glitch Impulse 10
10
0.5
1
20
10
1 LSB Change Around Major Carry. See Figure 21.
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power-Up Time
0.5
1
20
10
20
10
mA typ
ms typ
VDD = 3 V
Coming Out of Power-Down Mode. VDD = 3 V
REFERENCE OUTPUT
Output Voltage
AD5660x-1
1.248
1.252
25
1.248
1.252
25
1.248
1.252
10
V min
V max
ppm/°C max
Reference TC
LOGIC INPUTS3
Input Current
1
0.8
2
1
0.8
2
1
0.8
2
µA max
V max
V min
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
VDD = 3 V
VDD = 3 V
3
3
3
pF max
Rev. PrJ | Page 5 of 20
AD5660
Preliminary Technical Data
B Version 4
Conditions/Comments
Parameter
A Grade B Grade C Grade Unit
POWER REQUIREMENTS
VDD
2.7
3.6
2.7
3.6
2.7
3.6
V min
V max
All Digital Inputs at 0 V or VDD
DAC Active and Excluding
Load Current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
0.5
1
0.5
1
0.5
1
mA typ
mA max
0.2
1
0.2
1
0.2
1
µA typ
µA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
ILOAD = 2 mA, VDD = 3 V
4 Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
5 Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
6 Guaranteed by design and characterization, not production tested.
Rev. PrJ Page 6 of 20
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5660
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
Unit
Conditions/Comments
1
t1
50
33
ns min
SCLK Cycle Time
t2
t3
t4
t5
t6
t7
t8
t9
13
13
13
5
4.5
0
13
13
13
5
4.5
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK High Time
SCLK Low Time
SYNC
to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SYNC
SCLK Falling Edge to
SYNC
Rising Edge
50
13
33
13
Minimum
SYNC
High Time
Rising Edge to SCLK Fall Ignore
SYNC
t10
0
0
ns min
SCLK Falling Edge to
Fall Ignore
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
Figure 2. Serial Write Operation
Rev. PrJ | Page 7 of 20
AD5660
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic
Function
1
2
3
4
5
VDD
VREFOUT
VFB
VOUT
SYNC
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled to GND.
Reference Voltage Output.
Feedback connection for the output amplifier.
Analog output voltage from DAC. The output amplifier has rail to rail operation.
Level triggered control input (active low). This is the frame synchronization signal for the input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
SYNC
clocks. The DAC is updated following the 24th clock cycle unless
is taken high before this edge in which
SYNC
case the rising edge of
acts as an interrupt and the write sequence is ignored by the DAC.
6
7
8
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
GND
Ground reference point for all circuitry on the part.
Rev. PrJ Page 8 of 20
Preliminary Technical Data
AD5660
ABSOLUTE MAXIMUM RATINGS
TA = +25°C unless otherwise noted.
Table 4.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
VDD to GND
Digital Input Voltage to GND
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
SOT-23 Package
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +105°C
−65°C to +150°C
150°C
Power Dissipation
(TJ max − TA)/θJA
240°C/W
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrJ | Page 9 of 20
AD5660
Preliminary Technical Data
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
Total Unadjusted Error
Total Unadjusted Error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE vs.
code plot can be seen in Figure 6.
Differential Nonlinearity
Zero-Code Error Drift
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen in
Figure 5.
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in ( ppm of full-scale range)/°C.
Zero-Code Error
Digital-to-Analog Glitch Impulse
Zero-code error is a measure of the output error when zero
code (0000Hex) is loaded to the DAC register. Ideally the output
should be 0 V. The zero-code error is always positive in the
AD5660 because the output of the DAC cannot go below 0 V. It
is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mV. A plot of
zero-code error vs. temperature can be seen in Figure 8.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by 1
LSB at the major carry transition (7FFF Hex to 8000 Hex). See
Figure 21.
Digital Feedthrough
Full-Scale Error
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Full-scale error is a measure of the output error when full-scale
code (FFFF Hex) is loaded to the DAC register. Ideally the
output should be VDD – 1 LSB. Full-scale error is expressed in
percent of full-scale range. A plot of full-scale error vs.
temperature can be seen in Figure 8.
Gain Error
Rev. PrJ Page 10 of 20
Preliminary Technical Data
AD5660
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical INL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 5. Typical DNL Plot
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. Typical Total Unadjusted Error Plot
Figure 9. IDD Histogram with VDD = 3 V and VDD = 5 V
Rev. PrJ | Page 11 of 20
AD5660
Preliminary Technical Data
Figure 10. Source and Sink Current Capability with VDD = 3 V
Figure 13. Supply Current vs. Temperature
Figure 14. Supply Current vs. Supply Voltage
Figure 15. Power-Down Current vs. Supply Voltage
Figure 11. Source and Sink Current Capability with VDD = 5 V
Figure 12. Supply Current vs. Code
Rev. PrJ Page 12 of 20
Preliminary Technical Data
AD5660
Figure 16. Supply Current vs. Logic Input Voltage
Figure 19. Power-On Reset to 0V
Figure 20. Exiting Power-Down (800 Hex Loaded)
Figure 21. Digital-to-Analog Glitch Impulse
Figure 17. Full-Scale Settling Time
Figure 18. Half-Scale Settling Time
Rev. PrJ | Page 13 of 20
AD5660
Preliminary Technical Data
RESISTOR STRING
THEORY OF OPERATION
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
D/A SECTION
The AD5660 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. The parts include an internal 1.25 V/2.5 V,
10 ppm/°C reference with an internal gain of two. Figure 22
shows a block diagram of the DAC architecture.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to VDD
.
It is capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 10 and Figure 11. The slew rate is 1 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
Figure 22. DAC Architecture
SERIAL INTERFACE
SYNC
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
The AD5660 has a 3-wire serial interface (
, SCLK and
DIN), which is compatible with SPI, QSPI and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
D
⎛
⎜
⎞
⎟
VOUT = 2xVREF ×
65536
⎝
⎠
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5660compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change in
DAC register contents and/or a change in the mode of
where D = the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
SYNC
operation. At this stage, the
line may be kept low or be
brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
SYNC
the
does when VIN = 0.8 V,
falling edge of
can initiate the next write sequence. Since
buffer draws more current when VIN = 2.4 V than it
SYNC
SYNC
should be idled low between write
sequences for even lower power operation of the part. As is
mentioned above, however, it must be brought high again just
before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 24). The first
six bits are “don’t cares.” The next two are control bits that
control which mode of operation the part is in (normal mode
or any one of three power-down modes). There is a more
complete description of the various modes in the Power-Down
Modes section. The next sixteen bits are the data bits. These are
transferred to the DAC register on the24th falling edge of
SCLK.
Figure 23. Resistor String
Rev. PrJ Page 14 of 20
Preliminary Technical Data
AD5660
Figure 24. Input Register Contents
options. The output is connected internally to GND through a
1 kΩ resistor, a 100 kΩ resistor or it is left open-circuited
(Three-State). The output stage is illustrated in Figure 25.
SYNC INTERRUPT
SYNC
In a normal write sequence, the
least 24 falling edges of SCLK and the DAC is updated on the
SYNC
line is kept low for at
24th falling edge. However, if
is brought high before the
24th falling edge this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs—see Figure 27.
POWER-ON RESET
The AD5660 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5660x-1/2
DAC output powers up to zero volts and the AD5660x-3 DAC
output powers up to midscale. The output remains there until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
Figure 25. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for
VDD = 3 V. See Figure 20 for a plot.
POWER-DOWN MODES
The AD5660 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 5 shows how the state of
the bits corresponds to the mode of operation of the device.
MICROPROCESSOR INTERFACING
AD5660 to ADSP-2101/ADSP-2103 Interface
Figure 26 shows a serial interface between the AD5660 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 24-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
Table 5. Modes of Operation for the AD5660
DB17
DB16
Operating Mode
Normal Operation
Power Down Modes
1 kΩ to GND
100 kΩ to GND
Three State
0
0
0
1
1
1
0
1
When both bits are set to 0, the part works normally with its
normal power consumption of 250 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
Figure 26. AD5660 to ADSP-2101/ADSP-2103 Interface
Rev. PrJ | Page 15 of 20
AD5660
Preliminary Technical Data
Figure 27. SYNC Interrupt Facility
AD5660 to 68HC11/68L11 Interface
80C51/80L51 outputs the serial data in a format which has the
LSB first. The AD5660 requires its data with the MSB as the first
bit received. The 80C51/80L51 transmit routine should take this
into account.
Figure 28 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5660, while the MOSI output drives
SYNC
the serial data line of the DAC. The
signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that its CPOL bit is a 0 and its CPHA
SYNC
bit is a 1. When data is being transmitted to the DAC, the
line is taken low (PC7). When the 68HC11/68L11 is configured
as above, data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11/ 68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data to the AD5660, PC7 is left low after the
first eight bits are transferred, and a second serial write
operation is performed to the DAC and PC7 is taken high at the
end of this procedure.
Figure 29. AD5660 to 80C51 Interface
AD5660 to MICROWIRE Interface
Figure 30 shows an interface between the AD5320 and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
Figure 28. AD5660 to 68HC11/68L11 Interface
Figure 30. AD5660 to MICROWIRE Interface
AD5660 to 80C51/80L51 Interface
Figure 29 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5660,
SYNC
while RXD drives the serial data line of the part. The
signal is again derived from a bit programmable pin on the port.
In this case port line P3.3 is used. When data is to be
transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51
transmits data only in 8-bit bytes; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The
Rev. PrJ Page 16 of 20
Preliminary Technical Data
AD5660
This is an output voltage range of 5 V with 0000Hex
corresponding to a −5 V output and FFFF Hex corresponding
to a +5 V output.
APPLICATIONS
USING REF19X AS A POWER SUPPLY FOR AD5660
Because the supply current required by the AD5660 is extremely
low, an alternative option is to use a REF19x voltage reference
(REF195 for 5 V or REF193 for 3 V) to supply the required
voltage to the part—see Figure 31. This is especially useful if the
power supply is quite noisy or if the system supply voltages are
at some value other than 5 V or 3 V, for example, 15 V. The
REF19x will output a steady supply voltage for the AD5660. If
the low dropout REF195 is used, the current it needs to supply
to the AD5660 is 250 µA. This is with no load on the output of
the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is
Figure 32. Bipolar Operation with the AD5660
250µA +
5 V /5 κΩ =1.25 mA
USING AD5660 WITH AN OPTO-ISOLATED
INTERFACE
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.5 ppm (12.5 µV) for the 1.25 mA
current drawn from it. This corresponds to a 0.164 LSB error.
In process-control applications in industrial environments it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5660 uses a three-wire serial logic interface, it
requires only three opto-isolators to provide the required
isolation (see Figure 33). The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5660.
Figure 31. REF195 as Power Supply to AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 has been designed for single-supply operation but
a bipolar output range is also possible using the circuit in Figure
32. The circuit below will give an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
D
65536
R1+ R2
R1
R2
R1
⎡
⎤
⎛
⎜
⎝
⎞ ⎛
⎠ ⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = VDD
×
×
−V
×
⎟ ⎜
DD
⎢
⎥
⎣
⎦
where D represents the input code in decimal (0–65535). With
DD = 5 V, R1 = R2 = 10 kΩ:
V
10× D
65536
⎛
⎜
⎝
⎞
⎟
⎠
V =
− 5 V
O
Figure 33. AD5660 with an Opto-Isolated Interface
Rev. PrJ | Page 17 of 20
AD5660
Preliminary Technical Data
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5660 should
have separate analog and digital sections, each having its own
area of the board. If the AD5660 is in a system where other
devices require an AGND to DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5660.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
The power supply to the AD5660 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
Rev. PrJ Page 18 of 20
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5660
Figure 35. 8-Lead MSOP
(RJ-8)
Figure 34. 8-Lead SOT-23
(RJ-8)
ORDERING GUIDE
Internal
Model
Grade Power-On-Reset to
Reference
Branding
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Package Options1
Description
AD5660ARJ-1
AD5660ARJ-2
AD5660ARJ-3
AD5660BRJ-1
AD5660BRJ-2
AD5660BRJ-3
AD5660CRM-1
AD5660CRM-2
AD5660CRM-3
A
A
A
B
B
B
C
C
C
Zero
Zero
Midscale
Zero
Zero
Midscale
Zero
Zero
1.25 V
2.5 V
2.5 V
1.25 V
2.5 V
2.5 V
1.25 V
2.5 V
2.5 V
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RM-8
RM-8
RM-8
32 LSB INL, 25 ppm/°C Ref, 3 V
32 LSB INL, 25 ppm/°C Ref, 5 V
32 LSB INL, 25 ppm/°C Ref, 5 V
16 LSB INL, 25 ppm/°C Ref, 3 V
16 LSB INL, 25 ppm/°C Ref, 5 V
16 LSB INL, 25 ppm/°C Ref, 5 V
16 LSB INL, 10 ppm/°C Ref, 3 V
16 LSB INL, 10 ppm/°C Ref, 5 V
16 LSB INL, 10 ppm/°C Ref, 5 V
Midscale
TBD
1 RJ = SOT-23
RM = MSOP
Rev. PrJ | Page 19 of 20
AD5660
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04539-0-5/04(PrJ)
Rev. PrJ Page 20 of 20
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