AD5662BRJ-1 [ADI]
2.7 V to 5.5 V, 250 ??A, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23; 2.7 V至5.5 V ， 250 ?? A，轨到轨输出16位DAC D / A采用SOT- 23
| 型号： | AD5662BRJ-1 |
| 厂家： | 
ADI |
| 描述： | 2.7 V to 5.5 V, 250 ??A, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 |
| 文件： | 总20页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, 250 µA, Rail-to-Rail Output
16-Bit nanoDACTM D/A in a SOT-23
Preliminary Technical Data
AD5662
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low power (250 µA @ 5 V) single 16-bit nanoDACTM
True 12-bit accuracy guaranteed
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
Power-on-reset to zero/midscale
2.7 V to 5.5 V power supply
V
V
REF
DD
GND
POWER-ON
RESET
AD5662
V
FB
REF(+)
16-BIT
DAC
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
Guaranteed 16-bit monotonic by design
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC interrupt facility
APPLICATIONS
SYNC SCLK DIN
Process control
Data acquisition systems
Figure 1.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5662 parts are a member of the nanoDACTM family of
devices. They are low power, single, 16-bit buffered voltage-out
DACs. All devices operate from a single 2.7 V to 5.5 V, and are
guaranteed monotonic by design.
The AD5662 is designed with new technology, and is the next
generation to the AD53xx family.
PRODUCT HIGHLIGHTS
1. 16-bit DAC; true 12-bit accuracy guaranteed.
The AD5662 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on-
reset circuit that ensures the DAC output powers up to 0 V
(AD5662x-1) or midscale (AD5662x-2), and remains there until
a valid write takes place. The part contains a power-down
feature that reduces the current consumption of the device to
200 nA at 5 V, and provides software selectable output loads
while in power-down mode.
2. Available in 8-lead SOT-23 and 8-lead MSOP package.
3. Power-on-reset to zero or midscale.
4. Low power. Operates with 2.7 V to 5.5 V supply. Typically
consumes 0.35 mW at 3 V and 0.7 mW at 5 V, making it
ideal for battery-powered applications.
5. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.7 mW at 5 V, reducing to 1 µW in
power-down mode.
6. 10 µs settling time.
RELATED DEVICES
Part No.
Description
The AD5662’s on-chip precision output amplifier allows rail-to-
rail output swing to be achieved. The AD5662 utilizes a versatile
3-wire serial interface that operates at clock rates up to 30 MHz,
and is compatible with standard SPI™, QSPI™, MICROWIRE™,
and DSP interface standards.
AD5620/AD5640/AD5660
3 V/5 V 12-/14-/16-bit DAC with
internal ref in Sot-23
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5662
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
General Description....................................................................... 13
D/A Section................................................................................. 13
Resistor String............................................................................. 13
Output Amplifier........................................................................ 13
Serial Interface ............................................................................ 13
Input Shift Register .................................................................... 13
Interrupt .......................................................................... 13
SYNC
Power-On-Reset ......................................................................... 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing....................................................... 15
Applications..................................................................................... 16
Using REF19x as a Power Supply for AD5662 ....................... 16
Bipolar Operation Using the AD5662..................................... 16
Using AD5662 with an Opto-Isolated Interface .................... 17
Power Supply Bypassing and Grounding................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
10/04—Revision PrA
Rev. PrA | Page 2 of 20
Preliminary Technical Data
SPECIFICATIONS
AD5662
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD: all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade
Min Typ
B Grade
Min Typ
B Version1
Conditions/Comments
Parameter
STATIC PERFORMANCE2
Max
Max
Unit
Resolution
Relative Accuracy
Differential Nonlinearity
16
16
Bits
LSB
LSB
32
1
16
1
See Figure 4.
Guaranteed monotonic by design.
See Figure 5.
Zero Code Error
Full-Scale Error
Offset Error
1
5
1
5
mV
All 0s loaded to DAC register. See Figure 8.
All 1s loaded to DAC register. See Figure 8.
−0.15 −1.25
−0.15 −1.25 % FSR
10 mV
10
Gain Error
Zero Code Error Drift3
Gain Temperature Coefficient3
1.25
1.25 % FSR
µV/°C
2
2.5
2
2.5
ppm
Of FSR/°C
DC Power Supply Rejection
Ratio
-100
-100
dB
DAC code = midscale; VDD = 5V/3V 10%
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Output Voltage Settling Time
8
10
8
10
µs
¼ to ¾ scale;
RL = 2 kΩ; 0 pF < CL < 200 pF. See Figure 18.
µs
V/µs
nF
1 LSB Settling
¼ to ¾ scale
RL = ∞
Slew Rate
Capacitive Load Stability
1.5
2
1.5
2
10
80
10
-80
5
10
80
10
-80
5
nF
RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
THD, Total Harmonic Distortion
Digital-to-Analog Glitch Impulse
nV/√Hz DAC code = midscale,10 kHz
µVp-p
dB
nV-s
DAC code = midscale
VREF = 2 V 300 mV p-p, f = 5 kHz
1 LSB change around major carry.
See Figure 21.
Digital Feedthrough
DC Output Impedance
Short-Circuit Current4
Power-Up Time
0.1
0.5
30
4
0.1
0.5
30
4
nV-s
Ω
mA
µs
VDD = 5 V, 3 V
Coming out of power-down mode. VDD = 5 V
VDD = 3 V
10
10
µs
REFERENCE INPUTS
Reference Current
35
20
45
30
VDD
35
20
45
30
VDD
µA
µA
V
VREF = VDD = 5 V
VREF = VDD = 3.6 V
Reference Input Range
Reference Input Impedance
LOGIC INPUTS3
0
2
0
150
150
kΩ
Input Current
1
0.8
1
0.8
µA
V
V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
VDD = 5 V, 3 V
VDD = 5 V, 3 V
2
3
3
pF
Rev. PrA | Page 3 of 20
AD5662
Preliminary Technical Data
A Grade
Min Typ
B Grade
Min Typ
B Version1
Conditions/Comments
Parameter
Max
Max
Unit
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD= 4.5 V to 5.5 V
VDD= 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
250
240
400
390
250
240
400
390
µA
µA
VIH = VDD and VIL = GND
0.2
0.05
1
1
0.2
0.05
1
1
µA
µA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
89
89
%
ILOAD = 2 mA. VDD = 5 V
1 Temperature ranges are as follows: B version: −40°C to +105°C, typical at +25°C.
2 DC specifications tested with the outputs unloaded unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024.
3 Guaranteed by design and characterization, not production tested.
4 Output unloaded.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5662
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
1
t1
50
13
13
0
33
13
13
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t8
t9
t10
5
4.5
0
5
4.5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to sclk fall ignore
SCLK falling edge to SYNC fall ignore
50
13
0
33
13
0
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.
t10
t1
t9
SCLK
t2
t8
t3
t7
t4
SYNC
DIN
t6
t5
DB23
DB0
Figure 2. Serial Write Operation
Rev. PrA | Page 5 of 20
AD5662
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
Digital Input Voltage to GND
VOUT to GND
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VREF to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ Max)
SOT-23 Package
−40°C to +105°C
−65°C to +150°C
150°C
Power Dissipation
(TJ MAX − TA)/θJA
240°C/W
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 6 of 20
Preliminary Technical Data
AD5662
PIN CONFIGURATION AND FUNCTION DESCRIPTION
V
1
2
3
4
8
7
6
5
GND
DIN
DD
AD5662
V
REF
TOP VIEW
V
SCLK
SYNC
(Not to Scale)
FB
V
OUT
Figure 3. MSOP/SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
4
5
VDD
VREF
VFB
VOUT
SYNC
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V. VDD should be decoupled to GND.
Reference Voltage Input.
Feedback Connection for the Output Amplifier.
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
6
7
8
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
GND
Ground Reference Point for All Circuitry on the Part.
Rev. PrA | Page 7 of 20
AD5662
Preliminary Technical Data
TERMINOLOGY
Relative Accuracy
Gain Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in Figure 4.
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error
Differential Nonlinearity
Total unadjusted error (TUE) is a measure of the output error,
taking all the various errors into account. A typical TUE versus
code plot can be seen in Figure 6.
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL versus code plot can be
seen in Figure 5.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
Zero-Code Error
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5662 because the output of the DAC cannot go below 0 V. It
is due to a combination of the offset errors in the DAC and the
output amplifier. Zero-code error is expressed in mV. A plot of
zero-code error versus temperature can be seen in Figure 8.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 21.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in percent
of full-scale range. A plot of full-scale error versus temperature
can be seen in Figure 8.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Rev. PrA | Page 8 of 20
Preliminary Technical Data
AD5662
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical INL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 5. Typical DNL Plot
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. Typical Total Unadjusted Error Plot
Figure 9. IDD Histogram with VDD = 3 V and VDD = 5 V
Rev. PrA | Page 9 of 20
AD5662
Preliminary Technical Data
Figure 10. Source and Sink Current Capability with VDD = 3 V
Figure 13. Supply Current vs. Temperature
Figure 11. Source and Sink Current Capability with VDD = 5 V
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Supply Current vs. Code
Figure 15. Power-Down Current vs. Supply Voltage
Rev. PrA | Page 10 of 20
Preliminary Technical Data
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
AD5662
Figure 19. Power-On Reset to 0 V
SCLK
2
V
OUT
V
= V
= 5V
DD
REF
T
= 25°C
A
EXITS PD TO MIDSCALE
1
CH1 500mV CH2 5.0V
M1.0µs 500MS/s
2.0ns/pt
Figure 20. Exiting Power-Down to Midscale
2.502500
2.502250
2.502000
2.501750
2.501500
V
= V
= 5V
REF
DD
= 25°C
T
A
13nS/SAMPLE NUMBER
1 LSB CHANGE AROUND
MIDSCALE (0x8000 → 0x7FFF)
GLITCH IMPULSE = 2.723nV.s
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 18. Half-Scale Settling Time
Figure 21. Digital-to-Analog Glitch Impulse (Negative)
Rev. PrA | Page 11 of 20
AD5662
Preliminary Technical Data
2.500400
16
14
12
10
8
V
= V
DD
REF
2.500300
2.500200
2.500100
T
= 25°C
A
V
3V
DD =
2.500000
2.499900
2.499800
2.499700
2.499600
V
5V
DD =
2.499500
2.499400
2.499300
2.499200
V
= V
= 5V
REF
DD
= 25°C
T
A
13nS/SAMPLE NUMBER
6
4
1 LSB CHANGE AROUND
MIDSCALE (7FFFh → 8000h)
GLITCH IMPULSE = 1.271nV.s
2.499100
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 25. Settling Time vs. Capacitive Load
Figure 22. Digital-to-Analog Glitch Impulse (Positive)
2.500250
V
= V
= 5V
REF
DD
= 25°C
V
= V = 5V
REF
2.500200
2.500150
2.500100
DD
= 25°C
T
A
T
A
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV.s
DAC LOADED WITH MIDSCALE
2.500050
2.500000
2.499950
2.499900
2.499850
1
2.499800
2.499750
2.499700
2.499650
2.499600
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 23. Digital Feedthrough
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot
–20
–30
–40
V
= 5V
DD
= 25°C
T
A
DAC LOADED WITH FULLSCALE
V
= 2V ± 0.3Vp-p
REF
–50
–60
–70
–80
–90
–100
2k
4k
6k
8k
10k
Hz
Figure 24. Total Harmonic Distortion
Rev. PrA | Page 12 of 20
Preliminary Technical Data
AD5662
GENERAL DESCRIPTION
D/A SECTION
OUTPUT AMPLIFIER
The AD5662 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 27 shows a block diagram of the DAC
architecture.
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
VDD. It is capable of driving a load of 2 kΩ in parallel with 1000
pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 10 and Figure 11. The slew rate
is 1 V/µs with a half-scale settling time of 8 µs with the output
unloaded.
V
DD
V
FB
REF (+)
RESISTOR
STRING
V
DAC REGISTER
OUT
SERIAL INTERFACE
REF (–ٛ)
The AD5662 has a 3-wire serial interface (
, SCLK, and
SYNC
OUTPUT
AMPLIFIER
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
GND
Figure 27. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
The write sequence begins by bringing the
line low. Data
SYNC
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5662compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (i.e., a change in
DAC register contents and/or a change in the mode of operation).
⎛
⎜
D
⎞
⎟
VOUT = VREF ×
65,536
⎝
⎠
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
At this stage, the
line may be kept low or be brought
SYNC
high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of
RESISTOR STRING
The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
can initiate the next write sequence. Since the
SYNC
buffer draws more current when VIN = 2.4 V than it does when
VIN = 0.8 V, should be idled low between write sequences
SYNC
SYNC
for even lower power operation. As is mentioned previously,
however, it must be brought high again just before the next
write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 29). The first
six bits are don’t cares. The next two are control bits that control
the part’s mode of operation (normal mode or any one of three
power-down modes). See the Power-On Reset section for a
more complete description of the various modes. The next 16
bits are the data bits. These are transferred to the DAC register
on the 24th falling edge of SCLK.
R
R
TO OUTPUT
R
AMPLIFIER
SYNC INTERRUPT
In a normal write sequence, the
line is kept low for at
SYNC
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However if
is brought high before the
SYNC
R
R
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs—see Figure 30.
Figure 28. Resistor String
Rev. PrA | Page 13 of 20
AD5662
Preliminary Technical Data
DB23 (MSB)
DBO (LSB)
X
X
X
X
X
X
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
NORMAL OPERATION
0
0
1
1
0
1
0
1
1 kΩ TO GND
100 kΩ TO GND
POWER-DOWN MODES
THREE-STATE
Figure 29. Input Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
Figure 30.
Interrupt Facility
When both bits are set to 0, the part works normally with its
normal power consumption of 250 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ or 100 kΩ resistor, or is left open-circuited (three-state).
The output stage is illustrated in Figure 31.
POWER-ON RESET
The AD5662 family contains a power-on-reset circuit that
controls the output voltage during power-up. The AD5662x-1
DAC output powers up to 0 V, and the AD5662x-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
POWER-DOWN MODES
The AD5662 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 5 shows how the state
of the bits corresponds to the device’s mode of operation.
V
FB
AMPLIFIER
V
OUT
RESISTOR
STRING DAC
Table 5. Modes of Operation for the AD5662
DB17
DB16
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
0
0
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
0
1
1
1
0
1
Figure 31. Output Stage during Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for
VDD = 3 V. See Figure 20 for a plot.
Rev. PrA | Page 14 of 20
Preliminary Technical Data
AD5662
MICROPROCESSOR INTERFACING
AD5662 to ADSP-2101/ADSP-2103 Interface
AD5662 to 80C51/80L51 Interface
Figure 32 shows a serial interface between the AD5662 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, 24-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled.
Figure 34 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5662,
while RXD drives the serial data line of the part. The
SYNC
signal is again derived from a bit programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data only in 8-bit bytes; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.
ADSP-2101/
AD5662*
ADSP-2103*
TFS
DT
SYNC
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5662*
80C51/80L51*
Figure 32. AD5662 to ADSP-2101/ADSP-2103 Interface
P3.3
TXD
RXD
SYNC
SCLK
DIN
AD5662 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5662 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5662, while the MOSI output drives
the serial data line of the DAC.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 34. AD5662 to 80C51/80L51 Interface
The
signal is derived from a port line (PC7). The setup
SYNC
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured with its CPOL bit as a
0 and its CPHA bit as a 1. When data is being transmitted to the
AD5662 to MICROWIRE Interface
Figure 35 shows an interface between the AD5320 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
DAC, the
line is taken low (PC7). When the 68HC11/
SYNC
68L11 is configured as described above, data appearing on the
MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5662, PC7
is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC; PC7 is taken
high at the end of this procedure.
AD5662*
MICROWIRE*
CS
SK
SO
SYNC
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
68HC11/68L11*
AD5662*
Figure 35. AD5662 to MICROWIRE Interface
PC7
SCK
SYNC
SCLK
DIN
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. AD5662 to 68HC11/68L11 Interface
Rev. PrA | Page 15 of 20
AD5662
Preliminary Technical Data
APPLICATIONS
USING REF19x AS A POWER SUPPLY FOR AD5662
BIPOLAR OPERATION USING THE AD5662
Because the supply current required by the AD5662 is
extremely low, an alternative option is to use a REF19x voltage
reference (REF195 for 5 V, REF193 for 3 V) to supply the
required voltage to the part—see Figure 36. This is especially
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V or 3 V, for example, 15
V. The REF19x outputs a steady supply voltage for the AD5662.
If the low dropout REF195 is used, it must supply 250 µA of
current to the AD5662. This is with no load on the output of the
DAC. When the DAC output is loaded, the REF195 also needs
to supply the current to the load. The total current required
(with a 5 kΩ load on the DAC output) is
The AD5662 has been designed for single-supply operation but
a bipolar output range is also possible using the circuit in
Figure 37. The circuit below gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = V
×
×
−V
×
DD
⎢
DD
⎝
⎠
⎣
where D represents the input code in decimal (0 to 65535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
250 µA + (5 V/5 kΩ) = 1.25 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.5 ppm (12.5 µV) error for the 1.25 mA
current drawn from it. This corresponds to a 0.164 LSB error.
10×D
65,536
⎛
⎜
⎞
⎟
VO
=
−5V
⎝
⎠
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output and 0xFFFF corresponding to a 5 V
output.
+15V
+5V
REF195
250µA
R2 = 10kΩ
+5V
SYNC
THREE-WIRE
SERIAL
INTERFACE
V
= 0V TO 5V
+5V
OUT
R1 = 10kΩ
SCLK
DIN
AD5662
AD820/
±5V
OP295
V
V
OUT
DD
10µF
0.1µF
Figure 36. REF195 as Power Supply to AD5662
AD5662
–5V
THREE-WIRE
SERIAL
INTERFACE
Figure 37. Bipolar Operation with the AD5662
Rev. PrA | Page 16 of 20
Preliminary Technical Data
AD5662
POWER SUPPLY BYPASSING AND GROUNDING
USING AD5662 WITH A GALVANICALLY ISOLATED
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5662 should
have separate analog and digital sections, each having its own
area of the board. If the AD5662 is in a system where other
devices require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5662.
INTERFACE
In process-control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that may occur in the area where the
DAC is functioning. Isocouplers provide isolation in excess of
3 kV. The AD5662 uses a 3-wire serial logic interface so the
ADuM130x 3-channel digital isolator provides the required
isolation (see Figure 38). The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5662.
The power supply to the AD5662 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 µF capacitor ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. It is important that the 0.1 µF capacitor has low
effective series resistance (ESR) and effective series inductance
(ESI), for example, common ceramic types of capacitors. This
0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
+5V
REGULATOR
10µF
0.1µF
POWER
V
DD
10kΩ
10kΩ
V
DD
SCLK
SCLK
SYNC
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5662
V
V
DD
V
OUT
SYNC
DATA
DD
10kΩ
DIN
GND
Figure 38. AD5662 with an Opto-Isolated Interface
Rev. PrA | Page 17 of 20
AD5662
Preliminary Technical Data
OUTLINE DIMENSIONS
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 39. 8-Lead SOT-23
(RJ-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 40. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Grade
Power-On Reset to Code
Branding
D38
Package Options1
Description
32 LSB INL
32 LSB INL
32 LSB INL
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
AD5662ARJ-1
AD5662ARJ-2
AD5662ARM
A
A
A
Zero
RJ-8
RJ-8
RM-8
RJ-8
RJ-8
RM-8
Midscale
Zero
D39
D38
AD5662BRJ-1
AD5662BRJ-2
AD5662BRM
B
B
B
Zero
16 LSB INL
16 LSB INL
16 LSB INL
D36
Midscale
Zero
D37
D36
1RJ = SOT-23, RM = MSOP
Rev. PrA | Page 18 of 20
Preliminary Technical Data
NOTES
AD5662
Rev. PrA | Page 19 of 20
AD5662
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04777–0–10/04(PrA)
Rev. PrA | Page 20 of 20
相关型号：
©2020 ICPDF网 联系我们和版权申明