AD5663 [ADI]
串行16位DAC,电源电压2.7到5.5V;
| 型号： | AD5663 |
| 厂家： | 
ADI |
| 描述： | 串行16位DAC,电源电压2.7到5.5V |
| 文件： | 总24页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output,
Dual 16-Bit nanoDAC®
AD5663
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
DD
REF
Low power, dual 16-bit nanoDAC
Relative accuracy: 12 LSBs maximum
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
LDAC
INPUT
DAC
STRING
DAC A
V
V
A
B
SCLK
SYNC
DIN
BUFFER
BUFFER
OUT
OUT
REGISTER
REGISTER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
Per channel power-down
Power-on reset to zero scale or midscale
AD5663
LDAC
CLR
functions
Hardware
and
POWER-ON
RESET
POWER-DOWN
LOGIC
Serial interface; up to 50 MHz
LDAC CLR
GND
Figure 1.
APPLICATIONS
Process control
Data acquisition systems
Table 1. Related Devices
Part No.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Description
AD5623R/AD5643R/AD5663R
2.7 V to 5.5 V, dual 12-/14-/16-bit
DACs with internal reference
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Dual 16-bit DAC; relative accuracy of 12 ꢀSBs maximum.
The AD5663, a member of the nanoDAC family, is a low power,
dual, 16-bit buffered voltage-out DAC that operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm
ꢀFCSP_WD packages.
The AD5663 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V or
midscale (AD5663-1) and remains there until a valid write takes
place. The part contains a power-down feature that reduces the
current consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
3. ꢀow power; typically consumes 0.6 mW at 3 V and
1.25 mW at 5 V.
4. 7 μs maximum settling time.
The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 1.25 mW at 5 V, going down to
2.4 μW in power-down mode.
The on-chip precision output amplifier of the AD5663 allows
rail-to-rail output swing to be achieved.
The AD5663 uses a versatile, 3-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5663
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 14
Serial Interface............................................................................ 14
Input Shift Register .................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 14
D/A Section................................................................................. 14
Resistor String............................................................................. 14
SYNC
Interrupt .......................................................................... 15
Power-On Reset.......................................................................... 15
Software Reset............................................................................. 15
Power-Down Modes .................................................................. 16
ꢀDAC
Function .......................................................................... 16
Microprocessor Interfacing....................................................... 18
Applications..................................................................................... 19
Choosing a Reference for the AD5663.................................... 19
Using a Reference as a Power Supply for the AD5663 .......... 19
Bipolar Operation Using the AD5663..................................... 20
Using the AD5663 with a Galvanically Isolated Interface .... 20
Power Supply Bypassing and Grounding................................ 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5663
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; Rꢀ = 2 kΩ to GND; Cꢀ = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Min Typ
B Grade1
Max Min Typ
Parameter
STATIC PERFORMANCE2
Max
Unit
Conditions/Comments
AD5663
Resolution
16
16
Bits
LSB
LSB
mV
mV
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
±±
±16
±1
+10
±10
±6
±12
±1
+10
±10
Guaranteed monotonic by design
All 0s loaded to DAC register
+2
±1
+2
±1
Full-Scale Error
Gain Error
Zero-Scale Error Drift3
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk
−0.15 ±1
±1.5
±2
±2.5
−100
10
−0.15 ±1
±1.5
±2
±2.5
−100
10
% of FSR All 1s loaded to DAC register
% of FSR
μV/°C
ppm
dB
Of FSR/°C
DAC code = midscale, VDD ± 10%
μV
Due to full-scale output change
R = 2 kΩ to GND or VDD
L
10
5
10
5
μV/mA
μV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
ꢀs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode;
V
DD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS3
170
26
200
VDD
170
26
200
VDD
μA
V
kΩ
VREF = VDD = 5.5 V, 3.6 V
0.75
0.75
Input Current
±2
0.±
±2
0.±
μA
V
V
pF
pF
All digital inputs
VDD = 5 V, 3 V
VDD = 5 V, 3 V
DIN, SCLK, and SYNC
LDAC and CLR
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
2
2
3
3
19
19
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down
Modes)5
VIH = VDD and VIL = GND
VIH = VDD, VIL = GND
250
200
450
425
250
200
450
425
μA
μA
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
0.4±
0.2
1
1
0.4±
0.2
1
1
μA
μA
1 Temperature range: A grade and B grade are both equal to −40°C to +105°C.
2 Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 Both DACs powered down.
Rev. 0 | Page 3 of 24
AD5663
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; Rꢀ = 2 kΩ to GND; Cꢀ = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2
Min
Typ
4
1.±
10
0.1
−90
0.1
1
Max
Unit
μs
V/μs
nV-s
nV-s
dBs
nV-s
nV-s
nV-s
kHz
Conditions/Comments
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
7
1/4 to 3/4 scale settling to ±2 LSB
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
1
340
−±0
120
100
15
VREF = 2 V ± 0.1 V p-p
dB
VREF = 2 V ± 0.1 V p-p; frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
Rev. 0 | Page 4 of 24
AD5663
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIꢀ + VIH)/2.
V
DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 4.
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
Parameter
Unit
Conditions/Comments
2
t1
20
ns min
SCLK cycle time
t2
t3
t4
t5
t6
t7
t±
t9
t10
9
9
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
13
5
5
0
15
13
0
LDAC pulse width low
t11
t12
t13
t14
t15
10
15
5
ns min
ns min
ns min
ns min
ns max
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
0
300
1 Guaranteed by design and characterization; not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
t1
t9
SCLK
t2
t8
t3
t4
t7
SYNC
t6
t5
DIN
1
DB23
DB0
t14
t11
LDAC
t12
2
LDAC
t13
CLR
t15
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24
AD5663
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
LFCSP_WD Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
61°C/W
142°C/W
43.7°C/W
260(+0/−5)°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24
AD5663
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
10
9
V
V
A
B
V
V
OUT
REF
DD
OUT
AD5663
TOP VIEW
(Not to Scale)
8
GND
DIN
7
LDAC
CLR
SCLK
SYNC
6
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VOUT
VOUT
GND
LDAC
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part
exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write
sequence, the write is aborted.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the device.
7
SCLK
DIN
VDD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
±
9
10
VREF
Reference Voltage Input.
Rev. 0 | Page 7 of 24
AD5663
TYPICAL PERFORMANCE CHARACTERISTICS
10
8
10
MAX INL
V
= V = 5V
REF
DD
= 25°C
8
T
A
6
V
= 5V
DD
= 25°C
6
4
2
4
T
A
2
MAX DNL
MIN DNL
0
0
–2
–4
–2
–4
–6
MIN INL
4.25
–6
–8
–8
–10
0.75
1.25
1.75
2.25
2.75
3.25
(V)
3.75
4.75
–10
V
REF
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 4. INL
Figure 7. INL and DNL Error vs. VREF
8
6
1.0
0.8
0.6
0.4
0.2
MAX INL
V
T
= V
REF
= 5V
DD
= 25°C
A
T
A
= 25°C
4
2
MAX DNL
MIN DNL
0
0
–2
–4
–6
–8
–0.2
–0.4
–0.6
MIN INL
–0.8
–1.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
DD
0
10k
20k
30k
CODE
40k
50k
60k
Figure 5. DNL
Figure 8. INL and DNL Error vs. Supply
8
6
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
DD
MAX INL
V
= V = 5V
REF
DD
4
2
GAIN ERROR
MAX DNL
MIN DNL
0
–0.10
–0.12
–2
–4
–6
–8
–0.14
–0.16
FULL-SCALE ERROR
MIN INL
100
–0.18
–0.20
–40
–20
0
20
40
60
80
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Gain Error and Full-Scale Error vs. Temperature
Figure 6. INL Error and DNL Error vs. Temperature
Rev. 0 | Page ± of 24
AD5663
1.5
1.0
V
= 5.5V
DD
= 25°C
T
A
8
6
4
2
0
ZERO-SCALE ERROR
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
0.230
0.235
0.240
0.245
0.250
0.255
–40
–20
0
20
40
60
80
100
I
(mA)
DD
TEMPERATURE (°C)
Figure 10. Zero-Scale and Offset Error vs. Temperature
Figure 13. IDD Histogram with VDD = 5.5 V
0.20
1.0
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
V
T
= V
REF
= 5V, 3V
DD
= 25°C
0.15
0.10
0.05
A
0.5
0
GAIN ERROR
0
–0.05
–0.10
–0.15
FULL-SCALE ERROR
–0.5
–1.0
DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT
–1.5
–2.0
–0.20
–0.25
–5
–4
–3
–2
–1
0
1
2
3
4
5
2.7
3.2
3.7
4.2
(V)
4.7
5.2
I (mA)
V
DD
Figure 14. Headroom at Rails vs. Source and Sink Current
Figure 11. Gain Error and Full-Scale Error vs. Supply
0.30
1.0
T
= 25°C
T
= 25°C
A
A
V
= V
= 5V
= 3V
DD
DD
REFIN
REFIN
0.25
0.20
0.15
0.10
0.5
0
ZERO-SCALE ERROR
V
= V
–0.5
–1.0
–1.5
0.05
0
–2.0
–2.5
OFFSET ERROR
–40
–20
0
20
40
60
80
100
2.7
3.2
3.7
4.2
(V)
4.7
5.2
TEMPERATURE (°C)
V
DD
Figure 12. Zero-Scale and Offset Error vs. Supply
Figure 15. Supply Current vs. Temperature
Rev. 0 | Page 9 of 24
AD5663
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
V
= V = 5V
REF
DD
= 25°C
T
A
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
V
= V = 5V
REF
DD
= 25°C
T
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
= 909mV/DIV
OUT
1
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
TIME BASE = 4µs/DIV
Figure 19. Digital-to-Analog Glitch Impulse (Negative)
Figure 16. Full-Scale Settling Time, 5 V
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
T
= V = 5V
REF
DD
= 25°C
V
T
= V = 5V
REF
A
DD
= 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
A
V
DD
1
2
MAX(C2)*
420.0mV
V
OUT
CH2 500mV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
CH1 2.0V
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
Figure 17. Power-On Reset to 0 V
Figure 20. Analog Crosstalk
–20
–30
–40
V
= 5V
DD
= 25°C
SYNC
SLCK
T
A
DAC LOADED WITH FULL SCALE
= 2V ± 0.3V p-p
V
REF
1
3
–50
–60
–70
–80
V
OUT
V
= 5V
DD
–90
2
–100
2k
4k
6k
8k
10k
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
FREQUENCY (Hz)
Figure 18. Exiting Power-Down to Midscale
Figure 21. Total Harmonic Distortion
Rev. 0 | Page 10 of 24
AD5663
16
14
12
10
8
5
0
V
= 5V
DD
= 25°C
V
T
= V
DD
REF
= 25°C
T
A
A
–5
V
= 3V
DD
–10
–15
–20
–25
–30
–35
–40
V
DD
= 5V
6
4
0
1
2
3
4
5
6
7
8
9
10
10k
100k
FREQUENCY (Hz)
1M
10M
CAPACITANCE (nF)
Figure 22. Settling Time vs. Capacitive Load
Figure 25. Multiplying Bandwidth
V
= V = 5V
REF
DD
= 25°C
T
CLR
A
3
DAC LOADED WITH MIDSCALE
V
A
OUT
1
V
B
OUT
4
2
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
CH2 1.0V
CH4 1.0V
M200ns A CH3
1.10V
CH3 5.0V
Figure 23. 0.1 Hz to 10 Hz Output Noise Plot
CLR
Pulse Activation Time
Figure 26.
800
700
600
500
400
300
V
= V = 5V
REF
DD
= 25°C
T
A
200
100
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 24. Noise Spectral Density
Rev. 0 | Page 11 of 24
AD5663
TERMINOLOGY
Output Voltage Settling Time
Relative Accuracy or Integral Nonlinearity (INL)
Output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a 1/4 to 3/4 full-
scale input change and is measured from the 24th falling edge of
SCꢀK.
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in ꢀSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INꢀ vs. code plot is shown in Figure 4.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 ꢀSB at the major carry transition (0x7FFF to 0x8000). See
Figure 19.
Differential nonlinearity is the difference between the measured
change and the ideal 1 ꢀSB change between any two adjacent
codes. A specified differential nonlinearity of 1 ꢀSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNꢀ vs. code plot is shown in Figure 5.
Zero-Scale Error
Digital Feedthrough
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-scale error is always positive in
the AD5663 because the output of the DAC cannot go below
0 V. It is due to a combination of the offset errors in the DAC
and the output amplifier. Zero-scale error is expressed in mV.
A plot of zero-scale error vs. temperature is shown in Figure 10.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
It is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measurement of the harmonics present on the DAC output.
It is measured in dB.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 ꢀSB. Full-scale error is expressed in
percent of full-scale range. A plot of full-scale error vs. tempera-
ture is shown in Figure 9.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading the
DAC to midscale and measuring noise at the output. It is
measured in nV/√Hz. Figure 24 shows a plot of noise spectral
density.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Zero-Scale Error Drift
Zero-scale error drift is a measurement of the change in zero-
scale error with a change in temperature. It is expressed in μV/°C.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in ꢁV.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in (ppm
of full-scale range)/°C.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in ꢁV/mA.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the trans-
fer function. Offset error is measured on the AD5663 with
Code 512 loaded in the DAC register. It can be negative or
positive.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed
in nV-s.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by 10%.
Rev. 0 | Page 12 of 24
AD5663
Analog Crosstalk
Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) while keeping
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
ꢀDAC
ꢀDAC
high. Then pulse
low and monitor the output of
the DAC whose digital code was not changed. The area of the
glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
ꢀDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Rev. 0 | Page 13 of 24
AD5663
THEORY OF OPERATION
D/A SECTION
OUTPUT AMPLIFIER
The AD5663 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 27 shows a block diagram of the DAC
architecture.
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kꢂ in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be
seen in Figure 14. The slew rate is 1.8 V/μs with a 1/4 to 3/4
full-scale settling time of 10 μs.
V
DD
OUTPUT
AMPLIFIER
(GAIN = +2)
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
SERIAL INTERFACE
REF (–)
SYNC
The AD5663 has a 3-wire serial interface (
, SCꢀK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as with most DSPs. See Figure 2 for
a timing diagram of a typical write sequence.
GND
Figure 27. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCꢀK. The serial clock frequency can be as high
as 50 MHz, making the AD5663 compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed; that is, there is a
change in DAC register contents and/or a change in the mode
D
65,536
⎛
⎜
⎞
⎟
VOUT =VREF
×
⎝
⎠
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 65,535.
SYNC
of operation. At this stage, the
line can be kept low or be
RESISTOR STRING
brought high. In either case, it must be brought high for a mini-
mum of 15 ns before the next write sequence so that a falling edge
The resistor string section is shown in Figure 28. It is a string of
resistors, each of Value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
SYNC
SYNC
of
buffer draws more current when VIN = 2.0 V than it does when
SYNC
can initiate the next write sequence. Because the
VIN = 0.10 V,
should be idled low between write sequences
for even lower power operation. As mentioned previously,
however, it must be brought high again just before the next
write sequence.
R
INPUT SHIFT REGISTER
R
The input shift register is 24 bits wide (see Figure 29). The first
two bits are don’t cares. The next three are the Command Bit C2
to Command Bit C0 (see Table 7), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 8), and, finally, the
16-bit data-word. These are transferred to the DAC register on
the 24th falling edge of SCꢀK.
TO OUTPUT
R
AMPLIFIER
Table 7. Command Definition
R
R
C2
C1
C0
Command
0
0
0
0
0
1
Write to input register n
Update DAC register n
0
1
0
Write to input register n, update all
(software LDAC)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Write to and update DAC channel n
Power down DAC (power up)
Reset
LDAC register setup
Reserved
Figure 28. Resistor String
Rev. 0 | Page 14 of 24
AD5663
Table 8. Address Command
SOFTWARE RESET
A2
A1
A0
ADDRESS (n)
DAC A
DAC B
The AD5663 contains a software reset function. Command 101
is reserved for the software reset function (see Table 7). The
software reset command contains two reset modes that are
software-programmable by setting Bit DB0 in the control
register.
0
0
0
0
0
1
0
1
0
Reserved
Reserved
All DACs
0
1
1
1
1
1
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device. Table 10 shows the contents of the
input shift register during the software reset mode of operation.
SYNC INTERRUPT
SYNC
In a normal write sequence, the
least 24 falling edges of SCꢀK, and the DAC is updated on the
SYNC
line is kept low for at
Table 9. Software Reset Modes for the AD5663
24th falling edge. However, if
is brought high before the
DB0
Registers Reset to 0
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 30).
0
DAC register
Input register
DAC register
Input register
1 (Power-On Reset)
LDAC register
POWER-ON RESET
Power-down register
The AD5663 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5663 DAC
outputs power up to 0 V, the AD5663-1 powers up to midscale,
and the output remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
ꢀDAC CꢀR
in the process of powering up. Any events on
during power-on reset are ignored.
or
Table 10. 24-Bit Input Shift Register Contents for Software Reset Command
MSB
LSB
DB23 to DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
DB0
x
1
0
1
x
x
x
x
1/0
Don’t care
Command bits (C2 to C0)
Address bits (A2 to A0)
Don’t care
Determines software reset mode
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 29. Input Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24 FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
TH
TH
ON THE 24 FALLING EDGE
SYNC
Figure 30.
Interrupt Facility
Rev. 0 | Page 15 of 24
AD5663
The time required to exit power-down is typically 4 μs for
DD = 5 V and for VDD = 3 V (see Figure 18).
Table 11. Power-Down Modes of Operation for the AD5663
POWER-DOWN MODES
V
The AD5663 contains four separate modes of operation.
Command 100 is reserved for the power-down function
(see Table 7). These modes are software-programmable by
setting Bit DB5 and Bit DB4 in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC B and DAC A)
can be powered down to the selected mode by setting the
corresponding two bits (Bit DB1 and Bit DB0) to 1. By
executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal
operation mode. Again, to select which combination of DAC
channels to power up, set the corresponding two bits (Bit DB1
and Bit DB0) to 1. See Table 12 for contents of the input shift
register during power-down/power-up operation.
DB5
DB4
Operating Mode
Normal operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
LDAC FUNCTION
The AD5663 DAC has double-buffered interfaces consisting of
two banks of registers: input registers and DAC registers. The
input registers are connected directly to the input shift register
and the digital code is transferred to the relevant input register
on completion of a valid write sequence. The DAC registers
contain the digital code used by the resistor strings.
The DAC output powers up to the value in the input register
ꢀDAC
ꢀDAC
while
is low. If
is high, the DAC output powers up
to the value held in the DAC register before power-down.
ꢀDAC
Access to the DAC registers is controlled by the
pin.
pin is high, the DAC registers are latched and
the input registers can change state without affecting the
ꢀDAC
When both bits are set to 0, the part works normally with its
normal power consumption of 500 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ register
or left open-circuited (three-state) (see Figure 31).
ꢀDAC
When the
contents of the DAC registers. When
is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
ꢀDAC
low when writing to the other DAC input register, all
outputs update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
ꢀDAC
updated since the last time
was brought low. Normally,
ꢀDAC
when
is brought low, the DAC registers are filled with
the contents of the input registers. In the case of the AD5663,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 31. Output Stage During Power-Down
The outputs of all DACs can be updated simultaneously using
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down.
ꢀDAC
the hardware
pin.
Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function
MSB
LSB
DB23 to
DB22
DB15 to
DB6
DB21
DB20
DB19
DB18 DB17 DB16
DB5
DB4 DB3
PD0
DB2 DB1
DAC B
DB0
x
1
0
0
x
x
x
x
PD1
x
x
DAC A
Don’t
care
Command bits (C2 to C0)
Address bits (A2 to A0);
don’t care
Don’t
care
Power-down
mode
Don’t care
Power down/Power up
channel selection;
set bit to 1 to select
channel
Rev. 0 | Page 16 of 24
AD5663
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating
LDAC
Synchronous
: The DAC registers are updated after new
data is read in on the falling edge of the 24th SCꢀK pulse.
ꢀDAC
can be permanently low or pulsed, as shown in Figure 2.
ꢀDAC
Writing to the DAC using Command 110 loads the 2-bit
register [DB1:DB0]. The default for each channel is 0; that is,
ꢀDAC
LDAC
Asynchronous
: The outputs are not updated at the same
ꢀDAC
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
goes
the
DAC register is updated regardless of the state of the
See Table 14 for contents of the input shift register during the
pin works normally. Setting the bits to 1 means the
ꢀDAC
pin.
ꢀDAC
register setup command.
ꢀDAC
The
over the hardware
select which combination of channels to simultaneously update
register gives the user full flexibility and control
ꢀDAC
pin. This register allows the user to
LDAC
Table 13.
LDAC Bits
(DB1 to DB0)
Register Mode of Operation
ꢀDAC
ꢀDAC
when the hardware
register to 0 for a DAC channel means that the update of this
channel is controlled by the
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
pin is executed. Setting the
bit
LDAC Pin
LDAC Operation
0
1/0
Determined by LDAC pin
ꢀDAC
pin. If this bit is set to 1, this
1
x = don’t care
The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse
ꢀDAC
ꢀDAC
pin. It effectively sees the
pin as being pulled low.
ꢀDAC
See Table 13 for the
register mode of operation.
LDAC
Table 14. 24-Bit Input Shift Register Contents for
Register Setup Command
MSB
LSB
DB23 to DB22
DB21
DB20 DB19
DB18
DB17
DB16
DB15 to DB2
DB1
DB0
x
1
1
0
x
x
x
x
DAC B
DAC A
Set DAC to 0 or 1 for required mode of
operation
Don’t care
Command bits (C2 to C0)
Address bits (A3 to A0);
Don’t care
Don’t care
Rev. 0 | Page 17 of 24
AD5663
AD56631
SYNC
1
68HC11/68L11
MICROPROCESSOR INTERFACING
AD5663 to Blackfin® ADSP BF53x Interface
PC7
SCK
SCLK
Figure 32 shows a serial interface between the AD5663 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor
family incorporates two dual-channel synchronous serial ports,
SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5663, the
setup for the interface is as follows:
MOSI
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5663 to 68HC11/68L11 Interface
AD5663 to 80C51/80L51 Interface
•
•
•
DT0PRI drives the DIN pin of the AD5663.
TSCꢀK0 drives the SCꢀK of the part.
Figure 34 shows a serial interface between the AD5663 and the
80C51/80ꢀ51 microcontroller. The setup for the interface is as
follows:
SYNC
The
pin is driven from TFS0.
•
TxD of the 80C51/80ꢀ51 drives SCꢀK of the AD5663.
RxD drives the serial data line of the part.
1
ADSP-BF53x
AD56631
•
TFS0
SYNC
SYNC
The
signal is again derived from a bit-programmable pin
DTOPRI
TSCLK0
DIN
on the port. In this case, Port ꢀine P3.3 is used. When data is to be
transmitted to the AD5663, P3.3 is taken low. The 80C51/80ꢀ51
transmits data in 10-bit bytes only; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80ꢀ51 outputs the serial data in a format that has the ꢀSB first.
The AD5663 must receive data with the MSB first. The 80C51/
80ꢀ51 transmit routine should take this into account.
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. AD5663 to Blackfin ADSP-BF53x Interface
AD5663 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5663 and the
68HC11/68ꢀ11 microcontroller. SCK of the 68HC11/68ꢀ11
drives the SCꢀK of the AD5663, and the MOSI output drives
the serial data line of the DAC.
1
80C51/80L51
AD56631
SYNC
SYNC
The
signal is derived from a port line (PC7). The setup
P3.3
TxD
RxD
conditions for correct operation of this interface are as follows:
SCLK
•
The 68HC11/68ꢀ11 is configured with its CPOꢀ bit as 0.
The 68HC11/68ꢀ11 is configured with its CPHA bit as 1.
DIN
•
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
When data is being transmitted to the DAC, the
line is
Figure 34. AD5663 to 80C51/80L51 Interface
taken low (PC7). When the 68HC11/68ꢀ11 is configured as
previously described, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the
68HC11/68ꢀ11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5663, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5663 to MICROWIRE Interface
Figure 35 shows an interface between the AD5663 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5663
on the rising edge of the SK.
MICROWIRE
AD56631
SYNC
1
CS
SK
SO
SCLK
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5663 to MICROWIRE Interface
Rev. 0 | Page 1± of 24
AD5663
APPLICATIONS
CHOOSING A REFERENCE FOR THE AD5663
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5663
To achieve the optimum performance from the AD5663,
thought should be given to the choice of a precision voltage
Because the supply current required by the AD5663 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the part (see Figure 36). This is especially
useful if the power supply is quite noisy, or if the system supply
voltages are at some value other than 5 V or 3 V (for example,
15 V). The voltage reference outputs a steady supply voltage for
the AD5663; see Table 15 for a suitable reference. If the low drop-
out REF195 is used, it must supply 250 μA of current to the
AD5663, with no load on the output of the DAC. When the
DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ
load on the DAC output) is
reference. The AD5663 has only one reference input, VREF
.
The voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.
When choosing a voltage reference for high accuracy applica-
tions, the sources of error are initial accuracy, ppm drift, long-
term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the
DAC. To minimize these errors, a reference with high initial
accuracy is preferred. Also, choosing a reference with an output
trim adjustment, such as the ADR423, allows a system designer
to trim system errors out by setting a reference voltage to a
voltage other than the nominal. The trim adjustment can also
be used at temperature to trim out any error.
250 μA + (5 V/5 kΩ) = 1.25 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.5 ppm (12.5 μV) error for the 1.25 mA
current drawn from it. This corresponds to a 0.164 ꢀSB error.
ꢀong-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift specifi-
cation ensures that the overall solution remains relatively stable
during its entire lifetime.
15V
5V
REF195
500µA
The temperature coefficient of a reference’s output voltage
affects INꢀ, DNꢀ, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.
SYNC
SCLK
DIN
V
V
REF
DD
V
= 0V TO 5V
THREE-WIRE
SERIAL
INTERFACE
OUT
AD5663
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
It is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR425, produce low
output noise in the 0.1 Hz to 10 Hz range. Examples of recom-
mended precision references for use as supplies to the AD5663
are shown in the Table 15.
Figure 36. REF195 as Power Supply to the AD5663
Table 15. Partial List of Precision References for Use with the AD5663
Part No.
ADR425
ADR395
REF195
AD7±0
Initial Accuracy (mV Max)
Temperature Drift (ppmoC Max)
0.1 Hz to 10 Hz Noise (μV p-p Typ)
VOUT (V)
±2
±6
±2
±2
±2
3
25
5
3
3
3.4
5
50
4
5
5
5
2.5/3
3
ADR423
3.4
Rev. 0 | Page 19 of 24
AD5663
5V
BIPOLAR OPERATION USING THE AD5663
REGULATOR
10µF
0.1µF
POWER
The AD5663 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 37. The circuit gives an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V
V
V
V
OA
SCLK
IA
ADuM1300
AD5663
The output voltage for any input code can be calculated as
V
SDI
OUT
V
SYNC
DIN
IB
OB
OC
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = V
×
×
−V
×
⎢
DD
DD
V
DATA
IC
⎝
⎠
⎣
GND
where D represents the input code in decimal (0 to 65,535).
With VDD = 5 V, R1 = R2 = 10 kΩ
Figure 38. AD5663 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
10×D
65,536
⎛
⎜
⎞
⎟
V =
−5 V
O
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5663 should
have separate analog and digital sections, each having its own
area of the board. If the AD5663 is in a system where other
devices require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5663.
⎝
⎠
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
The power supply to the AD5663 should be bypassed with 10 μF
and 0.1 μF capacitors. The capacitors should be located as close
as possible to the device, with the 0.1 μF capacitor ideally right
up against the device. The 10 μF capacitors are of the tantalum
bead type. It is important that the 0.1 μF capacitor have low
effective series resistance (ESR) and effective series inductance
(ESI) as in, for example, common ceramic types of capacitors.
This 0.1 μF capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.
±5V
V
V
OUT
DD
10µF
0.1µF
AD5663
–5V
THREE-WIRE
SERIAL
INTERFACE
Figure 37. Bipolar Operation with the AD5663
USING THE AD5663 WITH
A GALVANICALLY ISOLATED INTERFACE
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. The AD5663 use a 3-wire serial logic interface, so the
ADuM1300 three-channel digital isolator provides the required
isolation (see Figure 38). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5663.
Rev. 0 | Page 20 of 24
AD5663
OUTLINE DIMENSIONS
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 39. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 40. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Power-On
Reset Code
Package
Package
Option
Model
Accuracy
Description
10-lead MSOP
10-lead MSOP
Branding
D±0
D±0
AD5663ARMZ1
AD5663ARMZ-REEL71
−40°C to +105°C
−40°C to +105°C
Zero
Zero
±16 LSB INL
±16 LSB INL
RM-10
RM-10
AD5663BRMZ1
AD5663BRMZ-REEL71
AD5663BRMZ-11
AD5663BRMZ-1REEL71
AD5663BCPZ-250RL71
AD5663BCPZ-REEL71
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Zero
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
10-lead MSOP
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
D±C
D±C
D7J
D7J
D±C
D±C
Zero
10-lead MSOP
Midscale
Midscale
Zero
10-lead MSOP
10-lead MSOP
10-lead LFCSP_WD
10-lead LFCSP_WD
Zero
1 Z = Pb-free part.
Rev. 0 | Page 21 of 24
AD5663
NOTES
Rev. 0 | Page 22 of 24
AD5663
NOTES
Rev. 0 | Page 23 of 24
AD5663
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05855-0-4/06(0)
Rev. 0 | Page 24 of 24
相关型号：
AD5663RBCPZ-3R2
SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, PDSO10, 3 X 3 MM, ROHS COMPLIANT, LFCSP-10
ROCHESTER
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