AD5664 [ADI]
2.7 V to 5.5 V, 450 レA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs; 2.7 V至5.5 V ， 450レA，轨到轨输出，四通道， 12位/ 16位nanoDACs
| 型号： | AD5664 |
| 厂家： | 
ADI |
| 描述： | 2.7 V to 5.5 V, 450 レA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs |
| 文件： | 总24页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output,
Quad, 12-/16-Bit nanoDACs®
AD5624/AD5664
FEATURES
Low power, quad nanoDACs
AD5664: 16 bits
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
GND
REF
AD5624/AD5664
BUFFER
AD5624: 12 bits
INPUT
DAC
STRING
DAC A
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
REGISTER
REGISTER
Relative accuracy: 12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Power-on reset to zero
SCLK
SYNC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
BUFFER
BUFFER
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
Per channel power-down
Serial interface, up to 50 MHz
POWER-ON
RESET
POWER-DOWN
LOGIC
APPLICATIONS
Figure 1.
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
AD5624R/AD5644R/AD5664R 2.7 V to 5.5 V quad, 12-, 14-,
Description
16-bit DACs with internal
reference
GENERAL DESCRIPTION
The AD5624/AD5664, members of the nanoDAC family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
PRODUCT HIGHLIGHTS
The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to 0 V
and remains there until a valid write takes place. The parts
contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
1. Relative accuracy: 12 ꢀSBs maximum.
2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,
ꢀFCSP_WD.
3. ꢀow power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
4. Maximum settling time of 4.5 ꢁs (AD5624) and 7 ꢁs
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is 2.25 mW at 5 V, going
down to 2.4 μW in power-down mode.
(AD5664).
The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5624/AD5664
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface............................................................................ 15
Input Shift Register .................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
D/A Section................................................................................. 15
Resistor String............................................................................. 15
Output Amplifier........................................................................ 15
SYNC
Interrupt .......................................................................... 16
Power-On Reset.......................................................................... 16
Software Reset............................................................................. 17
Power-Down Modes .................................................................. 17
ꢀDAC Function .......................................................................... 18
Microprocessor Interfacing....................................................... 19
Applications..................................................................................... 20
Choosing a Reference for the AD5624/AD5664.................... 20
Using a Reference as a Power Supply for the
AD5624/AD5664........................................................................ 20
Bipolar Operation Using the AD5624/AD5664..................... 21
Using AD5624/AD5664 with a Galvanically Isolated
Interface....................................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5624/AD5664
SPECIFICATIONS
VDD = +2.7 V to +5.5 V; Rꢀ = 2 kΩ to GND; Cꢀ = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ
B Grade1
Typ
Parameter
STATIC PERFORMANCE2
Min
Max
Min
Max
Unit
Conditions/Comments
AD5664
Resolution
Relative Accuracy
Differential Nonlinearity
16
16
Bits
LSB
LSB
±±
±16
±1
±6
±12
±1
Guaranteed monotonic by
design
AD5624
Resolution
Relative Accuracy
Differential Nonlinearity
12
Bits
LSB
LSB
±0.5
2
±1
±0.25
Guaranteed monotonic by
design
All zeroes loaded to DAC
register
Zero-Code Error
2
10
10
mV
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature
Coefficient
±1
−0.1
±10
±1
±1.5
±1
−0.1
±10
±1
±1.5
mV
% of FSR
% of FSR
μV/°C
ppm
All ones loaded to DAC register
±2
±2.5
±2
±2.5
of FSR/°C
DC Power Supply Rejection
Ratio
DC Crosstalk
−100
10
−100
10
dB
μV
DAC code = midscale ; VDD
10%
Due to full-scale output
change
±
RL = 2 kΩ to GND or VDD
10
5
10
5
μV/mA
μV
Due to load current change
Due to powering down (per
channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
10
0.5
30
4
10
0.5
30
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down
mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS3
170
26
200
VDD
170
26
200
VDD
μA
V
kΩ
VREF = VDD = 5.5 V
0.75
0.75
Input Current
±2
0.±
±2
0.±
μA
V
V
All digital inputs
VDD = 5 V, 3 V
VDD = 5 V, 3 V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
2
2
3
3
pF
Rev. 0 | Page 3 of 24
AD5624/AD5664
A Grade1
Typ
B Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Conditions/Comments
VIH = VDD, VIL = GND
VIH = VDD, VIL = GND
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down
Modes)5
0.45
0.44
0.9
0.±5
0.45
0.44
0.9
0.±5
mA
mA
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
0.4±
0.2
1
1
0.4±
0.2
1
1
μA
μA
1 Temperature range: A grade and B grade: −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; Rꢀ = 2 kΩ to GND; Cꢀ = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2, 3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5664
AD5624
4
3
7
4.5
μs
μs
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±0.5 LSB
Slew Rate
1.±
10
0.1
−90
0.1
1
V/μs
nV-s
nV-s
dBs
nV-s
nV-s
nV-s
kHz
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
1
340
−±0
120
100
15
VREF = 2 V ± 0.1 V p-p
dB
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization, not production tested.
2 Temperature range: −40°C to +105°C; typical at 25°C.
3 See the Terminology section.
Rev. 0 | Page 4 of 24
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIꢀ + VIH)/2 (see Figure 2).
DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
Parameter1
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
2
t1
20
9
9
13
5
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t±
t9
t10
Data hold time
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
15
13
0
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
t1
t9
SCLK
t2
t8
t3
t7
t4
SYNC
DIN
t6
t5
DB23
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24
AD5624/AD5664
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Digital Input Voltage to GND
Operating Temperature Range
Industrial (A Grade, B Grade)
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
LFCSP_WD Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
61°C/W
142°C/W
43.7°C/W
260°C ± 5°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24
AD5624/AD5664
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
V
A
V
OUT
REF
AD5624/
AD5664
9
V
B
V
OUT
DD
8
GND
DIN
TOP VIEW
7
V
V
C
SCLK
SYNC
(Not to Scale)
OUT
6
D
OUT
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
VOUT
VOUT
GND
VOUT
VOUT
SYNC
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the device.
C
D
7
SCLK
DIN
VDD
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
±
9
10
VREF
Reference Voltage Input.
Rev. 0 | Page 7 of 24
AD5624/AD5664
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.15
0.10
0.05
0
10
V
= V
REF
= 25°C
= 5V
DD
V
= V = 5V
DD
= 25°C
REF
T
A
8
T
A
6
4
2
0
–2
–4
–0.05
–0.10
–0.15
–0.20
–6
–8
–10
0
0
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 7. DNL AD5624
Figure 4. INL AD5664
8
6
1.0
0.8
V
= V = 5V
REF
DD
= 25°C
T
A
MAX INL
V
= V = 5V
REF
DD
0.6
4
2
0.4
0.2
MAX DNL
MIN DNL
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
MIN INL
80
–40
–20
0
20
40
60
100
500
1000
1500 2000
CODE
2500 3000 3500 4000
TEMPERATURE (°C)
Figure 5. INL AD5624
Figure 8. INL Error and DNL Error vs. Temperature
1.0
10
8
V
= V = 5V
REF
DD
T = 25°C
A
0.8
0.6
0.4
0.2
MAX INL
6
V
T
= 5V
DD
= 25°C
4
A
2
MAX DNL
MIN DNL
0
0
–0.2
–2
–4
–6
–0.4
–0.6
MIN INL
4.25
–0.8
–1.0
–8
–10
0.75 1.25
10k
20k
30k
CODE
40k
50k
60k
1.75
2.25
2.75
3.25
(V)
3.75
4.75
V
REF
Figure 9. INL and DNL Error vs. VREF
Figure 6. DNL AD5664
Rev. 0 | Page ± of 24
AD5624/AD5664
8
6
1.0
MAX INL
0.5
0
T
= 25°C
A
4
2
GAIN ERROR
MAX DNL
MIN DNL
FULL-SCALE ERROR
0
–0.5
–1.0
–2
–4
–6
–8
MIN INL
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
Figure 13. Gain Error and Full-Scale Error vs. Supply
Figure 10. INL and DNL Error vs. Supply
1.0
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
T
= 25°C
DD
A
0.5
0
ZERO-SCALE ERROR
GAIN ERROR
–0.5
–1.0
–1.5
–0.10
–0.12
–0.14
–0.16
FULL-SCALE ERROR
–2.0
–2.5
OFFSET ERROR
–0.18
–0.20
2.7
3.2
3.7
4.2
(V)
4.7
5.2
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD
Figure 11. Gain Error and Full-Scale Error vs. Temperature
Figure 14. Zero-Scale Error and Offset Error vs. Supply
1.5
V
= 5.5V
DD
= 25°C
6
5
4
T
A
1.0
ZERO-SCALE ERROR
0.5
0
–0.5
3
2
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
1
0
0.41
0.42
0.43
(mA)
0.44
0.45
–40
–20
0
20
40
60
80
100
I
TEMPERATURE (°C)
DD
Figure 15. IDD Histogram with VDD = 5.5 V
Figure 12. Zero-Scale Error and Offset Error vs. Temperature
Rev. 0 | Page 9 of 24
AD5624/AD5664
8
V
= 3.6V
DD
= 25°C
T
A
7
6
5
4
3
2
1
0
V
= V = 5V
REF
DD
= 25°C
T
A
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
= 909mV/DIV
OUT
1
0.39
0.40
0.41
0.42
0.43
TIME BASE = 4µs/DIV
I
(mA)
DD
Figure 16. IDD Histogram with VDD = 3.6 V
Figure 19. Full-Scale Settling Time, 5 V
0.20
DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT
V
T
= V
REF
= 5V, 3V
V
T
= V = 5V
REF
DD
= 25°C
DD
= 25°C
0.15
0.10
0.05
0
A
A
V
–0.05
–0.10
–0.15
DD
1
2
MAX(C2)
420.0mV
DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT
–0.20
–0.25
V
OUT
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
–5
–4
–3
–2
–1
0
1
2
3
4
5
I (mA)
Figure 20. Power-On Reset to 0 V
Figure 17. Headroom at Rails vs. Source and Sink Current
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= V
REFIN
= 5V
DD
SYNC
SLCK
1
3
V
= V
REFIN
= 3V
DD
V
OUT
V
= 5V
DD
2
T
= 25°C
–20
A
–40
0
20
40
60
80
100
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
TEMPERATURE (°C)
Figure 18. Supply Current vs. Temperature
Figure 21. Exiting Power-Down to Midscale
Rev. 0 | Page 10 of 24
AD5624/AD5664
16
14
12
10
8
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
V
= V = 5V
REF
DD
= 25°C
V
= V
DD
REF
= 25°C
T
A
T
A
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
V
= 3V
DD
V
= 5V
DD
6
4
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 22. Digital-to-Analog Glitch Impulse (Negative)
Figure 25. Settling Time vs. Capacitive Load
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
= V = 5V
REF
DD
= 25°C
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
V
= V = 5V
REF
DD
= 25°C
T
A
DAC LOADED WITH MIDSCALE
1
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 23. Analog Crosstalk
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot
–20
–30
–40
800
700
600
500
400
300
V
= 5V
V
= V = 5V
REF
DD
= 25°C
DD
T = 25°C
A
T
A
DAC LOADED WITH FULL SCALE
= 2V ± 0.3V p-p
V
REF
–50
–60
–70
–80
200
100
0
–90
–100
2k
4k
6k
8k
10k
10
100
1k
10k
100k
1M
(Hz)
FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
Figure 27. Noise Spectral Density
Rev. 0 | Page 11 of 24
AD5624/AD5664
5
V
A
= 5V
DD
= 25°C
T
0
–5
–10
–15
–20
–25
–30
–35
–40
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 28. Multiplying Bandwidth
Rev. 0 | Page 12 of 24
AD5624/AD5664
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in ꢀSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INꢀ vs. code plot can be seen in Figure 4
and Figure 5.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by 10%.
Output Voltage Settling Time
Differential Nonlinearity (DNL)
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24th falling edge of SCꢀK.
Differential nonlinearity is the difference between the measured
change and the ideal 1 ꢀSB change between any two adjacent
codes. A specified differential nonlinearity of 1 ꢀSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNꢀ vs. code plot can be seen in Figure 6 and
Figure 7.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 ꢀSB at the major carry transition (0x7FFF to 0x8000) as
shown in Figure 22.
Zero-Scale Error
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5624/AD5664 because the output of the DAC cannot go
below 0 V. It is due to a combination of the offset errors in the
DAC and the output amplifier. Zero-code error is expressed in
mV. A plot of zero-code error vs. temperature can be seen in
Figure 12.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Full-Scale Error
Total Harmonic Distortion (THD)
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 ꢀSB. Full-scale error is expressed in %
of FSR. A plot of full-scale error vs. temperature can be seen in
Figure 11.
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Noise Spectral Density
Gain Error
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density can be seen in Figure 27.
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a % of FSR.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in ꢁV.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
Offset Error
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in ꢁV/mA.
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5624/
AD5664 with code 512 loaded in the DAC register. It can be
negative or positive.
Rev. 0 | Page 13 of 24
AD5624/AD5664
Digital Crosstalk
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa) using the command write to and update while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software ꢀDAC
and monitor the output of the DAC whose digital code was
not changed. The area of the glitch is expressed in nV-s (see
Figure 23).
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. 0 | Page 14 of 24
AD5624/AD5664
THEORY OF OPERATION
D/A SECTION
R
The AD5624/AD5664 DACs are fabricated on a CMOS process.
The architecture consists of a string DAC followed by an output
buffer amplifier. Figure 29 shows a block diagram of the DAC
architecture.
R
R
TO OUTPUT
AMPLIFIER
V
DD
OUTPUT
AMPLIFIER
(GAIN = +2)
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
R
R
GND
Figure 29. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
Figure 30. Resistor String
SERIAL INTERFACE
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VREFIN
×
2N
The AD5624/AD5664 have a 3-wire serial interface (
,
SYNC
SCꢀK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as with most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
The write sequence begins by bringing the
line low. Data
SYNC
0 to 4095 for AD5624 (12 bit).
0 to 65535 for AD5664 (16 bit).
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCꢀK. The serial clock frequency can be as high
as 50 MHz, making the AD5624/AD5664 compatible with high
speed DSPs. On the 24th falling clock edge, the last data bit is
clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 30. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
of operation. At this stage, the
line can be kept low or be
SYNC
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of
can initiate the next write sequence. Since
SYNC
the
buffer draws more current when VIN = 2.0 V than it
SYNC
does when VIN = 0.8 V,
should be idled low between
SYNC
OUTPUT AMPLIFIER
write sequences for even lower power operation. It must,
however, be brought high again just before the next write
sequence.
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 17.
The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale settling time of
7 μs.
Rev. 0 | Page 15 of 24
AD5624/AD5664
INPUT SHIFT REGISTER
SYNC INTERRUPT
The input shift register is 24 bits wide The first two bits are
don’t care bits. The next three bits are the Command bits, C2 to
C0 (see Table 7), followed by the 3-bit DAC address, A2 to A0
(see Table 8), and then the 16-, 12-bit data-word. The data-word
comprises the 16-, 12- bit input code followed by 0 or 4 don’t
care bits for the AD5664 and AD5624 respectively (see Figure
31 and Figure 32). These data bits are transferred to the DAC
register on the 24th falling edge of SCꢀK.
In a normal write sequence, the
line is kept low for at least
SYNC
24 falling edges of SCꢀK, and the DAC is updated on the 24th
falling edge. However, if
is brought high before the 24th
SYNC
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 33).
POWER-ON RESET
Table 7. Command Definition
The AD5624/AD5664 family contains a power-on reset circuit
that controls the output voltage during power-up. The AD5624/
AD5664 DAC outputs power up to 0 V and the output remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the state of
the output of the DAC while it is in the process of powering up.
C2
C1
C0
Command
0
0
0
0
0
1
0
1
0
Write to input register n
Update DAC register n
Write to input register n, update all
(software LDAC)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Write to and update DAC channel n
Power down DAC (power-up)
Reset
Load LDAC register
Reserved
Table 8. Address Command
A2
A1
A0
ADDRESS (n)
0
0
0
DAC A
0
0
0
1
0
1
1
1
1
0
1
1
DAC B
DAC C
DAC D
All DACs
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 31. AD5664 Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 32. AD5624 Input Shift Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
TH
VALID WRITE SEQUENCE, OUTPUT UPDATES
TH
SYNC HIGH BEFORE 24 FALLING EDGE
ON THE 24 FALLING EDGE
SYNC
Figure 33.
Interrupt Facility
Rev. 0 | Page 16 of 24
AD5624/AD5664
Table 10. Modes of Operation for the AD5624/AD5664
SOFTWARE RESET
DB5
DB4
Operating Mode
The AD5624/AD5664 contain a software reset function.
Command 110 is reserved for the software reset function (see
Table 7). The software reset command contains two reset modes
that are software programmable by setting Bit DB0 in the
control register. Table 9 shows how the state of the bit
corresponds to the software reset modes of operation of the
devices.
0
0
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
1
1
1
0
1
When both bits are set to 0, the parts work normally with their
normal power consumption of 450 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This allows
the output impedance of the part to be known while the part is
in power-down mode.
Table 9. Software Reset Modes for the AD5624/AD5664
DB0
Registers Reset to Zero
0
DAC register
Input shift register
DAC register
1 (Power-On Reset)
Input shift register
LDAC register
Power-down register
The outputs can either be connected internally to GND through
a 1 kΩ or 100 kΩ resistor, or left open-circuited (three-state)
(see Figure 34).
POWER-DOWN MODES
The AD5624/AD5664 contain four separate modes of operation.
Command 100 is reserved for the power-down function (see
Table 7). These modes are software programmable by setting two
bits (DB5 and DB4) in the control register. Table 10 shows how
the state of the bits corresponds to the mode of operation of the
device. All DACs (DAC D to DAC A) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, and DB0) to 1. By executing the same Command 100,
any combination of DACs is powered up by setting Bit DB5 and
Bit DB4 to normal operation mode. To select which combination
of DAC channels to power-up, set the corresponding four bits
(DB3, DB2, DB1, and DB0) to 1. See Table 11 for contents of the
input shift register during the power-down/power-up operation.
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 34. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V
(see Figure 21).
Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
DB23 to
DB22 (MSB) DB21
DB15
DB0
(LSB)
DB20
DB19
DB18
DB17
DB16
to DB6 DB5 DB4 DB3
DB2
DB1
x
1
0
0
x
x
x
x
PD1 PD0 DAC D
DAC C DAC B DAC A
Don’t care
Command bits (C2 to C0)
Address bits (A2 to A0); don’t
care
Don’t
care
Power- Power-down/power-up channel
down mode selection, set bit to 1 to select
channel
Rev. 0 | Page 17 of 24
AD5624/AD5664
DAC registers. When the ꢀDAC bit register is set high,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them on the
falling edge of the 24th SCꢀK pulse. This is equivalent to having
LDAC FUNCTION
The AD5624/AD5664 DACs have double-buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor
strings.
ꢀDAC
an
hardware pin tied permanently low for the selected
DAC channel, that is, synchronous update mode. See Table 12
for the ꢀDAC register mode of operation. See Table 13 for
contents of the input shift register during the ꢀDAC register set-
up command.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register and update all DAC registers, the
outputs update simultaneously. Command 010 is reserved for
this software ꢀDAC.
This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.
Table 12. ꢀDAC Register Mode of Operation
Load DAC Register
Access to the DAC registers is controlled by the ꢀDAC
function. The ꢀDAC registers contain two modes of operation
for each DAC channel. The DAC channels are selected by
setting the bits of the 4-bit ꢀDAC register (DB3, DB2, DB1, and
DB0). Command 110 is reserved for setting up the ꢀDAC
register. When the ꢀDAC bit register is set low, the
LDAC Bits
(DB3 to DB0)
LDAC Mode of Operation
0
Normal operation (default), DAC register
update is controlled by write command.
1
The DAC registers are updated after new
data is read in on the falling edge of the
24th SCLK pulse.
corresponding DAC registers are latched and the input
registers can change state without affecting the contents of the
Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664
DB23 to
DB22
(MSB)
DB15 to
DB4
DB0
(LSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB3
DB2
DB1
x
1
1
0
x
x
x
x
DacD
DacC
DacB
DacA
Don’t Care Command bits (C2 to C0)
Address bits (A3 to A0); don’t care
Don’t
cares
Set bit to 0 or 1 for required mode of
operation on respective channel
Rev. 0 | Page 1± of 24
AD5624/AD5664
AD5624/AD5664 to 80C51/80L51 Interface
MICROPROCESSOR INTERFACING
Figure 37 shows a serial interface between the AD5624/AD5664
and the 80C51/80ꢀ51 microcontroller. The setup for the interface
is as follows. TxD of the 80C51/80ꢀ51 drives SCꢀK of the
AD5624/AD5664, while RxD drives the serial data line of the
AD5624/AD5664 to Blackfin® ADSP-BF53x Interface
Figure 35 shows a serial interface between the AD5624/AD5664 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor commu-
nications. Using SPORT0 to connect to the AD5624/AD5664, the
setup for the interface is as follows. DTOPRI drives the DIN pin of
the AD5624/AD5664, while TSCꢀK0 drives the SCꢀK of the part.
part. The
signal is derived from a bit-programmable pin
SYNC
on the port. In this case, port line P3.3 is used. When data is
transmitted to the AD5624/AD5664, P3.3 is taken low. The
80C51/80ꢀ51 transmits data in 10-bit bytes only; thus only eight
falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, and
a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80ꢀ51 output the serial data in a format that has the
ꢀSB first. The AD5624/AD5664 must receive data with the MSB
first. The 80C51/80ꢀ51 transmit routine should take this into
account.
The
is driven from TFS0.
SYNC
1
AD5624/
AD56641
ADSP-BF53x
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
1
AD5624/
Figure 35. Blackfin ADSP-BF53x Interface to AD5624/AD5664
80C51/80L51
AD56641
P3.3
TxD
RxD
SYNC
SCLK
DIN
AD5624/AD5664 to 68HC11/68L11 Interface
Figure 36 shows a serial interface between the AD5624/AD5664
and the 68HC11/68ꢀ11 microcontroller. SCK of the 68HC11/
68ꢀ11 drives the SCꢀK of the AD5624/AD5664, while the
MOSI output drives the serial data line of the DAC.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. 80C51/80L51 Interface to AD5624/AD5664
The
signal is derived from a port line (PC7). The setup
SYNC
AD5624/AD5664 to MICROWIRE Interface
conditions for correct operation of this interface are as follows.
The 68HC11/68ꢀ11 is configured with its CPOꢀ bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
Figure 38 shows an interface between the AD5624/AD5664 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5624/AD5664 on the rising edge of the SK.
the
line is taken low (PC7). When the 68HC11/68ꢀ11 is
SYNC
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68ꢀ11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5624/AD5664,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC; PC7 is
taken high at the end of this procedure.
1
AD5624/
AD56641
MICROWIRE
CS
SYNC
SCLK
DIN
SK
SO
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. MICROWIRE Interface to AD5624/AD5664
1
AD5624/
AD56641
68HC11/68L11
PC7
SCK
SYNC
SCLK
DIN
MOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. 68HC11/68L11 Interface to AD5624/AD5664
Rev. 0 | Page 19 of 24
AD5624/AD5664
APPLICATIONS
CHOOSING A REFERENCE FOR THE
AD5624/AD5664
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5624/AD5664
To achieve the optimum performance from the AD5624/
AD5664, thought should be given to the choice of a precision
voltage reference. The AD5624/AD5664 have only one
reference input, VREF. The voltage on the reference input is used
to supply the positive input to the DAC. Therefore, any error in
the reference is reflected in the DAC.
Because the supply current required by the AD5624/AD5664 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see Figure 39). This is
especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5624/AD5664 (see Table 14 for a suitable
reference). If the low dropout REF195 is used, it must supply
450 μA of current to the AD5624/AD5664, with no load on the
output of the DAC. When the DAC output is loaded, the
REF195 also needs to supply the current to the load. The total
current required (with a 5 kΩ load on the DAC output) is
When choosing a voltage reference for high accuracy applica-
tions, the sources of error are initial accuracy, ppm drift, long-
term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the DAC.
To minimize these errors, a reference with high initial accuracy
is preferred. Choosing a reference with an output trim
adjustment, such as the ADR423, allows a system designer to
trim out system errors by setting a reference voltage to a voltage
other than the nominal. The trim adjustment can also be used
at temperature to trim out any error.
450 μA + (5 V/5 kΩ) = 1.45 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 2.9 ppm (14.5 μV) error for the 1.45 mA
current drawn from it. This corresponds to a 0.191 ꢀSB error.
15V
ꢀong-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable during its entire lifetime.
5V
REF195
500mA
V
V
REF
DD
SYNC
SCLK
DIN
3-WIRE
SERIAL
INTERFACE
The temperature coefficient of a reference’s output voltage
affects INꢀ, DNꢀ, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.
AD5624/
AD5664
V
= 0V TO 5V
OUT
Figure 39. REF195 as Power Supply to the AD5624/AD5664
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references such as the ADR425 produce low
output noise in the 0.1 Hz to10 Hz range. Examples of recom-
mended precision references for use as supply to the
AD5624/AD5664 are shown in the Table 14.
Table 14. Partial List of Precision References for Use with the AD5624/AD5664
Temp Drift (ppmoC max)
VOUT (V)
Part No.
ADR425
ADR395
REF195
AD7±0
Initial Accuracy (mV max)
0.1 Hz to 10 Hz Noise (μV p-p typ)
±2
±6
±2
±2
±2
3
25
5
3
3
3.4
5
50
4
5
5
5
2.5/3
3
ADR423
3.4
Rev. 0 | Page 20 of 24
AD5624/AD5664
5V
REGULATOR
BIPOLAR OPERATION USING THE
AD5624/AD5664
10µF
0.1µF
POWER
The AD5624/AD5664 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 40. The circuit gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V1A
VOA
SCLK
AD5624/
AD5664
ADuM1300
V
SDI
V1B
OUT
VOB
SYNC
The output voltage for any input code can be calculated as
follows:
VOC
DATA
V1C
DIN
GND
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VO = V
×
×
−V
×
⎢
DD
DD
⎝
⎠
⎣
Figure 41. AD5624/AD5664 with a Galvanically Isolated Interface
where D represents the input code in decimal (0 to 65536).
With VDD = 5 V, R1 = R2 = 10 kΩ,
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5624/
AD5664 should have separate analog and digital sections, each
having its own area of the board. If the AD5624/AD5664 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5624/AD5664.
10×D
65,536
⎛
⎜
⎞
⎟
V =
−5 V
O
⎝
⎠
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
The power supply to the AD5624/AD5664 should be bypassed
with 10 μF and 0.1 μF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitor is the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
AD820/
OP295
±5V
V
V
OUT
DD
10µF
0.1µF
AD5624/
AD5664
–5V
3-WIRE
SERIAL
INTERFACE
Figure 40. Bipolar Operation with the AD5624/AD5664
USING AD5624/AD5664 WITH A
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where the
DAC is functioning. Isocouplers provide isolation in excess of
3 kV. The AD5624/AD5664 use a 3-wire serial logic interface,
so the ADuM130x 3-channel digital isolator provides the
required isolation (see Figure 41). The power supply to the part
also needs to be isolated, which is done by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides
the 5 V supply required for the AD5624/AD5664.
Rev. 0 | Page 21 of 24
AD5624/AD5664
OUTLINE DIMENSIONS
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 43. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Description
Package
Option
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
Branding
D5J
D5J
D5J
D5J
AD5624BRMZ
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±16 LSB INL
±16 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
RM-10
RM-10
AD5624BRMZ-REEL7
AD5624BCPZ-250RL7
AD5624BCPZ-REEL7
AD5664ARMZ
AD5664ARMZ-REEL7
AD5664BRMZ
AD5664BRMZ-REEL7
AD5664BCPZ-250RL7
AD5664BCPZ-REEL7
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD CP-10-9
10-Lead LFCSP_WD CP-10-9
RM-10
RM-10
RM-10
RM-10
D7C
D7C
D7±
D7±
D7±
D7±
Rev. 0 | Page 22 of 24
AD5624/AD5664
NOTES
Rev. 0 | Page 23 of 24
AD5624/AD5664
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05943-0-6/06(0)
Rev. 0 | Page 24 of 24
相关型号：
AD5664RBCPZ-3250R7
IC SERIAL INPUT LOADING, 4 us SETTLING TIME, 16-BIT DAC, DSO10, 3 X 3 MM, LEAD FREE, LFCSP-10, Digital to Analog Converter
ADI
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