AD5669RARUZ [ADI]
IC 16-BIT DAC, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16, Digital to Analog Converter;型号: | AD5669RARUZ |
厂家: | ADI |
描述: | IC 16-BIT DAC, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16, Digital to Analog Converter 光电二极管 转换器 |
文件: | 总33页 (文件大小:318K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Octal, 12-/16-Bit DAC, I2C®, 5ppm/°C On-
Chip Reference in 4mm X 4mm LFCSP
AD5629R/AD5669R
Preliminary Technical Data
(AD5669R-3) and remains powered up at this level until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 400 nA at 5 V
and provides software-selectable output loads while in power-
down mode for any or all DAC channels.
FEATURES
Low power, smallest-pin-compatible octal DACs
AD5669R: 16 bits
AD5629R: 12 bits
4mm X 4mm 16-lead LFCSP and 16-lead TSSOP
User selectable on-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
FUNCTIONAL BLOCK DIAGRAM
V
/V
V
REFIN REFO UT
DD
AD5629R/AD5669R
LDAC
1.25V/2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
DAC
REGISTER
STRING
DAC
INPUT
REGISTER
V
V
V
V
V
V
V
V
A
B
C
D
E
F
O UT
O UT
O UT
O UT
O UT
O UT
O UT
O UT
A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
B
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz)
and fast (400 kHz) modes
INPUT
DAC
STRING
DAC
SCL
SDA
A0
REGISTER
REGISTER
C
INTERFACE
LOG IC
DAC
REGISTER
STRING
DAC
INPUT
REGISTER
D
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
E
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
DAC
REGISTER
STRING
DAC
INPUT
REGISTER
F
DAC
REGISTER
STRING
DAC
INPUT
REGISTER
G
H
G
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
H
PO W ER-DOW N
POW ER-ON
RESET
LOGIC
GND
LDAC CLR
Figure 1
GENERAL DESCRIPTION
The AD5629R/AD5669R devices are low power, octal, 12-/16-
bit, buffered voltage-output DACs. All devices operate from a
single 2.7 V to 5.5 V supply and are guaranteed monotonic by
design.
The AD5629R/AD5669R has an on-chip reference with an
internal gain of 2. The AD5629R/AD5669R has a user selectable
1.25 V 5 ppm/°C reference, giving a full-scale output range of
2.5 V or a 2.5 V 5 ppm/°C reference, giving a full-scale output
range of 5 V depending on the option selected. The on-chip
reference is off at power-up, allowing the use of an external refer-
ence. The internal reference is enabled via a software write. The
AD5669/AD5629 require an external reference voltage to set
the output range of the DAC.
PRODUCT HIGHLIGHTS
1. Octal, 12-/16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 16-lead LFCSP/16-lead TSSOP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
The part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V (AD5629R/AD5669R) or midscale
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2010 Analog Devices, Inc. All rights reserved.
AD5629R/AD5669R
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String............................................................................. 23
Internal Reference ...................................................................... 23
Output Amplifier........................................................................ 24
Serial Interface............................................................................ 24
Write Operation.......................................................................... 24
Read Operation........................................................................... 24
Input Shift Register .................................................................... 27
Internal Reference Register....................................................... 27
Power-On Reset.......................................................................... 27
Power-Down Modes .................................................................. 27
Clear Code Register ................................................................... 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 7
I2C Timing Characteristics......................................................... 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 23
D/A Section................................................................................. 23
Function .......................................................................... 30
LDAC
Power Supply Bypassing and Grounding................................ 30
Outline Dimensions....................................................................... 32
AD5629R Ordering Guide........................................................ 33
AD5669R Ordering Guide........................................................ 33
REVISION HISTORY
Rev. PrA | Page 2 of 33
AD5629R/AD5669R
SPECIFICATIONS
Preliminary Technical Data
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
±±.25 LSB
±±.5 ±2
±±.25
±±.5 ±1
See Figure 5
Guaranteed monotonic by design
(see Figure 7)
AD5669R
Resolution
16
16
Bits
Relative Accuracy
Differential Nonlinearity
±ꢀ
±32
±1
±ꢀ
±16
±1
LSB
LSB
See Figure 4
Guaranteed monotonic by design
(see Figure 6)
Zero-Code Error
1
9
1
9
mV
All ±s loaded to DAC register
(see Figure 19)
Zero-Code Error Drift
Full-Scale Error
±2
−±.2 −1
±2
−±.2 −1
µV/°C
% FSR
All 1s loaded to DAC register
(see Figure 21)
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection Ratio
DC Crosstalk
±1
±1
% FSR
ppm
mV
dB
µV
±2.5
±1
–ꢀ±
1±
±2.5
Of FSR/°C
±9
±1
–ꢀ±
1±
±9
VDD ± 1±%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
(External Reference)
5
1±
25
5
1±
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
1±
1±
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
±
VDD
±
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
1±
±.5
3±
4
1±
±.5
3±
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode, VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT(1.25V)
Output Voltage
Reference Input Range
Output Impedance
REFERENCE OUTPUT(2.5V)
Output Voltage
Reference Input Range
Output Impedance
LOGIC INPUTS3
4±
5±
VDD
4±
5±
VDD
µA
V
kΩ
VREF = VDD = 5.5 V (per DAC channel)
±
±
14.6
14.6
1.247
1.253 1.247
2.5±5 2.495
±3
1.253 µA
±1± ppm/˚C
kΩ
At ambient
±5
7.5
±5
7.5
2.495
2.5±5 µA
At ambient
±5
7.5
±5
7.5
±1±
ppm/˚C
kΩ
Input Current
±3
µA
All digital inputs
Rev. PrA | Page 3 of 33
AD5629R/AD5669R
Preliminary Technical Data
A Grade1
Typ Max
B Grade1
Typ Max
±.ꢀ
Parameter
Min
Min
Unit
V
V
Conditions/Comments
VDD = 5 V
VDD = 5 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
±.ꢀ
2
2
3
3
pF
4.5
5.5
4.5
5.5
V
All digital inputs at ± or VDD,
DAC active, excludes load current
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)5
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
1.3
2
1.ꢀ
2.5
1.3
2
1.ꢀ
2.5
mA
mA
VDD = 4.5 V to 5.5 V
±.4
1
±.4
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −4±°C to +1±5°C, typical at 25°C.
2 Linearity calculated using a reduced code range of AD5629R (Code 32 to Code 4±64) and AD5669R (Code 512 to 65,±24). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
Rev. PrA | Page 4 of 33
AD5629R/AD5669R
Preliminary Technical Data
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
±±.25 LSB
±±.5 ±2
±±.25
±±.5 ±1
See Figure 5
Guaranteed monotonic by design
(see Figure 7)
AD5669R
Resolution
16
16
Bits
Relative Accuracy
Differential Nonlinearity
±ꢀ
±32
±1
±ꢀ
±16
±1
LSB
LSB
See Figure 4
Guaranteed monotonic by design
(see Figure 6)
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
1
±2
−±.2 −1
±1
±2.5
9
1
±2
−±.2 −1
±1
±2.5
9
mV
All ±s loaded to DAC register (see Figure 19)
All 1s loaded to DAC register (see Figure 21)
Of FSR/°C
µV/°C
% FSR
% FSR
ppm
mV
±1
±9
±1
±9
DC Power Supply Rejection
Ratio
–ꢀ±
–ꢀ±
dB
VDD ± 1±%
DC Crosstalk
(External Reference)
1±
1±
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
5
1±
25
5
1±
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
1±
1±
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
±
VDD
±
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
1±
±.5
3±
4
1±
±.5
3±
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
4±
5±
VDD
4±
5±
VDD
µA
kΩ
VREF = VDD = 3.6 V (per DAC channel)
±
±
14.6
14.6
AD5629R/AD5669R
Reference TC3
Reference Output
Impedance
1.247
1.253 1.247
1.253
±15
V
At ambient
±5
7.5
±5
7.5
ppm/°C
kΩ
LOGIC INPUTS3
Input Current
±3
±.ꢀ
2
±3
±.ꢀ
µA
V
V
All digital inputs
VDD = 3 V
VDD = 3 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
2
3
3
pF
2.7
3.6
2.7
3.6
V
All digital inputs at ± or VDD,
Rev. PrA | Page 5 of 33
AD5629R/AD5669R
Preliminary Technical Data
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
Min
Min
Unit
Conditions/Comments
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
IDD (Normal Mode)4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
1.2
1.7
1.5
2.25
1.2
1.7
1.5
2.25
mA
mA
Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V
±.2
1
±.2
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −4±°C to +1±5°C, typical at 25°C.
2 Linearity calculated using a reduced code range of AD5629R (Code 32 to Code 4±64) and AD5669R (Code 512 to 65±24). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
Rev. PrA | Page 6 of 33
AD5629R/AD5669R
Preliminary Technical Data
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Min
Typ
6
1.5
4
Max
Unit
µs
V/µs
nV-s
nV-s
dB
nV-s
nV-s
nV-s
kHz
Conditions/Comments3
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
1±
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry (see Figure 49)
VREF = 2 V ± ±.1 V p-p, frequency = 1± Hz to 2± MHz
±.1
−9±
±.5
2.5
3
34±
−ꢀ±
12±
1±±
15
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREF = 2 V ± ±.2 V p-p
dB
VREF = 2 V ± ±.1 V p-p, frequency = 1± kHz
DAC code = ±xꢀ4±±, 1 kHz
DAC code = ±xꢀ4±±, 1± kHz
±.1 Hz to 1± Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −4±°C to +1±5°C, typical at 25°C.
Rev. PrA | Page 7 of 33
AD5629R/AD5669R
Preliminary Technical Data
I2C TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Max
1±±
4±±
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
Description
1
fSCL
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Serial clock frequency
t1
t2
t3
t4
t5
4
tHIGH, SCL high time
tLOW, SCL low time
±.6
4.7
1.3
25±
1±±
±
tSU;DAT, data setup time
tHD;DAT, data hold time
Standard mode
Fast mode
Standard mode
3.45
±.9
±
4.7
μs
μs
tSU;STA, setup time for a repeated start
condition
Fast mode
Standard mode
Fast mode
±.6
4
±.6
4.7
μs
μs
μs
μs
t6
t7
tHD;STA, hold time (repeated) start condition
Standard mode
tBUF, bus-free time between a stop and a
start condition
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
1.3
4
±.6
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
tꢀ
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
t9
1±±±
3±±
3±±
3±±
1±±±
3±±
t1±
t11
t11A
tRCL, rise time of SCL signal
1±±±
tRCL1, rise time of SCL signal after a
repeated start condition and after an
acknowledge bit
Fast mode
3±±
ns
t12
t13
t14
Standard mode
Fast mode
Standard mode
Fast mode
3±±
3±±
ns
ns
ns
ns
ns
tFCL, fall time of SCL signal
LDAC pulse width low
1±
1±
3±±
Standard mode
Falling edge of ninth SCL clock pulse of
last byte of a valid write to LDAC falling
edge
Fast mode
Standard mode
Fast mode
3±±
2±
2±
±
ns
ns
ns
ns
t15
CLR pulse width low
2
tSP
Fast mode
5±
Pulse width of spike suppressed
1 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 5± ns for fast mode, or less than 1± ns for high speed mode.
Rev. PrA | Page ꢀ of 33
AD5629R/AD5669R
Preliminary Technical Data
t11
t12
t6
t2
t6
SCL
t1
t3
t5
t10
t8
t4
t9
SDA
t7
P
S
S
P
t14
t13
LDAC*
CLR
t15
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure2. Serial Write Operation
Rev. PrA | Page 9 of 33
AD5629R/AD5669R
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−±.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
−±.3 V to VDD + ±.3 V
−±.3 V to VDD + ±.3 V
−±.3 V to VDD + ±.3 V
−4±°C to +1±5°C
−65°C to +15±°C
+15±°C
Storage Temperature Range
Junction Temperature (TJ MAX
)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
(TJ MAX − TA)/θJA
15±.4°C/W
Reflow Soldering Peak Temperature
SnPb
Pb Free
24±°C
26±°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 1± of 33
AD5629R/AD5669R
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LDAC
A0
SCL
SDA
V
GND
DD
1
2
3
4
GND
12
11
10
9
V
V
D
D
AD5629R/
AD5669R
TOP VIEW
(Not to Scale)
V
V
V
V
A
C
E
V
V
V
V
B
D
F
O UT
O UT
O UT
O UT
O UT
O UT
O UT
O UT
A
C
E
AD5669R/29R
V
B
D
OUT
OUT
TOP
VIEW
V
OUT
V
OUT
V
F
V
OUT
OUT
G
H
V
/V
CLR
REFIN REFO UT
Figure 3. 16-Lead TSSOP (RU-16)
Figure 2. 16-Lead LFCSP (CP-16-17)
Table 6. Pin Function Descriptions
Pin No.
16-Lead
LFCSP
16-Lead
TSSOP
Mnemonic
Description
15
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.
Address Input. Sets the least significant bit of the 7-bit slave address.
16
1
2
3
A±
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 1± µF capacitor in parallel with a ±.1 µF capacitor to GND.
2
11
3
1±
6
4
13
5
12
ꢀ
VOUT
VOUT
VOUT
VOUT
A
B
C
D
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R has a common pin for reference input and reference output. When
using the internal reference, this is the reference output pin. When using an external
reference, this is the reference input pin. The default for this pin is as a reference input.
VREFIN/VREFOUT
7
9
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero, midscale, or full scale.
Default setting clears the output to ± V.
4
9
5
ꢀ
12
13
6
11
7
1±
14
15
VOUT
VOUT
VOUT
VOUT
GND
SDA
E
F
G
H
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on
the falling edge of the serial clock input.
14
16
SCL
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input.
Rev. PrA | Page 11 of 33
AD5629R/AD5669R
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. INL AD5669R—External Reference
Figure 7. DNL AD5629R—External Reference
Figure 5. INL AD5629R—External Reference
Figure 8. INL AD5669R-2/AD5669R-3
Figure 6. DNL AD5669R—External Reference
Figure 9
Figure 10. INL AD5629R-2
Rev. PrA | Page 12 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 11. DNL AD5669R-2/AD5669R-3
Figure 14. INL AD5629R-1
Figure 12. DNL AD5629R-2
Figure 15. DNL AD5629R-1
Figure 13. INL AD5669R-1
Rev. PrA | Page 13 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 16.
Figure 20.
Figure 17. Gain Error and Full-Scale Error vs. Temperature
Figure 21. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 22.
Figure 18.
Figure 23. Zero-Scale Error and Offset Error vs. Supply Voltage
Figure 19. Zero-Scale Error and Offset Error vs. Temperature
Rev. PrA | Page 14 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 24.
Figure 27.
Figure 25. IDD Histogram with External Reference
Figure 28. Headroom at Rails vs. Source and Sink
Figure 29.
Figure 26. IDD Histogram with Internal Reference
Figure 30. AD5669R-2/AD5669R-3 Source and Sink Capability
Rev. PrA | Page 15 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 31.
Figure 35.
Figure 32. AD5669R-1 Source and Sink Capability
Figure 36. Supply Current vs. Temperature
Figure 33.
Figure 37.
Figure 34. Supply Current vs. Code
Figure 38. Supply Current vs. Supply Voltage
Rev. PrA | Page 16 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 39.
Figure 43. Power-On Reset to 0 V
Figure 40. Supply Current vs. Logic Input Voltage
Figure 44.
Figure 45. Power-On Reset to Midscale
Figure 41.
Figure 42. Full-Scale Settling Time, 5 V
Rev. PrA | Page 17 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 46.
Figure 50.
Figure 47. Exiting Power-Down to Midscale
Figure 51. Analog Crosstalk
Figure 52.
Figure 48.
Figure 53. DAC-to-DAC Crosstalk
Figure 49. Digital-to-Analog Glitch Impulse (Negative)
Rev. PrA | Page 1ꢀ of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 54.
Figure 58.
Figure 55. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 59. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 56
Figure 57. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Figure 60.
Figure 61. Noise Spectral Density, Internal Reference
Rev. PrA | Page 19 of 33
AD5629R/AD5669R
Preliminary Technical Data
Figure 62.
Figure 66.
Figure 63. Total Harmonic Distortion
CLR
Figure 67. Hardware
Figure 64.
Figure 68.
Figure 65. Settling Time vs. Capacitive Load
Figure 69. Multiplying Bandwidth
Rev. PrA | Page 2± of 33
AD5629R/AD5669R
TERMINOLOGY
Preliminary Technical Data
Relative Accuracy
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight line
passing through the endpoints of the DAC transfer function.
Figure 4 to Figure 5, Figure 8 to Figure 10, and Figure 13 to
Figure 14 show plots of typical INL vs. code.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s and
is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000). See Figure 49.
Differential Nonlinearity
DC Power Supply Rejection Ratio (PSRR)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Figure 6 to Figure 7, Figure 11 to Figure 12, and
Error! Reference source not found. to Error! Reference source
not found. show plots of typical DNL vs. code.
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V, and VDD is varied 10ꢀ.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5669R with Code 512 loaded into the DAC register. It can
be negative or positive and is expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Zero-Code Error
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,
decibels.
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive
because the output of the DAC cannot go below 0 V. It is due to
a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in millivolts. Figure 23
shows a plot of typical zero-code error vs. temperature.
is high). It is expressed in
LDAC
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to. It
is specified in nV-s and measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s or vice versa.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Digital Crosstalk
Zero-Code Error Drift
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-s.
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Gain Error Drift
Analog Crosstalk
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
Full-Scale Error
code change (all 0s to all 1s or vice versa) while keeping
LDAC
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD – 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 17 shows a plot of
typical full-scale error vs. temperature.
high, and then pulsing
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
low and monitoring the output of
LDAC
DAC-to-DAC Crosstalk
Rev. PrA | Page 21 of 33
AD5629R/AD5669R
Preliminary Technical Data
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
low and monitoring the output of another DAC. The
LDAC
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. PrA | Page 22 of 33
AD5629R/AD5669R
Preliminary Technical Data
THEORY OF OPERATION
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
D/A SECTION
The AD5629R/AD5669R are fabricated on a CMOS process.
The architecture consists of a string of DACs followed by an
output buffer amplifier. Each part includes an internal 1.25
V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure
71 shows a block diagram of the DAC architecture.
R
R
TO OUTPUT
R
AMPLIFIER
Figure 70 DAC Architecture for internal reference configuration
R
R
Figure 72. Resistor String
INTERNAL REFERENCE
The AD5629R/AD5669R have an on-chip reference with an
internal gain of 2. The AD5629R/AD5669R have a 1.25 V, 5
ppm/°C reference, giving a full-scale output of 2.5 V; or a 2.5 V, 5
ppm/°C reference, which will only work from 4.5 to 5.5Vgiving
a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The
internal reference is enabled via a write to the control register
(see Table 8).
Figure 71. DAC Architecture for external reference configuration
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT =VREFIN
×
2N
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
The ideal output voltage when using the internal reference is
given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT
×
2N
Individual channel power-down is not supported while using
the internal reference.
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 4095 for AD5629R (12 bits).
0 to 65,535 for AD5669R (16 bits).
N = the DAC resolution.
RESISTOR STRING
The resistor string section is shown in Figure 72. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
Rev. PrA | Page 23 of 33
AD5629R/AD5669R
Preliminary Technical Data
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 30 and Figure 32. The slew rate
is 1.5 V/µs with a ¼ to ¾ scale settling time of 10 µs.
When all data bits have been read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10th clock pulse, and then high
during the 10th clock pulse to establish a stop condition.
SERIAL INTERFACE
The AD5629R/AD5669R have 2-wire I2C-compatible serial
interfaces (refer to The I2C-Bus Specification, Version 2.1,
January 2000, available from Philips Semiconductor). The
AD5629R/AD5669R can be connected to an I2C bus as a slave
device, under the control of a master device. See Figure X for a
timing diagram of a typical write sequence.
WRITE OPERATION
When writing to the AD5629R/AD5669R, the user must begin
W
with a start command followed by an address byte (R/ = 0),
The AD5629R/AD5669R support standard (100 kHz) and fast
(400 kHz) modes. High speed operation is only available on
selected models.
See the ordering guide for a full list of models. Support is not
provided for 10-bit addressing and general call addressing.
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5629R/AD5669R requires two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must therefore be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as shown in
Figures. After these data bytes are acknowledged by the
AD5629R/AD5669R, a stop condition follows.
The AD5629R/AD5669R each has a 7-bit slave address. The
part have a slave address whose five MSBs are 10101, and the
two LSBs are set by the state of the A0 address pin, which
determines the state of the A0 and A1 address bits.
READ OPERATION
The facility to make hardwired changes to the A0 pin allows the
user to incorporate up to three of these devices on one bus, as
outlined in Table 7.
When reading data back from the AD5629R/AD5669R, the
user begins with a start command followed by an address byte
W
(R/ = 1), after which the DAC acknowledges that it is prepared
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master as
shown in Figure 74 and Figure XX. A stop condition follows.
Table 7. ADDR Pin Settings (16-Lead Package)
A± Pin Connection
A1
A±
±
VDD
±
NC
1
±
GND
1
1
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
Rev. PrA | Page 24 of 33
AD5629R/AD5669R
Preliminary Technical Data
1
9
1
9
SCL
1
0
1
0
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
AD56x9
ACK. BY
AD56x9
START BY
MASTER
FRAM E 1
SLAVE ADDRESS
FRAM E 2
CO MM AND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CO NTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB8
STO P BY
M ASTER
ACK. BY
AD56x9
ACK. BY
AD56x9
FRAM E 3
MO ST SIG NIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 73. I2C Write Operation
1
9
1
9
SCL
SDA
1
0
1
0
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
AD56x9
ACK. BY
MASTER
START BY
MASTER
FRAM E 1
SLAVE ADDRESS
FRAM E 2
CO MM AND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CO NTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB8
STO P BY
MASTER
ACK. BY
MASTER
NO ACK.
FRAM E 3
MO ST SIG NIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 74. I2C Read Operation
Rev. PrA | Page 25 of 33
AD5629R/AD5669R
Preliminary Technical Data
Table 8. Command Definitions
Command
C3 C2 C1 C0 Description
±
±
±
±
±
±
±
±
1
±
1
±
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
±
±
±
±
±
1
1
–
1
±
1
1
1
1
±
±
–
1
1
±
±
1
1
±
±
–
1
1
±
1
±
1
±
1
–
1
Write to and update DAC Channel n
Power down/power up DAC 1
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up internal REF register
Enable multiple byte mode
Reserved
Reserved
Table 9. Address Commands
Address (n)
Selected DAC
Channel
A3
±
±
±
±
±
±
±
±
A2
±
±
±
±
1
1
1
1
A1
±
±
1
1
±
±
1
1
A0
±
1
±
1
±
1
±
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
1
1
1
1
1 Available on AD5629R and AD5669R versions only.
Rev. PrA | Page 26 of 33
AD5629R/AD5669R
Preliminary Technical Data
Multiple byte operation is supported on the AD5629R
/AD5669R.Command 1001 is reserved for multiple byte
operation(see Table 8) A 2-byte operation is useful for
applications that require fast DAC updating and do not need to
change the command byte. The S bit (DB22) in the command
register can be set to 1 for 2-byte mode of operation (see Figure
62). For standard 3-byte and 4-byte operation, the S bit (DB22)
in the command byte should be set to 0 (see Figure 61).
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure
X. The eight MSBs make up the command byte. DB23-DB20
are the command bits (C3, C2, C1, and C0) that control the
mode of operation of the device. See Table 9 for details. The last
four bits of the first byte are the address bits (A3, A2, A1, and
A0). See Table 10 for details. The rest of the bits are the 16-/12-
bit data word. The data word comprises the 16-/12-bit input
code followed by four don’t cares for the device (see Figure 57
and Figure 58).
MULTIPLE BYTE OPERATION
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9
DB8
D8
DB7
D7
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
COM M AND
DAC ADDRESS
DAC DATA
DAC DATA
CO MM AND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 75. AD5669R/AD5669 Input Register Contents
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5
DB8
D4
DB7
D3
DB6
D2
DB5
D1
DB4
D0
DB3
X
DB2
X
DB1
X
DB0
X
COM M AND
DAC ADDRESS
DAC DATA
DAC DATA
CO MM AND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 76. AD5629R/AD5629 Input Register Contents
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
INTERNAL REFERENCE REGISTER
The internal reference is available on all versions. The on-board
reference is off at power-up by default. This allows the use of an
external reference if the application requires it. The on-board
reference can be turned on or off by a user-programmable
internal REF register by setting Bit DB0 high or low (see Table
10). DB1 selects the internal reference value. When DB1 is set
to 1 the 1.25V reference is selected. When DB1 is set to 0 the
2.5V internal reference is selected. Command 1000 is reserved
for setting the internal REF register (see Table 8). Table 12
shows how the state of the bits in the input shift register
corresponds to the mode of operation of the device. Command
1000 is not functional in AD5669/29 models because there is no
internal reference available.
(see Table 8). Any events on
or during power-on
LDAC CLR
reset are ignored.
POWER-DOWN MODES
The AD5629R/AD5669R contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13.
Internal reference setup
POWER-ON RESET
The AD5629R/AD5669R family contains a power-on reset
circuit that controls the output voltage during power-up. The
AD5629R/AD5669R DAC output powers up to 0 V, and the
AD5669R-3 DAC output powers up to midscale. The output
remains powered up at this level until a valid write sequence is
DB9
DB8
Operating Mode
±
±
Internal reference off
Rev. PrA | Page 27 of 33
AD5629R/AD5669R
Preliminary Technical Data
value in the input register (
DAC register before powering down (
low) or to the value in the
LDAC
±
1
1
1
±
1
2.5V interenal reference on
Internal reference off
1.25V internal reference on
high).
LDAC
CLEAR CODE REGISTER
The AD5629R/AD5669R have a hardware
pin that
CLR
Table 14 for the contents of the input shift register during power-
down/power-up operation. When using the internal reference,
only all channel power-down to the selected modes is
supported.
is an asynchronous clear input. The
input is falling edge
CLR
sensitive. Bringing the
line low clears the contents of the
CLR
input register and the DAC registers to the data contained in
the user-configurable register and sets the analog outputs
CLR
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 µA at
5 V (0.2 µA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 77.
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits,
Bit DB1 and Bit DB0, in the
control register (see
CLR
Table 15). The default setting clears the outputs to 0 V.
Command 0101 is reserved for loading the clear code register
(see Table 8).
The part exits clear code mode on the 32nd falling edge of the next
write to the part. If
write is aborted.
is activated during a write sequence, the
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. The internal
reference is powered down only when all channels are powered
down. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
4 µs for VDD = 5 V and for VDD = 3 V. See Figure 47 for a plot.
CLR
The
pulse activation time—the falling edge of
to
CLR
CLR
when the output starts to change—is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing
for the output to start changing (see Figure 67).
CLR
See Table 16 for contents of the input shift register during the
loading clear code register operation.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
Rev. PrA | Page 2ꢀ of 33
AD5629R/AD5669R
Preliminary Technical Data
Table 10. Internal Reference Register
Internal REF Register (DB0)
Action
±
1
Reference off (default)
Reference on
Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command
LSB
DB23 DB22 DB21 DB20 DB19
DB18
DB17
DB16
DB15 to
DB2
DB1
DB0
1
±
±
±
X
X
X
X
X
1/±
1/±
Command bits (C3 to C±)
Address bits (A3 to A±)—don’t
cares
Don’t cares
2.5V/1.25V
internal REF
Internal REF
on/off
Table 12. Power-Down Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
1±± kΩ to GND
Three-state
±
±
±
1
1
1
±
1
Table 13. Internal reference setup
DB9
DB8
Operating Mode
±
±
1
1
±
1
±
1
Internal reference off
2.5V interenal reference on
Internal reference off
1.25V internal reference on
Table 14. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function
LSB
DB15
to
DB10
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
±
1
±
±
X
X
X
X
X
PD1
PD±
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Command bits (C3 to C±)
Address bits (A3 to A±)—
don’t cares
Don’t
cares
Power-
down mode
Power-down/power-up channel selection—set bit to 1 to select
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 77. Output Stage During Power-Down
Table 15. Clear Code Register
Clear Code Register
DB1
CR1
±
DB0
CR0
±
Clears to Code
±x±±±±
±xꢀ±±±
±
1
Rev. PrA | Page 29 of 33
AD5629R/AD5669R
Preliminary Technical Data
1
1
±
1
±xFFFF
No operation
Table 16. 32-Bit Input Shift Register Contents for Clear Code Function
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB2
X
DB1
DB0
±
1
±
1
X
X
X
X
CR1
CR±
Command bits (C3 to C±)
Address bits (A3 to A±)—don’t cares
Don’t cares
Clear code register
FUNCTION
POWER SUPPLY BYPASSING AND GROUNDING
LDAC
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5629R/
AD5669R should have separate analog and digital sections. If
the AD5629R/AD5669R are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5629R/AD5669R.
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
LDAC
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on.
Figure.
can be permanently low or pulsed as in
LDAC
Asynchronous
: The outputs are not updated at the same
LDAC
time that the input registers are written to. When
goes
LDAC
The power supply to the AD5629R/AD5669R should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor has low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software
function by writing to Input
LDAC
Register n and updating all DAC registers. Command 0011 is
reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
LDAC
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the pin. It
LDAC
pin as being tied low. (See Table 17
effectively sees the
LDAC
for the
register mode of operation.) This flexibility is
LDAC
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating. Writing to the DAC using command
0110 loads the 8-bit
register (DB7 to DB0). The default
LDAC
for each channel is 0, that is, the
pin works normally.
LDAC
Setting the bits to 1 means the DAC channel is updated
regardless of the state of the pin. See Table 18 for the
LDAC
contents of the input shift register during the load
register mode of operation.
LDAC
Rev. PrA | Page 3± of 33
AD5629R/AD5669R
Preliminary Technical Data
Table 17.
Register
LDAC
Load DAC Register
LDAC Bits (DB7 to DB0)
LDAC Pin
1/±
LDAC Operation
±
1
Determined by LDAC pin.
X—don’t care
DAC channels update, overriding the LDAC pin. DAC channels see LDAC as ±.
Table 18. 32-Bit Input Shift Register Contents for
Register Function
LDAC
LSB
DB15
to
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
±
1
1
±
X
X
X
X
X
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Command bits (C3 to C±)
Address bits (A3 to A±)—
don’t cares
Don’t
cares
LDAC
LDAC
bit to 1 overrides pin
Setting
Rev. PrA | Page 31 of 33
AD5629R/AD5669R
Preliminary Technical Data
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
1
0.65
BSC
12
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
5
9
8
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 78. 16-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 79. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. PrA | Page 32 of 33
AD5629R/AD5669R
Preliminary Technical Data
AD5629R ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Model
Temperature Range
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead TSSOP
16-Lead TSSOP
Accuracy
±2 LSB INL
±1 LSB INL
±2 LSB INL
±1 LSB INL
AD5629RACPZ1
AD5629RBCPZ1
AD5629RARUZ1
AD5629RBRUZ1
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
CP-16-17
CP-16-17
RU-16
Zero
Zero
Zero
Zero
RU-16
1 Z = Pb-free part.
AD5669R ORDERING GUIDE
Package Power-On
Model
Temperature Range
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
LFCSP Evaluation board
TSSOP Evaluation board
Option
Reset to Code
Accuracy
AD5669RACPZ1
AD5669RACPZ-31
AD5669 RBCPZ1
AD5669RARUZ1
AD5669RARUZ-31
AD5669RBRUZ 1
EVAL-AD5669REBZ-RU
EVAL-AD5669REBZ-CP
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
CP-16-17 Zero
CP-16-17 Midscale
CP-16-17 Zero
RU-16
RU-16
RU-16
±32 LSB INL
±32 LSB INL
±16 LSB INL
±32 LSB INL
±32 LSB INL
±16 LSB INL
Zero
Midscale
Zero
1 Z = Pb-free part.
©
2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08819-0-1/10(PrA)
Rev. PrA | Page 33 of 33
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